1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 1 31 #define DRV_MODULE_VER_SUBMINOR 0 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 40 41 #define GET_L4_HDR_LEN(mbuf) \ 42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 44 45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 47 #define ENA_HASH_KEY_SIZE 40 48 #define ETH_GSTRING_LEN 32 49 50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 51 52 #define ENA_MIN_RING_DESC 128 53 54 enum ethtool_stringset { 55 ETH_SS_TEST = 0, 56 ETH_SS_STATS, 57 }; 58 59 struct ena_stats { 60 char name[ETH_GSTRING_LEN]; 61 int stat_offset; 62 }; 63 64 #define ENA_STAT_ENTRY(stat, stat_type) { \ 65 .name = #stat, \ 66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 67 } 68 69 #define ENA_STAT_RX_ENTRY(stat) \ 70 ENA_STAT_ENTRY(stat, rx) 71 72 #define ENA_STAT_TX_ENTRY(stat) \ 73 ENA_STAT_ENTRY(stat, tx) 74 75 #define ENA_STAT_ENI_ENTRY(stat) \ 76 ENA_STAT_ENTRY(stat, eni) 77 78 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 79 ENA_STAT_ENTRY(stat, dev) 80 81 /* Device arguments */ 82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 83 84 /* 85 * Each rte_memzone should have unique name. 86 * To satisfy it, count number of allocation and add it to name. 87 */ 88 rte_atomic32_t ena_alloc_cnt; 89 90 static const struct ena_stats ena_stats_global_strings[] = { 91 ENA_STAT_GLOBAL_ENTRY(wd_expired), 92 ENA_STAT_GLOBAL_ENTRY(dev_start), 93 ENA_STAT_GLOBAL_ENTRY(dev_stop), 94 ENA_STAT_GLOBAL_ENTRY(tx_drops), 95 }; 96 97 static const struct ena_stats ena_stats_eni_strings[] = { 98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded), 99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded), 100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded), 101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded), 102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded), 103 }; 104 105 static const struct ena_stats ena_stats_tx_strings[] = { 106 ENA_STAT_TX_ENTRY(cnt), 107 ENA_STAT_TX_ENTRY(bytes), 108 ENA_STAT_TX_ENTRY(prepare_ctx_err), 109 ENA_STAT_TX_ENTRY(linearize), 110 ENA_STAT_TX_ENTRY(linearize_failed), 111 ENA_STAT_TX_ENTRY(tx_poll), 112 ENA_STAT_TX_ENTRY(doorbells), 113 ENA_STAT_TX_ENTRY(bad_req_id), 114 ENA_STAT_TX_ENTRY(available_desc), 115 }; 116 117 static const struct ena_stats ena_stats_rx_strings[] = { 118 ENA_STAT_RX_ENTRY(cnt), 119 ENA_STAT_RX_ENTRY(bytes), 120 ENA_STAT_RX_ENTRY(refill_partial), 121 ENA_STAT_RX_ENTRY(bad_csum), 122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 123 ENA_STAT_RX_ENTRY(bad_desc_num), 124 ENA_STAT_RX_ENTRY(bad_req_id), 125 }; 126 127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings) 129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 131 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 133 DEV_TX_OFFLOAD_UDP_CKSUM |\ 134 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 135 DEV_TX_OFFLOAD_TCP_TSO) 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 137 PKT_TX_IP_CKSUM |\ 138 PKT_TX_TCP_SEG) 139 140 /** Vendor ID used by Amazon devices */ 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F 142 /** Amazon devices */ 143 #define PCI_DEVICE_ID_ENA_VF 0xEC20 144 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 145 146 #define ENA_TX_OFFLOAD_MASK (\ 147 PKT_TX_L4_MASK | \ 148 PKT_TX_IPV6 | \ 149 PKT_TX_IPV4 | \ 150 PKT_TX_IP_CKSUM | \ 151 PKT_TX_TCP_SEG) 152 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 155 156 static const struct rte_pci_id pci_id_ena_map[] = { 157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 159 { .device_id = 0 }, 160 }; 161 162 static struct ena_aenq_handlers aenq_handlers; 163 164 static int ena_device_init(struct ena_com_dev *ena_dev, 165 struct ena_com_dev_get_features_ctx *get_feat_ctx, 166 bool *wd_state); 167 static int ena_dev_configure(struct rte_eth_dev *dev); 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 169 struct ena_tx_buffer *tx_info, 170 struct rte_mbuf *mbuf, 171 void **push_header, 172 uint16_t *header_len); 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 174 static void ena_tx_cleanup(struct ena_ring *tx_ring); 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 176 uint16_t nb_pkts); 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 178 uint16_t nb_pkts); 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 180 uint16_t nb_desc, unsigned int socket_id, 181 const struct rte_eth_txconf *tx_conf); 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 183 uint16_t nb_desc, unsigned int socket_id, 184 const struct rte_eth_rxconf *rx_conf, 185 struct rte_mempool *mp); 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 188 struct ena_com_rx_buf_info *ena_bufs, 189 uint32_t descs, 190 uint16_t *next_to_clean, 191 uint8_t offset); 192 static uint16_t eth_ena_recv_pkts(void *rx_queue, 193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 195 struct rte_mbuf *mbuf, uint16_t id); 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 197 static void ena_init_rings(struct ena_adapter *adapter, 198 bool disable_meta_caching); 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 200 static int ena_start(struct rte_eth_dev *dev); 201 static void ena_stop(struct rte_eth_dev *dev); 202 static int ena_close(struct rte_eth_dev *dev); 203 static int ena_dev_reset(struct rte_eth_dev *dev); 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 207 static void ena_rx_queue_release(void *queue); 208 static void ena_tx_queue_release(void *queue); 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 211 static int ena_link_update(struct rte_eth_dev *dev, 212 int wait_to_complete); 213 static int ena_create_io_queue(struct ena_ring *ring); 214 static void ena_queue_stop(struct ena_ring *ring); 215 static void ena_queue_stop_all(struct rte_eth_dev *dev, 216 enum ena_ring_type ring_type); 217 static int ena_queue_start(struct ena_ring *ring); 218 static int ena_queue_start_all(struct rte_eth_dev *dev, 219 enum ena_ring_type ring_type); 220 static void ena_stats_restart(struct rte_eth_dev *dev); 221 static int ena_infos_get(struct rte_eth_dev *dev, 222 struct rte_eth_dev_info *dev_info); 223 static int ena_rss_reta_update(struct rte_eth_dev *dev, 224 struct rte_eth_rss_reta_entry64 *reta_conf, 225 uint16_t reta_size); 226 static int ena_rss_reta_query(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 static void ena_interrupt_handler_rte(void *cb_arg); 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 233 static int ena_xstats_get_names(struct rte_eth_dev *dev, 234 struct rte_eth_xstat_name *xstats_names, 235 unsigned int n); 236 static int ena_xstats_get(struct rte_eth_dev *dev, 237 struct rte_eth_xstat *stats, 238 unsigned int n); 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 240 const uint64_t *ids, 241 uint64_t *values, 242 unsigned int n); 243 static int ena_process_bool_devarg(const char *key, 244 const char *value, 245 void *opaque); 246 static int ena_parse_devargs(struct ena_adapter *adapter, 247 struct rte_devargs *devargs); 248 static int ena_copy_eni_stats(struct ena_adapter *adapter); 249 250 static const struct eth_dev_ops ena_dev_ops = { 251 .dev_configure = ena_dev_configure, 252 .dev_infos_get = ena_infos_get, 253 .rx_queue_setup = ena_rx_queue_setup, 254 .tx_queue_setup = ena_tx_queue_setup, 255 .dev_start = ena_start, 256 .dev_stop = ena_stop, 257 .link_update = ena_link_update, 258 .stats_get = ena_stats_get, 259 .xstats_get_names = ena_xstats_get_names, 260 .xstats_get = ena_xstats_get, 261 .xstats_get_by_id = ena_xstats_get_by_id, 262 .mtu_set = ena_mtu_set, 263 .rx_queue_release = ena_rx_queue_release, 264 .tx_queue_release = ena_tx_queue_release, 265 .dev_close = ena_close, 266 .dev_reset = ena_dev_reset, 267 .reta_update = ena_rss_reta_update, 268 .reta_query = ena_rss_reta_query, 269 }; 270 271 void ena_rss_key_fill(void *key, size_t size) 272 { 273 static bool key_generated; 274 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 275 size_t i; 276 277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 278 279 if (!key_generated) { 280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 281 default_key[i] = rte_rand() & 0xff; 282 key_generated = true; 283 } 284 285 rte_memcpy(key, default_key, size); 286 } 287 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 289 struct ena_com_rx_ctx *ena_rx_ctx) 290 { 291 uint64_t ol_flags = 0; 292 uint32_t packet_type = 0; 293 294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 295 packet_type |= RTE_PTYPE_L4_TCP; 296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 297 packet_type |= RTE_PTYPE_L4_UDP; 298 299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 300 packet_type |= RTE_PTYPE_L3_IPV4; 301 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 302 packet_type |= RTE_PTYPE_L3_IPV6; 303 304 if (!ena_rx_ctx->l4_csum_checked) 305 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 306 else 307 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 308 ol_flags |= PKT_RX_L4_CKSUM_BAD; 309 else 310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 311 312 if (unlikely(ena_rx_ctx->l3_csum_err)) 313 ol_flags |= PKT_RX_IP_CKSUM_BAD; 314 315 mbuf->ol_flags = ol_flags; 316 mbuf->packet_type = packet_type; 317 } 318 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 320 struct ena_com_tx_ctx *ena_tx_ctx, 321 uint64_t queue_offloads, 322 bool disable_meta_caching) 323 { 324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 325 326 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 327 (queue_offloads & QUEUE_OFFLOADS)) { 328 /* check if TSO is required */ 329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 331 ena_tx_ctx->tso_enable = true; 332 333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 334 } 335 336 /* check if L3 checksum is needed */ 337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 339 ena_tx_ctx->l3_csum_enable = true; 340 341 if (mbuf->ol_flags & PKT_TX_IPV6) { 342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 343 } else { 344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 345 346 /* set don't fragment (DF) flag */ 347 if (mbuf->packet_type & 348 (RTE_PTYPE_L4_NONFRAG 349 | RTE_PTYPE_INNER_L4_NONFRAG)) 350 ena_tx_ctx->df = true; 351 } 352 353 /* check if L4 checksum is needed */ 354 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 357 ena_tx_ctx->l4_csum_enable = true; 358 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 359 PKT_TX_UDP_CKSUM) && 360 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 362 ena_tx_ctx->l4_csum_enable = true; 363 } else { 364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 365 ena_tx_ctx->l4_csum_enable = false; 366 } 367 368 ena_meta->mss = mbuf->tso_segsz; 369 ena_meta->l3_hdr_len = mbuf->l3_len; 370 ena_meta->l3_hdr_offset = mbuf->l2_len; 371 372 ena_tx_ctx->meta_valid = true; 373 } else if (disable_meta_caching) { 374 memset(ena_meta, 0, sizeof(*ena_meta)); 375 ena_tx_ctx->meta_valid = true; 376 } else { 377 ena_tx_ctx->meta_valid = false; 378 } 379 } 380 381 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 382 { 383 if (likely(req_id < rx_ring->ring_size)) 384 return 0; 385 386 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 387 388 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 389 rx_ring->adapter->trigger_reset = true; 390 ++rx_ring->rx_stats.bad_req_id; 391 392 return -EFAULT; 393 } 394 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 396 { 397 struct ena_tx_buffer *tx_info = NULL; 398 399 if (likely(req_id < tx_ring->ring_size)) { 400 tx_info = &tx_ring->tx_buffer_info[req_id]; 401 if (likely(tx_info->mbuf)) 402 return 0; 403 } 404 405 if (tx_info) 406 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 407 else 408 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 409 410 /* Trigger device reset */ 411 ++tx_ring->tx_stats.bad_req_id; 412 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 413 tx_ring->adapter->trigger_reset = true; 414 return -EFAULT; 415 } 416 417 static void ena_config_host_info(struct ena_com_dev *ena_dev) 418 { 419 struct ena_admin_host_info *host_info; 420 int rc; 421 422 /* Allocate only the host info */ 423 rc = ena_com_allocate_host_info(ena_dev); 424 if (rc) { 425 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 426 return; 427 } 428 429 host_info = ena_dev->host_attr.host_info; 430 431 host_info->os_type = ENA_ADMIN_OS_DPDK; 432 host_info->kernel_ver = RTE_VERSION; 433 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 434 sizeof(host_info->kernel_ver_str)); 435 host_info->os_dist = RTE_VERSION; 436 strlcpy((char *)host_info->os_dist_str, rte_version(), 437 sizeof(host_info->os_dist_str)); 438 host_info->driver_version = 439 (DRV_MODULE_VER_MAJOR) | 440 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 441 (DRV_MODULE_VER_SUBMINOR << 442 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 443 host_info->num_cpus = rte_lcore_count(); 444 445 host_info->driver_supported_features = 446 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 447 448 rc = ena_com_set_host_attributes(ena_dev); 449 if (rc) { 450 if (rc == -ENA_COM_UNSUPPORTED) 451 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 452 else 453 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 454 455 goto err; 456 } 457 458 return; 459 460 err: 461 ena_com_delete_host_info(ena_dev); 462 } 463 464 /* This function calculates the number of xstats based on the current config */ 465 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 466 { 467 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + 468 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 469 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 470 } 471 472 static void ena_config_debug_area(struct ena_adapter *adapter) 473 { 474 u32 debug_area_size; 475 int rc, ss_count; 476 477 ss_count = ena_xstats_calc_num(adapter->rte_dev); 478 479 /* allocate 32 bytes for each string and 64bit for the value */ 480 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 481 482 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 483 if (rc) { 484 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 485 return; 486 } 487 488 rc = ena_com_set_host_attributes(&adapter->ena_dev); 489 if (rc) { 490 if (rc == -ENA_COM_UNSUPPORTED) 491 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 492 else 493 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 494 495 goto err; 496 } 497 498 return; 499 err: 500 ena_com_delete_debug_area(&adapter->ena_dev); 501 } 502 503 static int ena_close(struct rte_eth_dev *dev) 504 { 505 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 507 struct ena_adapter *adapter = dev->data->dev_private; 508 509 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 510 ena_stop(dev); 511 adapter->state = ENA_ADAPTER_STATE_CLOSED; 512 513 ena_rx_queue_release_all(dev); 514 ena_tx_queue_release_all(dev); 515 516 rte_free(adapter->drv_stats); 517 adapter->drv_stats = NULL; 518 519 rte_intr_disable(intr_handle); 520 rte_intr_callback_unregister(intr_handle, 521 ena_interrupt_handler_rte, 522 adapter); 523 524 /* 525 * MAC is not allocated dynamically. Setting NULL should prevent from 526 * release of the resource in the rte_eth_dev_release_port(). 527 */ 528 dev->data->mac_addrs = NULL; 529 530 return 0; 531 } 532 533 static int 534 ena_dev_reset(struct rte_eth_dev *dev) 535 { 536 int rc = 0; 537 538 ena_destroy_device(dev); 539 rc = eth_ena_dev_init(dev); 540 if (rc) 541 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 542 543 return rc; 544 } 545 546 static int ena_rss_reta_update(struct rte_eth_dev *dev, 547 struct rte_eth_rss_reta_entry64 *reta_conf, 548 uint16_t reta_size) 549 { 550 struct ena_adapter *adapter = dev->data->dev_private; 551 struct ena_com_dev *ena_dev = &adapter->ena_dev; 552 int rc, i; 553 u16 entry_value; 554 int conf_idx; 555 int idx; 556 557 if ((reta_size == 0) || (reta_conf == NULL)) 558 return -EINVAL; 559 560 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 561 PMD_DRV_LOG(WARNING, 562 "indirection table %d is bigger than supported (%d)\n", 563 reta_size, ENA_RX_RSS_TABLE_SIZE); 564 return -EINVAL; 565 } 566 567 for (i = 0 ; i < reta_size ; i++) { 568 /* each reta_conf is for 64 entries. 569 * to support 128 we use 2 conf of 64 570 */ 571 conf_idx = i / RTE_RETA_GROUP_SIZE; 572 idx = i % RTE_RETA_GROUP_SIZE; 573 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 574 entry_value = 575 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 576 577 rc = ena_com_indirect_table_fill_entry(ena_dev, 578 i, 579 entry_value); 580 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 581 PMD_DRV_LOG(ERR, 582 "Cannot fill indirect table\n"); 583 return rc; 584 } 585 } 586 } 587 588 rte_spinlock_lock(&adapter->admin_lock); 589 rc = ena_com_indirect_table_set(ena_dev); 590 rte_spinlock_unlock(&adapter->admin_lock); 591 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 592 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 593 return rc; 594 } 595 596 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 597 __func__, reta_size, adapter->rte_dev->data->port_id); 598 599 return 0; 600 } 601 602 /* Query redirection table. */ 603 static int ena_rss_reta_query(struct rte_eth_dev *dev, 604 struct rte_eth_rss_reta_entry64 *reta_conf, 605 uint16_t reta_size) 606 { 607 struct ena_adapter *adapter = dev->data->dev_private; 608 struct ena_com_dev *ena_dev = &adapter->ena_dev; 609 int rc; 610 int i; 611 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 612 int reta_conf_idx; 613 int reta_idx; 614 615 if (reta_size == 0 || reta_conf == NULL || 616 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 617 return -EINVAL; 618 619 rte_spinlock_lock(&adapter->admin_lock); 620 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 621 rte_spinlock_unlock(&adapter->admin_lock); 622 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 623 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 624 return -ENOTSUP; 625 } 626 627 for (i = 0 ; i < reta_size ; i++) { 628 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 629 reta_idx = i % RTE_RETA_GROUP_SIZE; 630 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 631 reta_conf[reta_conf_idx].reta[reta_idx] = 632 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 633 } 634 635 return 0; 636 } 637 638 static int ena_rss_init_default(struct ena_adapter *adapter) 639 { 640 struct ena_com_dev *ena_dev = &adapter->ena_dev; 641 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 642 int rc, i; 643 u32 val; 644 645 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 646 if (unlikely(rc)) { 647 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 648 goto err_rss_init; 649 } 650 651 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 652 val = i % nb_rx_queues; 653 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 654 ENA_IO_RXQ_IDX(val)); 655 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 656 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 657 goto err_fill_indir; 658 } 659 } 660 661 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 662 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 663 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 664 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 665 goto err_fill_indir; 666 } 667 668 rc = ena_com_set_default_hash_ctrl(ena_dev); 669 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 670 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 671 goto err_fill_indir; 672 } 673 674 rc = ena_com_indirect_table_set(ena_dev); 675 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 676 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 677 goto err_fill_indir; 678 } 679 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 680 adapter->rte_dev->data->port_id); 681 682 return 0; 683 684 err_fill_indir: 685 ena_com_rss_destroy(ena_dev); 686 err_rss_init: 687 688 return rc; 689 } 690 691 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 692 { 693 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 694 int nb_queues = dev->data->nb_rx_queues; 695 int i; 696 697 for (i = 0; i < nb_queues; i++) 698 ena_rx_queue_release(queues[i]); 699 } 700 701 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 702 { 703 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 704 int nb_queues = dev->data->nb_tx_queues; 705 int i; 706 707 for (i = 0; i < nb_queues; i++) 708 ena_tx_queue_release(queues[i]); 709 } 710 711 static void ena_rx_queue_release(void *queue) 712 { 713 struct ena_ring *ring = (struct ena_ring *)queue; 714 715 /* Free ring resources */ 716 if (ring->rx_buffer_info) 717 rte_free(ring->rx_buffer_info); 718 ring->rx_buffer_info = NULL; 719 720 if (ring->rx_refill_buffer) 721 rte_free(ring->rx_refill_buffer); 722 ring->rx_refill_buffer = NULL; 723 724 if (ring->empty_rx_reqs) 725 rte_free(ring->empty_rx_reqs); 726 ring->empty_rx_reqs = NULL; 727 728 ring->configured = 0; 729 730 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 731 ring->port_id, ring->id); 732 } 733 734 static void ena_tx_queue_release(void *queue) 735 { 736 struct ena_ring *ring = (struct ena_ring *)queue; 737 738 /* Free ring resources */ 739 if (ring->push_buf_intermediate_buf) 740 rte_free(ring->push_buf_intermediate_buf); 741 742 if (ring->tx_buffer_info) 743 rte_free(ring->tx_buffer_info); 744 745 if (ring->empty_tx_reqs) 746 rte_free(ring->empty_tx_reqs); 747 748 ring->empty_tx_reqs = NULL; 749 ring->tx_buffer_info = NULL; 750 ring->push_buf_intermediate_buf = NULL; 751 752 ring->configured = 0; 753 754 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 755 ring->port_id, ring->id); 756 } 757 758 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 759 { 760 unsigned int i; 761 762 for (i = 0; i < ring->ring_size; ++i) { 763 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 764 if (rx_info->mbuf) { 765 rte_mbuf_raw_free(rx_info->mbuf); 766 rx_info->mbuf = NULL; 767 } 768 } 769 } 770 771 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 772 { 773 unsigned int i; 774 775 for (i = 0; i < ring->ring_size; ++i) { 776 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 777 778 if (tx_buf->mbuf) 779 rte_pktmbuf_free(tx_buf->mbuf); 780 } 781 } 782 783 static int ena_link_update(struct rte_eth_dev *dev, 784 __rte_unused int wait_to_complete) 785 { 786 struct rte_eth_link *link = &dev->data->dev_link; 787 struct ena_adapter *adapter = dev->data->dev_private; 788 789 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 790 link->link_speed = ETH_SPEED_NUM_NONE; 791 link->link_duplex = ETH_LINK_FULL_DUPLEX; 792 793 return 0; 794 } 795 796 static int ena_queue_start_all(struct rte_eth_dev *dev, 797 enum ena_ring_type ring_type) 798 { 799 struct ena_adapter *adapter = dev->data->dev_private; 800 struct ena_ring *queues = NULL; 801 int nb_queues; 802 int i = 0; 803 int rc = 0; 804 805 if (ring_type == ENA_RING_TYPE_RX) { 806 queues = adapter->rx_ring; 807 nb_queues = dev->data->nb_rx_queues; 808 } else { 809 queues = adapter->tx_ring; 810 nb_queues = dev->data->nb_tx_queues; 811 } 812 for (i = 0; i < nb_queues; i++) { 813 if (queues[i].configured) { 814 if (ring_type == ENA_RING_TYPE_RX) { 815 ena_assert_msg( 816 dev->data->rx_queues[i] == &queues[i], 817 "Inconsistent state of rx queues\n"); 818 } else { 819 ena_assert_msg( 820 dev->data->tx_queues[i] == &queues[i], 821 "Inconsistent state of tx queues\n"); 822 } 823 824 rc = ena_queue_start(&queues[i]); 825 826 if (rc) { 827 PMD_INIT_LOG(ERR, 828 "failed to start queue %d type(%d)", 829 i, ring_type); 830 goto err; 831 } 832 } 833 } 834 835 return 0; 836 837 err: 838 while (i--) 839 if (queues[i].configured) 840 ena_queue_stop(&queues[i]); 841 842 return rc; 843 } 844 845 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 846 { 847 uint32_t max_frame_len = adapter->max_mtu; 848 849 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 850 DEV_RX_OFFLOAD_JUMBO_FRAME) 851 max_frame_len = 852 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 853 854 return max_frame_len; 855 } 856 857 static int ena_check_valid_conf(struct ena_adapter *adapter) 858 { 859 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 860 861 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 862 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 863 "max mtu: %d, min mtu: %d", 864 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 865 return ENA_COM_UNSUPPORTED; 866 } 867 868 return 0; 869 } 870 871 static int 872 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 873 bool use_large_llq_hdr) 874 { 875 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 876 struct ena_com_dev *ena_dev = ctx->ena_dev; 877 uint32_t max_tx_queue_size; 878 uint32_t max_rx_queue_size; 879 880 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 881 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 882 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 883 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 884 max_queue_ext->max_rx_sq_depth); 885 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 886 887 if (ena_dev->tx_mem_queue_type == 888 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 889 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 890 llq->max_llq_depth); 891 } else { 892 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 893 max_queue_ext->max_tx_sq_depth); 894 } 895 896 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 897 max_queue_ext->max_per_packet_rx_descs); 898 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 899 max_queue_ext->max_per_packet_tx_descs); 900 } else { 901 struct ena_admin_queue_feature_desc *max_queues = 902 &ctx->get_feat_ctx->max_queues; 903 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 904 max_queues->max_sq_depth); 905 max_tx_queue_size = max_queues->max_cq_depth; 906 907 if (ena_dev->tx_mem_queue_type == 908 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 909 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 910 llq->max_llq_depth); 911 } else { 912 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 913 max_queues->max_sq_depth); 914 } 915 916 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 917 max_queues->max_packet_rx_descs); 918 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 919 max_queues->max_packet_tx_descs); 920 } 921 922 /* Round down to the nearest power of 2 */ 923 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 924 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 925 926 if (use_large_llq_hdr) { 927 if ((llq->entry_size_ctrl_supported & 928 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 929 (ena_dev->tx_mem_queue_type == 930 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 931 max_tx_queue_size /= 2; 932 PMD_INIT_LOG(INFO, 933 "Forcing large headers and decreasing maximum TX queue size to %d\n", 934 max_tx_queue_size); 935 } else { 936 PMD_INIT_LOG(ERR, 937 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 938 } 939 } 940 941 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 942 PMD_INIT_LOG(ERR, "Invalid queue size"); 943 return -EFAULT; 944 } 945 946 ctx->max_tx_queue_size = max_tx_queue_size; 947 ctx->max_rx_queue_size = max_rx_queue_size; 948 949 return 0; 950 } 951 952 static void ena_stats_restart(struct rte_eth_dev *dev) 953 { 954 struct ena_adapter *adapter = dev->data->dev_private; 955 956 rte_atomic64_init(&adapter->drv_stats->ierrors); 957 rte_atomic64_init(&adapter->drv_stats->oerrors); 958 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 959 adapter->drv_stats->rx_drops = 0; 960 } 961 962 static int ena_stats_get(struct rte_eth_dev *dev, 963 struct rte_eth_stats *stats) 964 { 965 struct ena_admin_basic_stats ena_stats; 966 struct ena_adapter *adapter = dev->data->dev_private; 967 struct ena_com_dev *ena_dev = &adapter->ena_dev; 968 int rc; 969 int i; 970 int max_rings_stats; 971 972 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 973 return -ENOTSUP; 974 975 memset(&ena_stats, 0, sizeof(ena_stats)); 976 977 rte_spinlock_lock(&adapter->admin_lock); 978 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 979 rte_spinlock_unlock(&adapter->admin_lock); 980 if (unlikely(rc)) { 981 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 982 return rc; 983 } 984 985 /* Set of basic statistics from ENA */ 986 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 987 ena_stats.rx_pkts_low); 988 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 989 ena_stats.tx_pkts_low); 990 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 991 ena_stats.rx_bytes_low); 992 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 993 ena_stats.tx_bytes_low); 994 995 /* Driver related stats */ 996 stats->imissed = adapter->drv_stats->rx_drops; 997 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 998 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 999 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 1000 1001 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 1002 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1003 for (i = 0; i < max_rings_stats; ++i) { 1004 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 1005 1006 stats->q_ibytes[i] = rx_stats->bytes; 1007 stats->q_ipackets[i] = rx_stats->cnt; 1008 stats->q_errors[i] = rx_stats->bad_desc_num + 1009 rx_stats->bad_req_id; 1010 } 1011 1012 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 1013 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1014 for (i = 0; i < max_rings_stats; ++i) { 1015 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 1016 1017 stats->q_obytes[i] = tx_stats->bytes; 1018 stats->q_opackets[i] = tx_stats->cnt; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1025 { 1026 struct ena_adapter *adapter; 1027 struct ena_com_dev *ena_dev; 1028 int rc = 0; 1029 1030 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1031 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1032 adapter = dev->data->dev_private; 1033 1034 ena_dev = &adapter->ena_dev; 1035 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1036 1037 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1038 PMD_DRV_LOG(ERR, 1039 "Invalid MTU setting. new_mtu: %d " 1040 "max mtu: %d min mtu: %d\n", 1041 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1042 return -EINVAL; 1043 } 1044 1045 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1046 if (rc) 1047 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1048 else 1049 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1050 1051 return rc; 1052 } 1053 1054 static int ena_start(struct rte_eth_dev *dev) 1055 { 1056 struct ena_adapter *adapter = dev->data->dev_private; 1057 uint64_t ticks; 1058 int rc = 0; 1059 1060 rc = ena_check_valid_conf(adapter); 1061 if (rc) 1062 return rc; 1063 1064 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1065 if (rc) 1066 return rc; 1067 1068 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1069 if (rc) 1070 goto err_start_tx; 1071 1072 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1073 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1074 rc = ena_rss_init_default(adapter); 1075 if (rc) 1076 goto err_rss_init; 1077 } 1078 1079 ena_stats_restart(dev); 1080 1081 adapter->timestamp_wd = rte_get_timer_cycles(); 1082 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1083 1084 ticks = rte_get_timer_hz(); 1085 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1086 ena_timer_wd_callback, adapter); 1087 1088 ++adapter->dev_stats.dev_start; 1089 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1090 1091 return 0; 1092 1093 err_rss_init: 1094 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1095 err_start_tx: 1096 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1097 return rc; 1098 } 1099 1100 static void ena_stop(struct rte_eth_dev *dev) 1101 { 1102 struct ena_adapter *adapter = dev->data->dev_private; 1103 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1104 int rc; 1105 1106 rte_timer_stop_sync(&adapter->timer_wd); 1107 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1108 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1109 1110 if (adapter->trigger_reset) { 1111 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1112 if (rc) 1113 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1114 } 1115 1116 ++adapter->dev_stats.dev_stop; 1117 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1118 } 1119 1120 static int ena_create_io_queue(struct ena_ring *ring) 1121 { 1122 struct ena_adapter *adapter; 1123 struct ena_com_dev *ena_dev; 1124 struct ena_com_create_io_ctx ctx = 1125 /* policy set to _HOST just to satisfy icc compiler */ 1126 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1127 0, 0, 0, 0, 0 }; 1128 uint16_t ena_qid; 1129 unsigned int i; 1130 int rc; 1131 1132 adapter = ring->adapter; 1133 ena_dev = &adapter->ena_dev; 1134 1135 if (ring->type == ENA_RING_TYPE_TX) { 1136 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1137 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1138 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1139 for (i = 0; i < ring->ring_size; i++) 1140 ring->empty_tx_reqs[i] = i; 1141 } else { 1142 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1143 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1144 for (i = 0; i < ring->ring_size; i++) 1145 ring->empty_rx_reqs[i] = i; 1146 } 1147 ctx.queue_size = ring->ring_size; 1148 ctx.qid = ena_qid; 1149 ctx.msix_vector = -1; /* interrupts not used */ 1150 ctx.numa_node = ring->numa_socket_id; 1151 1152 rc = ena_com_create_io_queue(ena_dev, &ctx); 1153 if (rc) { 1154 PMD_DRV_LOG(ERR, 1155 "failed to create io queue #%d (qid:%d) rc: %d\n", 1156 ring->id, ena_qid, rc); 1157 return rc; 1158 } 1159 1160 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1161 &ring->ena_com_io_sq, 1162 &ring->ena_com_io_cq); 1163 if (rc) { 1164 PMD_DRV_LOG(ERR, 1165 "Failed to get io queue handlers. queue num %d rc: %d\n", 1166 ring->id, rc); 1167 ena_com_destroy_io_queue(ena_dev, ena_qid); 1168 return rc; 1169 } 1170 1171 if (ring->type == ENA_RING_TYPE_TX) 1172 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1173 1174 return 0; 1175 } 1176 1177 static void ena_queue_stop(struct ena_ring *ring) 1178 { 1179 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1180 1181 if (ring->type == ENA_RING_TYPE_RX) { 1182 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1183 ena_rx_queue_release_bufs(ring); 1184 } else { 1185 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1186 ena_tx_queue_release_bufs(ring); 1187 } 1188 } 1189 1190 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1191 enum ena_ring_type ring_type) 1192 { 1193 struct ena_adapter *adapter = dev->data->dev_private; 1194 struct ena_ring *queues = NULL; 1195 uint16_t nb_queues, i; 1196 1197 if (ring_type == ENA_RING_TYPE_RX) { 1198 queues = adapter->rx_ring; 1199 nb_queues = dev->data->nb_rx_queues; 1200 } else { 1201 queues = adapter->tx_ring; 1202 nb_queues = dev->data->nb_tx_queues; 1203 } 1204 1205 for (i = 0; i < nb_queues; ++i) 1206 if (queues[i].configured) 1207 ena_queue_stop(&queues[i]); 1208 } 1209 1210 static int ena_queue_start(struct ena_ring *ring) 1211 { 1212 int rc, bufs_num; 1213 1214 ena_assert_msg(ring->configured == 1, 1215 "Trying to start unconfigured queue\n"); 1216 1217 rc = ena_create_io_queue(ring); 1218 if (rc) { 1219 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1220 return rc; 1221 } 1222 1223 ring->next_to_clean = 0; 1224 ring->next_to_use = 0; 1225 1226 if (ring->type == ENA_RING_TYPE_TX) { 1227 ring->tx_stats.available_desc = 1228 ena_com_free_q_entries(ring->ena_com_io_sq); 1229 return 0; 1230 } 1231 1232 bufs_num = ring->ring_size - 1; 1233 rc = ena_populate_rx_queue(ring, bufs_num); 1234 if (rc != bufs_num) { 1235 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1236 ENA_IO_RXQ_IDX(ring->id)); 1237 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1238 return ENA_COM_FAULT; 1239 } 1240 1241 return 0; 1242 } 1243 1244 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1245 uint16_t queue_idx, 1246 uint16_t nb_desc, 1247 unsigned int socket_id, 1248 const struct rte_eth_txconf *tx_conf) 1249 { 1250 struct ena_ring *txq = NULL; 1251 struct ena_adapter *adapter = dev->data->dev_private; 1252 unsigned int i; 1253 1254 txq = &adapter->tx_ring[queue_idx]; 1255 1256 if (txq->configured) { 1257 PMD_DRV_LOG(CRIT, 1258 "API violation. Queue %d is already configured\n", 1259 queue_idx); 1260 return ENA_COM_FAULT; 1261 } 1262 1263 if (!rte_is_power_of_2(nb_desc)) { 1264 PMD_DRV_LOG(ERR, 1265 "Unsupported size of TX queue: %d is not a power of 2.\n", 1266 nb_desc); 1267 return -EINVAL; 1268 } 1269 1270 if (nb_desc > adapter->max_tx_ring_size) { 1271 PMD_DRV_LOG(ERR, 1272 "Unsupported size of TX queue (max size: %d)\n", 1273 adapter->max_tx_ring_size); 1274 return -EINVAL; 1275 } 1276 1277 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1278 nb_desc = adapter->max_tx_ring_size; 1279 1280 txq->port_id = dev->data->port_id; 1281 txq->next_to_clean = 0; 1282 txq->next_to_use = 0; 1283 txq->ring_size = nb_desc; 1284 txq->size_mask = nb_desc - 1; 1285 txq->numa_socket_id = socket_id; 1286 1287 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1288 sizeof(struct ena_tx_buffer) * 1289 txq->ring_size, 1290 RTE_CACHE_LINE_SIZE); 1291 if (!txq->tx_buffer_info) { 1292 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1293 return -ENOMEM; 1294 } 1295 1296 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1297 sizeof(u16) * txq->ring_size, 1298 RTE_CACHE_LINE_SIZE); 1299 if (!txq->empty_tx_reqs) { 1300 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1301 rte_free(txq->tx_buffer_info); 1302 return -ENOMEM; 1303 } 1304 1305 txq->push_buf_intermediate_buf = 1306 rte_zmalloc("txq->push_buf_intermediate_buf", 1307 txq->tx_max_header_size, 1308 RTE_CACHE_LINE_SIZE); 1309 if (!txq->push_buf_intermediate_buf) { 1310 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1311 rte_free(txq->tx_buffer_info); 1312 rte_free(txq->empty_tx_reqs); 1313 return -ENOMEM; 1314 } 1315 1316 for (i = 0; i < txq->ring_size; i++) 1317 txq->empty_tx_reqs[i] = i; 1318 1319 if (tx_conf != NULL) { 1320 txq->offloads = 1321 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1322 } 1323 /* Store pointer to this queue in upper layer */ 1324 txq->configured = 1; 1325 dev->data->tx_queues[queue_idx] = txq; 1326 1327 return 0; 1328 } 1329 1330 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1331 uint16_t queue_idx, 1332 uint16_t nb_desc, 1333 unsigned int socket_id, 1334 __rte_unused const struct rte_eth_rxconf *rx_conf, 1335 struct rte_mempool *mp) 1336 { 1337 struct ena_adapter *adapter = dev->data->dev_private; 1338 struct ena_ring *rxq = NULL; 1339 size_t buffer_size; 1340 int i; 1341 1342 rxq = &adapter->rx_ring[queue_idx]; 1343 if (rxq->configured) { 1344 PMD_DRV_LOG(CRIT, 1345 "API violation. Queue %d is already configured\n", 1346 queue_idx); 1347 return ENA_COM_FAULT; 1348 } 1349 1350 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1351 nb_desc = adapter->max_rx_ring_size; 1352 1353 if (!rte_is_power_of_2(nb_desc)) { 1354 PMD_DRV_LOG(ERR, 1355 "Unsupported size of RX queue: %d is not a power of 2.\n", 1356 nb_desc); 1357 return -EINVAL; 1358 } 1359 1360 if (nb_desc > adapter->max_rx_ring_size) { 1361 PMD_DRV_LOG(ERR, 1362 "Unsupported size of RX queue (max size: %d)\n", 1363 adapter->max_rx_ring_size); 1364 return -EINVAL; 1365 } 1366 1367 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1368 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1369 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1370 PMD_DRV_LOG(ERR, 1371 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1372 buffer_size, ENA_RX_BUF_MIN_SIZE); 1373 return -EINVAL; 1374 } 1375 1376 rxq->port_id = dev->data->port_id; 1377 rxq->next_to_clean = 0; 1378 rxq->next_to_use = 0; 1379 rxq->ring_size = nb_desc; 1380 rxq->size_mask = nb_desc - 1; 1381 rxq->numa_socket_id = socket_id; 1382 rxq->mb_pool = mp; 1383 1384 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1385 sizeof(struct ena_rx_buffer) * nb_desc, 1386 RTE_CACHE_LINE_SIZE); 1387 if (!rxq->rx_buffer_info) { 1388 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1389 return -ENOMEM; 1390 } 1391 1392 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1393 sizeof(struct rte_mbuf *) * nb_desc, 1394 RTE_CACHE_LINE_SIZE); 1395 1396 if (!rxq->rx_refill_buffer) { 1397 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1398 rte_free(rxq->rx_buffer_info); 1399 rxq->rx_buffer_info = NULL; 1400 return -ENOMEM; 1401 } 1402 1403 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1404 sizeof(uint16_t) * nb_desc, 1405 RTE_CACHE_LINE_SIZE); 1406 if (!rxq->empty_rx_reqs) { 1407 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1408 rte_free(rxq->rx_buffer_info); 1409 rxq->rx_buffer_info = NULL; 1410 rte_free(rxq->rx_refill_buffer); 1411 rxq->rx_refill_buffer = NULL; 1412 return -ENOMEM; 1413 } 1414 1415 for (i = 0; i < nb_desc; i++) 1416 rxq->empty_rx_reqs[i] = i; 1417 1418 /* Store pointer to this queue in upper layer */ 1419 rxq->configured = 1; 1420 dev->data->rx_queues[queue_idx] = rxq; 1421 1422 return 0; 1423 } 1424 1425 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1426 struct rte_mbuf *mbuf, uint16_t id) 1427 { 1428 struct ena_com_buf ebuf; 1429 int rc; 1430 1431 /* prepare physical address for DMA transaction */ 1432 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1433 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1434 1435 /* pass resource to device */ 1436 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1437 if (unlikely(rc != 0)) 1438 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1439 1440 return rc; 1441 } 1442 1443 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1444 { 1445 unsigned int i; 1446 int rc; 1447 uint16_t next_to_use = rxq->next_to_use; 1448 uint16_t in_use, req_id; 1449 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1450 1451 if (unlikely(!count)) 1452 return 0; 1453 1454 in_use = rxq->ring_size - 1 - 1455 ena_com_free_q_entries(rxq->ena_com_io_sq); 1456 ena_assert_msg(((in_use + count) < rxq->ring_size), 1457 "bad ring state\n"); 1458 1459 /* get resources for incoming packets */ 1460 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1461 if (unlikely(rc < 0)) { 1462 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1463 ++rxq->rx_stats.mbuf_alloc_fail; 1464 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1465 return 0; 1466 } 1467 1468 for (i = 0; i < count; i++) { 1469 struct rte_mbuf *mbuf = mbufs[i]; 1470 struct ena_rx_buffer *rx_info; 1471 1472 if (likely((i + 4) < count)) 1473 rte_prefetch0(mbufs[i + 4]); 1474 1475 req_id = rxq->empty_rx_reqs[next_to_use]; 1476 rc = validate_rx_req_id(rxq, req_id); 1477 if (unlikely(rc)) 1478 break; 1479 1480 rx_info = &rxq->rx_buffer_info[req_id]; 1481 1482 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1483 if (unlikely(rc != 0)) 1484 break; 1485 1486 rx_info->mbuf = mbuf; 1487 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1488 } 1489 1490 if (unlikely(i < count)) { 1491 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1492 "buffers (from %d)\n", rxq->id, i, count); 1493 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1494 count - i); 1495 ++rxq->rx_stats.refill_partial; 1496 } 1497 1498 /* When we submitted free recources to device... */ 1499 if (likely(i > 0)) { 1500 /* ...let HW know that it can fill buffers with data. */ 1501 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1502 1503 rxq->next_to_use = next_to_use; 1504 } 1505 1506 return i; 1507 } 1508 1509 static int ena_device_init(struct ena_com_dev *ena_dev, 1510 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1511 bool *wd_state) 1512 { 1513 uint32_t aenq_groups; 1514 int rc; 1515 bool readless_supported; 1516 1517 /* Initialize mmio registers */ 1518 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1519 if (rc) { 1520 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1521 return rc; 1522 } 1523 1524 /* The PCIe configuration space revision id indicate if mmio reg 1525 * read is disabled. 1526 */ 1527 readless_supported = 1528 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1529 & ENA_MMIO_DISABLE_REG_READ); 1530 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1531 1532 /* reset device */ 1533 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1534 if (rc) { 1535 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1536 goto err_mmio_read_less; 1537 } 1538 1539 /* check FW version */ 1540 rc = ena_com_validate_version(ena_dev); 1541 if (rc) { 1542 PMD_DRV_LOG(ERR, "device version is too low\n"); 1543 goto err_mmio_read_less; 1544 } 1545 1546 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1547 1548 /* ENA device administration layer init */ 1549 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1550 if (rc) { 1551 PMD_DRV_LOG(ERR, 1552 "cannot initialize ena admin queue with device\n"); 1553 goto err_mmio_read_less; 1554 } 1555 1556 /* To enable the msix interrupts the driver needs to know the number 1557 * of queues. So the driver uses polling mode to retrieve this 1558 * information. 1559 */ 1560 ena_com_set_admin_polling_mode(ena_dev, true); 1561 1562 ena_config_host_info(ena_dev); 1563 1564 /* Get Device Attributes and features */ 1565 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1566 if (rc) { 1567 PMD_DRV_LOG(ERR, 1568 "cannot get attribute for ena device rc= %d\n", rc); 1569 goto err_admin_init; 1570 } 1571 1572 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1573 BIT(ENA_ADMIN_NOTIFICATION) | 1574 BIT(ENA_ADMIN_KEEP_ALIVE) | 1575 BIT(ENA_ADMIN_FATAL_ERROR) | 1576 BIT(ENA_ADMIN_WARNING); 1577 1578 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1579 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1580 if (rc) { 1581 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1582 goto err_admin_init; 1583 } 1584 1585 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1586 1587 return 0; 1588 1589 err_admin_init: 1590 ena_com_admin_destroy(ena_dev); 1591 1592 err_mmio_read_less: 1593 ena_com_mmio_reg_read_request_destroy(ena_dev); 1594 1595 return rc; 1596 } 1597 1598 static void ena_interrupt_handler_rte(void *cb_arg) 1599 { 1600 struct ena_adapter *adapter = cb_arg; 1601 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1602 1603 ena_com_admin_q_comp_intr_handler(ena_dev); 1604 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1605 ena_com_aenq_intr_handler(ena_dev, adapter); 1606 } 1607 1608 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1609 { 1610 if (!adapter->wd_state) 1611 return; 1612 1613 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1614 return; 1615 1616 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1617 adapter->keep_alive_timeout)) { 1618 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1619 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1620 adapter->trigger_reset = true; 1621 ++adapter->dev_stats.wd_expired; 1622 } 1623 } 1624 1625 /* Check if admin queue is enabled */ 1626 static void check_for_admin_com_state(struct ena_adapter *adapter) 1627 { 1628 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1629 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1630 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1631 adapter->trigger_reset = true; 1632 } 1633 } 1634 1635 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1636 void *arg) 1637 { 1638 struct ena_adapter *adapter = arg; 1639 struct rte_eth_dev *dev = adapter->rte_dev; 1640 1641 check_for_missing_keep_alive(adapter); 1642 check_for_admin_com_state(adapter); 1643 1644 if (unlikely(adapter->trigger_reset)) { 1645 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1646 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1647 NULL); 1648 } 1649 } 1650 1651 static inline void 1652 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1653 struct ena_admin_feature_llq_desc *llq, 1654 bool use_large_llq_hdr) 1655 { 1656 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1657 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1658 llq_config->llq_num_decs_before_header = 1659 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1660 1661 if (use_large_llq_hdr && 1662 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1663 llq_config->llq_ring_entry_size = 1664 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1665 llq_config->llq_ring_entry_size_value = 256; 1666 } else { 1667 llq_config->llq_ring_entry_size = 1668 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1669 llq_config->llq_ring_entry_size_value = 128; 1670 } 1671 } 1672 1673 static int 1674 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1675 struct ena_com_dev *ena_dev, 1676 struct ena_admin_feature_llq_desc *llq, 1677 struct ena_llq_configurations *llq_default_configurations) 1678 { 1679 int rc; 1680 u32 llq_feature_mask; 1681 1682 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1683 if (!(ena_dev->supported_features & llq_feature_mask)) { 1684 PMD_DRV_LOG(INFO, 1685 "LLQ is not supported. Fallback to host mode policy.\n"); 1686 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1687 return 0; 1688 } 1689 1690 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1691 if (unlikely(rc)) { 1692 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1693 "Fallback to host mode policy."); 1694 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1695 return 0; 1696 } 1697 1698 /* Nothing to config, exit */ 1699 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1700 return 0; 1701 1702 if (!adapter->dev_mem_base) { 1703 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1704 "Fallback to host mode policy.\n."); 1705 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1706 return 0; 1707 } 1708 1709 ena_dev->mem_bar = adapter->dev_mem_base; 1710 1711 return 0; 1712 } 1713 1714 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1715 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1716 { 1717 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1718 1719 /* Regular queues capabilities */ 1720 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1721 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1722 &get_feat_ctx->max_queue_ext.max_queue_ext; 1723 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1724 max_queue_ext->max_rx_cq_num); 1725 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1726 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1727 } else { 1728 struct ena_admin_queue_feature_desc *max_queues = 1729 &get_feat_ctx->max_queues; 1730 io_tx_sq_num = max_queues->max_sq_num; 1731 io_tx_cq_num = max_queues->max_cq_num; 1732 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1733 } 1734 1735 /* In case of LLQ use the llq number in the get feature cmd */ 1736 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1737 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1738 1739 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1740 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1741 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1742 1743 if (unlikely(max_num_io_queues == 0)) { 1744 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1745 return -EFAULT; 1746 } 1747 1748 return max_num_io_queues; 1749 } 1750 1751 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1752 { 1753 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1754 struct rte_pci_device *pci_dev; 1755 struct rte_intr_handle *intr_handle; 1756 struct ena_adapter *adapter = eth_dev->data->dev_private; 1757 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1758 struct ena_com_dev_get_features_ctx get_feat_ctx; 1759 struct ena_llq_configurations llq_config; 1760 const char *queue_type_str; 1761 uint32_t max_num_io_queues; 1762 int rc; 1763 static int adapters_found; 1764 bool disable_meta_caching; 1765 bool wd_state = false; 1766 1767 eth_dev->dev_ops = &ena_dev_ops; 1768 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1769 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1770 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1771 1772 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1773 return 0; 1774 1775 memset(adapter, 0, sizeof(struct ena_adapter)); 1776 ena_dev = &adapter->ena_dev; 1777 1778 adapter->rte_eth_dev_data = eth_dev->data; 1779 adapter->rte_dev = eth_dev; 1780 1781 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1782 adapter->pdev = pci_dev; 1783 1784 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1785 pci_dev->addr.domain, 1786 pci_dev->addr.bus, 1787 pci_dev->addr.devid, 1788 pci_dev->addr.function); 1789 1790 intr_handle = &pci_dev->intr_handle; 1791 1792 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1793 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1794 1795 if (!adapter->regs) { 1796 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1797 ENA_REGS_BAR); 1798 return -ENXIO; 1799 } 1800 1801 ena_dev->reg_bar = adapter->regs; 1802 ena_dev->dmadev = adapter->pdev; 1803 1804 adapter->id_number = adapters_found; 1805 1806 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1807 adapter->id_number); 1808 1809 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1810 if (rc != 0) { 1811 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1812 goto err; 1813 } 1814 1815 /* device specific initialization routine */ 1816 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1817 if (rc) { 1818 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1819 goto err; 1820 } 1821 adapter->wd_state = wd_state; 1822 1823 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1824 adapter->use_large_llq_hdr); 1825 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1826 &get_feat_ctx.llq, &llq_config); 1827 if (unlikely(rc)) { 1828 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1829 return rc; 1830 } 1831 1832 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1833 queue_type_str = "Regular"; 1834 else 1835 queue_type_str = "Low latency"; 1836 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1837 1838 calc_queue_ctx.ena_dev = ena_dev; 1839 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1840 1841 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1842 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1843 adapter->use_large_llq_hdr); 1844 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1845 rc = -EFAULT; 1846 goto err_device_destroy; 1847 } 1848 1849 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1850 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1851 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1852 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1853 adapter->max_num_io_queues = max_num_io_queues; 1854 1855 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1856 disable_meta_caching = 1857 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 1858 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 1859 } else { 1860 disable_meta_caching = false; 1861 } 1862 1863 /* prepare ring structures */ 1864 ena_init_rings(adapter, disable_meta_caching); 1865 1866 ena_config_debug_area(adapter); 1867 1868 /* Set max MTU for this device */ 1869 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1870 1871 /* set device support for offloads */ 1872 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1873 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1874 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1875 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1876 adapter->offloads.rx_csum_supported = 1877 (get_feat_ctx.offload.rx_supported & 1878 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1879 1880 /* Copy MAC address and point DPDK to it */ 1881 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1882 rte_ether_addr_copy((struct rte_ether_addr *) 1883 get_feat_ctx.dev_attr.mac_addr, 1884 (struct rte_ether_addr *)adapter->mac_addr); 1885 1886 adapter->drv_stats = rte_zmalloc("adapter stats", 1887 sizeof(*adapter->drv_stats), 1888 RTE_CACHE_LINE_SIZE); 1889 if (!adapter->drv_stats) { 1890 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1891 rc = -ENOMEM; 1892 goto err_delete_debug_area; 1893 } 1894 1895 rte_spinlock_init(&adapter->admin_lock); 1896 1897 rte_intr_callback_register(intr_handle, 1898 ena_interrupt_handler_rte, 1899 adapter); 1900 rte_intr_enable(intr_handle); 1901 ena_com_set_admin_polling_mode(ena_dev, false); 1902 ena_com_admin_aenq_enable(ena_dev); 1903 1904 if (adapters_found == 0) 1905 rte_timer_subsystem_init(); 1906 rte_timer_init(&adapter->timer_wd); 1907 1908 adapters_found++; 1909 adapter->state = ENA_ADAPTER_STATE_INIT; 1910 1911 return 0; 1912 1913 err_delete_debug_area: 1914 ena_com_delete_debug_area(ena_dev); 1915 1916 err_device_destroy: 1917 ena_com_delete_host_info(ena_dev); 1918 ena_com_admin_destroy(ena_dev); 1919 1920 err: 1921 return rc; 1922 } 1923 1924 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1925 { 1926 struct ena_adapter *adapter = eth_dev->data->dev_private; 1927 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1928 1929 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1930 return; 1931 1932 ena_com_set_admin_running_state(ena_dev, false); 1933 1934 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1935 ena_close(eth_dev); 1936 1937 ena_com_delete_debug_area(ena_dev); 1938 ena_com_delete_host_info(ena_dev); 1939 1940 ena_com_abort_admin_commands(ena_dev); 1941 ena_com_wait_for_abort_completion(ena_dev); 1942 ena_com_admin_destroy(ena_dev); 1943 ena_com_mmio_reg_read_request_destroy(ena_dev); 1944 1945 adapter->state = ENA_ADAPTER_STATE_FREE; 1946 } 1947 1948 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1949 { 1950 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1951 return 0; 1952 1953 ena_destroy_device(eth_dev); 1954 1955 eth_dev->dev_ops = NULL; 1956 eth_dev->rx_pkt_burst = NULL; 1957 eth_dev->tx_pkt_burst = NULL; 1958 eth_dev->tx_pkt_prepare = NULL; 1959 1960 return 0; 1961 } 1962 1963 static int ena_dev_configure(struct rte_eth_dev *dev) 1964 { 1965 struct ena_adapter *adapter = dev->data->dev_private; 1966 1967 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1968 1969 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1970 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1971 return 0; 1972 } 1973 1974 static void ena_init_rings(struct ena_adapter *adapter, 1975 bool disable_meta_caching) 1976 { 1977 size_t i; 1978 1979 for (i = 0; i < adapter->max_num_io_queues; i++) { 1980 struct ena_ring *ring = &adapter->tx_ring[i]; 1981 1982 ring->configured = 0; 1983 ring->type = ENA_RING_TYPE_TX; 1984 ring->adapter = adapter; 1985 ring->id = i; 1986 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1987 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1988 ring->sgl_size = adapter->max_tx_sgl_size; 1989 ring->disable_meta_caching = disable_meta_caching; 1990 } 1991 1992 for (i = 0; i < adapter->max_num_io_queues; i++) { 1993 struct ena_ring *ring = &adapter->rx_ring[i]; 1994 1995 ring->configured = 0; 1996 ring->type = ENA_RING_TYPE_RX; 1997 ring->adapter = adapter; 1998 ring->id = i; 1999 ring->sgl_size = adapter->max_rx_sgl_size; 2000 } 2001 } 2002 2003 static int ena_infos_get(struct rte_eth_dev *dev, 2004 struct rte_eth_dev_info *dev_info) 2005 { 2006 struct ena_adapter *adapter; 2007 struct ena_com_dev *ena_dev; 2008 uint64_t rx_feat = 0, tx_feat = 0; 2009 2010 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 2011 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 2012 adapter = dev->data->dev_private; 2013 2014 ena_dev = &adapter->ena_dev; 2015 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 2016 2017 dev_info->speed_capa = 2018 ETH_LINK_SPEED_1G | 2019 ETH_LINK_SPEED_2_5G | 2020 ETH_LINK_SPEED_5G | 2021 ETH_LINK_SPEED_10G | 2022 ETH_LINK_SPEED_25G | 2023 ETH_LINK_SPEED_40G | 2024 ETH_LINK_SPEED_50G | 2025 ETH_LINK_SPEED_100G; 2026 2027 /* Set Tx & Rx features available for device */ 2028 if (adapter->offloads.tso4_supported) 2029 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 2030 2031 if (adapter->offloads.tx_csum_supported) 2032 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 2033 DEV_TX_OFFLOAD_UDP_CKSUM | 2034 DEV_TX_OFFLOAD_TCP_CKSUM; 2035 2036 if (adapter->offloads.rx_csum_supported) 2037 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 2038 DEV_RX_OFFLOAD_UDP_CKSUM | 2039 DEV_RX_OFFLOAD_TCP_CKSUM; 2040 2041 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2042 2043 /* Inform framework about available features */ 2044 dev_info->rx_offload_capa = rx_feat; 2045 dev_info->rx_queue_offload_capa = rx_feat; 2046 dev_info->tx_offload_capa = tx_feat; 2047 dev_info->tx_queue_offload_capa = tx_feat; 2048 2049 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2050 ETH_RSS_UDP; 2051 2052 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2053 dev_info->max_rx_pktlen = adapter->max_mtu; 2054 dev_info->max_mac_addrs = 1; 2055 2056 dev_info->max_rx_queues = adapter->max_num_io_queues; 2057 dev_info->max_tx_queues = adapter->max_num_io_queues; 2058 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2059 2060 adapter->tx_supported_offloads = tx_feat; 2061 adapter->rx_supported_offloads = rx_feat; 2062 2063 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2064 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2065 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2066 adapter->max_rx_sgl_size); 2067 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2068 adapter->max_rx_sgl_size); 2069 2070 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2071 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2072 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2073 adapter->max_tx_sgl_size); 2074 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2075 adapter->max_tx_sgl_size); 2076 2077 return 0; 2078 } 2079 2080 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 2081 { 2082 mbuf->data_len = len; 2083 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2084 mbuf->refcnt = 1; 2085 mbuf->next = NULL; 2086 } 2087 2088 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 2089 struct ena_com_rx_buf_info *ena_bufs, 2090 uint32_t descs, 2091 uint16_t *next_to_clean, 2092 uint8_t offset) 2093 { 2094 struct rte_mbuf *mbuf; 2095 struct rte_mbuf *mbuf_head; 2096 struct ena_rx_buffer *rx_info; 2097 int rc; 2098 uint16_t ntc, len, req_id, buf = 0; 2099 2100 if (unlikely(descs == 0)) 2101 return NULL; 2102 2103 ntc = *next_to_clean; 2104 2105 len = ena_bufs[buf].len; 2106 req_id = ena_bufs[buf].req_id; 2107 if (unlikely(validate_rx_req_id(rx_ring, req_id))) 2108 return NULL; 2109 2110 rx_info = &rx_ring->rx_buffer_info[req_id]; 2111 2112 mbuf = rx_info->mbuf; 2113 RTE_ASSERT(mbuf != NULL); 2114 2115 ena_init_rx_mbuf(mbuf, len); 2116 2117 /* Fill the mbuf head with the data specific for 1st segment. */ 2118 mbuf_head = mbuf; 2119 mbuf_head->nb_segs = descs; 2120 mbuf_head->port = rx_ring->port_id; 2121 mbuf_head->pkt_len = len; 2122 mbuf_head->data_off += offset; 2123 2124 rx_info->mbuf = NULL; 2125 rx_ring->empty_rx_reqs[ntc] = req_id; 2126 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2127 2128 while (--descs) { 2129 ++buf; 2130 len = ena_bufs[buf].len; 2131 req_id = ena_bufs[buf].req_id; 2132 if (unlikely(validate_rx_req_id(rx_ring, req_id))) { 2133 rte_mbuf_raw_free(mbuf_head); 2134 return NULL; 2135 } 2136 2137 rx_info = &rx_ring->rx_buffer_info[req_id]; 2138 RTE_ASSERT(rx_info->mbuf != NULL); 2139 2140 if (unlikely(len == 0)) { 2141 /* 2142 * Some devices can pass descriptor with the length 0. 2143 * To avoid confusion, the PMD is simply putting the 2144 * descriptor back, as it was never used. We'll avoid 2145 * mbuf allocation that way. 2146 */ 2147 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2148 rx_info->mbuf, req_id); 2149 if (unlikely(rc != 0)) { 2150 /* Free the mbuf in case of an error. */ 2151 rte_mbuf_raw_free(rx_info->mbuf); 2152 } else { 2153 /* 2154 * If there was no error, just exit the loop as 2155 * 0 length descriptor is always the last one. 2156 */ 2157 break; 2158 } 2159 } else { 2160 /* Create an mbuf chain. */ 2161 mbuf->next = rx_info->mbuf; 2162 mbuf = mbuf->next; 2163 2164 ena_init_rx_mbuf(mbuf, len); 2165 mbuf_head->pkt_len += len; 2166 } 2167 2168 /* 2169 * Mark the descriptor as depleted and perform necessary 2170 * cleanup. 2171 * This code will execute in two cases: 2172 * 1. Descriptor len was greater than 0 - normal situation. 2173 * 2. Descriptor len was 0 and we failed to add the descriptor 2174 * to the device. In that situation, we should try to add 2175 * the mbuf again in the populate routine and mark the 2176 * descriptor as used up by the device. 2177 */ 2178 rx_info->mbuf = NULL; 2179 rx_ring->empty_rx_reqs[ntc] = req_id; 2180 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2181 } 2182 2183 *next_to_clean = ntc; 2184 2185 return mbuf_head; 2186 } 2187 2188 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2189 uint16_t nb_pkts) 2190 { 2191 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2192 unsigned int free_queue_entries; 2193 unsigned int refill_threshold; 2194 uint16_t next_to_clean = rx_ring->next_to_clean; 2195 uint16_t descs_in_use; 2196 struct rte_mbuf *mbuf; 2197 uint16_t completed; 2198 struct ena_com_rx_ctx ena_rx_ctx; 2199 int i, rc = 0; 2200 2201 /* Check adapter state */ 2202 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2203 PMD_DRV_LOG(ALERT, 2204 "Trying to receive pkts while device is NOT running\n"); 2205 return 0; 2206 } 2207 2208 descs_in_use = rx_ring->ring_size - 2209 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2210 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2211 2212 for (completed = 0; completed < nb_pkts; completed++) { 2213 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2214 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2215 ena_rx_ctx.descs = 0; 2216 ena_rx_ctx.pkt_offset = 0; 2217 /* receive packet context */ 2218 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2219 rx_ring->ena_com_io_sq, 2220 &ena_rx_ctx); 2221 if (unlikely(rc)) { 2222 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2223 rx_ring->adapter->reset_reason = 2224 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2225 rx_ring->adapter->trigger_reset = true; 2226 ++rx_ring->rx_stats.bad_desc_num; 2227 return 0; 2228 } 2229 2230 mbuf = ena_rx_mbuf(rx_ring, 2231 ena_rx_ctx.ena_bufs, 2232 ena_rx_ctx.descs, 2233 &next_to_clean, 2234 ena_rx_ctx.pkt_offset); 2235 if (unlikely(mbuf == NULL)) { 2236 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2237 rx_ring->empty_rx_reqs[next_to_clean] = 2238 rx_ring->ena_bufs[i].req_id; 2239 next_to_clean = ENA_IDX_NEXT_MASKED( 2240 next_to_clean, rx_ring->size_mask); 2241 } 2242 break; 2243 } 2244 2245 /* fill mbuf attributes if any */ 2246 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); 2247 2248 if (unlikely(mbuf->ol_flags & 2249 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2250 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2251 ++rx_ring->rx_stats.bad_csum; 2252 } 2253 2254 mbuf->hash.rss = ena_rx_ctx.hash; 2255 2256 rx_pkts[completed] = mbuf; 2257 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2258 } 2259 2260 rx_ring->rx_stats.cnt += completed; 2261 rx_ring->next_to_clean = next_to_clean; 2262 2263 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2264 refill_threshold = 2265 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2266 (unsigned int)ENA_REFILL_THRESH_PACKET); 2267 2268 /* Burst refill to save doorbells, memory barriers, const interval */ 2269 if (free_queue_entries > refill_threshold) { 2270 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2271 ena_populate_rx_queue(rx_ring, free_queue_entries); 2272 } 2273 2274 return completed; 2275 } 2276 2277 static uint16_t 2278 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2279 uint16_t nb_pkts) 2280 { 2281 int32_t ret; 2282 uint32_t i; 2283 struct rte_mbuf *m; 2284 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2285 struct rte_ipv4_hdr *ip_hdr; 2286 uint64_t ol_flags; 2287 uint16_t frag_field; 2288 2289 for (i = 0; i != nb_pkts; i++) { 2290 m = tx_pkts[i]; 2291 ol_flags = m->ol_flags; 2292 2293 if (!(ol_flags & PKT_TX_IPV4)) 2294 continue; 2295 2296 /* If there was not L2 header length specified, assume it is 2297 * length of the ethernet header. 2298 */ 2299 if (unlikely(m->l2_len == 0)) 2300 m->l2_len = sizeof(struct rte_ether_hdr); 2301 2302 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2303 m->l2_len); 2304 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2305 2306 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2307 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2308 2309 /* If IPv4 header has DF flag enabled and TSO support is 2310 * disabled, partial chcecksum should not be calculated. 2311 */ 2312 if (!tx_ring->adapter->offloads.tso4_supported) 2313 continue; 2314 } 2315 2316 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2317 (ol_flags & PKT_TX_L4_MASK) == 2318 PKT_TX_SCTP_CKSUM) { 2319 rte_errno = ENOTSUP; 2320 return i; 2321 } 2322 2323 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2324 ret = rte_validate_tx_offload(m); 2325 if (ret != 0) { 2326 rte_errno = -ret; 2327 return i; 2328 } 2329 #endif 2330 2331 /* In case we are supposed to TSO and have DF not set (DF=0) 2332 * hardware must be provided with partial checksum, otherwise 2333 * it will take care of necessary calculations. 2334 */ 2335 2336 ret = rte_net_intel_cksum_flags_prepare(m, 2337 ol_flags & ~PKT_TX_TCP_SEG); 2338 if (ret != 0) { 2339 rte_errno = -ret; 2340 return i; 2341 } 2342 } 2343 2344 return i; 2345 } 2346 2347 static void ena_update_hints(struct ena_adapter *adapter, 2348 struct ena_admin_ena_hw_hints *hints) 2349 { 2350 if (hints->admin_completion_tx_timeout) 2351 adapter->ena_dev.admin_queue.completion_timeout = 2352 hints->admin_completion_tx_timeout * 1000; 2353 2354 if (hints->mmio_read_timeout) 2355 /* convert to usec */ 2356 adapter->ena_dev.mmio_read.reg_read_to = 2357 hints->mmio_read_timeout * 1000; 2358 2359 if (hints->driver_watchdog_timeout) { 2360 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2361 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2362 else 2363 // Convert msecs to ticks 2364 adapter->keep_alive_timeout = 2365 (hints->driver_watchdog_timeout * 2366 rte_get_timer_hz()) / 1000; 2367 } 2368 } 2369 2370 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2371 struct rte_mbuf *mbuf) 2372 { 2373 struct ena_com_dev *ena_dev; 2374 int num_segments, header_len, rc; 2375 2376 ena_dev = &tx_ring->adapter->ena_dev; 2377 num_segments = mbuf->nb_segs; 2378 header_len = mbuf->data_len; 2379 2380 if (likely(num_segments < tx_ring->sgl_size)) 2381 return 0; 2382 2383 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2384 (num_segments == tx_ring->sgl_size) && 2385 (header_len < tx_ring->tx_max_header_size)) 2386 return 0; 2387 2388 ++tx_ring->tx_stats.linearize; 2389 rc = rte_pktmbuf_linearize(mbuf); 2390 if (unlikely(rc)) { 2391 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2392 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2393 ++tx_ring->tx_stats.linearize_failed; 2394 return rc; 2395 } 2396 2397 return rc; 2398 } 2399 2400 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2401 struct ena_tx_buffer *tx_info, 2402 struct rte_mbuf *mbuf, 2403 void **push_header, 2404 uint16_t *header_len) 2405 { 2406 struct ena_com_buf *ena_buf; 2407 uint16_t delta, seg_len, push_len; 2408 2409 delta = 0; 2410 seg_len = mbuf->data_len; 2411 2412 tx_info->mbuf = mbuf; 2413 ena_buf = tx_info->bufs; 2414 2415 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2416 /* 2417 * Tx header might be (and will be in most cases) smaller than 2418 * tx_max_header_size. But it's not an issue to send more data 2419 * to the device, than actually needed if the mbuf size is 2420 * greater than tx_max_header_size. 2421 */ 2422 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2423 *header_len = push_len; 2424 2425 if (likely(push_len <= seg_len)) { 2426 /* If the push header is in the single segment, then 2427 * just point it to the 1st mbuf data. 2428 */ 2429 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2430 } else { 2431 /* If the push header lays in the several segments, copy 2432 * it to the intermediate buffer. 2433 */ 2434 rte_pktmbuf_read(mbuf, 0, push_len, 2435 tx_ring->push_buf_intermediate_buf); 2436 *push_header = tx_ring->push_buf_intermediate_buf; 2437 delta = push_len - seg_len; 2438 } 2439 } else { 2440 *push_header = NULL; 2441 *header_len = 0; 2442 push_len = 0; 2443 } 2444 2445 /* Process first segment taking into consideration pushed header */ 2446 if (seg_len > push_len) { 2447 ena_buf->paddr = mbuf->buf_iova + 2448 mbuf->data_off + 2449 push_len; 2450 ena_buf->len = seg_len - push_len; 2451 ena_buf++; 2452 tx_info->num_of_bufs++; 2453 } 2454 2455 while ((mbuf = mbuf->next) != NULL) { 2456 seg_len = mbuf->data_len; 2457 2458 /* Skip mbufs if whole data is pushed as a header */ 2459 if (unlikely(delta > seg_len)) { 2460 delta -= seg_len; 2461 continue; 2462 } 2463 2464 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2465 ena_buf->len = seg_len - delta; 2466 ena_buf++; 2467 tx_info->num_of_bufs++; 2468 2469 delta = 0; 2470 } 2471 } 2472 2473 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 2474 { 2475 struct ena_tx_buffer *tx_info; 2476 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 2477 uint16_t next_to_use; 2478 uint16_t header_len; 2479 uint16_t req_id; 2480 void *push_header; 2481 int nb_hw_desc; 2482 int rc; 2483 2484 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2485 if (unlikely(rc)) 2486 return rc; 2487 2488 next_to_use = tx_ring->next_to_use; 2489 2490 req_id = tx_ring->empty_tx_reqs[next_to_use]; 2491 tx_info = &tx_ring->tx_buffer_info[req_id]; 2492 tx_info->num_of_bufs = 0; 2493 2494 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 2495 2496 ena_tx_ctx.ena_bufs = tx_info->bufs; 2497 ena_tx_ctx.push_header = push_header; 2498 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2499 ena_tx_ctx.req_id = req_id; 2500 ena_tx_ctx.header_len = header_len; 2501 2502 /* Set Tx offloads flags, if applicable */ 2503 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 2504 tx_ring->disable_meta_caching); 2505 2506 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2507 &ena_tx_ctx))) { 2508 PMD_DRV_LOG(DEBUG, 2509 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2510 tx_ring->id); 2511 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2512 } 2513 2514 /* prepare the packet's descriptors to dma engine */ 2515 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2516 &nb_hw_desc); 2517 if (unlikely(rc)) { 2518 ++tx_ring->tx_stats.prepare_ctx_err; 2519 return rc; 2520 } 2521 2522 tx_info->tx_descs = nb_hw_desc; 2523 2524 tx_ring->tx_stats.cnt++; 2525 tx_ring->tx_stats.bytes += mbuf->pkt_len; 2526 2527 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 2528 tx_ring->size_mask); 2529 2530 return 0; 2531 } 2532 2533 static void ena_tx_cleanup(struct ena_ring *tx_ring) 2534 { 2535 unsigned int cleanup_budget; 2536 unsigned int total_tx_descs = 0; 2537 uint16_t next_to_clean = tx_ring->next_to_clean; 2538 2539 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2540 (unsigned int)ENA_REFILL_THRESH_PACKET); 2541 2542 while (likely(total_tx_descs < cleanup_budget)) { 2543 struct rte_mbuf *mbuf; 2544 struct ena_tx_buffer *tx_info; 2545 uint16_t req_id; 2546 2547 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 2548 break; 2549 2550 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 2551 break; 2552 2553 /* Get Tx info & store how many descs were processed */ 2554 tx_info = &tx_ring->tx_buffer_info[req_id]; 2555 2556 mbuf = tx_info->mbuf; 2557 rte_pktmbuf_free(mbuf); 2558 2559 tx_info->mbuf = NULL; 2560 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 2561 2562 total_tx_descs += tx_info->tx_descs; 2563 2564 /* Put back descriptor to the ring for reuse */ 2565 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 2566 tx_ring->size_mask); 2567 } 2568 2569 if (likely(total_tx_descs > 0)) { 2570 /* acknowledge completion of sent packets */ 2571 tx_ring->next_to_clean = next_to_clean; 2572 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2573 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2574 } 2575 } 2576 2577 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2578 uint16_t nb_pkts) 2579 { 2580 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2581 uint16_t sent_idx = 0; 2582 2583 /* Check adapter state */ 2584 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2585 PMD_DRV_LOG(ALERT, 2586 "Trying to xmit pkts while device is NOT running\n"); 2587 return 0; 2588 } 2589 2590 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), 2591 nb_pkts); 2592 2593 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2594 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 2595 break; 2596 2597 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 2598 tx_ring->size_mask)]); 2599 } 2600 2601 tx_ring->tx_stats.available_desc = 2602 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2603 2604 /* If there are ready packets to be xmitted... */ 2605 if (sent_idx > 0) { 2606 /* ...let HW do its best :-) */ 2607 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2608 tx_ring->tx_stats.doorbells++; 2609 } 2610 2611 ena_tx_cleanup(tx_ring); 2612 2613 tx_ring->tx_stats.available_desc = 2614 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2615 tx_ring->tx_stats.tx_poll++; 2616 2617 return sent_idx; 2618 } 2619 2620 int ena_copy_eni_stats(struct ena_adapter *adapter) 2621 { 2622 struct ena_admin_eni_stats admin_eni_stats; 2623 int rc; 2624 2625 rte_spinlock_lock(&adapter->admin_lock); 2626 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats); 2627 rte_spinlock_unlock(&adapter->admin_lock); 2628 if (rc != 0) { 2629 if (rc == ENA_COM_UNSUPPORTED) { 2630 PMD_DRV_LOG(DEBUG, 2631 "Retrieving ENI metrics is not supported.\n"); 2632 } else { 2633 PMD_DRV_LOG(WARNING, 2634 "Failed to get ENI metrics: %d\n", rc); 2635 } 2636 return rc; 2637 } 2638 2639 rte_memcpy(&adapter->eni_stats, &admin_eni_stats, 2640 sizeof(struct ena_stats_eni)); 2641 2642 return 0; 2643 } 2644 2645 /** 2646 * DPDK callback to retrieve names of extended device statistics 2647 * 2648 * @param dev 2649 * Pointer to Ethernet device structure. 2650 * @param[out] xstats_names 2651 * Buffer to insert names into. 2652 * @param n 2653 * Number of names. 2654 * 2655 * @return 2656 * Number of xstats names. 2657 */ 2658 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2659 struct rte_eth_xstat_name *xstats_names, 2660 unsigned int n) 2661 { 2662 unsigned int xstats_count = ena_xstats_calc_num(dev); 2663 unsigned int stat, i, count = 0; 2664 2665 if (n < xstats_count || !xstats_names) 2666 return xstats_count; 2667 2668 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2669 strcpy(xstats_names[count].name, 2670 ena_stats_global_strings[stat].name); 2671 2672 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) 2673 strcpy(xstats_names[count].name, 2674 ena_stats_eni_strings[stat].name); 2675 2676 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2677 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2678 snprintf(xstats_names[count].name, 2679 sizeof(xstats_names[count].name), 2680 "rx_q%d_%s", i, 2681 ena_stats_rx_strings[stat].name); 2682 2683 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2684 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2685 snprintf(xstats_names[count].name, 2686 sizeof(xstats_names[count].name), 2687 "tx_q%d_%s", i, 2688 ena_stats_tx_strings[stat].name); 2689 2690 return xstats_count; 2691 } 2692 2693 /** 2694 * DPDK callback to get extended device statistics. 2695 * 2696 * @param dev 2697 * Pointer to Ethernet device structure. 2698 * @param[out] stats 2699 * Stats table output buffer. 2700 * @param n 2701 * The size of the stats table. 2702 * 2703 * @return 2704 * Number of xstats on success, negative on failure. 2705 */ 2706 static int ena_xstats_get(struct rte_eth_dev *dev, 2707 struct rte_eth_xstat *xstats, 2708 unsigned int n) 2709 { 2710 struct ena_adapter *adapter = dev->data->dev_private; 2711 unsigned int xstats_count = ena_xstats_calc_num(dev); 2712 unsigned int stat, i, count = 0; 2713 int stat_offset; 2714 void *stats_begin; 2715 2716 if (n < xstats_count) 2717 return xstats_count; 2718 2719 if (!xstats) 2720 return 0; 2721 2722 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2723 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2724 stats_begin = &adapter->dev_stats; 2725 2726 xstats[count].id = count; 2727 xstats[count].value = *((uint64_t *) 2728 ((char *)stats_begin + stat_offset)); 2729 } 2730 2731 /* Even if the function below fails, we should copy previous (or initial 2732 * values) to keep structure of rte_eth_xstat consistent. 2733 */ 2734 ena_copy_eni_stats(adapter); 2735 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) { 2736 stat_offset = ena_stats_eni_strings[stat].stat_offset; 2737 stats_begin = &adapter->eni_stats; 2738 2739 xstats[count].id = count; 2740 xstats[count].value = *((uint64_t *) 2741 ((char *)stats_begin + stat_offset)); 2742 } 2743 2744 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2745 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2746 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2747 stats_begin = &adapter->rx_ring[i].rx_stats; 2748 2749 xstats[count].id = count; 2750 xstats[count].value = *((uint64_t *) 2751 ((char *)stats_begin + stat_offset)); 2752 } 2753 } 2754 2755 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2756 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2757 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2758 stats_begin = &adapter->tx_ring[i].rx_stats; 2759 2760 xstats[count].id = count; 2761 xstats[count].value = *((uint64_t *) 2762 ((char *)stats_begin + stat_offset)); 2763 } 2764 } 2765 2766 return count; 2767 } 2768 2769 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2770 const uint64_t *ids, 2771 uint64_t *values, 2772 unsigned int n) 2773 { 2774 struct ena_adapter *adapter = dev->data->dev_private; 2775 uint64_t id; 2776 uint64_t rx_entries, tx_entries; 2777 unsigned int i; 2778 int qid; 2779 int valid = 0; 2780 bool was_eni_copied = false; 2781 2782 for (i = 0; i < n; ++i) { 2783 id = ids[i]; 2784 /* Check if id belongs to global statistics */ 2785 if (id < ENA_STATS_ARRAY_GLOBAL) { 2786 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2787 ++valid; 2788 continue; 2789 } 2790 2791 /* Check if id belongs to ENI statistics */ 2792 id -= ENA_STATS_ARRAY_GLOBAL; 2793 if (id < ENA_STATS_ARRAY_ENI) { 2794 /* Avoid reading ENI stats multiple times in a single 2795 * function call, as it requires communication with the 2796 * admin queue. 2797 */ 2798 if (!was_eni_copied) { 2799 was_eni_copied = true; 2800 ena_copy_eni_stats(adapter); 2801 } 2802 values[i] = *((uint64_t *)&adapter->eni_stats + id); 2803 ++valid; 2804 continue; 2805 } 2806 2807 /* Check if id belongs to rx queue statistics */ 2808 id -= ENA_STATS_ARRAY_ENI; 2809 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2810 if (id < rx_entries) { 2811 qid = id % dev->data->nb_rx_queues; 2812 id /= dev->data->nb_rx_queues; 2813 values[i] = *((uint64_t *) 2814 &adapter->rx_ring[qid].rx_stats + id); 2815 ++valid; 2816 continue; 2817 } 2818 /* Check if id belongs to rx queue statistics */ 2819 id -= rx_entries; 2820 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2821 if (id < tx_entries) { 2822 qid = id % dev->data->nb_tx_queues; 2823 id /= dev->data->nb_tx_queues; 2824 values[i] = *((uint64_t *) 2825 &adapter->tx_ring[qid].tx_stats + id); 2826 ++valid; 2827 continue; 2828 } 2829 } 2830 2831 return valid; 2832 } 2833 2834 static int ena_process_bool_devarg(const char *key, 2835 const char *value, 2836 void *opaque) 2837 { 2838 struct ena_adapter *adapter = opaque; 2839 bool bool_value; 2840 2841 /* Parse the value. */ 2842 if (strcmp(value, "1") == 0) { 2843 bool_value = true; 2844 } else if (strcmp(value, "0") == 0) { 2845 bool_value = false; 2846 } else { 2847 PMD_INIT_LOG(ERR, 2848 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2849 value, key); 2850 return -EINVAL; 2851 } 2852 2853 /* Now, assign it to the proper adapter field. */ 2854 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) 2855 adapter->use_large_llq_hdr = bool_value; 2856 2857 return 0; 2858 } 2859 2860 static int ena_parse_devargs(struct ena_adapter *adapter, 2861 struct rte_devargs *devargs) 2862 { 2863 static const char * const allowed_args[] = { 2864 ENA_DEVARG_LARGE_LLQ_HDR, 2865 }; 2866 struct rte_kvargs *kvlist; 2867 int rc; 2868 2869 if (devargs == NULL) 2870 return 0; 2871 2872 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2873 if (kvlist == NULL) { 2874 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2875 devargs->args); 2876 return -EINVAL; 2877 } 2878 2879 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2880 ena_process_bool_devarg, adapter); 2881 2882 rte_kvargs_free(kvlist); 2883 2884 return rc; 2885 } 2886 2887 /********************************************************************* 2888 * PMD configuration 2889 *********************************************************************/ 2890 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2891 struct rte_pci_device *pci_dev) 2892 { 2893 return rte_eth_dev_pci_generic_probe(pci_dev, 2894 sizeof(struct ena_adapter), eth_ena_dev_init); 2895 } 2896 2897 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2898 { 2899 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2900 } 2901 2902 static struct rte_pci_driver rte_ena_pmd = { 2903 .id_table = pci_id_ena_map, 2904 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2905 RTE_PCI_DRV_WC_ACTIVATE, 2906 .probe = eth_ena_pci_probe, 2907 .remove = eth_ena_pci_remove, 2908 }; 2909 2910 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2911 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2912 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2913 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2914 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE); 2915 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE); 2916 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2917 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE); 2918 #endif 2919 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2920 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE); 2921 #endif 2922 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2923 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE); 2924 #endif 2925 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2926 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); 2927 #endif 2928 2929 /****************************************************************************** 2930 ******************************** AENQ Handlers ******************************* 2931 *****************************************************************************/ 2932 static void ena_update_on_link_change(void *adapter_data, 2933 struct ena_admin_aenq_entry *aenq_e) 2934 { 2935 struct rte_eth_dev *eth_dev; 2936 struct ena_adapter *adapter; 2937 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2938 uint32_t status; 2939 2940 adapter = adapter_data; 2941 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2942 eth_dev = adapter->rte_dev; 2943 2944 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2945 adapter->link_status = status; 2946 2947 ena_link_update(eth_dev, 0); 2948 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2949 } 2950 2951 static void ena_notification(void *data, 2952 struct ena_admin_aenq_entry *aenq_e) 2953 { 2954 struct ena_adapter *adapter = data; 2955 struct ena_admin_ena_hw_hints *hints; 2956 2957 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2958 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2959 aenq_e->aenq_common_desc.group, 2960 ENA_ADMIN_NOTIFICATION); 2961 2962 switch (aenq_e->aenq_common_desc.syndrom) { 2963 case ENA_ADMIN_UPDATE_HINTS: 2964 hints = (struct ena_admin_ena_hw_hints *) 2965 (&aenq_e->inline_data_w4); 2966 ena_update_hints(adapter, hints); 2967 break; 2968 default: 2969 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2970 aenq_e->aenq_common_desc.syndrom); 2971 } 2972 } 2973 2974 static void ena_keep_alive(void *adapter_data, 2975 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2976 { 2977 struct ena_adapter *adapter = adapter_data; 2978 struct ena_admin_aenq_keep_alive_desc *desc; 2979 uint64_t rx_drops; 2980 uint64_t tx_drops; 2981 2982 adapter->timestamp_wd = rte_get_timer_cycles(); 2983 2984 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2985 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2986 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 2987 2988 adapter->drv_stats->rx_drops = rx_drops; 2989 adapter->dev_stats.tx_drops = tx_drops; 2990 } 2991 2992 /** 2993 * This handler will called for unknown event group or unimplemented handlers 2994 **/ 2995 static void unimplemented_aenq_handler(__rte_unused void *data, 2996 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2997 { 2998 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 2999 "unimplemented handler\n"); 3000 } 3001 3002 static struct ena_aenq_handlers aenq_handlers = { 3003 .handlers = { 3004 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3005 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3006 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 3007 }, 3008 .unimplemented_handler = unimplemented_aenq_handler 3009 }; 3010