1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 1 31 #define DRV_MODULE_VER_SUBMINOR 0 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 40 41 #define GET_L4_HDR_LEN(mbuf) \ 42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 44 45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 47 #define ENA_HASH_KEY_SIZE 40 48 #define ETH_GSTRING_LEN 32 49 50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 51 52 #define ENA_MIN_RING_DESC 128 53 54 enum ethtool_stringset { 55 ETH_SS_TEST = 0, 56 ETH_SS_STATS, 57 }; 58 59 struct ena_stats { 60 char name[ETH_GSTRING_LEN]; 61 int stat_offset; 62 }; 63 64 #define ENA_STAT_ENTRY(stat, stat_type) { \ 65 .name = #stat, \ 66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 67 } 68 69 #define ENA_STAT_RX_ENTRY(stat) \ 70 ENA_STAT_ENTRY(stat, rx) 71 72 #define ENA_STAT_TX_ENTRY(stat) \ 73 ENA_STAT_ENTRY(stat, tx) 74 75 #define ENA_STAT_ENI_ENTRY(stat) \ 76 ENA_STAT_ENTRY(stat, eni) 77 78 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 79 ENA_STAT_ENTRY(stat, dev) 80 81 /* Device arguments */ 82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 83 84 /* 85 * Each rte_memzone should have unique name. 86 * To satisfy it, count number of allocation and add it to name. 87 */ 88 rte_atomic32_t ena_alloc_cnt; 89 90 static const struct ena_stats ena_stats_global_strings[] = { 91 ENA_STAT_GLOBAL_ENTRY(wd_expired), 92 ENA_STAT_GLOBAL_ENTRY(dev_start), 93 ENA_STAT_GLOBAL_ENTRY(dev_stop), 94 ENA_STAT_GLOBAL_ENTRY(tx_drops), 95 }; 96 97 static const struct ena_stats ena_stats_eni_strings[] = { 98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded), 99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded), 100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded), 101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded), 102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded), 103 }; 104 105 static const struct ena_stats ena_stats_tx_strings[] = { 106 ENA_STAT_TX_ENTRY(cnt), 107 ENA_STAT_TX_ENTRY(bytes), 108 ENA_STAT_TX_ENTRY(prepare_ctx_err), 109 ENA_STAT_TX_ENTRY(linearize), 110 ENA_STAT_TX_ENTRY(linearize_failed), 111 ENA_STAT_TX_ENTRY(tx_poll), 112 ENA_STAT_TX_ENTRY(doorbells), 113 ENA_STAT_TX_ENTRY(bad_req_id), 114 ENA_STAT_TX_ENTRY(available_desc), 115 }; 116 117 static const struct ena_stats ena_stats_rx_strings[] = { 118 ENA_STAT_RX_ENTRY(cnt), 119 ENA_STAT_RX_ENTRY(bytes), 120 ENA_STAT_RX_ENTRY(refill_partial), 121 ENA_STAT_RX_ENTRY(bad_csum), 122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 123 ENA_STAT_RX_ENTRY(bad_desc_num), 124 ENA_STAT_RX_ENTRY(bad_req_id), 125 }; 126 127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings) 129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 131 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 133 DEV_TX_OFFLOAD_UDP_CKSUM |\ 134 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 135 DEV_TX_OFFLOAD_TCP_TSO) 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 137 PKT_TX_IP_CKSUM |\ 138 PKT_TX_TCP_SEG) 139 140 /** Vendor ID used by Amazon devices */ 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F 142 /** Amazon devices */ 143 #define PCI_DEVICE_ID_ENA_VF 0xEC20 144 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 145 146 #define ENA_TX_OFFLOAD_MASK (\ 147 PKT_TX_L4_MASK | \ 148 PKT_TX_IPV6 | \ 149 PKT_TX_IPV4 | \ 150 PKT_TX_IP_CKSUM | \ 151 PKT_TX_TCP_SEG) 152 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 155 156 static const struct rte_pci_id pci_id_ena_map[] = { 157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 159 { .device_id = 0 }, 160 }; 161 162 static struct ena_aenq_handlers aenq_handlers; 163 164 static int ena_device_init(struct ena_com_dev *ena_dev, 165 struct ena_com_dev_get_features_ctx *get_feat_ctx, 166 bool *wd_state); 167 static int ena_dev_configure(struct rte_eth_dev *dev); 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 169 struct ena_tx_buffer *tx_info, 170 struct rte_mbuf *mbuf, 171 void **push_header, 172 uint16_t *header_len); 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 174 static void ena_tx_cleanup(struct ena_ring *tx_ring); 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 176 uint16_t nb_pkts); 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 178 uint16_t nb_pkts); 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 180 uint16_t nb_desc, unsigned int socket_id, 181 const struct rte_eth_txconf *tx_conf); 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 183 uint16_t nb_desc, unsigned int socket_id, 184 const struct rte_eth_rxconf *rx_conf, 185 struct rte_mempool *mp); 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 188 struct ena_com_rx_buf_info *ena_bufs, 189 uint32_t descs, 190 uint16_t *next_to_clean, 191 uint8_t offset); 192 static uint16_t eth_ena_recv_pkts(void *rx_queue, 193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 195 struct rte_mbuf *mbuf, uint16_t id); 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 197 static void ena_init_rings(struct ena_adapter *adapter, 198 bool disable_meta_caching); 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 200 static int ena_start(struct rte_eth_dev *dev); 201 static void ena_stop(struct rte_eth_dev *dev); 202 static int ena_close(struct rte_eth_dev *dev); 203 static int ena_dev_reset(struct rte_eth_dev *dev); 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 207 static void ena_rx_queue_release(void *queue); 208 static void ena_tx_queue_release(void *queue); 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 211 static int ena_link_update(struct rte_eth_dev *dev, 212 int wait_to_complete); 213 static int ena_create_io_queue(struct ena_ring *ring); 214 static void ena_queue_stop(struct ena_ring *ring); 215 static void ena_queue_stop_all(struct rte_eth_dev *dev, 216 enum ena_ring_type ring_type); 217 static int ena_queue_start(struct ena_ring *ring); 218 static int ena_queue_start_all(struct rte_eth_dev *dev, 219 enum ena_ring_type ring_type); 220 static void ena_stats_restart(struct rte_eth_dev *dev); 221 static int ena_infos_get(struct rte_eth_dev *dev, 222 struct rte_eth_dev_info *dev_info); 223 static int ena_rss_reta_update(struct rte_eth_dev *dev, 224 struct rte_eth_rss_reta_entry64 *reta_conf, 225 uint16_t reta_size); 226 static int ena_rss_reta_query(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 static void ena_interrupt_handler_rte(void *cb_arg); 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 233 static int ena_xstats_get_names(struct rte_eth_dev *dev, 234 struct rte_eth_xstat_name *xstats_names, 235 unsigned int n); 236 static int ena_xstats_get(struct rte_eth_dev *dev, 237 struct rte_eth_xstat *stats, 238 unsigned int n); 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 240 const uint64_t *ids, 241 uint64_t *values, 242 unsigned int n); 243 static int ena_process_bool_devarg(const char *key, 244 const char *value, 245 void *opaque); 246 static int ena_parse_devargs(struct ena_adapter *adapter, 247 struct rte_devargs *devargs); 248 static int ena_copy_eni_stats(struct ena_adapter *adapter); 249 250 static const struct eth_dev_ops ena_dev_ops = { 251 .dev_configure = ena_dev_configure, 252 .dev_infos_get = ena_infos_get, 253 .rx_queue_setup = ena_rx_queue_setup, 254 .tx_queue_setup = ena_tx_queue_setup, 255 .dev_start = ena_start, 256 .dev_stop = ena_stop, 257 .link_update = ena_link_update, 258 .stats_get = ena_stats_get, 259 .xstats_get_names = ena_xstats_get_names, 260 .xstats_get = ena_xstats_get, 261 .xstats_get_by_id = ena_xstats_get_by_id, 262 .mtu_set = ena_mtu_set, 263 .rx_queue_release = ena_rx_queue_release, 264 .tx_queue_release = ena_tx_queue_release, 265 .dev_close = ena_close, 266 .dev_reset = ena_dev_reset, 267 .reta_update = ena_rss_reta_update, 268 .reta_query = ena_rss_reta_query, 269 }; 270 271 void ena_rss_key_fill(void *key, size_t size) 272 { 273 static bool key_generated; 274 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 275 size_t i; 276 277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 278 279 if (!key_generated) { 280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 281 default_key[i] = rte_rand() & 0xff; 282 key_generated = true; 283 } 284 285 rte_memcpy(key, default_key, size); 286 } 287 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 289 struct ena_com_rx_ctx *ena_rx_ctx) 290 { 291 uint64_t ol_flags = 0; 292 uint32_t packet_type = 0; 293 294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 295 packet_type |= RTE_PTYPE_L4_TCP; 296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 297 packet_type |= RTE_PTYPE_L4_UDP; 298 299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 300 packet_type |= RTE_PTYPE_L3_IPV4; 301 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 302 packet_type |= RTE_PTYPE_L3_IPV6; 303 304 if (!ena_rx_ctx->l4_csum_checked) 305 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 306 else 307 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 308 ol_flags |= PKT_RX_L4_CKSUM_BAD; 309 else 310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 311 312 if (unlikely(ena_rx_ctx->l3_csum_err)) 313 ol_flags |= PKT_RX_IP_CKSUM_BAD; 314 315 mbuf->ol_flags = ol_flags; 316 mbuf->packet_type = packet_type; 317 } 318 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 320 struct ena_com_tx_ctx *ena_tx_ctx, 321 uint64_t queue_offloads, 322 bool disable_meta_caching) 323 { 324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 325 326 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 327 (queue_offloads & QUEUE_OFFLOADS)) { 328 /* check if TSO is required */ 329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 331 ena_tx_ctx->tso_enable = true; 332 333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 334 } 335 336 /* check if L3 checksum is needed */ 337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 339 ena_tx_ctx->l3_csum_enable = true; 340 341 if (mbuf->ol_flags & PKT_TX_IPV6) { 342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 343 } else { 344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 345 346 /* set don't fragment (DF) flag */ 347 if (mbuf->packet_type & 348 (RTE_PTYPE_L4_NONFRAG 349 | RTE_PTYPE_INNER_L4_NONFRAG)) 350 ena_tx_ctx->df = true; 351 } 352 353 /* check if L4 checksum is needed */ 354 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 357 ena_tx_ctx->l4_csum_enable = true; 358 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 359 PKT_TX_UDP_CKSUM) && 360 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 362 ena_tx_ctx->l4_csum_enable = true; 363 } else { 364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 365 ena_tx_ctx->l4_csum_enable = false; 366 } 367 368 ena_meta->mss = mbuf->tso_segsz; 369 ena_meta->l3_hdr_len = mbuf->l3_len; 370 ena_meta->l3_hdr_offset = mbuf->l2_len; 371 372 ena_tx_ctx->meta_valid = true; 373 } else if (disable_meta_caching) { 374 memset(ena_meta, 0, sizeof(*ena_meta)); 375 ena_tx_ctx->meta_valid = true; 376 } else { 377 ena_tx_ctx->meta_valid = false; 378 } 379 } 380 381 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 382 { 383 if (likely(req_id < rx_ring->ring_size)) 384 return 0; 385 386 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 387 388 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 389 rx_ring->adapter->trigger_reset = true; 390 ++rx_ring->rx_stats.bad_req_id; 391 392 return -EFAULT; 393 } 394 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 396 { 397 struct ena_tx_buffer *tx_info = NULL; 398 399 if (likely(req_id < tx_ring->ring_size)) { 400 tx_info = &tx_ring->tx_buffer_info[req_id]; 401 if (likely(tx_info->mbuf)) 402 return 0; 403 } 404 405 if (tx_info) 406 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 407 else 408 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 409 410 /* Trigger device reset */ 411 ++tx_ring->tx_stats.bad_req_id; 412 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 413 tx_ring->adapter->trigger_reset = true; 414 return -EFAULT; 415 } 416 417 static void ena_config_host_info(struct ena_com_dev *ena_dev) 418 { 419 struct ena_admin_host_info *host_info; 420 int rc; 421 422 /* Allocate only the host info */ 423 rc = ena_com_allocate_host_info(ena_dev); 424 if (rc) { 425 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 426 return; 427 } 428 429 host_info = ena_dev->host_attr.host_info; 430 431 host_info->os_type = ENA_ADMIN_OS_DPDK; 432 host_info->kernel_ver = RTE_VERSION; 433 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 434 sizeof(host_info->kernel_ver_str)); 435 host_info->os_dist = RTE_VERSION; 436 strlcpy((char *)host_info->os_dist_str, rte_version(), 437 sizeof(host_info->os_dist_str)); 438 host_info->driver_version = 439 (DRV_MODULE_VER_MAJOR) | 440 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 441 (DRV_MODULE_VER_SUBMINOR << 442 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 443 host_info->num_cpus = rte_lcore_count(); 444 445 host_info->driver_supported_features = 446 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 447 448 rc = ena_com_set_host_attributes(ena_dev); 449 if (rc) { 450 if (rc == -ENA_COM_UNSUPPORTED) 451 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 452 else 453 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 454 455 goto err; 456 } 457 458 return; 459 460 err: 461 ena_com_delete_host_info(ena_dev); 462 } 463 464 /* This function calculates the number of xstats based on the current config */ 465 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 466 { 467 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + 468 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 469 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 470 } 471 472 static void ena_config_debug_area(struct ena_adapter *adapter) 473 { 474 u32 debug_area_size; 475 int rc, ss_count; 476 477 ss_count = ena_xstats_calc_num(adapter->rte_dev); 478 479 /* allocate 32 bytes for each string and 64bit for the value */ 480 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 481 482 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 483 if (rc) { 484 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 485 return; 486 } 487 488 rc = ena_com_set_host_attributes(&adapter->ena_dev); 489 if (rc) { 490 if (rc == -ENA_COM_UNSUPPORTED) 491 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 492 else 493 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 494 495 goto err; 496 } 497 498 return; 499 err: 500 ena_com_delete_debug_area(&adapter->ena_dev); 501 } 502 503 static int ena_close(struct rte_eth_dev *dev) 504 { 505 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 507 struct ena_adapter *adapter = dev->data->dev_private; 508 509 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 510 return 0; 511 512 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 513 ena_stop(dev); 514 adapter->state = ENA_ADAPTER_STATE_CLOSED; 515 516 ena_rx_queue_release_all(dev); 517 ena_tx_queue_release_all(dev); 518 519 rte_free(adapter->drv_stats); 520 adapter->drv_stats = NULL; 521 522 rte_intr_disable(intr_handle); 523 rte_intr_callback_unregister(intr_handle, 524 ena_interrupt_handler_rte, 525 adapter); 526 527 /* 528 * MAC is not allocated dynamically. Setting NULL should prevent from 529 * release of the resource in the rte_eth_dev_release_port(). 530 */ 531 dev->data->mac_addrs = NULL; 532 533 return 0; 534 } 535 536 static int 537 ena_dev_reset(struct rte_eth_dev *dev) 538 { 539 int rc = 0; 540 541 ena_destroy_device(dev); 542 rc = eth_ena_dev_init(dev); 543 if (rc) 544 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 545 546 return rc; 547 } 548 549 static int ena_rss_reta_update(struct rte_eth_dev *dev, 550 struct rte_eth_rss_reta_entry64 *reta_conf, 551 uint16_t reta_size) 552 { 553 struct ena_adapter *adapter = dev->data->dev_private; 554 struct ena_com_dev *ena_dev = &adapter->ena_dev; 555 int rc, i; 556 u16 entry_value; 557 int conf_idx; 558 int idx; 559 560 if ((reta_size == 0) || (reta_conf == NULL)) 561 return -EINVAL; 562 563 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 564 PMD_DRV_LOG(WARNING, 565 "indirection table %d is bigger than supported (%d)\n", 566 reta_size, ENA_RX_RSS_TABLE_SIZE); 567 return -EINVAL; 568 } 569 570 for (i = 0 ; i < reta_size ; i++) { 571 /* each reta_conf is for 64 entries. 572 * to support 128 we use 2 conf of 64 573 */ 574 conf_idx = i / RTE_RETA_GROUP_SIZE; 575 idx = i % RTE_RETA_GROUP_SIZE; 576 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 577 entry_value = 578 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 579 580 rc = ena_com_indirect_table_fill_entry(ena_dev, 581 i, 582 entry_value); 583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 584 PMD_DRV_LOG(ERR, 585 "Cannot fill indirect table\n"); 586 return rc; 587 } 588 } 589 } 590 591 rte_spinlock_lock(&adapter->admin_lock); 592 rc = ena_com_indirect_table_set(ena_dev); 593 rte_spinlock_unlock(&adapter->admin_lock); 594 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 595 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 596 return rc; 597 } 598 599 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 600 __func__, reta_size, adapter->rte_dev->data->port_id); 601 602 return 0; 603 } 604 605 /* Query redirection table. */ 606 static int ena_rss_reta_query(struct rte_eth_dev *dev, 607 struct rte_eth_rss_reta_entry64 *reta_conf, 608 uint16_t reta_size) 609 { 610 struct ena_adapter *adapter = dev->data->dev_private; 611 struct ena_com_dev *ena_dev = &adapter->ena_dev; 612 int rc; 613 int i; 614 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 615 int reta_conf_idx; 616 int reta_idx; 617 618 if (reta_size == 0 || reta_conf == NULL || 619 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 620 return -EINVAL; 621 622 rte_spinlock_lock(&adapter->admin_lock); 623 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 624 rte_spinlock_unlock(&adapter->admin_lock); 625 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 626 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 627 return -ENOTSUP; 628 } 629 630 for (i = 0 ; i < reta_size ; i++) { 631 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 632 reta_idx = i % RTE_RETA_GROUP_SIZE; 633 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 634 reta_conf[reta_conf_idx].reta[reta_idx] = 635 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 636 } 637 638 return 0; 639 } 640 641 static int ena_rss_init_default(struct ena_adapter *adapter) 642 { 643 struct ena_com_dev *ena_dev = &adapter->ena_dev; 644 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 645 int rc, i; 646 u32 val; 647 648 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 649 if (unlikely(rc)) { 650 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 651 goto err_rss_init; 652 } 653 654 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 655 val = i % nb_rx_queues; 656 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 657 ENA_IO_RXQ_IDX(val)); 658 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 659 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 660 goto err_fill_indir; 661 } 662 } 663 664 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 665 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 666 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 667 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 668 goto err_fill_indir; 669 } 670 671 rc = ena_com_set_default_hash_ctrl(ena_dev); 672 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 673 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 674 goto err_fill_indir; 675 } 676 677 rc = ena_com_indirect_table_set(ena_dev); 678 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 679 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 680 goto err_fill_indir; 681 } 682 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 683 adapter->rte_dev->data->port_id); 684 685 return 0; 686 687 err_fill_indir: 688 ena_com_rss_destroy(ena_dev); 689 err_rss_init: 690 691 return rc; 692 } 693 694 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 695 { 696 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 697 int nb_queues = dev->data->nb_rx_queues; 698 int i; 699 700 for (i = 0; i < nb_queues; i++) 701 ena_rx_queue_release(queues[i]); 702 } 703 704 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 705 { 706 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 707 int nb_queues = dev->data->nb_tx_queues; 708 int i; 709 710 for (i = 0; i < nb_queues; i++) 711 ena_tx_queue_release(queues[i]); 712 } 713 714 static void ena_rx_queue_release(void *queue) 715 { 716 struct ena_ring *ring = (struct ena_ring *)queue; 717 718 /* Free ring resources */ 719 if (ring->rx_buffer_info) 720 rte_free(ring->rx_buffer_info); 721 ring->rx_buffer_info = NULL; 722 723 if (ring->rx_refill_buffer) 724 rte_free(ring->rx_refill_buffer); 725 ring->rx_refill_buffer = NULL; 726 727 if (ring->empty_rx_reqs) 728 rte_free(ring->empty_rx_reqs); 729 ring->empty_rx_reqs = NULL; 730 731 ring->configured = 0; 732 733 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 734 ring->port_id, ring->id); 735 } 736 737 static void ena_tx_queue_release(void *queue) 738 { 739 struct ena_ring *ring = (struct ena_ring *)queue; 740 741 /* Free ring resources */ 742 if (ring->push_buf_intermediate_buf) 743 rte_free(ring->push_buf_intermediate_buf); 744 745 if (ring->tx_buffer_info) 746 rte_free(ring->tx_buffer_info); 747 748 if (ring->empty_tx_reqs) 749 rte_free(ring->empty_tx_reqs); 750 751 ring->empty_tx_reqs = NULL; 752 ring->tx_buffer_info = NULL; 753 ring->push_buf_intermediate_buf = NULL; 754 755 ring->configured = 0; 756 757 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 758 ring->port_id, ring->id); 759 } 760 761 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 762 { 763 unsigned int i; 764 765 for (i = 0; i < ring->ring_size; ++i) { 766 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 767 if (rx_info->mbuf) { 768 rte_mbuf_raw_free(rx_info->mbuf); 769 rx_info->mbuf = NULL; 770 } 771 } 772 } 773 774 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 775 { 776 unsigned int i; 777 778 for (i = 0; i < ring->ring_size; ++i) { 779 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 780 781 if (tx_buf->mbuf) 782 rte_pktmbuf_free(tx_buf->mbuf); 783 } 784 } 785 786 static int ena_link_update(struct rte_eth_dev *dev, 787 __rte_unused int wait_to_complete) 788 { 789 struct rte_eth_link *link = &dev->data->dev_link; 790 struct ena_adapter *adapter = dev->data->dev_private; 791 792 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 793 link->link_speed = ETH_SPEED_NUM_NONE; 794 link->link_duplex = ETH_LINK_FULL_DUPLEX; 795 796 return 0; 797 } 798 799 static int ena_queue_start_all(struct rte_eth_dev *dev, 800 enum ena_ring_type ring_type) 801 { 802 struct ena_adapter *adapter = dev->data->dev_private; 803 struct ena_ring *queues = NULL; 804 int nb_queues; 805 int i = 0; 806 int rc = 0; 807 808 if (ring_type == ENA_RING_TYPE_RX) { 809 queues = adapter->rx_ring; 810 nb_queues = dev->data->nb_rx_queues; 811 } else { 812 queues = adapter->tx_ring; 813 nb_queues = dev->data->nb_tx_queues; 814 } 815 for (i = 0; i < nb_queues; i++) { 816 if (queues[i].configured) { 817 if (ring_type == ENA_RING_TYPE_RX) { 818 ena_assert_msg( 819 dev->data->rx_queues[i] == &queues[i], 820 "Inconsistent state of rx queues\n"); 821 } else { 822 ena_assert_msg( 823 dev->data->tx_queues[i] == &queues[i], 824 "Inconsistent state of tx queues\n"); 825 } 826 827 rc = ena_queue_start(&queues[i]); 828 829 if (rc) { 830 PMD_INIT_LOG(ERR, 831 "failed to start queue %d type(%d)", 832 i, ring_type); 833 goto err; 834 } 835 } 836 } 837 838 return 0; 839 840 err: 841 while (i--) 842 if (queues[i].configured) 843 ena_queue_stop(&queues[i]); 844 845 return rc; 846 } 847 848 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 849 { 850 uint32_t max_frame_len = adapter->max_mtu; 851 852 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 853 DEV_RX_OFFLOAD_JUMBO_FRAME) 854 max_frame_len = 855 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 856 857 return max_frame_len; 858 } 859 860 static int ena_check_valid_conf(struct ena_adapter *adapter) 861 { 862 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 863 864 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 865 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 866 "max mtu: %d, min mtu: %d", 867 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 868 return ENA_COM_UNSUPPORTED; 869 } 870 871 return 0; 872 } 873 874 static int 875 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 876 bool use_large_llq_hdr) 877 { 878 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 879 struct ena_com_dev *ena_dev = ctx->ena_dev; 880 uint32_t max_tx_queue_size; 881 uint32_t max_rx_queue_size; 882 883 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 884 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 885 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 886 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 887 max_queue_ext->max_rx_sq_depth); 888 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 889 890 if (ena_dev->tx_mem_queue_type == 891 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 892 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 893 llq->max_llq_depth); 894 } else { 895 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 896 max_queue_ext->max_tx_sq_depth); 897 } 898 899 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 900 max_queue_ext->max_per_packet_rx_descs); 901 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 902 max_queue_ext->max_per_packet_tx_descs); 903 } else { 904 struct ena_admin_queue_feature_desc *max_queues = 905 &ctx->get_feat_ctx->max_queues; 906 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 907 max_queues->max_sq_depth); 908 max_tx_queue_size = max_queues->max_cq_depth; 909 910 if (ena_dev->tx_mem_queue_type == 911 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 912 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 913 llq->max_llq_depth); 914 } else { 915 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 916 max_queues->max_sq_depth); 917 } 918 919 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 920 max_queues->max_packet_rx_descs); 921 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 922 max_queues->max_packet_tx_descs); 923 } 924 925 /* Round down to the nearest power of 2 */ 926 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 927 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 928 929 if (use_large_llq_hdr) { 930 if ((llq->entry_size_ctrl_supported & 931 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 932 (ena_dev->tx_mem_queue_type == 933 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 934 max_tx_queue_size /= 2; 935 PMD_INIT_LOG(INFO, 936 "Forcing large headers and decreasing maximum TX queue size to %d\n", 937 max_tx_queue_size); 938 } else { 939 PMD_INIT_LOG(ERR, 940 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 941 } 942 } 943 944 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 945 PMD_INIT_LOG(ERR, "Invalid queue size"); 946 return -EFAULT; 947 } 948 949 ctx->max_tx_queue_size = max_tx_queue_size; 950 ctx->max_rx_queue_size = max_rx_queue_size; 951 952 return 0; 953 } 954 955 static void ena_stats_restart(struct rte_eth_dev *dev) 956 { 957 struct ena_adapter *adapter = dev->data->dev_private; 958 959 rte_atomic64_init(&adapter->drv_stats->ierrors); 960 rte_atomic64_init(&adapter->drv_stats->oerrors); 961 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 962 adapter->drv_stats->rx_drops = 0; 963 } 964 965 static int ena_stats_get(struct rte_eth_dev *dev, 966 struct rte_eth_stats *stats) 967 { 968 struct ena_admin_basic_stats ena_stats; 969 struct ena_adapter *adapter = dev->data->dev_private; 970 struct ena_com_dev *ena_dev = &adapter->ena_dev; 971 int rc; 972 int i; 973 int max_rings_stats; 974 975 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 976 return -ENOTSUP; 977 978 memset(&ena_stats, 0, sizeof(ena_stats)); 979 980 rte_spinlock_lock(&adapter->admin_lock); 981 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 982 rte_spinlock_unlock(&adapter->admin_lock); 983 if (unlikely(rc)) { 984 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 985 return rc; 986 } 987 988 /* Set of basic statistics from ENA */ 989 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 990 ena_stats.rx_pkts_low); 991 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 992 ena_stats.tx_pkts_low); 993 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 994 ena_stats.rx_bytes_low); 995 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 996 ena_stats.tx_bytes_low); 997 998 /* Driver related stats */ 999 stats->imissed = adapter->drv_stats->rx_drops; 1000 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 1001 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 1002 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 1003 1004 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 1005 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1006 for (i = 0; i < max_rings_stats; ++i) { 1007 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 1008 1009 stats->q_ibytes[i] = rx_stats->bytes; 1010 stats->q_ipackets[i] = rx_stats->cnt; 1011 stats->q_errors[i] = rx_stats->bad_desc_num + 1012 rx_stats->bad_req_id; 1013 } 1014 1015 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 1016 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1017 for (i = 0; i < max_rings_stats; ++i) { 1018 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 1019 1020 stats->q_obytes[i] = tx_stats->bytes; 1021 stats->q_opackets[i] = tx_stats->cnt; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1028 { 1029 struct ena_adapter *adapter; 1030 struct ena_com_dev *ena_dev; 1031 int rc = 0; 1032 1033 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1034 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1035 adapter = dev->data->dev_private; 1036 1037 ena_dev = &adapter->ena_dev; 1038 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1039 1040 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1041 PMD_DRV_LOG(ERR, 1042 "Invalid MTU setting. new_mtu: %d " 1043 "max mtu: %d min mtu: %d\n", 1044 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1045 return -EINVAL; 1046 } 1047 1048 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1049 if (rc) 1050 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1051 else 1052 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1053 1054 return rc; 1055 } 1056 1057 static int ena_start(struct rte_eth_dev *dev) 1058 { 1059 struct ena_adapter *adapter = dev->data->dev_private; 1060 uint64_t ticks; 1061 int rc = 0; 1062 1063 rc = ena_check_valid_conf(adapter); 1064 if (rc) 1065 return rc; 1066 1067 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1068 if (rc) 1069 return rc; 1070 1071 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1072 if (rc) 1073 goto err_start_tx; 1074 1075 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1076 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1077 rc = ena_rss_init_default(adapter); 1078 if (rc) 1079 goto err_rss_init; 1080 } 1081 1082 ena_stats_restart(dev); 1083 1084 adapter->timestamp_wd = rte_get_timer_cycles(); 1085 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1086 1087 ticks = rte_get_timer_hz(); 1088 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1089 ena_timer_wd_callback, adapter); 1090 1091 ++adapter->dev_stats.dev_start; 1092 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1093 1094 return 0; 1095 1096 err_rss_init: 1097 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1098 err_start_tx: 1099 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1100 return rc; 1101 } 1102 1103 static void ena_stop(struct rte_eth_dev *dev) 1104 { 1105 struct ena_adapter *adapter = dev->data->dev_private; 1106 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1107 int rc; 1108 1109 rte_timer_stop_sync(&adapter->timer_wd); 1110 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1111 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1112 1113 if (adapter->trigger_reset) { 1114 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1115 if (rc) 1116 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1117 } 1118 1119 ++adapter->dev_stats.dev_stop; 1120 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1121 } 1122 1123 static int ena_create_io_queue(struct ena_ring *ring) 1124 { 1125 struct ena_adapter *adapter; 1126 struct ena_com_dev *ena_dev; 1127 struct ena_com_create_io_ctx ctx = 1128 /* policy set to _HOST just to satisfy icc compiler */ 1129 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1130 0, 0, 0, 0, 0 }; 1131 uint16_t ena_qid; 1132 unsigned int i; 1133 int rc; 1134 1135 adapter = ring->adapter; 1136 ena_dev = &adapter->ena_dev; 1137 1138 if (ring->type == ENA_RING_TYPE_TX) { 1139 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1140 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1141 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1142 for (i = 0; i < ring->ring_size; i++) 1143 ring->empty_tx_reqs[i] = i; 1144 } else { 1145 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1146 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1147 for (i = 0; i < ring->ring_size; i++) 1148 ring->empty_rx_reqs[i] = i; 1149 } 1150 ctx.queue_size = ring->ring_size; 1151 ctx.qid = ena_qid; 1152 ctx.msix_vector = -1; /* interrupts not used */ 1153 ctx.numa_node = ring->numa_socket_id; 1154 1155 rc = ena_com_create_io_queue(ena_dev, &ctx); 1156 if (rc) { 1157 PMD_DRV_LOG(ERR, 1158 "failed to create io queue #%d (qid:%d) rc: %d\n", 1159 ring->id, ena_qid, rc); 1160 return rc; 1161 } 1162 1163 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1164 &ring->ena_com_io_sq, 1165 &ring->ena_com_io_cq); 1166 if (rc) { 1167 PMD_DRV_LOG(ERR, 1168 "Failed to get io queue handlers. queue num %d rc: %d\n", 1169 ring->id, rc); 1170 ena_com_destroy_io_queue(ena_dev, ena_qid); 1171 return rc; 1172 } 1173 1174 if (ring->type == ENA_RING_TYPE_TX) 1175 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1176 1177 return 0; 1178 } 1179 1180 static void ena_queue_stop(struct ena_ring *ring) 1181 { 1182 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1183 1184 if (ring->type == ENA_RING_TYPE_RX) { 1185 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1186 ena_rx_queue_release_bufs(ring); 1187 } else { 1188 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1189 ena_tx_queue_release_bufs(ring); 1190 } 1191 } 1192 1193 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1194 enum ena_ring_type ring_type) 1195 { 1196 struct ena_adapter *adapter = dev->data->dev_private; 1197 struct ena_ring *queues = NULL; 1198 uint16_t nb_queues, i; 1199 1200 if (ring_type == ENA_RING_TYPE_RX) { 1201 queues = adapter->rx_ring; 1202 nb_queues = dev->data->nb_rx_queues; 1203 } else { 1204 queues = adapter->tx_ring; 1205 nb_queues = dev->data->nb_tx_queues; 1206 } 1207 1208 for (i = 0; i < nb_queues; ++i) 1209 if (queues[i].configured) 1210 ena_queue_stop(&queues[i]); 1211 } 1212 1213 static int ena_queue_start(struct ena_ring *ring) 1214 { 1215 int rc, bufs_num; 1216 1217 ena_assert_msg(ring->configured == 1, 1218 "Trying to start unconfigured queue\n"); 1219 1220 rc = ena_create_io_queue(ring); 1221 if (rc) { 1222 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1223 return rc; 1224 } 1225 1226 ring->next_to_clean = 0; 1227 ring->next_to_use = 0; 1228 1229 if (ring->type == ENA_RING_TYPE_TX) { 1230 ring->tx_stats.available_desc = 1231 ena_com_free_q_entries(ring->ena_com_io_sq); 1232 return 0; 1233 } 1234 1235 bufs_num = ring->ring_size - 1; 1236 rc = ena_populate_rx_queue(ring, bufs_num); 1237 if (rc != bufs_num) { 1238 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1239 ENA_IO_RXQ_IDX(ring->id)); 1240 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1241 return ENA_COM_FAULT; 1242 } 1243 1244 return 0; 1245 } 1246 1247 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1248 uint16_t queue_idx, 1249 uint16_t nb_desc, 1250 unsigned int socket_id, 1251 const struct rte_eth_txconf *tx_conf) 1252 { 1253 struct ena_ring *txq = NULL; 1254 struct ena_adapter *adapter = dev->data->dev_private; 1255 unsigned int i; 1256 1257 txq = &adapter->tx_ring[queue_idx]; 1258 1259 if (txq->configured) { 1260 PMD_DRV_LOG(CRIT, 1261 "API violation. Queue %d is already configured\n", 1262 queue_idx); 1263 return ENA_COM_FAULT; 1264 } 1265 1266 if (!rte_is_power_of_2(nb_desc)) { 1267 PMD_DRV_LOG(ERR, 1268 "Unsupported size of TX queue: %d is not a power of 2.\n", 1269 nb_desc); 1270 return -EINVAL; 1271 } 1272 1273 if (nb_desc > adapter->max_tx_ring_size) { 1274 PMD_DRV_LOG(ERR, 1275 "Unsupported size of TX queue (max size: %d)\n", 1276 adapter->max_tx_ring_size); 1277 return -EINVAL; 1278 } 1279 1280 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1281 nb_desc = adapter->max_tx_ring_size; 1282 1283 txq->port_id = dev->data->port_id; 1284 txq->next_to_clean = 0; 1285 txq->next_to_use = 0; 1286 txq->ring_size = nb_desc; 1287 txq->size_mask = nb_desc - 1; 1288 txq->numa_socket_id = socket_id; 1289 1290 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1291 sizeof(struct ena_tx_buffer) * 1292 txq->ring_size, 1293 RTE_CACHE_LINE_SIZE); 1294 if (!txq->tx_buffer_info) { 1295 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1296 return -ENOMEM; 1297 } 1298 1299 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1300 sizeof(u16) * txq->ring_size, 1301 RTE_CACHE_LINE_SIZE); 1302 if (!txq->empty_tx_reqs) { 1303 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1304 rte_free(txq->tx_buffer_info); 1305 return -ENOMEM; 1306 } 1307 1308 txq->push_buf_intermediate_buf = 1309 rte_zmalloc("txq->push_buf_intermediate_buf", 1310 txq->tx_max_header_size, 1311 RTE_CACHE_LINE_SIZE); 1312 if (!txq->push_buf_intermediate_buf) { 1313 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1314 rte_free(txq->tx_buffer_info); 1315 rte_free(txq->empty_tx_reqs); 1316 return -ENOMEM; 1317 } 1318 1319 for (i = 0; i < txq->ring_size; i++) 1320 txq->empty_tx_reqs[i] = i; 1321 1322 if (tx_conf != NULL) { 1323 txq->offloads = 1324 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1325 } 1326 /* Store pointer to this queue in upper layer */ 1327 txq->configured = 1; 1328 dev->data->tx_queues[queue_idx] = txq; 1329 1330 return 0; 1331 } 1332 1333 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1334 uint16_t queue_idx, 1335 uint16_t nb_desc, 1336 unsigned int socket_id, 1337 __rte_unused const struct rte_eth_rxconf *rx_conf, 1338 struct rte_mempool *mp) 1339 { 1340 struct ena_adapter *adapter = dev->data->dev_private; 1341 struct ena_ring *rxq = NULL; 1342 size_t buffer_size; 1343 int i; 1344 1345 rxq = &adapter->rx_ring[queue_idx]; 1346 if (rxq->configured) { 1347 PMD_DRV_LOG(CRIT, 1348 "API violation. Queue %d is already configured\n", 1349 queue_idx); 1350 return ENA_COM_FAULT; 1351 } 1352 1353 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1354 nb_desc = adapter->max_rx_ring_size; 1355 1356 if (!rte_is_power_of_2(nb_desc)) { 1357 PMD_DRV_LOG(ERR, 1358 "Unsupported size of RX queue: %d is not a power of 2.\n", 1359 nb_desc); 1360 return -EINVAL; 1361 } 1362 1363 if (nb_desc > adapter->max_rx_ring_size) { 1364 PMD_DRV_LOG(ERR, 1365 "Unsupported size of RX queue (max size: %d)\n", 1366 adapter->max_rx_ring_size); 1367 return -EINVAL; 1368 } 1369 1370 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1371 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1372 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1373 PMD_DRV_LOG(ERR, 1374 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1375 buffer_size, ENA_RX_BUF_MIN_SIZE); 1376 return -EINVAL; 1377 } 1378 1379 rxq->port_id = dev->data->port_id; 1380 rxq->next_to_clean = 0; 1381 rxq->next_to_use = 0; 1382 rxq->ring_size = nb_desc; 1383 rxq->size_mask = nb_desc - 1; 1384 rxq->numa_socket_id = socket_id; 1385 rxq->mb_pool = mp; 1386 1387 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1388 sizeof(struct ena_rx_buffer) * nb_desc, 1389 RTE_CACHE_LINE_SIZE); 1390 if (!rxq->rx_buffer_info) { 1391 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1392 return -ENOMEM; 1393 } 1394 1395 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1396 sizeof(struct rte_mbuf *) * nb_desc, 1397 RTE_CACHE_LINE_SIZE); 1398 1399 if (!rxq->rx_refill_buffer) { 1400 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1401 rte_free(rxq->rx_buffer_info); 1402 rxq->rx_buffer_info = NULL; 1403 return -ENOMEM; 1404 } 1405 1406 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1407 sizeof(uint16_t) * nb_desc, 1408 RTE_CACHE_LINE_SIZE); 1409 if (!rxq->empty_rx_reqs) { 1410 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1411 rte_free(rxq->rx_buffer_info); 1412 rxq->rx_buffer_info = NULL; 1413 rte_free(rxq->rx_refill_buffer); 1414 rxq->rx_refill_buffer = NULL; 1415 return -ENOMEM; 1416 } 1417 1418 for (i = 0; i < nb_desc; i++) 1419 rxq->empty_rx_reqs[i] = i; 1420 1421 /* Store pointer to this queue in upper layer */ 1422 rxq->configured = 1; 1423 dev->data->rx_queues[queue_idx] = rxq; 1424 1425 return 0; 1426 } 1427 1428 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1429 struct rte_mbuf *mbuf, uint16_t id) 1430 { 1431 struct ena_com_buf ebuf; 1432 int rc; 1433 1434 /* prepare physical address for DMA transaction */ 1435 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1436 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1437 1438 /* pass resource to device */ 1439 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1440 if (unlikely(rc != 0)) 1441 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1442 1443 return rc; 1444 } 1445 1446 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1447 { 1448 unsigned int i; 1449 int rc; 1450 uint16_t next_to_use = rxq->next_to_use; 1451 uint16_t in_use, req_id; 1452 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1453 1454 if (unlikely(!count)) 1455 return 0; 1456 1457 in_use = rxq->ring_size - 1 - 1458 ena_com_free_q_entries(rxq->ena_com_io_sq); 1459 ena_assert_msg(((in_use + count) < rxq->ring_size), 1460 "bad ring state\n"); 1461 1462 /* get resources for incoming packets */ 1463 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1464 if (unlikely(rc < 0)) { 1465 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1466 ++rxq->rx_stats.mbuf_alloc_fail; 1467 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1468 return 0; 1469 } 1470 1471 for (i = 0; i < count; i++) { 1472 struct rte_mbuf *mbuf = mbufs[i]; 1473 struct ena_rx_buffer *rx_info; 1474 1475 if (likely((i + 4) < count)) 1476 rte_prefetch0(mbufs[i + 4]); 1477 1478 req_id = rxq->empty_rx_reqs[next_to_use]; 1479 rc = validate_rx_req_id(rxq, req_id); 1480 if (unlikely(rc)) 1481 break; 1482 1483 rx_info = &rxq->rx_buffer_info[req_id]; 1484 1485 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1486 if (unlikely(rc != 0)) 1487 break; 1488 1489 rx_info->mbuf = mbuf; 1490 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1491 } 1492 1493 if (unlikely(i < count)) { 1494 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1495 "buffers (from %d)\n", rxq->id, i, count); 1496 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1497 count - i); 1498 ++rxq->rx_stats.refill_partial; 1499 } 1500 1501 /* When we submitted free recources to device... */ 1502 if (likely(i > 0)) { 1503 /* ...let HW know that it can fill buffers with data. */ 1504 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1505 1506 rxq->next_to_use = next_to_use; 1507 } 1508 1509 return i; 1510 } 1511 1512 static int ena_device_init(struct ena_com_dev *ena_dev, 1513 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1514 bool *wd_state) 1515 { 1516 uint32_t aenq_groups; 1517 int rc; 1518 bool readless_supported; 1519 1520 /* Initialize mmio registers */ 1521 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1522 if (rc) { 1523 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1524 return rc; 1525 } 1526 1527 /* The PCIe configuration space revision id indicate if mmio reg 1528 * read is disabled. 1529 */ 1530 readless_supported = 1531 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1532 & ENA_MMIO_DISABLE_REG_READ); 1533 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1534 1535 /* reset device */ 1536 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1537 if (rc) { 1538 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1539 goto err_mmio_read_less; 1540 } 1541 1542 /* check FW version */ 1543 rc = ena_com_validate_version(ena_dev); 1544 if (rc) { 1545 PMD_DRV_LOG(ERR, "device version is too low\n"); 1546 goto err_mmio_read_less; 1547 } 1548 1549 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1550 1551 /* ENA device administration layer init */ 1552 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1553 if (rc) { 1554 PMD_DRV_LOG(ERR, 1555 "cannot initialize ena admin queue with device\n"); 1556 goto err_mmio_read_less; 1557 } 1558 1559 /* To enable the msix interrupts the driver needs to know the number 1560 * of queues. So the driver uses polling mode to retrieve this 1561 * information. 1562 */ 1563 ena_com_set_admin_polling_mode(ena_dev, true); 1564 1565 ena_config_host_info(ena_dev); 1566 1567 /* Get Device Attributes and features */ 1568 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1569 if (rc) { 1570 PMD_DRV_LOG(ERR, 1571 "cannot get attribute for ena device rc= %d\n", rc); 1572 goto err_admin_init; 1573 } 1574 1575 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1576 BIT(ENA_ADMIN_NOTIFICATION) | 1577 BIT(ENA_ADMIN_KEEP_ALIVE) | 1578 BIT(ENA_ADMIN_FATAL_ERROR) | 1579 BIT(ENA_ADMIN_WARNING); 1580 1581 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1582 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1583 if (rc) { 1584 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1585 goto err_admin_init; 1586 } 1587 1588 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1589 1590 return 0; 1591 1592 err_admin_init: 1593 ena_com_admin_destroy(ena_dev); 1594 1595 err_mmio_read_less: 1596 ena_com_mmio_reg_read_request_destroy(ena_dev); 1597 1598 return rc; 1599 } 1600 1601 static void ena_interrupt_handler_rte(void *cb_arg) 1602 { 1603 struct ena_adapter *adapter = cb_arg; 1604 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1605 1606 ena_com_admin_q_comp_intr_handler(ena_dev); 1607 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1608 ena_com_aenq_intr_handler(ena_dev, adapter); 1609 } 1610 1611 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1612 { 1613 if (!adapter->wd_state) 1614 return; 1615 1616 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1617 return; 1618 1619 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1620 adapter->keep_alive_timeout)) { 1621 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1622 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1623 adapter->trigger_reset = true; 1624 ++adapter->dev_stats.wd_expired; 1625 } 1626 } 1627 1628 /* Check if admin queue is enabled */ 1629 static void check_for_admin_com_state(struct ena_adapter *adapter) 1630 { 1631 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1632 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1633 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1634 adapter->trigger_reset = true; 1635 } 1636 } 1637 1638 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1639 void *arg) 1640 { 1641 struct ena_adapter *adapter = arg; 1642 struct rte_eth_dev *dev = adapter->rte_dev; 1643 1644 check_for_missing_keep_alive(adapter); 1645 check_for_admin_com_state(adapter); 1646 1647 if (unlikely(adapter->trigger_reset)) { 1648 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1649 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1650 NULL); 1651 } 1652 } 1653 1654 static inline void 1655 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1656 struct ena_admin_feature_llq_desc *llq, 1657 bool use_large_llq_hdr) 1658 { 1659 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1660 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1661 llq_config->llq_num_decs_before_header = 1662 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1663 1664 if (use_large_llq_hdr && 1665 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1666 llq_config->llq_ring_entry_size = 1667 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1668 llq_config->llq_ring_entry_size_value = 256; 1669 } else { 1670 llq_config->llq_ring_entry_size = 1671 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1672 llq_config->llq_ring_entry_size_value = 128; 1673 } 1674 } 1675 1676 static int 1677 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1678 struct ena_com_dev *ena_dev, 1679 struct ena_admin_feature_llq_desc *llq, 1680 struct ena_llq_configurations *llq_default_configurations) 1681 { 1682 int rc; 1683 u32 llq_feature_mask; 1684 1685 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1686 if (!(ena_dev->supported_features & llq_feature_mask)) { 1687 PMD_DRV_LOG(INFO, 1688 "LLQ is not supported. Fallback to host mode policy.\n"); 1689 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1690 return 0; 1691 } 1692 1693 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1694 if (unlikely(rc)) { 1695 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1696 "Fallback to host mode policy."); 1697 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1698 return 0; 1699 } 1700 1701 /* Nothing to config, exit */ 1702 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1703 return 0; 1704 1705 if (!adapter->dev_mem_base) { 1706 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1707 "Fallback to host mode policy.\n."); 1708 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1709 return 0; 1710 } 1711 1712 ena_dev->mem_bar = adapter->dev_mem_base; 1713 1714 return 0; 1715 } 1716 1717 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1718 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1719 { 1720 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1721 1722 /* Regular queues capabilities */ 1723 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1724 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1725 &get_feat_ctx->max_queue_ext.max_queue_ext; 1726 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1727 max_queue_ext->max_rx_cq_num); 1728 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1729 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1730 } else { 1731 struct ena_admin_queue_feature_desc *max_queues = 1732 &get_feat_ctx->max_queues; 1733 io_tx_sq_num = max_queues->max_sq_num; 1734 io_tx_cq_num = max_queues->max_cq_num; 1735 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1736 } 1737 1738 /* In case of LLQ use the llq number in the get feature cmd */ 1739 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1740 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1741 1742 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1743 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1744 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1745 1746 if (unlikely(max_num_io_queues == 0)) { 1747 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1748 return -EFAULT; 1749 } 1750 1751 return max_num_io_queues; 1752 } 1753 1754 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1755 { 1756 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1757 struct rte_pci_device *pci_dev; 1758 struct rte_intr_handle *intr_handle; 1759 struct ena_adapter *adapter = eth_dev->data->dev_private; 1760 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1761 struct ena_com_dev_get_features_ctx get_feat_ctx; 1762 struct ena_llq_configurations llq_config; 1763 const char *queue_type_str; 1764 uint32_t max_num_io_queues; 1765 int rc; 1766 static int adapters_found; 1767 bool disable_meta_caching; 1768 bool wd_state = false; 1769 1770 eth_dev->dev_ops = &ena_dev_ops; 1771 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1772 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1773 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1774 1775 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1776 return 0; 1777 1778 memset(adapter, 0, sizeof(struct ena_adapter)); 1779 ena_dev = &adapter->ena_dev; 1780 1781 adapter->rte_eth_dev_data = eth_dev->data; 1782 adapter->rte_dev = eth_dev; 1783 1784 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1785 adapter->pdev = pci_dev; 1786 1787 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1788 pci_dev->addr.domain, 1789 pci_dev->addr.bus, 1790 pci_dev->addr.devid, 1791 pci_dev->addr.function); 1792 1793 intr_handle = &pci_dev->intr_handle; 1794 1795 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1796 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1797 1798 if (!adapter->regs) { 1799 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1800 ENA_REGS_BAR); 1801 return -ENXIO; 1802 } 1803 1804 ena_dev->reg_bar = adapter->regs; 1805 ena_dev->dmadev = adapter->pdev; 1806 1807 adapter->id_number = adapters_found; 1808 1809 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1810 adapter->id_number); 1811 1812 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1813 if (rc != 0) { 1814 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1815 goto err; 1816 } 1817 1818 /* device specific initialization routine */ 1819 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1820 if (rc) { 1821 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1822 goto err; 1823 } 1824 adapter->wd_state = wd_state; 1825 1826 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1827 adapter->use_large_llq_hdr); 1828 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1829 &get_feat_ctx.llq, &llq_config); 1830 if (unlikely(rc)) { 1831 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1832 return rc; 1833 } 1834 1835 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1836 queue_type_str = "Regular"; 1837 else 1838 queue_type_str = "Low latency"; 1839 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1840 1841 calc_queue_ctx.ena_dev = ena_dev; 1842 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1843 1844 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1845 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1846 adapter->use_large_llq_hdr); 1847 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1848 rc = -EFAULT; 1849 goto err_device_destroy; 1850 } 1851 1852 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1853 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1854 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1855 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1856 adapter->max_num_io_queues = max_num_io_queues; 1857 1858 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1859 disable_meta_caching = 1860 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 1861 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 1862 } else { 1863 disable_meta_caching = false; 1864 } 1865 1866 /* prepare ring structures */ 1867 ena_init_rings(adapter, disable_meta_caching); 1868 1869 ena_config_debug_area(adapter); 1870 1871 /* Set max MTU for this device */ 1872 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1873 1874 /* set device support for offloads */ 1875 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1876 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1877 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1878 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1879 adapter->offloads.rx_csum_supported = 1880 (get_feat_ctx.offload.rx_supported & 1881 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1882 1883 /* Copy MAC address and point DPDK to it */ 1884 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1885 rte_ether_addr_copy((struct rte_ether_addr *) 1886 get_feat_ctx.dev_attr.mac_addr, 1887 (struct rte_ether_addr *)adapter->mac_addr); 1888 1889 adapter->drv_stats = rte_zmalloc("adapter stats", 1890 sizeof(*adapter->drv_stats), 1891 RTE_CACHE_LINE_SIZE); 1892 if (!adapter->drv_stats) { 1893 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1894 rc = -ENOMEM; 1895 goto err_delete_debug_area; 1896 } 1897 1898 rte_spinlock_init(&adapter->admin_lock); 1899 1900 rte_intr_callback_register(intr_handle, 1901 ena_interrupt_handler_rte, 1902 adapter); 1903 rte_intr_enable(intr_handle); 1904 ena_com_set_admin_polling_mode(ena_dev, false); 1905 ena_com_admin_aenq_enable(ena_dev); 1906 1907 if (adapters_found == 0) 1908 rte_timer_subsystem_init(); 1909 rte_timer_init(&adapter->timer_wd); 1910 1911 adapters_found++; 1912 adapter->state = ENA_ADAPTER_STATE_INIT; 1913 1914 return 0; 1915 1916 err_delete_debug_area: 1917 ena_com_delete_debug_area(ena_dev); 1918 1919 err_device_destroy: 1920 ena_com_delete_host_info(ena_dev); 1921 ena_com_admin_destroy(ena_dev); 1922 1923 err: 1924 return rc; 1925 } 1926 1927 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1928 { 1929 struct ena_adapter *adapter = eth_dev->data->dev_private; 1930 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1931 1932 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1933 return; 1934 1935 ena_com_set_admin_running_state(ena_dev, false); 1936 1937 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1938 ena_close(eth_dev); 1939 1940 ena_com_delete_debug_area(ena_dev); 1941 ena_com_delete_host_info(ena_dev); 1942 1943 ena_com_abort_admin_commands(ena_dev); 1944 ena_com_wait_for_abort_completion(ena_dev); 1945 ena_com_admin_destroy(ena_dev); 1946 ena_com_mmio_reg_read_request_destroy(ena_dev); 1947 1948 adapter->state = ENA_ADAPTER_STATE_FREE; 1949 } 1950 1951 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1952 { 1953 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1954 return 0; 1955 1956 ena_destroy_device(eth_dev); 1957 1958 eth_dev->dev_ops = NULL; 1959 eth_dev->rx_pkt_burst = NULL; 1960 eth_dev->tx_pkt_burst = NULL; 1961 eth_dev->tx_pkt_prepare = NULL; 1962 1963 return 0; 1964 } 1965 1966 static int ena_dev_configure(struct rte_eth_dev *dev) 1967 { 1968 struct ena_adapter *adapter = dev->data->dev_private; 1969 1970 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1971 1972 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1973 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1974 return 0; 1975 } 1976 1977 static void ena_init_rings(struct ena_adapter *adapter, 1978 bool disable_meta_caching) 1979 { 1980 size_t i; 1981 1982 for (i = 0; i < adapter->max_num_io_queues; i++) { 1983 struct ena_ring *ring = &adapter->tx_ring[i]; 1984 1985 ring->configured = 0; 1986 ring->type = ENA_RING_TYPE_TX; 1987 ring->adapter = adapter; 1988 ring->id = i; 1989 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1990 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1991 ring->sgl_size = adapter->max_tx_sgl_size; 1992 ring->disable_meta_caching = disable_meta_caching; 1993 } 1994 1995 for (i = 0; i < adapter->max_num_io_queues; i++) { 1996 struct ena_ring *ring = &adapter->rx_ring[i]; 1997 1998 ring->configured = 0; 1999 ring->type = ENA_RING_TYPE_RX; 2000 ring->adapter = adapter; 2001 ring->id = i; 2002 ring->sgl_size = adapter->max_rx_sgl_size; 2003 } 2004 } 2005 2006 static int ena_infos_get(struct rte_eth_dev *dev, 2007 struct rte_eth_dev_info *dev_info) 2008 { 2009 struct ena_adapter *adapter; 2010 struct ena_com_dev *ena_dev; 2011 uint64_t rx_feat = 0, tx_feat = 0; 2012 2013 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 2014 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 2015 adapter = dev->data->dev_private; 2016 2017 ena_dev = &adapter->ena_dev; 2018 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 2019 2020 dev_info->speed_capa = 2021 ETH_LINK_SPEED_1G | 2022 ETH_LINK_SPEED_2_5G | 2023 ETH_LINK_SPEED_5G | 2024 ETH_LINK_SPEED_10G | 2025 ETH_LINK_SPEED_25G | 2026 ETH_LINK_SPEED_40G | 2027 ETH_LINK_SPEED_50G | 2028 ETH_LINK_SPEED_100G; 2029 2030 /* Set Tx & Rx features available for device */ 2031 if (adapter->offloads.tso4_supported) 2032 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 2033 2034 if (adapter->offloads.tx_csum_supported) 2035 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 2036 DEV_TX_OFFLOAD_UDP_CKSUM | 2037 DEV_TX_OFFLOAD_TCP_CKSUM; 2038 2039 if (adapter->offloads.rx_csum_supported) 2040 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 2041 DEV_RX_OFFLOAD_UDP_CKSUM | 2042 DEV_RX_OFFLOAD_TCP_CKSUM; 2043 2044 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2045 2046 /* Inform framework about available features */ 2047 dev_info->rx_offload_capa = rx_feat; 2048 dev_info->rx_queue_offload_capa = rx_feat; 2049 dev_info->tx_offload_capa = tx_feat; 2050 dev_info->tx_queue_offload_capa = tx_feat; 2051 2052 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2053 ETH_RSS_UDP; 2054 2055 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2056 dev_info->max_rx_pktlen = adapter->max_mtu; 2057 dev_info->max_mac_addrs = 1; 2058 2059 dev_info->max_rx_queues = adapter->max_num_io_queues; 2060 dev_info->max_tx_queues = adapter->max_num_io_queues; 2061 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2062 2063 adapter->tx_supported_offloads = tx_feat; 2064 adapter->rx_supported_offloads = rx_feat; 2065 2066 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2067 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2068 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2069 adapter->max_rx_sgl_size); 2070 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2071 adapter->max_rx_sgl_size); 2072 2073 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2074 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2075 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2076 adapter->max_tx_sgl_size); 2077 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2078 adapter->max_tx_sgl_size); 2079 2080 return 0; 2081 } 2082 2083 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 2084 { 2085 mbuf->data_len = len; 2086 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2087 mbuf->refcnt = 1; 2088 mbuf->next = NULL; 2089 } 2090 2091 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 2092 struct ena_com_rx_buf_info *ena_bufs, 2093 uint32_t descs, 2094 uint16_t *next_to_clean, 2095 uint8_t offset) 2096 { 2097 struct rte_mbuf *mbuf; 2098 struct rte_mbuf *mbuf_head; 2099 struct ena_rx_buffer *rx_info; 2100 int rc; 2101 uint16_t ntc, len, req_id, buf = 0; 2102 2103 if (unlikely(descs == 0)) 2104 return NULL; 2105 2106 ntc = *next_to_clean; 2107 2108 len = ena_bufs[buf].len; 2109 req_id = ena_bufs[buf].req_id; 2110 if (unlikely(validate_rx_req_id(rx_ring, req_id))) 2111 return NULL; 2112 2113 rx_info = &rx_ring->rx_buffer_info[req_id]; 2114 2115 mbuf = rx_info->mbuf; 2116 RTE_ASSERT(mbuf != NULL); 2117 2118 ena_init_rx_mbuf(mbuf, len); 2119 2120 /* Fill the mbuf head with the data specific for 1st segment. */ 2121 mbuf_head = mbuf; 2122 mbuf_head->nb_segs = descs; 2123 mbuf_head->port = rx_ring->port_id; 2124 mbuf_head->pkt_len = len; 2125 mbuf_head->data_off += offset; 2126 2127 rx_info->mbuf = NULL; 2128 rx_ring->empty_rx_reqs[ntc] = req_id; 2129 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2130 2131 while (--descs) { 2132 ++buf; 2133 len = ena_bufs[buf].len; 2134 req_id = ena_bufs[buf].req_id; 2135 if (unlikely(validate_rx_req_id(rx_ring, req_id))) { 2136 rte_mbuf_raw_free(mbuf_head); 2137 return NULL; 2138 } 2139 2140 rx_info = &rx_ring->rx_buffer_info[req_id]; 2141 RTE_ASSERT(rx_info->mbuf != NULL); 2142 2143 if (unlikely(len == 0)) { 2144 /* 2145 * Some devices can pass descriptor with the length 0. 2146 * To avoid confusion, the PMD is simply putting the 2147 * descriptor back, as it was never used. We'll avoid 2148 * mbuf allocation that way. 2149 */ 2150 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2151 rx_info->mbuf, req_id); 2152 if (unlikely(rc != 0)) { 2153 /* Free the mbuf in case of an error. */ 2154 rte_mbuf_raw_free(rx_info->mbuf); 2155 } else { 2156 /* 2157 * If there was no error, just exit the loop as 2158 * 0 length descriptor is always the last one. 2159 */ 2160 break; 2161 } 2162 } else { 2163 /* Create an mbuf chain. */ 2164 mbuf->next = rx_info->mbuf; 2165 mbuf = mbuf->next; 2166 2167 ena_init_rx_mbuf(mbuf, len); 2168 mbuf_head->pkt_len += len; 2169 } 2170 2171 /* 2172 * Mark the descriptor as depleted and perform necessary 2173 * cleanup. 2174 * This code will execute in two cases: 2175 * 1. Descriptor len was greater than 0 - normal situation. 2176 * 2. Descriptor len was 0 and we failed to add the descriptor 2177 * to the device. In that situation, we should try to add 2178 * the mbuf again in the populate routine and mark the 2179 * descriptor as used up by the device. 2180 */ 2181 rx_info->mbuf = NULL; 2182 rx_ring->empty_rx_reqs[ntc] = req_id; 2183 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2184 } 2185 2186 *next_to_clean = ntc; 2187 2188 return mbuf_head; 2189 } 2190 2191 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2192 uint16_t nb_pkts) 2193 { 2194 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2195 unsigned int free_queue_entries; 2196 unsigned int refill_threshold; 2197 uint16_t next_to_clean = rx_ring->next_to_clean; 2198 uint16_t descs_in_use; 2199 struct rte_mbuf *mbuf; 2200 uint16_t completed; 2201 struct ena_com_rx_ctx ena_rx_ctx; 2202 int i, rc = 0; 2203 2204 /* Check adapter state */ 2205 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2206 PMD_DRV_LOG(ALERT, 2207 "Trying to receive pkts while device is NOT running\n"); 2208 return 0; 2209 } 2210 2211 descs_in_use = rx_ring->ring_size - 2212 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2213 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2214 2215 for (completed = 0; completed < nb_pkts; completed++) { 2216 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2217 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2218 ena_rx_ctx.descs = 0; 2219 ena_rx_ctx.pkt_offset = 0; 2220 /* receive packet context */ 2221 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2222 rx_ring->ena_com_io_sq, 2223 &ena_rx_ctx); 2224 if (unlikely(rc)) { 2225 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2226 rx_ring->adapter->reset_reason = 2227 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2228 rx_ring->adapter->trigger_reset = true; 2229 ++rx_ring->rx_stats.bad_desc_num; 2230 return 0; 2231 } 2232 2233 mbuf = ena_rx_mbuf(rx_ring, 2234 ena_rx_ctx.ena_bufs, 2235 ena_rx_ctx.descs, 2236 &next_to_clean, 2237 ena_rx_ctx.pkt_offset); 2238 if (unlikely(mbuf == NULL)) { 2239 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2240 rx_ring->empty_rx_reqs[next_to_clean] = 2241 rx_ring->ena_bufs[i].req_id; 2242 next_to_clean = ENA_IDX_NEXT_MASKED( 2243 next_to_clean, rx_ring->size_mask); 2244 } 2245 break; 2246 } 2247 2248 /* fill mbuf attributes if any */ 2249 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); 2250 2251 if (unlikely(mbuf->ol_flags & 2252 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2253 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2254 ++rx_ring->rx_stats.bad_csum; 2255 } 2256 2257 mbuf->hash.rss = ena_rx_ctx.hash; 2258 2259 rx_pkts[completed] = mbuf; 2260 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2261 } 2262 2263 rx_ring->rx_stats.cnt += completed; 2264 rx_ring->next_to_clean = next_to_clean; 2265 2266 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2267 refill_threshold = 2268 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2269 (unsigned int)ENA_REFILL_THRESH_PACKET); 2270 2271 /* Burst refill to save doorbells, memory barriers, const interval */ 2272 if (free_queue_entries > refill_threshold) { 2273 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2274 ena_populate_rx_queue(rx_ring, free_queue_entries); 2275 } 2276 2277 return completed; 2278 } 2279 2280 static uint16_t 2281 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2282 uint16_t nb_pkts) 2283 { 2284 int32_t ret; 2285 uint32_t i; 2286 struct rte_mbuf *m; 2287 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2288 struct rte_ipv4_hdr *ip_hdr; 2289 uint64_t ol_flags; 2290 uint16_t frag_field; 2291 2292 for (i = 0; i != nb_pkts; i++) { 2293 m = tx_pkts[i]; 2294 ol_flags = m->ol_flags; 2295 2296 if (!(ol_flags & PKT_TX_IPV4)) 2297 continue; 2298 2299 /* If there was not L2 header length specified, assume it is 2300 * length of the ethernet header. 2301 */ 2302 if (unlikely(m->l2_len == 0)) 2303 m->l2_len = sizeof(struct rte_ether_hdr); 2304 2305 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2306 m->l2_len); 2307 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2308 2309 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2310 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2311 2312 /* If IPv4 header has DF flag enabled and TSO support is 2313 * disabled, partial chcecksum should not be calculated. 2314 */ 2315 if (!tx_ring->adapter->offloads.tso4_supported) 2316 continue; 2317 } 2318 2319 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2320 (ol_flags & PKT_TX_L4_MASK) == 2321 PKT_TX_SCTP_CKSUM) { 2322 rte_errno = ENOTSUP; 2323 return i; 2324 } 2325 2326 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2327 ret = rte_validate_tx_offload(m); 2328 if (ret != 0) { 2329 rte_errno = -ret; 2330 return i; 2331 } 2332 #endif 2333 2334 /* In case we are supposed to TSO and have DF not set (DF=0) 2335 * hardware must be provided with partial checksum, otherwise 2336 * it will take care of necessary calculations. 2337 */ 2338 2339 ret = rte_net_intel_cksum_flags_prepare(m, 2340 ol_flags & ~PKT_TX_TCP_SEG); 2341 if (ret != 0) { 2342 rte_errno = -ret; 2343 return i; 2344 } 2345 } 2346 2347 return i; 2348 } 2349 2350 static void ena_update_hints(struct ena_adapter *adapter, 2351 struct ena_admin_ena_hw_hints *hints) 2352 { 2353 if (hints->admin_completion_tx_timeout) 2354 adapter->ena_dev.admin_queue.completion_timeout = 2355 hints->admin_completion_tx_timeout * 1000; 2356 2357 if (hints->mmio_read_timeout) 2358 /* convert to usec */ 2359 adapter->ena_dev.mmio_read.reg_read_to = 2360 hints->mmio_read_timeout * 1000; 2361 2362 if (hints->driver_watchdog_timeout) { 2363 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2364 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2365 else 2366 // Convert msecs to ticks 2367 adapter->keep_alive_timeout = 2368 (hints->driver_watchdog_timeout * 2369 rte_get_timer_hz()) / 1000; 2370 } 2371 } 2372 2373 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2374 struct rte_mbuf *mbuf) 2375 { 2376 struct ena_com_dev *ena_dev; 2377 int num_segments, header_len, rc; 2378 2379 ena_dev = &tx_ring->adapter->ena_dev; 2380 num_segments = mbuf->nb_segs; 2381 header_len = mbuf->data_len; 2382 2383 if (likely(num_segments < tx_ring->sgl_size)) 2384 return 0; 2385 2386 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2387 (num_segments == tx_ring->sgl_size) && 2388 (header_len < tx_ring->tx_max_header_size)) 2389 return 0; 2390 2391 ++tx_ring->tx_stats.linearize; 2392 rc = rte_pktmbuf_linearize(mbuf); 2393 if (unlikely(rc)) { 2394 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2395 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2396 ++tx_ring->tx_stats.linearize_failed; 2397 return rc; 2398 } 2399 2400 return rc; 2401 } 2402 2403 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2404 struct ena_tx_buffer *tx_info, 2405 struct rte_mbuf *mbuf, 2406 void **push_header, 2407 uint16_t *header_len) 2408 { 2409 struct ena_com_buf *ena_buf; 2410 uint16_t delta, seg_len, push_len; 2411 2412 delta = 0; 2413 seg_len = mbuf->data_len; 2414 2415 tx_info->mbuf = mbuf; 2416 ena_buf = tx_info->bufs; 2417 2418 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2419 /* 2420 * Tx header might be (and will be in most cases) smaller than 2421 * tx_max_header_size. But it's not an issue to send more data 2422 * to the device, than actually needed if the mbuf size is 2423 * greater than tx_max_header_size. 2424 */ 2425 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2426 *header_len = push_len; 2427 2428 if (likely(push_len <= seg_len)) { 2429 /* If the push header is in the single segment, then 2430 * just point it to the 1st mbuf data. 2431 */ 2432 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2433 } else { 2434 /* If the push header lays in the several segments, copy 2435 * it to the intermediate buffer. 2436 */ 2437 rte_pktmbuf_read(mbuf, 0, push_len, 2438 tx_ring->push_buf_intermediate_buf); 2439 *push_header = tx_ring->push_buf_intermediate_buf; 2440 delta = push_len - seg_len; 2441 } 2442 } else { 2443 *push_header = NULL; 2444 *header_len = 0; 2445 push_len = 0; 2446 } 2447 2448 /* Process first segment taking into consideration pushed header */ 2449 if (seg_len > push_len) { 2450 ena_buf->paddr = mbuf->buf_iova + 2451 mbuf->data_off + 2452 push_len; 2453 ena_buf->len = seg_len - push_len; 2454 ena_buf++; 2455 tx_info->num_of_bufs++; 2456 } 2457 2458 while ((mbuf = mbuf->next) != NULL) { 2459 seg_len = mbuf->data_len; 2460 2461 /* Skip mbufs if whole data is pushed as a header */ 2462 if (unlikely(delta > seg_len)) { 2463 delta -= seg_len; 2464 continue; 2465 } 2466 2467 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2468 ena_buf->len = seg_len - delta; 2469 ena_buf++; 2470 tx_info->num_of_bufs++; 2471 2472 delta = 0; 2473 } 2474 } 2475 2476 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 2477 { 2478 struct ena_tx_buffer *tx_info; 2479 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 2480 uint16_t next_to_use; 2481 uint16_t header_len; 2482 uint16_t req_id; 2483 void *push_header; 2484 int nb_hw_desc; 2485 int rc; 2486 2487 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2488 if (unlikely(rc)) 2489 return rc; 2490 2491 next_to_use = tx_ring->next_to_use; 2492 2493 req_id = tx_ring->empty_tx_reqs[next_to_use]; 2494 tx_info = &tx_ring->tx_buffer_info[req_id]; 2495 tx_info->num_of_bufs = 0; 2496 2497 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 2498 2499 ena_tx_ctx.ena_bufs = tx_info->bufs; 2500 ena_tx_ctx.push_header = push_header; 2501 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2502 ena_tx_ctx.req_id = req_id; 2503 ena_tx_ctx.header_len = header_len; 2504 2505 /* Set Tx offloads flags, if applicable */ 2506 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 2507 tx_ring->disable_meta_caching); 2508 2509 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2510 &ena_tx_ctx))) { 2511 PMD_DRV_LOG(DEBUG, 2512 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2513 tx_ring->id); 2514 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2515 } 2516 2517 /* prepare the packet's descriptors to dma engine */ 2518 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2519 &nb_hw_desc); 2520 if (unlikely(rc)) { 2521 ++tx_ring->tx_stats.prepare_ctx_err; 2522 return rc; 2523 } 2524 2525 tx_info->tx_descs = nb_hw_desc; 2526 2527 tx_ring->tx_stats.cnt++; 2528 tx_ring->tx_stats.bytes += mbuf->pkt_len; 2529 2530 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 2531 tx_ring->size_mask); 2532 2533 return 0; 2534 } 2535 2536 static void ena_tx_cleanup(struct ena_ring *tx_ring) 2537 { 2538 unsigned int cleanup_budget; 2539 unsigned int total_tx_descs = 0; 2540 uint16_t next_to_clean = tx_ring->next_to_clean; 2541 2542 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2543 (unsigned int)ENA_REFILL_THRESH_PACKET); 2544 2545 while (likely(total_tx_descs < cleanup_budget)) { 2546 struct rte_mbuf *mbuf; 2547 struct ena_tx_buffer *tx_info; 2548 uint16_t req_id; 2549 2550 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 2551 break; 2552 2553 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 2554 break; 2555 2556 /* Get Tx info & store how many descs were processed */ 2557 tx_info = &tx_ring->tx_buffer_info[req_id]; 2558 2559 mbuf = tx_info->mbuf; 2560 rte_pktmbuf_free(mbuf); 2561 2562 tx_info->mbuf = NULL; 2563 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 2564 2565 total_tx_descs += tx_info->tx_descs; 2566 2567 /* Put back descriptor to the ring for reuse */ 2568 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 2569 tx_ring->size_mask); 2570 } 2571 2572 if (likely(total_tx_descs > 0)) { 2573 /* acknowledge completion of sent packets */ 2574 tx_ring->next_to_clean = next_to_clean; 2575 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2576 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2577 } 2578 } 2579 2580 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2581 uint16_t nb_pkts) 2582 { 2583 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2584 uint16_t sent_idx = 0; 2585 2586 /* Check adapter state */ 2587 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2588 PMD_DRV_LOG(ALERT, 2589 "Trying to xmit pkts while device is NOT running\n"); 2590 return 0; 2591 } 2592 2593 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), 2594 nb_pkts); 2595 2596 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2597 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 2598 break; 2599 2600 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 2601 tx_ring->size_mask)]); 2602 } 2603 2604 tx_ring->tx_stats.available_desc = 2605 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2606 2607 /* If there are ready packets to be xmitted... */ 2608 if (sent_idx > 0) { 2609 /* ...let HW do its best :-) */ 2610 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2611 tx_ring->tx_stats.doorbells++; 2612 } 2613 2614 ena_tx_cleanup(tx_ring); 2615 2616 tx_ring->tx_stats.available_desc = 2617 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2618 tx_ring->tx_stats.tx_poll++; 2619 2620 return sent_idx; 2621 } 2622 2623 int ena_copy_eni_stats(struct ena_adapter *adapter) 2624 { 2625 struct ena_admin_eni_stats admin_eni_stats; 2626 int rc; 2627 2628 rte_spinlock_lock(&adapter->admin_lock); 2629 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats); 2630 rte_spinlock_unlock(&adapter->admin_lock); 2631 if (rc != 0) { 2632 if (rc == ENA_COM_UNSUPPORTED) { 2633 PMD_DRV_LOG(DEBUG, 2634 "Retrieving ENI metrics is not supported.\n"); 2635 } else { 2636 PMD_DRV_LOG(WARNING, 2637 "Failed to get ENI metrics: %d\n", rc); 2638 } 2639 return rc; 2640 } 2641 2642 rte_memcpy(&adapter->eni_stats, &admin_eni_stats, 2643 sizeof(struct ena_stats_eni)); 2644 2645 return 0; 2646 } 2647 2648 /** 2649 * DPDK callback to retrieve names of extended device statistics 2650 * 2651 * @param dev 2652 * Pointer to Ethernet device structure. 2653 * @param[out] xstats_names 2654 * Buffer to insert names into. 2655 * @param n 2656 * Number of names. 2657 * 2658 * @return 2659 * Number of xstats names. 2660 */ 2661 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2662 struct rte_eth_xstat_name *xstats_names, 2663 unsigned int n) 2664 { 2665 unsigned int xstats_count = ena_xstats_calc_num(dev); 2666 unsigned int stat, i, count = 0; 2667 2668 if (n < xstats_count || !xstats_names) 2669 return xstats_count; 2670 2671 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2672 strcpy(xstats_names[count].name, 2673 ena_stats_global_strings[stat].name); 2674 2675 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) 2676 strcpy(xstats_names[count].name, 2677 ena_stats_eni_strings[stat].name); 2678 2679 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2680 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2681 snprintf(xstats_names[count].name, 2682 sizeof(xstats_names[count].name), 2683 "rx_q%d_%s", i, 2684 ena_stats_rx_strings[stat].name); 2685 2686 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2687 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2688 snprintf(xstats_names[count].name, 2689 sizeof(xstats_names[count].name), 2690 "tx_q%d_%s", i, 2691 ena_stats_tx_strings[stat].name); 2692 2693 return xstats_count; 2694 } 2695 2696 /** 2697 * DPDK callback to get extended device statistics. 2698 * 2699 * @param dev 2700 * Pointer to Ethernet device structure. 2701 * @param[out] stats 2702 * Stats table output buffer. 2703 * @param n 2704 * The size of the stats table. 2705 * 2706 * @return 2707 * Number of xstats on success, negative on failure. 2708 */ 2709 static int ena_xstats_get(struct rte_eth_dev *dev, 2710 struct rte_eth_xstat *xstats, 2711 unsigned int n) 2712 { 2713 struct ena_adapter *adapter = dev->data->dev_private; 2714 unsigned int xstats_count = ena_xstats_calc_num(dev); 2715 unsigned int stat, i, count = 0; 2716 int stat_offset; 2717 void *stats_begin; 2718 2719 if (n < xstats_count) 2720 return xstats_count; 2721 2722 if (!xstats) 2723 return 0; 2724 2725 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2726 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2727 stats_begin = &adapter->dev_stats; 2728 2729 xstats[count].id = count; 2730 xstats[count].value = *((uint64_t *) 2731 ((char *)stats_begin + stat_offset)); 2732 } 2733 2734 /* Even if the function below fails, we should copy previous (or initial 2735 * values) to keep structure of rte_eth_xstat consistent. 2736 */ 2737 ena_copy_eni_stats(adapter); 2738 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) { 2739 stat_offset = ena_stats_eni_strings[stat].stat_offset; 2740 stats_begin = &adapter->eni_stats; 2741 2742 xstats[count].id = count; 2743 xstats[count].value = *((uint64_t *) 2744 ((char *)stats_begin + stat_offset)); 2745 } 2746 2747 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2748 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2749 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2750 stats_begin = &adapter->rx_ring[i].rx_stats; 2751 2752 xstats[count].id = count; 2753 xstats[count].value = *((uint64_t *) 2754 ((char *)stats_begin + stat_offset)); 2755 } 2756 } 2757 2758 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2759 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2760 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2761 stats_begin = &adapter->tx_ring[i].rx_stats; 2762 2763 xstats[count].id = count; 2764 xstats[count].value = *((uint64_t *) 2765 ((char *)stats_begin + stat_offset)); 2766 } 2767 } 2768 2769 return count; 2770 } 2771 2772 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2773 const uint64_t *ids, 2774 uint64_t *values, 2775 unsigned int n) 2776 { 2777 struct ena_adapter *adapter = dev->data->dev_private; 2778 uint64_t id; 2779 uint64_t rx_entries, tx_entries; 2780 unsigned int i; 2781 int qid; 2782 int valid = 0; 2783 bool was_eni_copied = false; 2784 2785 for (i = 0; i < n; ++i) { 2786 id = ids[i]; 2787 /* Check if id belongs to global statistics */ 2788 if (id < ENA_STATS_ARRAY_GLOBAL) { 2789 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2790 ++valid; 2791 continue; 2792 } 2793 2794 /* Check if id belongs to ENI statistics */ 2795 id -= ENA_STATS_ARRAY_GLOBAL; 2796 if (id < ENA_STATS_ARRAY_ENI) { 2797 /* Avoid reading ENI stats multiple times in a single 2798 * function call, as it requires communication with the 2799 * admin queue. 2800 */ 2801 if (!was_eni_copied) { 2802 was_eni_copied = true; 2803 ena_copy_eni_stats(adapter); 2804 } 2805 values[i] = *((uint64_t *)&adapter->eni_stats + id); 2806 ++valid; 2807 continue; 2808 } 2809 2810 /* Check if id belongs to rx queue statistics */ 2811 id -= ENA_STATS_ARRAY_ENI; 2812 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2813 if (id < rx_entries) { 2814 qid = id % dev->data->nb_rx_queues; 2815 id /= dev->data->nb_rx_queues; 2816 values[i] = *((uint64_t *) 2817 &adapter->rx_ring[qid].rx_stats + id); 2818 ++valid; 2819 continue; 2820 } 2821 /* Check if id belongs to rx queue statistics */ 2822 id -= rx_entries; 2823 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2824 if (id < tx_entries) { 2825 qid = id % dev->data->nb_tx_queues; 2826 id /= dev->data->nb_tx_queues; 2827 values[i] = *((uint64_t *) 2828 &adapter->tx_ring[qid].tx_stats + id); 2829 ++valid; 2830 continue; 2831 } 2832 } 2833 2834 return valid; 2835 } 2836 2837 static int ena_process_bool_devarg(const char *key, 2838 const char *value, 2839 void *opaque) 2840 { 2841 struct ena_adapter *adapter = opaque; 2842 bool bool_value; 2843 2844 /* Parse the value. */ 2845 if (strcmp(value, "1") == 0) { 2846 bool_value = true; 2847 } else if (strcmp(value, "0") == 0) { 2848 bool_value = false; 2849 } else { 2850 PMD_INIT_LOG(ERR, 2851 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2852 value, key); 2853 return -EINVAL; 2854 } 2855 2856 /* Now, assign it to the proper adapter field. */ 2857 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) 2858 adapter->use_large_llq_hdr = bool_value; 2859 2860 return 0; 2861 } 2862 2863 static int ena_parse_devargs(struct ena_adapter *adapter, 2864 struct rte_devargs *devargs) 2865 { 2866 static const char * const allowed_args[] = { 2867 ENA_DEVARG_LARGE_LLQ_HDR, 2868 }; 2869 struct rte_kvargs *kvlist; 2870 int rc; 2871 2872 if (devargs == NULL) 2873 return 0; 2874 2875 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2876 if (kvlist == NULL) { 2877 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2878 devargs->args); 2879 return -EINVAL; 2880 } 2881 2882 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2883 ena_process_bool_devarg, adapter); 2884 2885 rte_kvargs_free(kvlist); 2886 2887 return rc; 2888 } 2889 2890 /********************************************************************* 2891 * PMD configuration 2892 *********************************************************************/ 2893 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2894 struct rte_pci_device *pci_dev) 2895 { 2896 return rte_eth_dev_pci_generic_probe(pci_dev, 2897 sizeof(struct ena_adapter), eth_ena_dev_init); 2898 } 2899 2900 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2901 { 2902 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2903 } 2904 2905 static struct rte_pci_driver rte_ena_pmd = { 2906 .id_table = pci_id_ena_map, 2907 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2908 RTE_PCI_DRV_WC_ACTIVATE, 2909 .probe = eth_ena_pci_probe, 2910 .remove = eth_ena_pci_remove, 2911 }; 2912 2913 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2914 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2915 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2916 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2917 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE); 2918 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE); 2919 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2920 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE); 2921 #endif 2922 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2923 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE); 2924 #endif 2925 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2926 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE); 2927 #endif 2928 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2929 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); 2930 #endif 2931 2932 /****************************************************************************** 2933 ******************************** AENQ Handlers ******************************* 2934 *****************************************************************************/ 2935 static void ena_update_on_link_change(void *adapter_data, 2936 struct ena_admin_aenq_entry *aenq_e) 2937 { 2938 struct rte_eth_dev *eth_dev; 2939 struct ena_adapter *adapter; 2940 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2941 uint32_t status; 2942 2943 adapter = adapter_data; 2944 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2945 eth_dev = adapter->rte_dev; 2946 2947 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2948 adapter->link_status = status; 2949 2950 ena_link_update(eth_dev, 0); 2951 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2952 } 2953 2954 static void ena_notification(void *data, 2955 struct ena_admin_aenq_entry *aenq_e) 2956 { 2957 struct ena_adapter *adapter = data; 2958 struct ena_admin_ena_hw_hints *hints; 2959 2960 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2961 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2962 aenq_e->aenq_common_desc.group, 2963 ENA_ADMIN_NOTIFICATION); 2964 2965 switch (aenq_e->aenq_common_desc.syndrom) { 2966 case ENA_ADMIN_UPDATE_HINTS: 2967 hints = (struct ena_admin_ena_hw_hints *) 2968 (&aenq_e->inline_data_w4); 2969 ena_update_hints(adapter, hints); 2970 break; 2971 default: 2972 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2973 aenq_e->aenq_common_desc.syndrom); 2974 } 2975 } 2976 2977 static void ena_keep_alive(void *adapter_data, 2978 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2979 { 2980 struct ena_adapter *adapter = adapter_data; 2981 struct ena_admin_aenq_keep_alive_desc *desc; 2982 uint64_t rx_drops; 2983 uint64_t tx_drops; 2984 2985 adapter->timestamp_wd = rte_get_timer_cycles(); 2986 2987 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2988 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2989 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 2990 2991 adapter->drv_stats->rx_drops = rx_drops; 2992 adapter->dev_stats.tx_drops = tx_drops; 2993 } 2994 2995 /** 2996 * This handler will called for unknown event group or unimplemented handlers 2997 **/ 2998 static void unimplemented_aenq_handler(__rte_unused void *data, 2999 __rte_unused struct ena_admin_aenq_entry *aenq_e) 3000 { 3001 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 3002 "unimplemented handler\n"); 3003 } 3004 3005 static struct ena_aenq_handlers aenq_handlers = { 3006 .handlers = { 3007 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3008 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3009 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 3010 }, 3011 .unimplemented_handler = unimplemented_aenq_handler 3012 }; 3013