1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_errno.h> 8 #include <rte_version.h> 9 #include <rte_net.h> 10 #include <rte_kvargs.h> 11 12 #include "ena_ethdev.h" 13 #include "ena_logs.h" 14 #include "ena_platform.h" 15 #include "ena_com.h" 16 #include "ena_eth_com.h" 17 18 #include <ena_common_defs.h> 19 #include <ena_regs_defs.h> 20 #include <ena_admin_defs.h> 21 #include <ena_eth_io_defs.h> 22 23 #define DRV_MODULE_VER_MAJOR 2 24 #define DRV_MODULE_VER_MINOR 8 25 #define DRV_MODULE_VER_SUBMINOR 0 26 27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 28 29 #define GET_L4_HDR_LEN(mbuf) \ 30 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 31 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 32 33 #define ETH_GSTRING_LEN 32 34 35 #define ARRAY_SIZE(x) RTE_DIM(x) 36 37 #define ENA_MIN_RING_DESC 128 38 39 /* 40 * We should try to keep ENA_CLEANUP_BUF_SIZE lower than 41 * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache. 42 */ 43 #define ENA_CLEANUP_BUF_SIZE 256 44 45 #define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP) 46 47 struct ena_stats { 48 char name[ETH_GSTRING_LEN]; 49 int stat_offset; 50 }; 51 52 #define ENA_STAT_ENTRY(stat, stat_type) { \ 53 .name = #stat, \ 54 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 55 } 56 57 #define ENA_STAT_RX_ENTRY(stat) \ 58 ENA_STAT_ENTRY(stat, rx) 59 60 #define ENA_STAT_TX_ENTRY(stat) \ 61 ENA_STAT_ENTRY(stat, tx) 62 63 #define ENA_STAT_METRICS_ENTRY(stat) \ 64 ENA_STAT_ENTRY(stat, metrics) 65 66 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 67 ENA_STAT_ENTRY(stat, dev) 68 69 #define ENA_STAT_ENA_SRD_ENTRY(stat) \ 70 ENA_STAT_ENTRY(stat, srd) 71 72 /* Device arguments */ 73 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 74 /* Timeout in seconds after which a single uncompleted Tx packet should be 75 * considered as a missing. 76 */ 77 #define ENA_DEVARG_MISS_TXC_TO "miss_txc_to" 78 /* 79 * Controls whether LLQ should be used (if available). Enabled by default. 80 * NOTE: It's highly not recommended to disable the LLQ, as it may lead to a 81 * huge performance degradation on 6th generation AWS instances. 82 */ 83 #define ENA_DEVARG_ENABLE_LLQ "enable_llq" 84 85 /* 86 * Each rte_memzone should have unique name. 87 * To satisfy it, count number of allocation and add it to name. 88 */ 89 rte_atomic64_t ena_alloc_cnt; 90 91 static const struct ena_stats ena_stats_global_strings[] = { 92 ENA_STAT_GLOBAL_ENTRY(wd_expired), 93 ENA_STAT_GLOBAL_ENTRY(dev_start), 94 ENA_STAT_GLOBAL_ENTRY(dev_stop), 95 ENA_STAT_GLOBAL_ENTRY(tx_drops), 96 ENA_STAT_GLOBAL_ENTRY(rx_overruns), 97 }; 98 99 /* 100 * The legacy metrics (also known as eni stats) consisted of 5 stats, while the reworked 101 * metrics (also known as customer metrics) support an additional stat. 102 */ 103 static struct ena_stats ena_stats_metrics_strings[] = { 104 ENA_STAT_METRICS_ENTRY(bw_in_allowance_exceeded), 105 ENA_STAT_METRICS_ENTRY(bw_out_allowance_exceeded), 106 ENA_STAT_METRICS_ENTRY(pps_allowance_exceeded), 107 ENA_STAT_METRICS_ENTRY(conntrack_allowance_exceeded), 108 ENA_STAT_METRICS_ENTRY(linklocal_allowance_exceeded), 109 ENA_STAT_METRICS_ENTRY(conntrack_allowance_available), 110 }; 111 112 static const struct ena_stats ena_stats_srd_strings[] = { 113 ENA_STAT_ENA_SRD_ENTRY(ena_srd_mode), 114 ENA_STAT_ENA_SRD_ENTRY(ena_srd_tx_pkts), 115 ENA_STAT_ENA_SRD_ENTRY(ena_srd_eligible_tx_pkts), 116 ENA_STAT_ENA_SRD_ENTRY(ena_srd_rx_pkts), 117 ENA_STAT_ENA_SRD_ENTRY(ena_srd_resource_utilization), 118 }; 119 120 static const struct ena_stats ena_stats_tx_strings[] = { 121 ENA_STAT_TX_ENTRY(cnt), 122 ENA_STAT_TX_ENTRY(bytes), 123 ENA_STAT_TX_ENTRY(prepare_ctx_err), 124 ENA_STAT_TX_ENTRY(tx_poll), 125 ENA_STAT_TX_ENTRY(doorbells), 126 ENA_STAT_TX_ENTRY(bad_req_id), 127 ENA_STAT_TX_ENTRY(available_desc), 128 ENA_STAT_TX_ENTRY(missed_tx), 129 }; 130 131 static const struct ena_stats ena_stats_rx_strings[] = { 132 ENA_STAT_RX_ENTRY(cnt), 133 ENA_STAT_RX_ENTRY(bytes), 134 ENA_STAT_RX_ENTRY(refill_partial), 135 ENA_STAT_RX_ENTRY(l3_csum_bad), 136 ENA_STAT_RX_ENTRY(l4_csum_bad), 137 ENA_STAT_RX_ENTRY(l4_csum_good), 138 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 139 ENA_STAT_RX_ENTRY(bad_desc_num), 140 ENA_STAT_RX_ENTRY(bad_req_id), 141 }; 142 143 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 144 #define ENA_STATS_ARRAY_METRICS ARRAY_SIZE(ena_stats_metrics_strings) 145 #define ENA_STATS_ARRAY_METRICS_LEGACY (ENA_STATS_ARRAY_METRICS - 1) 146 #define ENA_STATS_ARRAY_ENA_SRD ARRAY_SIZE(ena_stats_srd_strings) 147 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 148 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 149 150 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\ 151 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\ 152 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\ 153 RTE_ETH_TX_OFFLOAD_TCP_TSO) 154 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\ 155 RTE_MBUF_F_TX_IP_CKSUM |\ 156 RTE_MBUF_F_TX_TCP_SEG) 157 158 /** Vendor ID used by Amazon devices */ 159 #define PCI_VENDOR_ID_AMAZON 0x1D0F 160 /** Amazon devices */ 161 #define PCI_DEVICE_ID_ENA_VF 0xEC20 162 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21 163 164 #define ENA_TX_OFFLOAD_MASK (RTE_MBUF_F_TX_L4_MASK | \ 165 RTE_MBUF_F_TX_IPV6 | \ 166 RTE_MBUF_F_TX_IPV4 | \ 167 RTE_MBUF_F_TX_IP_CKSUM | \ 168 RTE_MBUF_F_TX_TCP_SEG) 169 170 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 171 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 172 173 /** HW specific offloads capabilities. */ 174 /* IPv4 checksum offload. */ 175 #define ENA_L3_IPV4_CSUM 0x0001 176 /* TCP/UDP checksum offload for IPv4 packets. */ 177 #define ENA_L4_IPV4_CSUM 0x0002 178 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */ 179 #define ENA_L4_IPV4_CSUM_PARTIAL 0x0004 180 /* TCP/UDP checksum offload for IPv6 packets. */ 181 #define ENA_L4_IPV6_CSUM 0x0008 182 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */ 183 #define ENA_L4_IPV6_CSUM_PARTIAL 0x0010 184 /* TSO support for IPv4 packets. */ 185 #define ENA_IPV4_TSO 0x0020 186 187 /* Device supports setting RSS hash. */ 188 #define ENA_RX_RSS_HASH 0x0040 189 190 static const struct rte_pci_id pci_id_ena_map[] = { 191 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 192 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) }, 193 { .device_id = 0 }, 194 }; 195 196 static struct ena_aenq_handlers aenq_handlers; 197 198 static int ena_device_init(struct ena_adapter *adapter, 199 struct rte_pci_device *pdev, 200 struct ena_com_dev_get_features_ctx *get_feat_ctx); 201 static int ena_dev_configure(struct rte_eth_dev *dev); 202 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 203 struct ena_tx_buffer *tx_info, 204 struct rte_mbuf *mbuf, 205 void **push_header, 206 uint16_t *header_len); 207 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 208 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt); 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 210 uint16_t nb_pkts); 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 212 uint16_t nb_pkts); 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 214 uint16_t nb_desc, unsigned int socket_id, 215 const struct rte_eth_txconf *tx_conf); 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 217 uint16_t nb_desc, unsigned int socket_id, 218 const struct rte_eth_rxconf *rx_conf, 219 struct rte_mempool *mp); 220 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 221 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 222 struct ena_com_rx_buf_info *ena_bufs, 223 uint32_t descs, 224 uint16_t *next_to_clean, 225 uint8_t offset); 226 static uint16_t eth_ena_recv_pkts(void *rx_queue, 227 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 228 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 229 struct rte_mbuf *mbuf, uint16_t id); 230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 231 static void ena_init_rings(struct ena_adapter *adapter, 232 bool disable_meta_caching); 233 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 234 static int ena_start(struct rte_eth_dev *dev); 235 static int ena_stop(struct rte_eth_dev *dev); 236 static int ena_close(struct rte_eth_dev *dev); 237 static int ena_dev_reset(struct rte_eth_dev *dev); 238 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 239 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 240 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 241 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 242 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 243 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 244 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 245 static int ena_link_update(struct rte_eth_dev *dev, 246 int wait_to_complete); 247 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring); 248 static void ena_queue_stop(struct ena_ring *ring); 249 static void ena_queue_stop_all(struct rte_eth_dev *dev, 250 enum ena_ring_type ring_type); 251 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring); 252 static int ena_queue_start_all(struct rte_eth_dev *dev, 253 enum ena_ring_type ring_type); 254 static void ena_stats_restart(struct rte_eth_dev *dev); 255 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter); 256 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter); 257 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter); 258 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter); 259 static int ena_infos_get(struct rte_eth_dev *dev, 260 struct rte_eth_dev_info *dev_info); 261 static void ena_interrupt_handler_rte(void *cb_arg); 262 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 263 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 264 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 265 static int ena_xstats_get_names(struct rte_eth_dev *dev, 266 struct rte_eth_xstat_name *xstats_names, 267 unsigned int n); 268 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev, 269 const uint64_t *ids, 270 struct rte_eth_xstat_name *xstats_names, 271 unsigned int size); 272 static int ena_xstats_get(struct rte_eth_dev *dev, 273 struct rte_eth_xstat *stats, 274 unsigned int n); 275 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 276 const uint64_t *ids, 277 uint64_t *values, 278 unsigned int n); 279 static int ena_process_bool_devarg(const char *key, 280 const char *value, 281 void *opaque); 282 static int ena_parse_devargs(struct ena_adapter *adapter, 283 struct rte_devargs *devargs); 284 static void ena_copy_customer_metrics(struct ena_adapter *adapter, 285 uint64_t *buf, 286 size_t buf_size); 287 static void ena_copy_ena_srd_info(struct ena_adapter *adapter, 288 struct ena_stats_srd *srd_info); 289 static int ena_setup_rx_intr(struct rte_eth_dev *dev); 290 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, 291 uint16_t queue_id); 292 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, 293 uint16_t queue_id); 294 static int ena_configure_aenq(struct ena_adapter *adapter); 295 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, 296 const void *peer); 297 298 static const struct eth_dev_ops ena_dev_ops = { 299 .dev_configure = ena_dev_configure, 300 .dev_infos_get = ena_infos_get, 301 .rx_queue_setup = ena_rx_queue_setup, 302 .tx_queue_setup = ena_tx_queue_setup, 303 .dev_start = ena_start, 304 .dev_stop = ena_stop, 305 .link_update = ena_link_update, 306 .stats_get = ena_stats_get, 307 .xstats_get_names = ena_xstats_get_names, 308 .xstats_get_names_by_id = ena_xstats_get_names_by_id, 309 .xstats_get = ena_xstats_get, 310 .xstats_get_by_id = ena_xstats_get_by_id, 311 .mtu_set = ena_mtu_set, 312 .rx_queue_release = ena_rx_queue_release, 313 .tx_queue_release = ena_tx_queue_release, 314 .dev_close = ena_close, 315 .dev_reset = ena_dev_reset, 316 .reta_update = ena_rss_reta_update, 317 .reta_query = ena_rss_reta_query, 318 .rx_queue_intr_enable = ena_rx_queue_intr_enable, 319 .rx_queue_intr_disable = ena_rx_queue_intr_disable, 320 .rss_hash_update = ena_rss_hash_update, 321 .rss_hash_conf_get = ena_rss_hash_conf_get, 322 .tx_done_cleanup = ena_tx_cleanup, 323 }; 324 325 /********************************************************************* 326 * Multi-Process communication bits 327 *********************************************************************/ 328 /* rte_mp IPC message name */ 329 #define ENA_MP_NAME "net_ena_mp" 330 /* Request timeout in seconds */ 331 #define ENA_MP_REQ_TMO 5 332 333 /** Proxy request type */ 334 enum ena_mp_req { 335 ENA_MP_DEV_STATS_GET, 336 ENA_MP_ENI_STATS_GET, 337 ENA_MP_MTU_SET, 338 ENA_MP_IND_TBL_GET, 339 ENA_MP_IND_TBL_SET, 340 ENA_MP_CUSTOMER_METRICS_GET, 341 ENA_MP_SRD_STATS_GET, 342 }; 343 344 /** Proxy message body. Shared between requests and responses. */ 345 struct ena_mp_body { 346 /* Message type */ 347 enum ena_mp_req type; 348 int port_id; 349 /* Processing result. Set in replies. 0 if message succeeded, negative 350 * error code otherwise. 351 */ 352 int result; 353 union { 354 int mtu; /* For ENA_MP_MTU_SET */ 355 } args; 356 }; 357 358 /** 359 * Initialize IPC message. 360 * 361 * @param[out] msg 362 * Pointer to the message to initialize. 363 * @param[in] type 364 * Message type. 365 * @param[in] port_id 366 * Port ID of target device. 367 * 368 */ 369 static void 370 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id) 371 { 372 struct ena_mp_body *body = (struct ena_mp_body *)&msg->param; 373 374 memset(msg, 0, sizeof(*msg)); 375 strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name)); 376 msg->len_param = sizeof(*body); 377 body->type = type; 378 body->port_id = port_id; 379 } 380 381 /********************************************************************* 382 * Multi-Process communication PMD API 383 *********************************************************************/ 384 /** 385 * Define proxy request descriptor 386 * 387 * Used to define all structures and functions required for proxying a given 388 * function to the primary process including the code to perform to prepare the 389 * request and process the response. 390 * 391 * @param[in] f 392 * Name of the function to proxy 393 * @param[in] t 394 * Message type to use 395 * @param[in] prep 396 * Body of a function to prepare the request in form of a statement 397 * expression. It is passed all the original function arguments along with two 398 * extra ones: 399 * - struct ena_adapter *adapter - PMD data of the device calling the proxy. 400 * - struct ena_mp_body *req - body of a request to prepare. 401 * @param[in] proc 402 * Body of a function to process the response in form of a statement 403 * expression. It is passed all the original function arguments along with two 404 * extra ones: 405 * - struct ena_adapter *adapter - PMD data of the device calling the proxy. 406 * - struct ena_mp_body *rsp - body of a response to process. 407 * @param ... 408 * Proxied function's arguments 409 * 410 * @note Inside prep and proc any parameters which aren't used should be marked 411 * as such (with ENA_TOUCH or __rte_unused). 412 */ 413 #define ENA_PROXY_DESC(f, t, prep, proc, ...) \ 414 static const enum ena_mp_req mp_type_ ## f = t; \ 415 static const char *mp_name_ ## f = #t; \ 416 static void mp_prep_ ## f(struct ena_adapter *adapter, \ 417 struct ena_mp_body *req, \ 418 __VA_ARGS__) \ 419 { \ 420 prep; \ 421 } \ 422 static void mp_proc_ ## f(struct ena_adapter *adapter, \ 423 struct ena_mp_body *rsp, \ 424 __VA_ARGS__) \ 425 { \ 426 proc; \ 427 } 428 429 /** 430 * Proxy wrapper for calling primary functions in a secondary process. 431 * 432 * Depending on whether called in primary or secondary process, calls the 433 * @p func directly or proxies the call to the primary process via rte_mp IPC. 434 * This macro requires a proxy request descriptor to be defined for @p func 435 * using ENA_PROXY_DESC() macro. 436 * 437 * @param[in/out] a 438 * Device PMD data. Used for sending the message and sharing message results 439 * between primary and secondary. 440 * @param[in] f 441 * Function to proxy. 442 * @param ... 443 * Arguments of @p func. 444 * 445 * @return 446 * - 0: Processing succeeded and response handler was called. 447 * - -EPERM: IPC is unavailable on this platform. This means only primary 448 * process may call the proxied function. 449 * - -EIO: IPC returned error on request send. Inspect rte_errno detailed 450 * error code. 451 * - Negative error code from the proxied function. 452 * 453 * @note This mechanism is geared towards control-path tasks. Avoid calling it 454 * in fast-path unless unbound delays are allowed. This is due to the IPC 455 * mechanism itself (socket based). 456 * @note Due to IPC parameter size limitations the proxy logic shares call 457 * results through the struct ena_adapter shared memory. This makes the 458 * proxy mechanism strictly single-threaded. Therefore be sure to make all 459 * calls to the same proxied function under the same lock. 460 */ 461 #define ENA_PROXY(a, f, ...) \ 462 __extension__ ({ \ 463 struct ena_adapter *_a = (a); \ 464 struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO }; \ 465 struct ena_mp_body *req, *rsp; \ 466 struct rte_mp_reply mp_rep; \ 467 struct rte_mp_msg mp_req; \ 468 int ret; \ 469 \ 470 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { \ 471 ret = f(__VA_ARGS__); \ 472 } else { \ 473 /* Prepare and send request */ \ 474 req = (struct ena_mp_body *)&mp_req.param; \ 475 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \ 476 mp_prep_ ## f(_a, req, ## __VA_ARGS__); \ 477 \ 478 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts); \ 479 if (likely(!ret)) { \ 480 RTE_ASSERT(mp_rep.nb_received == 1); \ 481 rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \ 482 ret = rsp->result; \ 483 if (ret == 0) { \ 484 mp_proc_##f(_a, rsp, ## __VA_ARGS__); \ 485 } else { \ 486 PMD_DRV_LOG(ERR, \ 487 "%s returned error: %d\n", \ 488 mp_name_ ## f, rsp->result);\ 489 } \ 490 free(mp_rep.msgs); \ 491 } else if (rte_errno == ENOTSUP) { \ 492 PMD_DRV_LOG(ERR, \ 493 "No IPC, can't proxy to primary\n");\ 494 ret = -rte_errno; \ 495 } else { \ 496 PMD_DRV_LOG(ERR, "Request %s failed: %s\n", \ 497 mp_name_ ## f, \ 498 rte_strerror(rte_errno)); \ 499 ret = -EIO; \ 500 } \ 501 } \ 502 ret; \ 503 }) 504 505 /********************************************************************* 506 * Multi-Process communication request descriptors 507 *********************************************************************/ 508 509 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET, 510 __extension__ ({ 511 ENA_TOUCH(adapter); 512 ENA_TOUCH(req); 513 ENA_TOUCH(ena_dev); 514 ENA_TOUCH(stats); 515 }), 516 __extension__ ({ 517 ENA_TOUCH(rsp); 518 ENA_TOUCH(ena_dev); 519 if (stats != &adapter->basic_stats) 520 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats)); 521 }), 522 struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats); 523 524 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET, 525 __extension__ ({ 526 ENA_TOUCH(adapter); 527 ENA_TOUCH(req); 528 ENA_TOUCH(ena_dev); 529 ENA_TOUCH(stats); 530 }), 531 __extension__ ({ 532 ENA_TOUCH(rsp); 533 ENA_TOUCH(ena_dev); 534 if (stats != (struct ena_admin_eni_stats *)&adapter->metrics_stats) 535 rte_memcpy(stats, &adapter->metrics_stats, sizeof(*stats)); 536 }), 537 struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats); 538 539 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET, 540 __extension__ ({ 541 ENA_TOUCH(adapter); 542 ENA_TOUCH(ena_dev); 543 req->args.mtu = mtu; 544 }), 545 __extension__ ({ 546 ENA_TOUCH(adapter); 547 ENA_TOUCH(rsp); 548 ENA_TOUCH(ena_dev); 549 ENA_TOUCH(mtu); 550 }), 551 struct ena_com_dev *ena_dev, int mtu); 552 553 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET, 554 __extension__ ({ 555 ENA_TOUCH(adapter); 556 ENA_TOUCH(req); 557 ENA_TOUCH(ena_dev); 558 }), 559 __extension__ ({ 560 ENA_TOUCH(adapter); 561 ENA_TOUCH(rsp); 562 ENA_TOUCH(ena_dev); 563 }), 564 struct ena_com_dev *ena_dev); 565 566 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET, 567 __extension__ ({ 568 ENA_TOUCH(adapter); 569 ENA_TOUCH(req); 570 ENA_TOUCH(ena_dev); 571 ENA_TOUCH(ind_tbl); 572 }), 573 __extension__ ({ 574 ENA_TOUCH(rsp); 575 ENA_TOUCH(ena_dev); 576 if (ind_tbl != adapter->indirect_table) 577 rte_memcpy(ind_tbl, adapter->indirect_table, 578 sizeof(adapter->indirect_table)); 579 }), 580 struct ena_com_dev *ena_dev, u32 *ind_tbl); 581 582 ENA_PROXY_DESC(ena_com_get_customer_metrics, ENA_MP_CUSTOMER_METRICS_GET, 583 __extension__ ({ 584 ENA_TOUCH(adapter); 585 ENA_TOUCH(req); 586 ENA_TOUCH(ena_dev); 587 ENA_TOUCH(buf); 588 ENA_TOUCH(buf_size); 589 }), 590 __extension__ ({ 591 ENA_TOUCH(rsp); 592 ENA_TOUCH(ena_dev); 593 ENA_TOUCH(buf_size); 594 if (buf != (char *)&adapter->metrics_stats) 595 rte_memcpy(buf, &adapter->metrics_stats, adapter->metrics_num * sizeof(uint64_t)); 596 }), 597 struct ena_com_dev *ena_dev, char *buf, size_t buf_size); 598 599 ENA_PROXY_DESC(ena_com_get_ena_srd_info, ENA_MP_SRD_STATS_GET, 600 __extension__ ({ 601 ENA_TOUCH(adapter); 602 ENA_TOUCH(req); 603 ENA_TOUCH(ena_dev); 604 ENA_TOUCH(info); 605 }), 606 __extension__ ({ 607 ENA_TOUCH(rsp); 608 ENA_TOUCH(ena_dev); 609 if ((struct ena_stats_srd *)info != &adapter->srd_stats) 610 rte_memcpy((struct ena_stats_srd *)info, 611 &adapter->srd_stats, 612 sizeof(struct ena_stats_srd)); 613 }), 614 struct ena_com_dev *ena_dev, struct ena_admin_ena_srd_info *info); 615 616 static inline void ena_trigger_reset(struct ena_adapter *adapter, 617 enum ena_regs_reset_reason_types reason) 618 { 619 if (likely(!adapter->trigger_reset)) { 620 adapter->reset_reason = reason; 621 adapter->trigger_reset = true; 622 } 623 } 624 625 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring, 626 struct rte_mbuf *mbuf, 627 struct ena_com_rx_ctx *ena_rx_ctx, 628 bool fill_hash) 629 { 630 struct ena_stats_rx *rx_stats = &rx_ring->rx_stats; 631 uint64_t ol_flags = 0; 632 uint32_t packet_type = 0; 633 634 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 635 packet_type |= RTE_PTYPE_L4_TCP; 636 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 637 packet_type |= RTE_PTYPE_L4_UDP; 638 639 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 640 packet_type |= RTE_PTYPE_L3_IPV4; 641 if (unlikely(ena_rx_ctx->l3_csum_err)) { 642 ++rx_stats->l3_csum_bad; 643 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; 644 } else { 645 ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 646 } 647 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 648 packet_type |= RTE_PTYPE_L3_IPV6; 649 } 650 651 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) { 652 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN; 653 } else { 654 if (unlikely(ena_rx_ctx->l4_csum_err)) { 655 ++rx_stats->l4_csum_bad; 656 /* 657 * For the L4 Rx checksum offload the HW may indicate 658 * bad checksum although it's valid. Because of that, 659 * we're setting the UNKNOWN flag to let the app 660 * re-verify the checksum. 661 */ 662 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN; 663 } else { 664 ++rx_stats->l4_csum_good; 665 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 666 } 667 } 668 669 if (fill_hash && 670 likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) { 671 ol_flags |= RTE_MBUF_F_RX_RSS_HASH; 672 mbuf->hash.rss = ena_rx_ctx->hash; 673 } 674 675 mbuf->ol_flags = ol_flags; 676 mbuf->packet_type = packet_type; 677 } 678 679 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 680 struct ena_com_tx_ctx *ena_tx_ctx, 681 uint64_t queue_offloads, 682 bool disable_meta_caching) 683 { 684 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 685 686 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 687 (queue_offloads & QUEUE_OFFLOADS)) { 688 /* check if TSO is required */ 689 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) && 690 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) { 691 ena_tx_ctx->tso_enable = true; 692 693 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 694 } 695 696 /* check if L3 checksum is needed */ 697 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) && 698 (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) 699 ena_tx_ctx->l3_csum_enable = true; 700 701 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) { 702 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 703 /* For the IPv6 packets, DF always needs to be true. */ 704 ena_tx_ctx->df = 1; 705 } else { 706 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 707 708 /* set don't fragment (DF) flag */ 709 if (mbuf->packet_type & 710 (RTE_PTYPE_L4_NONFRAG 711 | RTE_PTYPE_INNER_L4_NONFRAG)) 712 ena_tx_ctx->df = 1; 713 } 714 715 /* check if L4 checksum is needed */ 716 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) && 717 (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) { 718 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 719 ena_tx_ctx->l4_csum_enable = true; 720 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == 721 RTE_MBUF_F_TX_UDP_CKSUM) && 722 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) { 723 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 724 ena_tx_ctx->l4_csum_enable = true; 725 } else { 726 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 727 ena_tx_ctx->l4_csum_enable = false; 728 } 729 730 ena_meta->mss = mbuf->tso_segsz; 731 ena_meta->l3_hdr_len = mbuf->l3_len; 732 ena_meta->l3_hdr_offset = mbuf->l2_len; 733 734 ena_tx_ctx->meta_valid = true; 735 } else if (disable_meta_caching) { 736 memset(ena_meta, 0, sizeof(*ena_meta)); 737 ena_tx_ctx->meta_valid = true; 738 } else { 739 ena_tx_ctx->meta_valid = false; 740 } 741 } 742 743 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 744 { 745 struct ena_tx_buffer *tx_info = NULL; 746 747 if (likely(req_id < tx_ring->ring_size)) { 748 tx_info = &tx_ring->tx_buffer_info[req_id]; 749 if (likely(tx_info->mbuf)) 750 return 0; 751 } 752 753 if (tx_info) 754 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf. queue %d:%d req_id %u\n", 755 tx_ring->port_id, tx_ring->id, req_id); 756 else 757 PMD_TX_LOG(ERR, "Invalid req_id: %hu in queue %d:%d\n", 758 req_id, tx_ring->port_id, tx_ring->id); 759 760 /* Trigger device reset */ 761 ++tx_ring->tx_stats.bad_req_id; 762 ena_trigger_reset(tx_ring->adapter, ENA_REGS_RESET_INV_TX_REQ_ID); 763 return -EFAULT; 764 } 765 766 static void ena_config_host_info(struct ena_com_dev *ena_dev) 767 { 768 struct ena_admin_host_info *host_info; 769 int rc; 770 771 /* Allocate only the host info */ 772 rc = ena_com_allocate_host_info(ena_dev); 773 if (rc) { 774 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 775 return; 776 } 777 778 host_info = ena_dev->host_attr.host_info; 779 780 host_info->os_type = ENA_ADMIN_OS_DPDK; 781 host_info->kernel_ver = RTE_VERSION; 782 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 783 sizeof(host_info->kernel_ver_str)); 784 host_info->os_dist = RTE_VERSION; 785 strlcpy((char *)host_info->os_dist_str, rte_version(), 786 sizeof(host_info->os_dist_str)); 787 host_info->driver_version = 788 (DRV_MODULE_VER_MAJOR) | 789 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 790 (DRV_MODULE_VER_SUBMINOR << 791 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 792 host_info->num_cpus = rte_lcore_count(); 793 794 host_info->driver_supported_features = 795 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK | 796 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK; 797 798 rc = ena_com_set_host_attributes(ena_dev); 799 if (rc) { 800 if (rc == -ENA_COM_UNSUPPORTED) 801 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 802 else 803 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 804 805 goto err; 806 } 807 808 return; 809 810 err: 811 ena_com_delete_host_info(ena_dev); 812 } 813 814 /* This function calculates the number of xstats based on the current config */ 815 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data) 816 { 817 struct ena_adapter *adapter = data->dev_private; 818 819 return ENA_STATS_ARRAY_GLOBAL + 820 adapter->metrics_num + 821 ENA_STATS_ARRAY_ENA_SRD + 822 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 823 (data->nb_rx_queues * ENA_STATS_ARRAY_RX); 824 } 825 826 static void ena_config_debug_area(struct ena_adapter *adapter) 827 { 828 u32 debug_area_size; 829 int rc, ss_count; 830 831 ss_count = ena_xstats_calc_num(adapter->edev_data); 832 833 /* allocate 32 bytes for each string and 64bit for the value */ 834 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 835 836 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 837 if (rc) { 838 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 839 return; 840 } 841 842 rc = ena_com_set_host_attributes(&adapter->ena_dev); 843 if (rc) { 844 if (rc == -ENA_COM_UNSUPPORTED) 845 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 846 else 847 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 848 849 goto err; 850 } 851 852 return; 853 err: 854 ena_com_delete_debug_area(&adapter->ena_dev); 855 } 856 857 static int ena_close(struct rte_eth_dev *dev) 858 { 859 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 860 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 861 struct ena_adapter *adapter = dev->data->dev_private; 862 int ret = 0; 863 864 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 865 return 0; 866 867 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 868 ret = ena_stop(dev); 869 adapter->state = ENA_ADAPTER_STATE_CLOSED; 870 871 ena_rx_queue_release_all(dev); 872 ena_tx_queue_release_all(dev); 873 874 rte_free(adapter->drv_stats); 875 adapter->drv_stats = NULL; 876 877 rte_intr_disable(intr_handle); 878 rte_intr_callback_unregister(intr_handle, 879 ena_interrupt_handler_rte, 880 dev); 881 882 /* 883 * MAC is not allocated dynamically. Setting NULL should prevent from 884 * release of the resource in the rte_eth_dev_release_port(). 885 */ 886 dev->data->mac_addrs = NULL; 887 888 return ret; 889 } 890 891 static int 892 ena_dev_reset(struct rte_eth_dev *dev) 893 { 894 int rc = 0; 895 896 /* Cannot release memory in secondary process */ 897 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 898 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n"); 899 return -EPERM; 900 } 901 902 ena_destroy_device(dev); 903 rc = eth_ena_dev_init(dev); 904 if (rc) 905 PMD_INIT_LOG(CRIT, "Cannot initialize device\n"); 906 907 return rc; 908 } 909 910 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 911 { 912 int nb_queues = dev->data->nb_rx_queues; 913 int i; 914 915 for (i = 0; i < nb_queues; i++) 916 ena_rx_queue_release(dev, i); 917 } 918 919 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 920 { 921 int nb_queues = dev->data->nb_tx_queues; 922 int i; 923 924 for (i = 0; i < nb_queues; i++) 925 ena_tx_queue_release(dev, i); 926 } 927 928 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 929 { 930 struct ena_ring *ring = dev->data->rx_queues[qid]; 931 932 /* Free ring resources */ 933 rte_free(ring->rx_buffer_info); 934 ring->rx_buffer_info = NULL; 935 936 rte_free(ring->rx_refill_buffer); 937 ring->rx_refill_buffer = NULL; 938 939 rte_free(ring->empty_rx_reqs); 940 ring->empty_rx_reqs = NULL; 941 942 ring->configured = 0; 943 944 PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n", 945 ring->port_id, ring->id); 946 } 947 948 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 949 { 950 struct ena_ring *ring = dev->data->tx_queues[qid]; 951 952 /* Free ring resources */ 953 rte_free(ring->push_buf_intermediate_buf); 954 955 rte_free(ring->tx_buffer_info); 956 957 rte_free(ring->empty_tx_reqs); 958 959 ring->empty_tx_reqs = NULL; 960 ring->tx_buffer_info = NULL; 961 ring->push_buf_intermediate_buf = NULL; 962 963 ring->configured = 0; 964 965 PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n", 966 ring->port_id, ring->id); 967 } 968 969 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 970 { 971 unsigned int i; 972 973 for (i = 0; i < ring->ring_size; ++i) { 974 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 975 if (rx_info->mbuf) { 976 rte_mbuf_raw_free(rx_info->mbuf); 977 rx_info->mbuf = NULL; 978 } 979 } 980 } 981 982 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 983 { 984 unsigned int i; 985 986 for (i = 0; i < ring->ring_size; ++i) { 987 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 988 989 if (tx_buf->mbuf) { 990 rte_pktmbuf_free(tx_buf->mbuf); 991 tx_buf->mbuf = NULL; 992 } 993 } 994 } 995 996 static int ena_link_update(struct rte_eth_dev *dev, 997 __rte_unused int wait_to_complete) 998 { 999 struct rte_eth_link *link = &dev->data->dev_link; 1000 struct ena_adapter *adapter = dev->data->dev_private; 1001 1002 link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 1003 link->link_speed = RTE_ETH_SPEED_NUM_NONE; 1004 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1005 1006 return 0; 1007 } 1008 1009 static int ena_queue_start_all(struct rte_eth_dev *dev, 1010 enum ena_ring_type ring_type) 1011 { 1012 struct ena_adapter *adapter = dev->data->dev_private; 1013 struct ena_ring *queues = NULL; 1014 int nb_queues; 1015 int i = 0; 1016 int rc = 0; 1017 1018 if (ring_type == ENA_RING_TYPE_RX) { 1019 queues = adapter->rx_ring; 1020 nb_queues = dev->data->nb_rx_queues; 1021 } else { 1022 queues = adapter->tx_ring; 1023 nb_queues = dev->data->nb_tx_queues; 1024 } 1025 for (i = 0; i < nb_queues; i++) { 1026 if (queues[i].configured) { 1027 if (ring_type == ENA_RING_TYPE_RX) { 1028 ena_assert_msg( 1029 dev->data->rx_queues[i] == &queues[i], 1030 "Inconsistent state of Rx queues\n"); 1031 } else { 1032 ena_assert_msg( 1033 dev->data->tx_queues[i] == &queues[i], 1034 "Inconsistent state of Tx queues\n"); 1035 } 1036 1037 rc = ena_queue_start(dev, &queues[i]); 1038 1039 if (rc) { 1040 PMD_INIT_LOG(ERR, 1041 "Failed to start queue[%d] of type(%d)\n", 1042 i, ring_type); 1043 goto err; 1044 } 1045 } 1046 } 1047 1048 return 0; 1049 1050 err: 1051 while (i--) 1052 if (queues[i].configured) 1053 ena_queue_stop(&queues[i]); 1054 1055 return rc; 1056 } 1057 1058 static int 1059 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 1060 bool use_large_llq_hdr) 1061 { 1062 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 1063 struct ena_com_dev *ena_dev = ctx->ena_dev; 1064 uint32_t max_tx_queue_size; 1065 uint32_t max_rx_queue_size; 1066 1067 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1068 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1069 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 1070 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 1071 max_queue_ext->max_rx_sq_depth); 1072 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 1073 1074 if (ena_dev->tx_mem_queue_type == 1075 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1076 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 1077 llq->max_llq_depth); 1078 } else { 1079 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 1080 max_queue_ext->max_tx_sq_depth); 1081 } 1082 1083 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 1084 max_queue_ext->max_per_packet_rx_descs); 1085 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 1086 max_queue_ext->max_per_packet_tx_descs); 1087 } else { 1088 struct ena_admin_queue_feature_desc *max_queues = 1089 &ctx->get_feat_ctx->max_queues; 1090 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 1091 max_queues->max_sq_depth); 1092 max_tx_queue_size = max_queues->max_cq_depth; 1093 1094 if (ena_dev->tx_mem_queue_type == 1095 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1096 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 1097 llq->max_llq_depth); 1098 } else { 1099 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 1100 max_queues->max_sq_depth); 1101 } 1102 1103 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 1104 max_queues->max_packet_rx_descs); 1105 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 1106 max_queues->max_packet_tx_descs); 1107 } 1108 1109 /* Round down to the nearest power of 2 */ 1110 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 1111 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 1112 1113 if (use_large_llq_hdr) { 1114 if ((llq->entry_size_ctrl_supported & 1115 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 1116 (ena_dev->tx_mem_queue_type == 1117 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 1118 max_tx_queue_size /= 2; 1119 PMD_INIT_LOG(INFO, 1120 "Forcing large headers and decreasing maximum Tx queue size to %d\n", 1121 max_tx_queue_size); 1122 } else { 1123 PMD_INIT_LOG(ERR, 1124 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 1125 } 1126 } 1127 1128 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 1129 PMD_INIT_LOG(ERR, "Invalid queue size\n"); 1130 return -EFAULT; 1131 } 1132 1133 ctx->max_tx_queue_size = max_tx_queue_size; 1134 ctx->max_rx_queue_size = max_rx_queue_size; 1135 1136 return 0; 1137 } 1138 1139 static void ena_stats_restart(struct rte_eth_dev *dev) 1140 { 1141 struct ena_adapter *adapter = dev->data->dev_private; 1142 1143 rte_atomic64_init(&adapter->drv_stats->ierrors); 1144 rte_atomic64_init(&adapter->drv_stats->oerrors); 1145 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 1146 adapter->drv_stats->rx_drops = 0; 1147 } 1148 1149 static int ena_stats_get(struct rte_eth_dev *dev, 1150 struct rte_eth_stats *stats) 1151 { 1152 struct ena_admin_basic_stats ena_stats; 1153 struct ena_adapter *adapter = dev->data->dev_private; 1154 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1155 int rc; 1156 int i; 1157 int max_rings_stats; 1158 1159 memset(&ena_stats, 0, sizeof(ena_stats)); 1160 1161 rte_spinlock_lock(&adapter->admin_lock); 1162 rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev, 1163 &ena_stats); 1164 rte_spinlock_unlock(&adapter->admin_lock); 1165 if (unlikely(rc)) { 1166 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 1167 return rc; 1168 } 1169 1170 /* Set of basic statistics from ENA */ 1171 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 1172 ena_stats.rx_pkts_low); 1173 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 1174 ena_stats.tx_pkts_low); 1175 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 1176 ena_stats.rx_bytes_low); 1177 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 1178 ena_stats.tx_bytes_low); 1179 1180 /* Driver related stats */ 1181 stats->imissed = adapter->drv_stats->rx_drops; 1182 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 1183 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 1184 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 1185 1186 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 1187 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1188 for (i = 0; i < max_rings_stats; ++i) { 1189 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 1190 1191 stats->q_ibytes[i] = rx_stats->bytes; 1192 stats->q_ipackets[i] = rx_stats->cnt; 1193 stats->q_errors[i] = rx_stats->bad_desc_num + 1194 rx_stats->bad_req_id; 1195 } 1196 1197 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 1198 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1199 for (i = 0; i < max_rings_stats; ++i) { 1200 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 1201 1202 stats->q_obytes[i] = tx_stats->bytes; 1203 stats->q_opackets[i] = tx_stats->cnt; 1204 } 1205 1206 return 0; 1207 } 1208 1209 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1210 { 1211 struct ena_adapter *adapter; 1212 struct ena_com_dev *ena_dev; 1213 int rc = 0; 1214 1215 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1216 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1217 adapter = dev->data->dev_private; 1218 1219 ena_dev = &adapter->ena_dev; 1220 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1221 1222 rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu); 1223 if (rc) 1224 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1225 else 1226 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu); 1227 1228 return rc; 1229 } 1230 1231 static int ena_start(struct rte_eth_dev *dev) 1232 { 1233 struct ena_adapter *adapter = dev->data->dev_private; 1234 uint64_t ticks; 1235 int rc = 0; 1236 uint16_t i; 1237 1238 /* Cannot allocate memory in secondary process */ 1239 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1240 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n"); 1241 return -EPERM; 1242 } 1243 1244 rc = ena_setup_rx_intr(dev); 1245 if (rc) 1246 return rc; 1247 1248 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1249 if (rc) 1250 return rc; 1251 1252 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1253 if (rc) 1254 goto err_start_tx; 1255 1256 if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { 1257 rc = ena_rss_configure(adapter); 1258 if (rc) 1259 goto err_rss_init; 1260 } 1261 1262 ena_stats_restart(dev); 1263 1264 adapter->timestamp_wd = rte_get_timer_cycles(); 1265 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1266 1267 ticks = rte_get_timer_hz(); 1268 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1269 ena_timer_wd_callback, dev); 1270 1271 ++adapter->dev_stats.dev_start; 1272 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1273 1274 for (i = 0; i < dev->data->nb_rx_queues; i++) 1275 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1276 for (i = 0; i < dev->data->nb_tx_queues; i++) 1277 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1278 1279 return 0; 1280 1281 err_rss_init: 1282 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1283 err_start_tx: 1284 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1285 return rc; 1286 } 1287 1288 static int ena_stop(struct rte_eth_dev *dev) 1289 { 1290 struct ena_adapter *adapter = dev->data->dev_private; 1291 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1292 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1293 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1294 uint16_t i; 1295 int rc; 1296 1297 /* Cannot free memory in secondary process */ 1298 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1299 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n"); 1300 return -EPERM; 1301 } 1302 1303 rte_timer_stop_sync(&adapter->timer_wd); 1304 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1305 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1306 1307 if (adapter->trigger_reset) { 1308 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1309 if (rc) 1310 PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc); 1311 } 1312 1313 rte_intr_disable(intr_handle); 1314 1315 rte_intr_efd_disable(intr_handle); 1316 1317 /* Cleanup vector list */ 1318 rte_intr_vec_list_free(intr_handle); 1319 1320 rte_intr_enable(intr_handle); 1321 1322 ++adapter->dev_stats.dev_stop; 1323 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1324 dev->data->dev_started = 0; 1325 1326 for (i = 0; i < dev->data->nb_rx_queues; i++) 1327 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1328 for (i = 0; i < dev->data->nb_tx_queues; i++) 1329 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1330 1331 return 0; 1332 } 1333 1334 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring) 1335 { 1336 struct ena_adapter *adapter = ring->adapter; 1337 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1339 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1340 struct ena_com_create_io_ctx ctx = 1341 /* policy set to _HOST just to satisfy icc compiler */ 1342 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1343 0, 0, 0, 0, 0 }; 1344 uint16_t ena_qid; 1345 unsigned int i; 1346 int rc; 1347 1348 ctx.msix_vector = -1; 1349 if (ring->type == ENA_RING_TYPE_TX) { 1350 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1351 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1352 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1353 for (i = 0; i < ring->ring_size; i++) 1354 ring->empty_tx_reqs[i] = i; 1355 } else { 1356 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1357 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1358 if (rte_intr_dp_is_en(intr_handle)) 1359 ctx.msix_vector = 1360 rte_intr_vec_list_index_get(intr_handle, 1361 ring->id); 1362 1363 for (i = 0; i < ring->ring_size; i++) 1364 ring->empty_rx_reqs[i] = i; 1365 } 1366 ctx.queue_size = ring->ring_size; 1367 ctx.qid = ena_qid; 1368 ctx.numa_node = ring->numa_socket_id; 1369 1370 rc = ena_com_create_io_queue(ena_dev, &ctx); 1371 if (rc) { 1372 PMD_DRV_LOG(ERR, 1373 "Failed to create IO queue[%d] (qid:%d), rc: %d\n", 1374 ring->id, ena_qid, rc); 1375 return rc; 1376 } 1377 1378 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1379 &ring->ena_com_io_sq, 1380 &ring->ena_com_io_cq); 1381 if (rc) { 1382 PMD_DRV_LOG(ERR, 1383 "Failed to get IO queue[%d] handlers, rc: %d\n", 1384 ring->id, rc); 1385 ena_com_destroy_io_queue(ena_dev, ena_qid); 1386 return rc; 1387 } 1388 1389 if (ring->type == ENA_RING_TYPE_TX) 1390 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1391 1392 /* Start with Rx interrupts being masked. */ 1393 if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle)) 1394 ena_rx_queue_intr_disable(dev, ring->id); 1395 1396 return 0; 1397 } 1398 1399 static void ena_queue_stop(struct ena_ring *ring) 1400 { 1401 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1402 1403 if (ring->type == ENA_RING_TYPE_RX) { 1404 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1405 ena_rx_queue_release_bufs(ring); 1406 } else { 1407 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1408 ena_tx_queue_release_bufs(ring); 1409 } 1410 } 1411 1412 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1413 enum ena_ring_type ring_type) 1414 { 1415 struct ena_adapter *adapter = dev->data->dev_private; 1416 struct ena_ring *queues = NULL; 1417 uint16_t nb_queues, i; 1418 1419 if (ring_type == ENA_RING_TYPE_RX) { 1420 queues = adapter->rx_ring; 1421 nb_queues = dev->data->nb_rx_queues; 1422 } else { 1423 queues = adapter->tx_ring; 1424 nb_queues = dev->data->nb_tx_queues; 1425 } 1426 1427 for (i = 0; i < nb_queues; ++i) 1428 if (queues[i].configured) 1429 ena_queue_stop(&queues[i]); 1430 } 1431 1432 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring) 1433 { 1434 int rc, bufs_num; 1435 1436 ena_assert_msg(ring->configured == 1, 1437 "Trying to start unconfigured queue\n"); 1438 1439 rc = ena_create_io_queue(dev, ring); 1440 if (rc) { 1441 PMD_INIT_LOG(ERR, "Failed to create IO queue\n"); 1442 return rc; 1443 } 1444 1445 ring->next_to_clean = 0; 1446 ring->next_to_use = 0; 1447 1448 if (ring->type == ENA_RING_TYPE_TX) { 1449 ring->tx_stats.available_desc = 1450 ena_com_free_q_entries(ring->ena_com_io_sq); 1451 return 0; 1452 } 1453 1454 bufs_num = ring->ring_size - 1; 1455 rc = ena_populate_rx_queue(ring, bufs_num); 1456 if (rc != bufs_num) { 1457 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1458 ENA_IO_RXQ_IDX(ring->id)); 1459 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n"); 1460 return ENA_COM_FAULT; 1461 } 1462 /* Flush per-core RX buffers pools cache as they can be used on other 1463 * cores as well. 1464 */ 1465 rte_mempool_cache_flush(NULL, ring->mb_pool); 1466 1467 return 0; 1468 } 1469 1470 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1471 uint16_t queue_idx, 1472 uint16_t nb_desc, 1473 unsigned int socket_id, 1474 const struct rte_eth_txconf *tx_conf) 1475 { 1476 struct ena_ring *txq = NULL; 1477 struct ena_adapter *adapter = dev->data->dev_private; 1478 unsigned int i; 1479 uint16_t dyn_thresh; 1480 1481 txq = &adapter->tx_ring[queue_idx]; 1482 1483 if (txq->configured) { 1484 PMD_DRV_LOG(CRIT, 1485 "API violation. Queue[%d] is already configured\n", 1486 queue_idx); 1487 return ENA_COM_FAULT; 1488 } 1489 1490 if (!rte_is_power_of_2(nb_desc)) { 1491 PMD_DRV_LOG(ERR, 1492 "Unsupported size of Tx queue: %d is not a power of 2.\n", 1493 nb_desc); 1494 return -EINVAL; 1495 } 1496 1497 if (nb_desc > adapter->max_tx_ring_size) { 1498 PMD_DRV_LOG(ERR, 1499 "Unsupported size of Tx queue (max size: %d)\n", 1500 adapter->max_tx_ring_size); 1501 return -EINVAL; 1502 } 1503 1504 txq->port_id = dev->data->port_id; 1505 txq->next_to_clean = 0; 1506 txq->next_to_use = 0; 1507 txq->ring_size = nb_desc; 1508 txq->size_mask = nb_desc - 1; 1509 txq->numa_socket_id = socket_id; 1510 txq->pkts_without_db = false; 1511 txq->last_cleanup_ticks = 0; 1512 1513 txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info", 1514 sizeof(struct ena_tx_buffer) * txq->ring_size, 1515 RTE_CACHE_LINE_SIZE, 1516 socket_id); 1517 if (!txq->tx_buffer_info) { 1518 PMD_DRV_LOG(ERR, 1519 "Failed to allocate memory for Tx buffer info\n"); 1520 return -ENOMEM; 1521 } 1522 1523 txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs", 1524 sizeof(uint16_t) * txq->ring_size, 1525 RTE_CACHE_LINE_SIZE, 1526 socket_id); 1527 if (!txq->empty_tx_reqs) { 1528 PMD_DRV_LOG(ERR, 1529 "Failed to allocate memory for empty Tx requests\n"); 1530 rte_free(txq->tx_buffer_info); 1531 return -ENOMEM; 1532 } 1533 1534 txq->push_buf_intermediate_buf = 1535 rte_zmalloc_socket("txq->push_buf_intermediate_buf", 1536 txq->tx_max_header_size, 1537 RTE_CACHE_LINE_SIZE, 1538 socket_id); 1539 if (!txq->push_buf_intermediate_buf) { 1540 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n"); 1541 rte_free(txq->tx_buffer_info); 1542 rte_free(txq->empty_tx_reqs); 1543 return -ENOMEM; 1544 } 1545 1546 for (i = 0; i < txq->ring_size; i++) 1547 txq->empty_tx_reqs[i] = i; 1548 1549 txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1550 1551 /* Check if caller provided the Tx cleanup threshold value. */ 1552 if (tx_conf->tx_free_thresh != 0) { 1553 txq->tx_free_thresh = tx_conf->tx_free_thresh; 1554 } else { 1555 dyn_thresh = txq->ring_size - 1556 txq->ring_size / ENA_REFILL_THRESH_DIVIDER; 1557 txq->tx_free_thresh = RTE_MAX(dyn_thresh, 1558 txq->ring_size - ENA_REFILL_THRESH_PACKET); 1559 } 1560 1561 txq->missing_tx_completion_threshold = 1562 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP); 1563 1564 /* Store pointer to this queue in upper layer */ 1565 txq->configured = 1; 1566 dev->data->tx_queues[queue_idx] = txq; 1567 1568 return 0; 1569 } 1570 1571 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1572 uint16_t queue_idx, 1573 uint16_t nb_desc, 1574 unsigned int socket_id, 1575 const struct rte_eth_rxconf *rx_conf, 1576 struct rte_mempool *mp) 1577 { 1578 struct ena_adapter *adapter = dev->data->dev_private; 1579 struct ena_ring *rxq = NULL; 1580 size_t buffer_size; 1581 int i; 1582 uint16_t dyn_thresh; 1583 1584 rxq = &adapter->rx_ring[queue_idx]; 1585 if (rxq->configured) { 1586 PMD_DRV_LOG(CRIT, 1587 "API violation. Queue[%d] is already configured\n", 1588 queue_idx); 1589 return ENA_COM_FAULT; 1590 } 1591 1592 if (!rte_is_power_of_2(nb_desc)) { 1593 PMD_DRV_LOG(ERR, 1594 "Unsupported size of Rx queue: %d is not a power of 2.\n", 1595 nb_desc); 1596 return -EINVAL; 1597 } 1598 1599 if (nb_desc > adapter->max_rx_ring_size) { 1600 PMD_DRV_LOG(ERR, 1601 "Unsupported size of Rx queue (max size: %d)\n", 1602 adapter->max_rx_ring_size); 1603 return -EINVAL; 1604 } 1605 1606 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1607 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1608 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1609 PMD_DRV_LOG(ERR, 1610 "Unsupported size of Rx buffer: %zu (min size: %d)\n", 1611 buffer_size, ENA_RX_BUF_MIN_SIZE); 1612 return -EINVAL; 1613 } 1614 1615 rxq->port_id = dev->data->port_id; 1616 rxq->next_to_clean = 0; 1617 rxq->next_to_use = 0; 1618 rxq->ring_size = nb_desc; 1619 rxq->size_mask = nb_desc - 1; 1620 rxq->numa_socket_id = socket_id; 1621 rxq->mb_pool = mp; 1622 1623 rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info", 1624 sizeof(struct ena_rx_buffer) * nb_desc, 1625 RTE_CACHE_LINE_SIZE, 1626 socket_id); 1627 if (!rxq->rx_buffer_info) { 1628 PMD_DRV_LOG(ERR, 1629 "Failed to allocate memory for Rx buffer info\n"); 1630 return -ENOMEM; 1631 } 1632 1633 rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer", 1634 sizeof(struct rte_mbuf *) * nb_desc, 1635 RTE_CACHE_LINE_SIZE, 1636 socket_id); 1637 if (!rxq->rx_refill_buffer) { 1638 PMD_DRV_LOG(ERR, 1639 "Failed to allocate memory for Rx refill buffer\n"); 1640 rte_free(rxq->rx_buffer_info); 1641 rxq->rx_buffer_info = NULL; 1642 return -ENOMEM; 1643 } 1644 1645 rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs", 1646 sizeof(uint16_t) * nb_desc, 1647 RTE_CACHE_LINE_SIZE, 1648 socket_id); 1649 if (!rxq->empty_rx_reqs) { 1650 PMD_DRV_LOG(ERR, 1651 "Failed to allocate memory for empty Rx requests\n"); 1652 rte_free(rxq->rx_buffer_info); 1653 rxq->rx_buffer_info = NULL; 1654 rte_free(rxq->rx_refill_buffer); 1655 rxq->rx_refill_buffer = NULL; 1656 return -ENOMEM; 1657 } 1658 1659 for (i = 0; i < nb_desc; i++) 1660 rxq->empty_rx_reqs[i] = i; 1661 1662 rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1663 1664 if (rx_conf->rx_free_thresh != 0) { 1665 rxq->rx_free_thresh = rx_conf->rx_free_thresh; 1666 } else { 1667 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER; 1668 rxq->rx_free_thresh = RTE_MIN(dyn_thresh, 1669 (uint16_t)(ENA_REFILL_THRESH_PACKET)); 1670 } 1671 1672 /* Store pointer to this queue in upper layer */ 1673 rxq->configured = 1; 1674 dev->data->rx_queues[queue_idx] = rxq; 1675 1676 return 0; 1677 } 1678 1679 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1680 struct rte_mbuf *mbuf, uint16_t id) 1681 { 1682 struct ena_com_buf ebuf; 1683 int rc; 1684 1685 /* prepare physical address for DMA transaction */ 1686 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1687 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1688 1689 /* pass resource to device */ 1690 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1691 if (unlikely(rc != 0)) 1692 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n"); 1693 1694 return rc; 1695 } 1696 1697 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1698 { 1699 unsigned int i; 1700 int rc; 1701 uint16_t next_to_use = rxq->next_to_use; 1702 uint16_t req_id; 1703 #ifdef RTE_ETHDEV_DEBUG_RX 1704 uint16_t in_use; 1705 #endif 1706 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1707 1708 if (unlikely(!count)) 1709 return 0; 1710 1711 #ifdef RTE_ETHDEV_DEBUG_RX 1712 in_use = rxq->ring_size - 1 - 1713 ena_com_free_q_entries(rxq->ena_com_io_sq); 1714 if (unlikely((in_use + count) >= rxq->ring_size)) 1715 PMD_RX_LOG(ERR, "Bad Rx ring state\n"); 1716 #endif 1717 1718 /* get resources for incoming packets */ 1719 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count); 1720 if (unlikely(rc < 0)) { 1721 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1722 ++rxq->rx_stats.mbuf_alloc_fail; 1723 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n"); 1724 return 0; 1725 } 1726 1727 for (i = 0; i < count; i++) { 1728 struct rte_mbuf *mbuf = mbufs[i]; 1729 struct ena_rx_buffer *rx_info; 1730 1731 if (likely((i + 4) < count)) 1732 rte_prefetch0(mbufs[i + 4]); 1733 1734 req_id = rxq->empty_rx_reqs[next_to_use]; 1735 rx_info = &rxq->rx_buffer_info[req_id]; 1736 1737 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1738 if (unlikely(rc != 0)) 1739 break; 1740 1741 rx_info->mbuf = mbuf; 1742 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1743 } 1744 1745 if (unlikely(i < count)) { 1746 PMD_RX_LOG(WARNING, 1747 "Refilled Rx queue[%d] with only %d/%d buffers\n", 1748 rxq->id, i, count); 1749 rte_pktmbuf_free_bulk(&mbufs[i], count - i); 1750 ++rxq->rx_stats.refill_partial; 1751 } 1752 1753 /* When we submitted free resources to device... */ 1754 if (likely(i > 0)) { 1755 /* ...let HW know that it can fill buffers with data. */ 1756 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1757 1758 rxq->next_to_use = next_to_use; 1759 } 1760 1761 return i; 1762 } 1763 1764 static size_t ena_get_metrics_entries(struct ena_adapter *adapter) 1765 { 1766 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1767 size_t metrics_num = 0; 1768 1769 if (ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) 1770 metrics_num = ENA_STATS_ARRAY_METRICS; 1771 else if (ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) 1772 metrics_num = ENA_STATS_ARRAY_METRICS_LEGACY; 1773 PMD_DRV_LOG(NOTICE, "0x%x customer metrics are supported\n", (unsigned int)metrics_num); 1774 if (metrics_num > ENA_MAX_CUSTOMER_METRICS) { 1775 PMD_DRV_LOG(NOTICE, "Not enough space for the requested customer metrics\n"); 1776 metrics_num = ENA_MAX_CUSTOMER_METRICS; 1777 } 1778 return metrics_num; 1779 } 1780 1781 static int ena_device_init(struct ena_adapter *adapter, 1782 struct rte_pci_device *pdev, 1783 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1784 { 1785 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1786 uint32_t aenq_groups; 1787 int rc; 1788 bool readless_supported; 1789 1790 /* Initialize mmio registers */ 1791 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1792 if (rc) { 1793 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n"); 1794 return rc; 1795 } 1796 1797 /* The PCIe configuration space revision id indicate if mmio reg 1798 * read is disabled. 1799 */ 1800 readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ); 1801 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1802 1803 /* reset device */ 1804 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1805 if (rc) { 1806 PMD_DRV_LOG(ERR, "Cannot reset device\n"); 1807 goto err_mmio_read_less; 1808 } 1809 1810 /* check FW version */ 1811 rc = ena_com_validate_version(ena_dev); 1812 if (rc) { 1813 PMD_DRV_LOG(ERR, "Device version is too low\n"); 1814 goto err_mmio_read_less; 1815 } 1816 1817 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1818 1819 /* ENA device administration layer init */ 1820 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1821 if (rc) { 1822 PMD_DRV_LOG(ERR, 1823 "Cannot initialize ENA admin queue\n"); 1824 goto err_mmio_read_less; 1825 } 1826 1827 /* To enable the msix interrupts the driver needs to know the number 1828 * of queues. So the driver uses polling mode to retrieve this 1829 * information. 1830 */ 1831 ena_com_set_admin_polling_mode(ena_dev, true); 1832 1833 ena_config_host_info(ena_dev); 1834 1835 /* Get Device Attributes and features */ 1836 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1837 if (rc) { 1838 PMD_DRV_LOG(ERR, 1839 "Cannot get attribute for ENA device, rc: %d\n", rc); 1840 goto err_admin_init; 1841 } 1842 1843 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1844 BIT(ENA_ADMIN_NOTIFICATION) | 1845 BIT(ENA_ADMIN_KEEP_ALIVE) | 1846 BIT(ENA_ADMIN_FATAL_ERROR) | 1847 BIT(ENA_ADMIN_WARNING); 1848 1849 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1850 1851 adapter->all_aenq_groups = aenq_groups; 1852 /* The actual supported number of metrics is negotiated with the device at runtime */ 1853 adapter->metrics_num = ena_get_metrics_entries(adapter); 1854 1855 return 0; 1856 1857 err_admin_init: 1858 ena_com_admin_destroy(ena_dev); 1859 1860 err_mmio_read_less: 1861 ena_com_mmio_reg_read_request_destroy(ena_dev); 1862 1863 return rc; 1864 } 1865 1866 static void ena_interrupt_handler_rte(void *cb_arg) 1867 { 1868 struct rte_eth_dev *dev = cb_arg; 1869 struct ena_adapter *adapter = dev->data->dev_private; 1870 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1871 1872 ena_com_admin_q_comp_intr_handler(ena_dev); 1873 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1874 ena_com_aenq_intr_handler(ena_dev, dev); 1875 } 1876 1877 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1878 { 1879 if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE))) 1880 return; 1881 1882 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1883 return; 1884 1885 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1886 adapter->keep_alive_timeout)) { 1887 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1888 ena_trigger_reset(adapter, ENA_REGS_RESET_KEEP_ALIVE_TO); 1889 ++adapter->dev_stats.wd_expired; 1890 } 1891 } 1892 1893 /* Check if admin queue is enabled */ 1894 static void check_for_admin_com_state(struct ena_adapter *adapter) 1895 { 1896 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1897 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n"); 1898 ena_trigger_reset(adapter, ENA_REGS_RESET_ADMIN_TO); 1899 } 1900 } 1901 1902 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter, 1903 struct ena_ring *tx_ring) 1904 { 1905 struct ena_tx_buffer *tx_buf; 1906 uint64_t timestamp; 1907 uint64_t completion_delay; 1908 uint32_t missed_tx = 0; 1909 unsigned int i; 1910 int rc = 0; 1911 1912 for (i = 0; i < tx_ring->ring_size; ++i) { 1913 tx_buf = &tx_ring->tx_buffer_info[i]; 1914 timestamp = tx_buf->timestamp; 1915 1916 if (timestamp == 0) 1917 continue; 1918 1919 completion_delay = rte_get_timer_cycles() - timestamp; 1920 if (completion_delay > adapter->missing_tx_completion_to) { 1921 if (unlikely(!tx_buf->print_once)) { 1922 PMD_TX_LOG(WARNING, 1923 "Found a Tx that wasn't completed on time, qid %d, index %d. " 1924 "Missing Tx outstanding for %" PRIu64 " msecs.\n", 1925 tx_ring->id, i, completion_delay / 1926 rte_get_timer_hz() * 1000); 1927 tx_buf->print_once = true; 1928 } 1929 ++missed_tx; 1930 } 1931 } 1932 1933 if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) { 1934 PMD_DRV_LOG(ERR, 1935 "The number of lost Tx completions is above the threshold (%d > %d). " 1936 "Trigger the device reset.\n", 1937 missed_tx, 1938 tx_ring->missing_tx_completion_threshold); 1939 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL; 1940 adapter->trigger_reset = true; 1941 rc = -EIO; 1942 } 1943 1944 tx_ring->tx_stats.missed_tx += missed_tx; 1945 1946 return rc; 1947 } 1948 1949 static void check_for_tx_completions(struct ena_adapter *adapter) 1950 { 1951 struct ena_ring *tx_ring; 1952 uint64_t tx_cleanup_delay; 1953 size_t qid; 1954 int budget; 1955 uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues; 1956 1957 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT) 1958 return; 1959 1960 nb_tx_queues = adapter->edev_data->nb_tx_queues; 1961 budget = adapter->missing_tx_completion_budget; 1962 1963 qid = adapter->last_tx_comp_qid; 1964 while (budget-- > 0) { 1965 tx_ring = &adapter->tx_ring[qid]; 1966 1967 /* Tx cleanup is called only by the burst function and can be 1968 * called dynamically by the application. Also cleanup is 1969 * limited by the threshold. To avoid false detection of the 1970 * missing HW Tx completion, get the delay since last cleanup 1971 * function was called. 1972 */ 1973 tx_cleanup_delay = rte_get_timer_cycles() - 1974 tx_ring->last_cleanup_ticks; 1975 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay) 1976 check_for_tx_completion_in_queue(adapter, tx_ring); 1977 qid = (qid + 1) % nb_tx_queues; 1978 } 1979 1980 adapter->last_tx_comp_qid = qid; 1981 } 1982 1983 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1984 void *arg) 1985 { 1986 struct rte_eth_dev *dev = arg; 1987 struct ena_adapter *adapter = dev->data->dev_private; 1988 1989 if (unlikely(adapter->trigger_reset)) 1990 return; 1991 1992 check_for_missing_keep_alive(adapter); 1993 check_for_admin_com_state(adapter); 1994 check_for_tx_completions(adapter); 1995 1996 if (unlikely(adapter->trigger_reset)) { 1997 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1998 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1999 NULL); 2000 } 2001 } 2002 2003 static inline void 2004 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 2005 struct ena_admin_feature_llq_desc *llq, 2006 bool use_large_llq_hdr) 2007 { 2008 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 2009 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 2010 llq_config->llq_num_decs_before_header = 2011 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 2012 2013 if (use_large_llq_hdr && 2014 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 2015 llq_config->llq_ring_entry_size = 2016 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 2017 llq_config->llq_ring_entry_size_value = 256; 2018 } else { 2019 llq_config->llq_ring_entry_size = 2020 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 2021 llq_config->llq_ring_entry_size_value = 128; 2022 } 2023 } 2024 2025 static int 2026 ena_set_queues_placement_policy(struct ena_adapter *adapter, 2027 struct ena_com_dev *ena_dev, 2028 struct ena_admin_feature_llq_desc *llq, 2029 struct ena_llq_configurations *llq_default_configurations) 2030 { 2031 int rc; 2032 u32 llq_feature_mask; 2033 2034 if (!adapter->enable_llq) { 2035 PMD_DRV_LOG(WARNING, 2036 "NOTE: LLQ has been disabled as per user's request. " 2037 "This may lead to a huge performance degradation!\n"); 2038 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2039 return 0; 2040 } 2041 2042 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 2043 if (!(ena_dev->supported_features & llq_feature_mask)) { 2044 PMD_DRV_LOG(INFO, 2045 "LLQ is not supported. Fallback to host mode policy.\n"); 2046 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2047 return 0; 2048 } 2049 2050 if (adapter->dev_mem_base == NULL) { 2051 PMD_DRV_LOG(ERR, 2052 "LLQ is advertised as supported, but device doesn't expose mem bar\n"); 2053 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2054 return 0; 2055 } 2056 2057 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 2058 if (unlikely(rc)) { 2059 PMD_INIT_LOG(WARNING, 2060 "Failed to config dev mode. Fallback to host mode policy.\n"); 2061 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2062 return 0; 2063 } 2064 2065 /* Nothing to config, exit */ 2066 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 2067 return 0; 2068 2069 ena_dev->mem_bar = adapter->dev_mem_base; 2070 2071 return 0; 2072 } 2073 2074 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 2075 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2076 { 2077 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 2078 2079 /* Regular queues capabilities */ 2080 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 2081 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 2082 &get_feat_ctx->max_queue_ext.max_queue_ext; 2083 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 2084 max_queue_ext->max_rx_cq_num); 2085 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 2086 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 2087 } else { 2088 struct ena_admin_queue_feature_desc *max_queues = 2089 &get_feat_ctx->max_queues; 2090 io_tx_sq_num = max_queues->max_sq_num; 2091 io_tx_cq_num = max_queues->max_cq_num; 2092 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 2093 } 2094 2095 /* In case of LLQ use the llq number in the get feature cmd */ 2096 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 2097 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 2098 2099 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 2100 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 2101 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 2102 2103 if (unlikely(max_num_io_queues == 0)) { 2104 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n"); 2105 return -EFAULT; 2106 } 2107 2108 return max_num_io_queues; 2109 } 2110 2111 static void 2112 ena_set_offloads(struct ena_offloads *offloads, 2113 struct ena_admin_feature_offload_desc *offload_desc) 2114 { 2115 if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 2116 offloads->tx_offloads |= ENA_IPV4_TSO; 2117 2118 /* Tx IPv4 checksum offloads */ 2119 if (offload_desc->tx & 2120 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) 2121 offloads->tx_offloads |= ENA_L3_IPV4_CSUM; 2122 if (offload_desc->tx & 2123 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) 2124 offloads->tx_offloads |= ENA_L4_IPV4_CSUM; 2125 if (offload_desc->tx & 2126 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 2127 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL; 2128 2129 /* Tx IPv6 checksum offloads */ 2130 if (offload_desc->tx & 2131 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) 2132 offloads->tx_offloads |= ENA_L4_IPV6_CSUM; 2133 if (offload_desc->tx & 2134 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) 2135 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL; 2136 2137 /* Rx IPv4 checksum offloads */ 2138 if (offload_desc->rx_supported & 2139 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK) 2140 offloads->rx_offloads |= ENA_L3_IPV4_CSUM; 2141 if (offload_desc->rx_supported & 2142 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 2143 offloads->rx_offloads |= ENA_L4_IPV4_CSUM; 2144 2145 /* Rx IPv6 checksum offloads */ 2146 if (offload_desc->rx_supported & 2147 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) 2148 offloads->rx_offloads |= ENA_L4_IPV6_CSUM; 2149 2150 if (offload_desc->rx_supported & 2151 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) 2152 offloads->rx_offloads |= ENA_RX_RSS_HASH; 2153 } 2154 2155 static int ena_init_once(void) 2156 { 2157 static bool init_done; 2158 2159 if (init_done) 2160 return 0; 2161 2162 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2163 /* Init timer subsystem for the ENA timer service. */ 2164 rte_timer_subsystem_init(); 2165 /* Register handler for requests from secondary processes. */ 2166 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle); 2167 } 2168 2169 init_done = true; 2170 return 0; 2171 } 2172 2173 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 2174 { 2175 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 2176 struct rte_pci_device *pci_dev; 2177 struct rte_intr_handle *intr_handle; 2178 struct ena_adapter *adapter = eth_dev->data->dev_private; 2179 struct ena_com_dev *ena_dev = &adapter->ena_dev; 2180 struct ena_com_dev_get_features_ctx get_feat_ctx; 2181 struct ena_llq_configurations llq_config; 2182 const char *queue_type_str; 2183 uint32_t max_num_io_queues; 2184 int rc; 2185 static int adapters_found; 2186 bool disable_meta_caching; 2187 2188 eth_dev->dev_ops = &ena_dev_ops; 2189 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 2190 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 2191 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 2192 2193 rc = ena_init_once(); 2194 if (rc != 0) 2195 return rc; 2196 2197 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2198 return 0; 2199 2200 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2201 2202 memset(adapter, 0, sizeof(struct ena_adapter)); 2203 ena_dev = &adapter->ena_dev; 2204 2205 adapter->edev_data = eth_dev->data; 2206 2207 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2208 2209 PMD_INIT_LOG(INFO, "Initializing " PCI_PRI_FMT "\n", 2210 pci_dev->addr.domain, 2211 pci_dev->addr.bus, 2212 pci_dev->addr.devid, 2213 pci_dev->addr.function); 2214 2215 intr_handle = pci_dev->intr_handle; 2216 2217 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 2218 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 2219 2220 if (!adapter->regs) { 2221 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n", 2222 ENA_REGS_BAR); 2223 return -ENXIO; 2224 } 2225 2226 ena_dev->reg_bar = adapter->regs; 2227 /* Pass device data as a pointer which can be passed to the IO functions 2228 * by the ena_com (for example - the memory allocation). 2229 */ 2230 ena_dev->dmadev = eth_dev->data; 2231 2232 adapter->id_number = adapters_found; 2233 2234 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 2235 adapter->id_number); 2236 2237 /* Assign default devargs values */ 2238 adapter->missing_tx_completion_to = ENA_TX_TIMEOUT; 2239 adapter->enable_llq = true; 2240 adapter->use_large_llq_hdr = false; 2241 2242 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 2243 if (rc != 0) { 2244 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 2245 goto err; 2246 } 2247 rc = ena_com_allocate_customer_metrics_buffer(ena_dev); 2248 if (rc != 0) { 2249 PMD_INIT_LOG(CRIT, "Failed to allocate customer metrics buffer\n"); 2250 goto err; 2251 } 2252 2253 /* device specific initialization routine */ 2254 rc = ena_device_init(adapter, pci_dev, &get_feat_ctx); 2255 if (rc) { 2256 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n"); 2257 goto err_metrics_delete; 2258 } 2259 2260 /* Check if device supports LSC */ 2261 if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) 2262 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 2263 2264 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 2265 adapter->use_large_llq_hdr); 2266 rc = ena_set_queues_placement_policy(adapter, ena_dev, 2267 &get_feat_ctx.llq, &llq_config); 2268 if (unlikely(rc)) { 2269 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n"); 2270 return rc; 2271 } 2272 2273 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 2274 queue_type_str = "Regular"; 2275 else 2276 queue_type_str = "Low latency"; 2277 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 2278 2279 calc_queue_ctx.ena_dev = ena_dev; 2280 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 2281 2282 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 2283 rc = ena_calc_io_queue_size(&calc_queue_ctx, 2284 adapter->use_large_llq_hdr); 2285 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 2286 rc = -EFAULT; 2287 goto err_device_destroy; 2288 } 2289 2290 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 2291 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 2292 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 2293 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 2294 adapter->max_num_io_queues = max_num_io_queues; 2295 2296 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2297 disable_meta_caching = 2298 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 2299 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 2300 } else { 2301 disable_meta_caching = false; 2302 } 2303 2304 /* prepare ring structures */ 2305 ena_init_rings(adapter, disable_meta_caching); 2306 2307 ena_config_debug_area(adapter); 2308 2309 /* Set max MTU for this device */ 2310 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 2311 2312 ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload); 2313 2314 /* Copy MAC address and point DPDK to it */ 2315 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 2316 rte_ether_addr_copy((struct rte_ether_addr *) 2317 get_feat_ctx.dev_attr.mac_addr, 2318 (struct rte_ether_addr *)adapter->mac_addr); 2319 2320 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 2321 if (unlikely(rc != 0)) { 2322 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n"); 2323 goto err_delete_debug_area; 2324 } 2325 2326 adapter->drv_stats = rte_zmalloc("adapter stats", 2327 sizeof(*adapter->drv_stats), 2328 RTE_CACHE_LINE_SIZE); 2329 if (!adapter->drv_stats) { 2330 PMD_DRV_LOG(ERR, 2331 "Failed to allocate memory for adapter statistics\n"); 2332 rc = -ENOMEM; 2333 goto err_rss_destroy; 2334 } 2335 2336 rte_spinlock_init(&adapter->admin_lock); 2337 2338 rte_intr_callback_register(intr_handle, 2339 ena_interrupt_handler_rte, 2340 eth_dev); 2341 rte_intr_enable(intr_handle); 2342 ena_com_set_admin_polling_mode(ena_dev, false); 2343 ena_com_admin_aenq_enable(ena_dev); 2344 2345 rte_timer_init(&adapter->timer_wd); 2346 2347 adapters_found++; 2348 adapter->state = ENA_ADAPTER_STATE_INIT; 2349 2350 return 0; 2351 2352 err_rss_destroy: 2353 ena_com_rss_destroy(ena_dev); 2354 err_delete_debug_area: 2355 ena_com_delete_debug_area(ena_dev); 2356 2357 err_device_destroy: 2358 ena_com_delete_host_info(ena_dev); 2359 ena_com_admin_destroy(ena_dev); 2360 err_metrics_delete: 2361 ena_com_delete_customer_metrics_buffer(ena_dev); 2362 err: 2363 return rc; 2364 } 2365 2366 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 2367 { 2368 struct ena_adapter *adapter = eth_dev->data->dev_private; 2369 struct ena_com_dev *ena_dev = &adapter->ena_dev; 2370 2371 if (adapter->state == ENA_ADAPTER_STATE_FREE) 2372 return; 2373 2374 ena_com_set_admin_running_state(ena_dev, false); 2375 2376 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 2377 ena_close(eth_dev); 2378 2379 ena_com_rss_destroy(ena_dev); 2380 2381 ena_com_delete_debug_area(ena_dev); 2382 ena_com_delete_host_info(ena_dev); 2383 2384 ena_com_abort_admin_commands(ena_dev); 2385 ena_com_wait_for_abort_completion(ena_dev); 2386 ena_com_admin_destroy(ena_dev); 2387 ena_com_mmio_reg_read_request_destroy(ena_dev); 2388 ena_com_delete_customer_metrics_buffer(ena_dev); 2389 2390 adapter->state = ENA_ADAPTER_STATE_FREE; 2391 } 2392 2393 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 2394 { 2395 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2396 return 0; 2397 2398 ena_destroy_device(eth_dev); 2399 2400 return 0; 2401 } 2402 2403 static int ena_dev_configure(struct rte_eth_dev *dev) 2404 { 2405 struct ena_adapter *adapter = dev->data->dev_private; 2406 int rc; 2407 2408 adapter->state = ENA_ADAPTER_STATE_CONFIG; 2409 2410 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 2411 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2412 dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 2413 2414 /* Scattered Rx cannot be turned off in the HW, so this capability must 2415 * be forced. 2416 */ 2417 dev->data->scattered_rx = 1; 2418 2419 adapter->last_tx_comp_qid = 0; 2420 2421 adapter->missing_tx_completion_budget = 2422 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues); 2423 2424 /* To avoid detection of the spurious Tx completion timeout due to 2425 * application not calling the Tx cleanup function, set timeout for the 2426 * Tx queue which should be half of the missing completion timeout for a 2427 * safety. If there will be a lot of missing Tx completions in the 2428 * queue, they will be detected sooner or later. 2429 */ 2430 adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2; 2431 2432 rc = ena_configure_aenq(adapter); 2433 2434 return rc; 2435 } 2436 2437 static void ena_init_rings(struct ena_adapter *adapter, 2438 bool disable_meta_caching) 2439 { 2440 size_t i; 2441 2442 for (i = 0; i < adapter->max_num_io_queues; i++) { 2443 struct ena_ring *ring = &adapter->tx_ring[i]; 2444 2445 ring->configured = 0; 2446 ring->type = ENA_RING_TYPE_TX; 2447 ring->adapter = adapter; 2448 ring->id = i; 2449 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 2450 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 2451 ring->sgl_size = adapter->max_tx_sgl_size; 2452 ring->disable_meta_caching = disable_meta_caching; 2453 } 2454 2455 for (i = 0; i < adapter->max_num_io_queues; i++) { 2456 struct ena_ring *ring = &adapter->rx_ring[i]; 2457 2458 ring->configured = 0; 2459 ring->type = ENA_RING_TYPE_RX; 2460 ring->adapter = adapter; 2461 ring->id = i; 2462 ring->sgl_size = adapter->max_rx_sgl_size; 2463 } 2464 } 2465 2466 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter) 2467 { 2468 uint64_t port_offloads = 0; 2469 2470 if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM) 2471 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM; 2472 2473 if (adapter->offloads.rx_offloads & 2474 (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM)) 2475 port_offloads |= 2476 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM; 2477 2478 if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH) 2479 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2480 2481 port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; 2482 2483 return port_offloads; 2484 } 2485 2486 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter) 2487 { 2488 uint64_t port_offloads = 0; 2489 2490 if (adapter->offloads.tx_offloads & ENA_IPV4_TSO) 2491 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; 2492 2493 if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM) 2494 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; 2495 if (adapter->offloads.tx_offloads & 2496 (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM | 2497 ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL)) 2498 port_offloads |= 2499 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 2500 2501 port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 2502 2503 port_offloads |= RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 2504 2505 return port_offloads; 2506 } 2507 2508 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter) 2509 { 2510 RTE_SET_USED(adapter); 2511 2512 return 0; 2513 } 2514 2515 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter) 2516 { 2517 uint64_t queue_offloads = 0; 2518 RTE_SET_USED(adapter); 2519 2520 queue_offloads |= RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 2521 2522 return queue_offloads; 2523 } 2524 2525 static int ena_infos_get(struct rte_eth_dev *dev, 2526 struct rte_eth_dev_info *dev_info) 2527 { 2528 struct ena_adapter *adapter; 2529 struct ena_com_dev *ena_dev; 2530 2531 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 2532 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 2533 adapter = dev->data->dev_private; 2534 2535 ena_dev = &adapter->ena_dev; 2536 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 2537 2538 dev_info->speed_capa = 2539 RTE_ETH_LINK_SPEED_1G | 2540 RTE_ETH_LINK_SPEED_2_5G | 2541 RTE_ETH_LINK_SPEED_5G | 2542 RTE_ETH_LINK_SPEED_10G | 2543 RTE_ETH_LINK_SPEED_25G | 2544 RTE_ETH_LINK_SPEED_40G | 2545 RTE_ETH_LINK_SPEED_50G | 2546 RTE_ETH_LINK_SPEED_100G; 2547 2548 /* Inform framework about available features */ 2549 dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter); 2550 dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter); 2551 dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter); 2552 dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter); 2553 2554 dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF; 2555 dev_info->hash_key_size = ENA_HASH_KEY_SIZE; 2556 2557 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2558 dev_info->max_rx_pktlen = adapter->max_mtu + RTE_ETHER_HDR_LEN + 2559 RTE_ETHER_CRC_LEN; 2560 dev_info->min_mtu = ENA_MIN_MTU; 2561 dev_info->max_mtu = adapter->max_mtu; 2562 dev_info->max_mac_addrs = 1; 2563 2564 dev_info->max_rx_queues = adapter->max_num_io_queues; 2565 dev_info->max_tx_queues = adapter->max_num_io_queues; 2566 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2567 2568 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2569 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2570 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2571 adapter->max_rx_sgl_size); 2572 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2573 adapter->max_rx_sgl_size); 2574 2575 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2576 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2577 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2578 adapter->max_tx_sgl_size); 2579 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2580 adapter->max_tx_sgl_size); 2581 2582 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; 2583 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; 2584 2585 dev_info->err_handle_mode = RTE_ETH_ERROR_HANDLE_MODE_PASSIVE; 2586 2587 return 0; 2588 } 2589 2590 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 2591 { 2592 mbuf->data_len = len; 2593 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2594 mbuf->refcnt = 1; 2595 mbuf->next = NULL; 2596 } 2597 2598 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 2599 struct ena_com_rx_buf_info *ena_bufs, 2600 uint32_t descs, 2601 uint16_t *next_to_clean, 2602 uint8_t offset) 2603 { 2604 struct rte_mbuf *mbuf; 2605 struct rte_mbuf *mbuf_head; 2606 struct ena_rx_buffer *rx_info; 2607 int rc; 2608 uint16_t ntc, len, req_id, buf = 0; 2609 2610 if (unlikely(descs == 0)) 2611 return NULL; 2612 2613 ntc = *next_to_clean; 2614 2615 len = ena_bufs[buf].len; 2616 req_id = ena_bufs[buf].req_id; 2617 2618 rx_info = &rx_ring->rx_buffer_info[req_id]; 2619 2620 mbuf = rx_info->mbuf; 2621 RTE_ASSERT(mbuf != NULL); 2622 2623 ena_init_rx_mbuf(mbuf, len); 2624 2625 /* Fill the mbuf head with the data specific for 1st segment. */ 2626 mbuf_head = mbuf; 2627 mbuf_head->nb_segs = descs; 2628 mbuf_head->port = rx_ring->port_id; 2629 mbuf_head->pkt_len = len; 2630 mbuf_head->data_off += offset; 2631 2632 rx_info->mbuf = NULL; 2633 rx_ring->empty_rx_reqs[ntc] = req_id; 2634 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2635 2636 while (--descs) { 2637 ++buf; 2638 len = ena_bufs[buf].len; 2639 req_id = ena_bufs[buf].req_id; 2640 2641 rx_info = &rx_ring->rx_buffer_info[req_id]; 2642 RTE_ASSERT(rx_info->mbuf != NULL); 2643 2644 if (unlikely(len == 0)) { 2645 /* 2646 * Some devices can pass descriptor with the length 0. 2647 * To avoid confusion, the PMD is simply putting the 2648 * descriptor back, as it was never used. We'll avoid 2649 * mbuf allocation that way. 2650 */ 2651 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2652 rx_info->mbuf, req_id); 2653 if (unlikely(rc != 0)) { 2654 /* Free the mbuf in case of an error. */ 2655 rte_mbuf_raw_free(rx_info->mbuf); 2656 } else { 2657 /* 2658 * If there was no error, just exit the loop as 2659 * 0 length descriptor is always the last one. 2660 */ 2661 break; 2662 } 2663 } else { 2664 /* Create an mbuf chain. */ 2665 mbuf->next = rx_info->mbuf; 2666 mbuf = mbuf->next; 2667 2668 ena_init_rx_mbuf(mbuf, len); 2669 mbuf_head->pkt_len += len; 2670 } 2671 2672 /* 2673 * Mark the descriptor as depleted and perform necessary 2674 * cleanup. 2675 * This code will execute in two cases: 2676 * 1. Descriptor len was greater than 0 - normal situation. 2677 * 2. Descriptor len was 0 and we failed to add the descriptor 2678 * to the device. In that situation, we should try to add 2679 * the mbuf again in the populate routine and mark the 2680 * descriptor as used up by the device. 2681 */ 2682 rx_info->mbuf = NULL; 2683 rx_ring->empty_rx_reqs[ntc] = req_id; 2684 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2685 } 2686 2687 *next_to_clean = ntc; 2688 2689 return mbuf_head; 2690 } 2691 2692 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2693 uint16_t nb_pkts) 2694 { 2695 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2696 unsigned int free_queue_entries; 2697 uint16_t next_to_clean = rx_ring->next_to_clean; 2698 uint16_t descs_in_use; 2699 struct rte_mbuf *mbuf; 2700 uint16_t completed; 2701 struct ena_com_rx_ctx ena_rx_ctx; 2702 int i, rc = 0; 2703 bool fill_hash; 2704 2705 #ifdef RTE_ETHDEV_DEBUG_RX 2706 /* Check adapter state */ 2707 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2708 PMD_RX_LOG(ALERT, 2709 "Trying to receive pkts while device is NOT running\n"); 2710 return 0; 2711 } 2712 #endif 2713 2714 fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH; 2715 2716 descs_in_use = rx_ring->ring_size - 2717 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2718 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2719 2720 for (completed = 0; completed < nb_pkts; completed++) { 2721 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2722 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2723 ena_rx_ctx.descs = 0; 2724 ena_rx_ctx.pkt_offset = 0; 2725 /* receive packet context */ 2726 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2727 rx_ring->ena_com_io_sq, 2728 &ena_rx_ctx); 2729 if (unlikely(rc)) { 2730 PMD_RX_LOG(ERR, 2731 "Failed to get the packet from the device, rc: %d\n", 2732 rc); 2733 if (rc == ENA_COM_NO_SPACE) { 2734 ++rx_ring->rx_stats.bad_desc_num; 2735 ena_trigger_reset(rx_ring->adapter, 2736 ENA_REGS_RESET_TOO_MANY_RX_DESCS); 2737 } else { 2738 ++rx_ring->rx_stats.bad_req_id; 2739 ena_trigger_reset(rx_ring->adapter, 2740 ENA_REGS_RESET_INV_RX_REQ_ID); 2741 } 2742 return 0; 2743 } 2744 2745 mbuf = ena_rx_mbuf(rx_ring, 2746 ena_rx_ctx.ena_bufs, 2747 ena_rx_ctx.descs, 2748 &next_to_clean, 2749 ena_rx_ctx.pkt_offset); 2750 if (unlikely(mbuf == NULL)) { 2751 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2752 rx_ring->empty_rx_reqs[next_to_clean] = 2753 rx_ring->ena_bufs[i].req_id; 2754 next_to_clean = ENA_IDX_NEXT_MASKED( 2755 next_to_clean, rx_ring->size_mask); 2756 } 2757 break; 2758 } 2759 2760 /* fill mbuf attributes if any */ 2761 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash); 2762 2763 if (unlikely(mbuf->ol_flags & 2764 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD))) 2765 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2766 2767 rx_pkts[completed] = mbuf; 2768 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2769 } 2770 2771 rx_ring->rx_stats.cnt += completed; 2772 rx_ring->next_to_clean = next_to_clean; 2773 2774 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2775 2776 /* Burst refill to save doorbells, memory barriers, const interval */ 2777 if (free_queue_entries >= rx_ring->rx_free_thresh) { 2778 ena_populate_rx_queue(rx_ring, free_queue_entries); 2779 } 2780 2781 return completed; 2782 } 2783 2784 static uint16_t 2785 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2786 uint16_t nb_pkts) 2787 { 2788 int32_t ret; 2789 uint32_t i; 2790 struct rte_mbuf *m; 2791 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2792 struct ena_adapter *adapter = tx_ring->adapter; 2793 struct rte_ipv4_hdr *ip_hdr; 2794 uint64_t ol_flags; 2795 uint64_t l4_csum_flag; 2796 uint64_t dev_offload_capa; 2797 uint16_t frag_field; 2798 bool need_pseudo_csum; 2799 2800 dev_offload_capa = adapter->offloads.tx_offloads; 2801 for (i = 0; i != nb_pkts; i++) { 2802 m = tx_pkts[i]; 2803 ol_flags = m->ol_flags; 2804 2805 /* Check if any offload flag was set */ 2806 if (ol_flags == 0) 2807 continue; 2808 2809 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK; 2810 /* SCTP checksum offload is not supported by the ENA. */ 2811 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) || 2812 l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) { 2813 PMD_TX_LOG(DEBUG, 2814 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n", 2815 i, ol_flags); 2816 rte_errno = ENOTSUP; 2817 return i; 2818 } 2819 2820 if (unlikely(m->nb_segs >= tx_ring->sgl_size && 2821 !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2822 m->nb_segs == tx_ring->sgl_size && 2823 m->data_len < tx_ring->tx_max_header_size))) { 2824 PMD_TX_LOG(DEBUG, 2825 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n", 2826 i, m->nb_segs); 2827 rte_errno = EINVAL; 2828 return i; 2829 } 2830 2831 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2832 /* Check if requested offload is also enabled for the queue */ 2833 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM && 2834 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) || 2835 (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM && 2836 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) || 2837 (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM && 2838 !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) { 2839 PMD_TX_LOG(DEBUG, 2840 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n", 2841 i, m->nb_segs, tx_ring->id); 2842 rte_errno = EINVAL; 2843 return i; 2844 } 2845 2846 /* The caller is obligated to set l2 and l3 len if any cksum 2847 * offload is enabled. 2848 */ 2849 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) && 2850 (m->l2_len == 0 || m->l3_len == 0))) { 2851 PMD_TX_LOG(DEBUG, 2852 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n", 2853 i); 2854 rte_errno = EINVAL; 2855 return i; 2856 } 2857 ret = rte_validate_tx_offload(m); 2858 if (ret != 0) { 2859 rte_errno = -ret; 2860 return i; 2861 } 2862 #endif 2863 2864 /* Verify HW support for requested offloads and determine if 2865 * pseudo header checksum is needed. 2866 */ 2867 need_pseudo_csum = false; 2868 if (ol_flags & RTE_MBUF_F_TX_IPV4) { 2869 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM && 2870 !(dev_offload_capa & ENA_L3_IPV4_CSUM)) { 2871 rte_errno = ENOTSUP; 2872 return i; 2873 } 2874 2875 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG && 2876 !(dev_offload_capa & ENA_IPV4_TSO)) { 2877 rte_errno = ENOTSUP; 2878 return i; 2879 } 2880 2881 /* Check HW capabilities and if pseudo csum is needed 2882 * for L4 offloads. 2883 */ 2884 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM && 2885 !(dev_offload_capa & ENA_L4_IPV4_CSUM)) { 2886 if (dev_offload_capa & 2887 ENA_L4_IPV4_CSUM_PARTIAL) { 2888 need_pseudo_csum = true; 2889 } else { 2890 rte_errno = ENOTSUP; 2891 return i; 2892 } 2893 } 2894 2895 /* Parse the DF flag */ 2896 ip_hdr = rte_pktmbuf_mtod_offset(m, 2897 struct rte_ipv4_hdr *, m->l2_len); 2898 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2899 if (frag_field & RTE_IPV4_HDR_DF_FLAG) { 2900 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2901 } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { 2902 /* In case we are supposed to TSO and have DF 2903 * not set (DF=0) hardware must be provided with 2904 * partial checksum. 2905 */ 2906 need_pseudo_csum = true; 2907 } 2908 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) { 2909 /* There is no support for IPv6 TSO as for now. */ 2910 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { 2911 rte_errno = ENOTSUP; 2912 return i; 2913 } 2914 2915 /* Check HW capabilities and if pseudo csum is needed */ 2916 if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM && 2917 !(dev_offload_capa & ENA_L4_IPV6_CSUM)) { 2918 if (dev_offload_capa & 2919 ENA_L4_IPV6_CSUM_PARTIAL) { 2920 need_pseudo_csum = true; 2921 } else { 2922 rte_errno = ENOTSUP; 2923 return i; 2924 } 2925 } 2926 } 2927 2928 if (need_pseudo_csum) { 2929 ret = rte_net_intel_cksum_flags_prepare(m, ol_flags); 2930 if (ret != 0) { 2931 rte_errno = -ret; 2932 return i; 2933 } 2934 } 2935 } 2936 2937 return i; 2938 } 2939 2940 static void ena_update_hints(struct ena_adapter *adapter, 2941 struct ena_admin_ena_hw_hints *hints) 2942 { 2943 if (hints->admin_completion_tx_timeout) 2944 adapter->ena_dev.admin_queue.completion_timeout = 2945 hints->admin_completion_tx_timeout * 1000; 2946 2947 if (hints->mmio_read_timeout) 2948 /* convert to usec */ 2949 adapter->ena_dev.mmio_read.reg_read_to = 2950 hints->mmio_read_timeout * 1000; 2951 2952 if (hints->driver_watchdog_timeout) { 2953 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2954 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2955 else 2956 // Convert msecs to ticks 2957 adapter->keep_alive_timeout = 2958 (hints->driver_watchdog_timeout * 2959 rte_get_timer_hz()) / 1000; 2960 } 2961 } 2962 2963 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2964 struct ena_tx_buffer *tx_info, 2965 struct rte_mbuf *mbuf, 2966 void **push_header, 2967 uint16_t *header_len) 2968 { 2969 struct ena_com_buf *ena_buf; 2970 uint16_t delta, seg_len, push_len; 2971 2972 delta = 0; 2973 seg_len = mbuf->data_len; 2974 2975 tx_info->mbuf = mbuf; 2976 ena_buf = tx_info->bufs; 2977 2978 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2979 /* 2980 * Tx header might be (and will be in most cases) smaller than 2981 * tx_max_header_size. But it's not an issue to send more data 2982 * to the device, than actually needed if the mbuf size is 2983 * greater than tx_max_header_size. 2984 */ 2985 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2986 *header_len = push_len; 2987 2988 if (likely(push_len <= seg_len)) { 2989 /* If the push header is in the single segment, then 2990 * just point it to the 1st mbuf data. 2991 */ 2992 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2993 } else { 2994 /* If the push header lays in the several segments, copy 2995 * it to the intermediate buffer. 2996 */ 2997 rte_pktmbuf_read(mbuf, 0, push_len, 2998 tx_ring->push_buf_intermediate_buf); 2999 *push_header = tx_ring->push_buf_intermediate_buf; 3000 delta = push_len - seg_len; 3001 } 3002 } else { 3003 *push_header = NULL; 3004 *header_len = 0; 3005 push_len = 0; 3006 } 3007 3008 /* Process first segment taking into consideration pushed header */ 3009 if (seg_len > push_len) { 3010 ena_buf->paddr = mbuf->buf_iova + 3011 mbuf->data_off + 3012 push_len; 3013 ena_buf->len = seg_len - push_len; 3014 ena_buf++; 3015 tx_info->num_of_bufs++; 3016 } 3017 3018 while ((mbuf = mbuf->next) != NULL) { 3019 seg_len = mbuf->data_len; 3020 3021 /* Skip mbufs if whole data is pushed as a header */ 3022 if (unlikely(delta > seg_len)) { 3023 delta -= seg_len; 3024 continue; 3025 } 3026 3027 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 3028 ena_buf->len = seg_len - delta; 3029 ena_buf++; 3030 tx_info->num_of_bufs++; 3031 3032 delta = 0; 3033 } 3034 } 3035 3036 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 3037 { 3038 struct ena_tx_buffer *tx_info; 3039 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 3040 uint16_t next_to_use; 3041 uint16_t header_len; 3042 uint16_t req_id; 3043 void *push_header; 3044 int nb_hw_desc; 3045 int rc; 3046 3047 /* Checking for space for 2 additional metadata descriptors due to 3048 * possible header split and metadata descriptor 3049 */ 3050 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3051 mbuf->nb_segs + 2)) { 3052 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n"); 3053 return ENA_COM_NO_MEM; 3054 } 3055 3056 next_to_use = tx_ring->next_to_use; 3057 3058 req_id = tx_ring->empty_tx_reqs[next_to_use]; 3059 tx_info = &tx_ring->tx_buffer_info[req_id]; 3060 tx_info->num_of_bufs = 0; 3061 RTE_ASSERT(tx_info->mbuf == NULL); 3062 3063 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 3064 3065 ena_tx_ctx.ena_bufs = tx_info->bufs; 3066 ena_tx_ctx.push_header = push_header; 3067 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 3068 ena_tx_ctx.req_id = req_id; 3069 ena_tx_ctx.header_len = header_len; 3070 3071 /* Set Tx offloads flags, if applicable */ 3072 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 3073 tx_ring->disable_meta_caching); 3074 3075 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 3076 &ena_tx_ctx))) { 3077 PMD_TX_LOG(DEBUG, 3078 "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n", 3079 tx_ring->id); 3080 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 3081 tx_ring->tx_stats.doorbells++; 3082 tx_ring->pkts_without_db = false; 3083 } 3084 3085 /* prepare the packet's descriptors to dma engine */ 3086 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 3087 &nb_hw_desc); 3088 if (unlikely(rc)) { 3089 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc); 3090 ++tx_ring->tx_stats.prepare_ctx_err; 3091 ena_trigger_reset(tx_ring->adapter, 3092 ENA_REGS_RESET_DRIVER_INVALID_STATE); 3093 return rc; 3094 } 3095 3096 tx_info->tx_descs = nb_hw_desc; 3097 tx_info->timestamp = rte_get_timer_cycles(); 3098 3099 tx_ring->tx_stats.cnt++; 3100 tx_ring->tx_stats.bytes += mbuf->pkt_len; 3101 3102 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 3103 tx_ring->size_mask); 3104 3105 return 0; 3106 } 3107 3108 static __rte_always_inline size_t 3109 ena_tx_cleanup_mbuf_fast(struct rte_mbuf **mbufs_to_clean, 3110 struct rte_mbuf *mbuf, 3111 size_t mbuf_cnt, 3112 size_t buf_size) 3113 { 3114 struct rte_mbuf *m_next; 3115 3116 while (mbuf != NULL) { 3117 m_next = mbuf->next; 3118 mbufs_to_clean[mbuf_cnt++] = mbuf; 3119 if (mbuf_cnt == buf_size) { 3120 rte_mempool_put_bulk(mbufs_to_clean[0]->pool, (void **)mbufs_to_clean, 3121 (unsigned int)mbuf_cnt); 3122 mbuf_cnt = 0; 3123 } 3124 mbuf = m_next; 3125 } 3126 3127 return mbuf_cnt; 3128 } 3129 3130 static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt) 3131 { 3132 struct rte_mbuf *mbufs_to_clean[ENA_CLEANUP_BUF_SIZE]; 3133 struct ena_ring *tx_ring = (struct ena_ring *)txp; 3134 size_t mbuf_cnt = 0; 3135 unsigned int total_tx_descs = 0; 3136 unsigned int total_tx_pkts = 0; 3137 uint16_t cleanup_budget; 3138 uint16_t next_to_clean = tx_ring->next_to_clean; 3139 bool fast_free = tx_ring->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 3140 3141 /* 3142 * If free_pkt_cnt is equal to 0, it means that the user requested 3143 * full cleanup, so attempt to release all Tx descriptors 3144 * (ring_size - 1 -> size_mask) 3145 */ 3146 cleanup_budget = (free_pkt_cnt == 0) ? tx_ring->size_mask : free_pkt_cnt; 3147 3148 while (likely(total_tx_pkts < cleanup_budget)) { 3149 struct rte_mbuf *mbuf; 3150 struct ena_tx_buffer *tx_info; 3151 uint16_t req_id; 3152 3153 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 3154 break; 3155 3156 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 3157 break; 3158 3159 /* Get Tx info & store how many descs were processed */ 3160 tx_info = &tx_ring->tx_buffer_info[req_id]; 3161 tx_info->timestamp = 0; 3162 3163 mbuf = tx_info->mbuf; 3164 if (fast_free) { 3165 mbuf_cnt = ena_tx_cleanup_mbuf_fast(mbufs_to_clean, mbuf, mbuf_cnt, 3166 ENA_CLEANUP_BUF_SIZE); 3167 } else { 3168 rte_pktmbuf_free(mbuf); 3169 } 3170 3171 tx_info->mbuf = NULL; 3172 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 3173 3174 total_tx_descs += tx_info->tx_descs; 3175 total_tx_pkts++; 3176 3177 /* Put back descriptor to the ring for reuse */ 3178 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 3179 tx_ring->size_mask); 3180 } 3181 3182 if (likely(total_tx_descs > 0)) { 3183 /* acknowledge completion of sent packets */ 3184 tx_ring->next_to_clean = next_to_clean; 3185 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 3186 } 3187 3188 if (mbuf_cnt != 0) 3189 rte_mempool_put_bulk(mbufs_to_clean[0]->pool, 3190 (void **)mbufs_to_clean, mbuf_cnt); 3191 3192 /* Notify completion handler that full cleanup was performed */ 3193 if (free_pkt_cnt == 0 || total_tx_pkts < cleanup_budget) 3194 tx_ring->last_cleanup_ticks = rte_get_timer_cycles(); 3195 3196 return total_tx_pkts; 3197 } 3198 3199 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 3200 uint16_t nb_pkts) 3201 { 3202 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 3203 int available_desc; 3204 uint16_t sent_idx = 0; 3205 3206 #ifdef RTE_ETHDEV_DEBUG_TX 3207 /* Check adapter state */ 3208 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 3209 PMD_TX_LOG(ALERT, 3210 "Trying to xmit pkts while device is NOT running\n"); 3211 return 0; 3212 } 3213 #endif 3214 3215 available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq); 3216 if (available_desc < tx_ring->tx_free_thresh) 3217 ena_tx_cleanup((void *)tx_ring, 0); 3218 3219 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 3220 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 3221 break; 3222 tx_ring->pkts_without_db = true; 3223 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 3224 tx_ring->size_mask)]); 3225 } 3226 3227 /* If there are ready packets to be xmitted... */ 3228 if (likely(tx_ring->pkts_without_db)) { 3229 /* ...let HW do its best :-) */ 3230 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 3231 tx_ring->tx_stats.doorbells++; 3232 tx_ring->pkts_without_db = false; 3233 } 3234 3235 tx_ring->tx_stats.available_desc = 3236 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 3237 tx_ring->tx_stats.tx_poll++; 3238 3239 return sent_idx; 3240 } 3241 3242 static void ena_copy_customer_metrics(struct ena_adapter *adapter, uint64_t *buf, 3243 size_t num_metrics) 3244 { 3245 struct ena_com_dev *ena_dev = &adapter->ena_dev; 3246 int rc; 3247 3248 if (ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) { 3249 if (num_metrics != ENA_STATS_ARRAY_METRICS) { 3250 PMD_DRV_LOG(ERR, "Detected discrepancy in the number of customer metrics"); 3251 return; 3252 } 3253 rte_spinlock_lock(&adapter->admin_lock); 3254 rc = ENA_PROXY(adapter, 3255 ena_com_get_customer_metrics, 3256 &adapter->ena_dev, 3257 (char *)buf, 3258 num_metrics * sizeof(uint64_t)); 3259 rte_spinlock_unlock(&adapter->admin_lock); 3260 if (rc != 0) { 3261 PMD_DRV_LOG(WARNING, "Failed to get customer metrics, rc: %d\n", rc); 3262 return; 3263 } 3264 3265 } else if (ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) { 3266 if (num_metrics != ENA_STATS_ARRAY_METRICS_LEGACY) { 3267 PMD_DRV_LOG(ERR, "Detected discrepancy in the number of legacy metrics"); 3268 return; 3269 } 3270 3271 rte_spinlock_lock(&adapter->admin_lock); 3272 rc = ENA_PROXY(adapter, 3273 ena_com_get_eni_stats, 3274 &adapter->ena_dev, 3275 (struct ena_admin_eni_stats *)buf); 3276 rte_spinlock_unlock(&adapter->admin_lock); 3277 if (rc != 0) { 3278 PMD_DRV_LOG(WARNING, 3279 "Failed to get ENI metrics, rc: %d\n", rc); 3280 return; 3281 } 3282 } 3283 } 3284 3285 static void ena_copy_ena_srd_info(struct ena_adapter *adapter, 3286 struct ena_stats_srd *srd_info) 3287 { 3288 int rc; 3289 3290 if (!ena_com_get_cap(&adapter->ena_dev, ENA_ADMIN_ENA_SRD_INFO)) 3291 return; 3292 3293 rte_spinlock_lock(&adapter->admin_lock); 3294 rc = ENA_PROXY(adapter, 3295 ena_com_get_ena_srd_info, 3296 &adapter->ena_dev, 3297 (struct ena_admin_ena_srd_info *)srd_info); 3298 rte_spinlock_unlock(&adapter->admin_lock); 3299 if (rc != ENA_COM_OK && rc != ENA_COM_UNSUPPORTED) { 3300 PMD_DRV_LOG(WARNING, 3301 "Failed to get ENA express srd info, rc: %d\n", rc); 3302 return; 3303 } 3304 } 3305 3306 /** 3307 * DPDK callback to retrieve names of extended device statistics 3308 * 3309 * @param dev 3310 * Pointer to Ethernet device structure. 3311 * @param[out] xstats_names 3312 * Buffer to insert names into. 3313 * @param n 3314 * Number of names. 3315 * 3316 * @return 3317 * Number of xstats names. 3318 */ 3319 static int ena_xstats_get_names(struct rte_eth_dev *dev, 3320 struct rte_eth_xstat_name *xstats_names, 3321 unsigned int n) 3322 { 3323 struct ena_adapter *adapter = dev->data->dev_private; 3324 unsigned int xstats_count = ena_xstats_calc_num(dev->data); 3325 unsigned int stat, i, count = 0; 3326 3327 if (n < xstats_count || !xstats_names) 3328 return xstats_count; 3329 3330 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 3331 strcpy(xstats_names[count].name, 3332 ena_stats_global_strings[stat].name); 3333 3334 for (stat = 0; stat < adapter->metrics_num; stat++, count++) 3335 rte_strscpy(xstats_names[count].name, 3336 ena_stats_metrics_strings[stat].name, 3337 RTE_ETH_XSTATS_NAME_SIZE); 3338 for (stat = 0; stat < ENA_STATS_ARRAY_ENA_SRD; stat++, count++) 3339 rte_strscpy(xstats_names[count].name, 3340 ena_stats_srd_strings[stat].name, 3341 RTE_ETH_XSTATS_NAME_SIZE); 3342 3343 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 3344 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 3345 snprintf(xstats_names[count].name, 3346 sizeof(xstats_names[count].name), 3347 "rx_q%d_%s", i, 3348 ena_stats_rx_strings[stat].name); 3349 3350 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 3351 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 3352 snprintf(xstats_names[count].name, 3353 sizeof(xstats_names[count].name), 3354 "tx_q%d_%s", i, 3355 ena_stats_tx_strings[stat].name); 3356 3357 return xstats_count; 3358 } 3359 3360 /** 3361 * DPDK callback to retrieve names of extended device statistics for the given 3362 * ids. 3363 * 3364 * @param dev 3365 * Pointer to Ethernet device structure. 3366 * @param[out] xstats_names 3367 * Buffer to insert names into. 3368 * @param ids 3369 * IDs array for which the names should be retrieved. 3370 * @param size 3371 * Number of ids. 3372 * 3373 * @return 3374 * Positive value: number of xstats names. Negative value: error code. 3375 */ 3376 static int ena_xstats_get_names_by_id(struct rte_eth_dev *dev, 3377 const uint64_t *ids, 3378 struct rte_eth_xstat_name *xstats_names, 3379 unsigned int size) 3380 { 3381 struct ena_adapter *adapter = dev->data->dev_private; 3382 uint64_t xstats_count = ena_xstats_calc_num(dev->data); 3383 uint64_t id, qid; 3384 unsigned int i; 3385 3386 if (xstats_names == NULL) 3387 return xstats_count; 3388 3389 for (i = 0; i < size; ++i) { 3390 id = ids[i]; 3391 if (id > xstats_count) { 3392 PMD_DRV_LOG(ERR, 3393 "ID value out of range: id=%" PRIu64 ", xstats_num=%" PRIu64 "\n", 3394 id, xstats_count); 3395 return -EINVAL; 3396 } 3397 3398 if (id < ENA_STATS_ARRAY_GLOBAL) { 3399 strcpy(xstats_names[i].name, 3400 ena_stats_global_strings[id].name); 3401 continue; 3402 } 3403 3404 id -= ENA_STATS_ARRAY_GLOBAL; 3405 if (id < adapter->metrics_num) { 3406 rte_strscpy(xstats_names[i].name, 3407 ena_stats_metrics_strings[id].name, 3408 RTE_ETH_XSTATS_NAME_SIZE); 3409 continue; 3410 } 3411 3412 id -= adapter->metrics_num; 3413 3414 if (id < ENA_STATS_ARRAY_ENA_SRD) { 3415 rte_strscpy(xstats_names[i].name, 3416 ena_stats_srd_strings[id].name, 3417 RTE_ETH_XSTATS_NAME_SIZE); 3418 continue; 3419 } 3420 id -= ENA_STATS_ARRAY_ENA_SRD; 3421 3422 if (id < ENA_STATS_ARRAY_RX) { 3423 qid = id / dev->data->nb_rx_queues; 3424 id %= dev->data->nb_rx_queues; 3425 snprintf(xstats_names[i].name, 3426 sizeof(xstats_names[i].name), 3427 "rx_q%" PRIu64 "d_%s", 3428 qid, ena_stats_rx_strings[id].name); 3429 continue; 3430 } 3431 3432 id -= ENA_STATS_ARRAY_RX; 3433 /* Although this condition is not needed, it was added for 3434 * compatibility if new xstat structure would be ever added. 3435 */ 3436 if (id < ENA_STATS_ARRAY_TX) { 3437 qid = id / dev->data->nb_tx_queues; 3438 id %= dev->data->nb_tx_queues; 3439 snprintf(xstats_names[i].name, 3440 sizeof(xstats_names[i].name), 3441 "tx_q%" PRIu64 "_%s", 3442 qid, ena_stats_tx_strings[id].name); 3443 continue; 3444 } 3445 } 3446 3447 return i; 3448 } 3449 3450 /** 3451 * DPDK callback to get extended device statistics. 3452 * 3453 * @param dev 3454 * Pointer to Ethernet device structure. 3455 * @param[out] stats 3456 * Stats table output buffer. 3457 * @param n 3458 * The size of the stats table. 3459 * 3460 * @return 3461 * Number of xstats on success, negative on failure. 3462 */ 3463 static int ena_xstats_get(struct rte_eth_dev *dev, 3464 struct rte_eth_xstat *xstats, 3465 unsigned int n) 3466 { 3467 struct ena_adapter *adapter = dev->data->dev_private; 3468 unsigned int xstats_count = ena_xstats_calc_num(dev->data); 3469 unsigned int stat, i, count = 0; 3470 int stat_offset; 3471 void *stats_begin; 3472 uint64_t metrics_stats[ENA_MAX_CUSTOMER_METRICS]; 3473 struct ena_stats_srd srd_info = {0}; 3474 3475 if (n < xstats_count) 3476 return xstats_count; 3477 3478 if (!xstats) 3479 return 0; 3480 3481 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 3482 stat_offset = ena_stats_global_strings[stat].stat_offset; 3483 stats_begin = &adapter->dev_stats; 3484 3485 xstats[count].id = count; 3486 xstats[count].value = *((uint64_t *) 3487 ((char *)stats_begin + stat_offset)); 3488 } 3489 3490 ena_copy_customer_metrics(adapter, metrics_stats, adapter->metrics_num); 3491 stats_begin = metrics_stats; 3492 for (stat = 0; stat < adapter->metrics_num; stat++, count++) { 3493 stat_offset = ena_stats_metrics_strings[stat].stat_offset; 3494 3495 xstats[count].id = count; 3496 xstats[count].value = *((uint64_t *) 3497 ((char *)stats_begin + stat_offset)); 3498 } 3499 3500 ena_copy_ena_srd_info(adapter, &srd_info); 3501 stats_begin = &srd_info; 3502 for (stat = 0; stat < ENA_STATS_ARRAY_ENA_SRD; stat++, count++) { 3503 stat_offset = ena_stats_srd_strings[stat].stat_offset; 3504 xstats[count].id = count; 3505 xstats[count].value = *((uint64_t *) 3506 ((char *)stats_begin + stat_offset)); 3507 } 3508 3509 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 3510 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 3511 stat_offset = ena_stats_rx_strings[stat].stat_offset; 3512 stats_begin = &adapter->rx_ring[i].rx_stats; 3513 3514 xstats[count].id = count; 3515 xstats[count].value = *((uint64_t *) 3516 ((char *)stats_begin + stat_offset)); 3517 } 3518 } 3519 3520 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 3521 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 3522 stat_offset = ena_stats_tx_strings[stat].stat_offset; 3523 stats_begin = &adapter->tx_ring[i].rx_stats; 3524 3525 xstats[count].id = count; 3526 xstats[count].value = *((uint64_t *) 3527 ((char *)stats_begin + stat_offset)); 3528 } 3529 } 3530 3531 return count; 3532 } 3533 3534 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 3535 const uint64_t *ids, 3536 uint64_t *values, 3537 unsigned int n) 3538 { 3539 struct ena_adapter *adapter = dev->data->dev_private; 3540 uint64_t id; 3541 uint64_t rx_entries, tx_entries; 3542 unsigned int i; 3543 int qid; 3544 int valid = 0; 3545 bool were_metrics_copied = false; 3546 bool was_srd_info_copied = false; 3547 uint64_t metrics_stats[ENA_MAX_CUSTOMER_METRICS]; 3548 struct ena_stats_srd srd_info = {0}; 3549 3550 for (i = 0; i < n; ++i) { 3551 id = ids[i]; 3552 /* Check if id belongs to global statistics */ 3553 if (id < ENA_STATS_ARRAY_GLOBAL) { 3554 values[i] = *((uint64_t *)&adapter->dev_stats + id); 3555 ++valid; 3556 continue; 3557 } 3558 3559 /* Check if id belongs to ENI statistics */ 3560 id -= ENA_STATS_ARRAY_GLOBAL; 3561 if (id < adapter->metrics_num) { 3562 /* Avoid reading metrics multiple times in a single 3563 * function call, as it requires communication with the 3564 * admin queue. 3565 */ 3566 if (!were_metrics_copied) { 3567 were_metrics_copied = true; 3568 ena_copy_customer_metrics(adapter, 3569 metrics_stats, 3570 adapter->metrics_num); 3571 } 3572 3573 values[i] = *((uint64_t *)&metrics_stats + id); 3574 ++valid; 3575 continue; 3576 } 3577 3578 /* Check if id belongs to SRD info statistics */ 3579 id -= adapter->metrics_num; 3580 3581 if (id < ENA_STATS_ARRAY_ENA_SRD) { 3582 /* 3583 * Avoid reading srd info multiple times in a single 3584 * function call, as it requires communication with the 3585 * admin queue. 3586 */ 3587 if (!was_srd_info_copied) { 3588 was_srd_info_copied = true; 3589 ena_copy_ena_srd_info(adapter, &srd_info); 3590 } 3591 values[i] = *((uint64_t *)&adapter->srd_stats + id); 3592 ++valid; 3593 continue; 3594 } 3595 3596 /* Check if id belongs to rx queue statistics */ 3597 id -= ENA_STATS_ARRAY_ENA_SRD; 3598 3599 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 3600 if (id < rx_entries) { 3601 qid = id % dev->data->nb_rx_queues; 3602 id /= dev->data->nb_rx_queues; 3603 values[i] = *((uint64_t *) 3604 &adapter->rx_ring[qid].rx_stats + id); 3605 ++valid; 3606 continue; 3607 } 3608 /* Check if id belongs to rx queue statistics */ 3609 id -= rx_entries; 3610 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 3611 if (id < tx_entries) { 3612 qid = id % dev->data->nb_tx_queues; 3613 id /= dev->data->nb_tx_queues; 3614 values[i] = *((uint64_t *) 3615 &adapter->tx_ring[qid].tx_stats + id); 3616 ++valid; 3617 continue; 3618 } 3619 } 3620 3621 return valid; 3622 } 3623 3624 static int ena_process_uint_devarg(const char *key, 3625 const char *value, 3626 void *opaque) 3627 { 3628 struct ena_adapter *adapter = opaque; 3629 char *str_end; 3630 uint64_t uint_value; 3631 3632 uint_value = strtoull(value, &str_end, 10); 3633 if (value == str_end) { 3634 PMD_INIT_LOG(ERR, 3635 "Invalid value for key '%s'. Only uint values are accepted.\n", 3636 key); 3637 return -EINVAL; 3638 } 3639 3640 if (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) { 3641 if (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) { 3642 PMD_INIT_LOG(ERR, 3643 "Tx timeout too high: %" PRIu64 " sec. Maximum allowed: %d sec.\n", 3644 uint_value, ENA_MAX_TX_TIMEOUT_SECONDS); 3645 return -EINVAL; 3646 } else if (uint_value == 0) { 3647 PMD_INIT_LOG(INFO, 3648 "Check for missing Tx completions has been disabled.\n"); 3649 adapter->missing_tx_completion_to = 3650 ENA_HW_HINTS_NO_TIMEOUT; 3651 } else { 3652 PMD_INIT_LOG(INFO, 3653 "Tx packet completion timeout set to %" PRIu64 " seconds.\n", 3654 uint_value); 3655 adapter->missing_tx_completion_to = 3656 uint_value * rte_get_timer_hz(); 3657 } 3658 } 3659 3660 return 0; 3661 } 3662 3663 static int ena_process_bool_devarg(const char *key, 3664 const char *value, 3665 void *opaque) 3666 { 3667 struct ena_adapter *adapter = opaque; 3668 bool bool_value; 3669 3670 /* Parse the value. */ 3671 if (strcmp(value, "1") == 0) { 3672 bool_value = true; 3673 } else if (strcmp(value, "0") == 0) { 3674 bool_value = false; 3675 } else { 3676 PMD_INIT_LOG(ERR, 3677 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 3678 value, key); 3679 return -EINVAL; 3680 } 3681 3682 /* Now, assign it to the proper adapter field. */ 3683 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) 3684 adapter->use_large_llq_hdr = bool_value; 3685 else if (strcmp(key, ENA_DEVARG_ENABLE_LLQ) == 0) 3686 adapter->enable_llq = bool_value; 3687 3688 return 0; 3689 } 3690 3691 static int ena_parse_devargs(struct ena_adapter *adapter, 3692 struct rte_devargs *devargs) 3693 { 3694 static const char * const allowed_args[] = { 3695 ENA_DEVARG_LARGE_LLQ_HDR, 3696 ENA_DEVARG_MISS_TXC_TO, 3697 ENA_DEVARG_ENABLE_LLQ, 3698 NULL, 3699 }; 3700 struct rte_kvargs *kvlist; 3701 int rc; 3702 3703 if (devargs == NULL) 3704 return 0; 3705 3706 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 3707 if (kvlist == NULL) { 3708 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 3709 devargs->args); 3710 return -EINVAL; 3711 } 3712 3713 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 3714 ena_process_bool_devarg, adapter); 3715 if (rc != 0) 3716 goto exit; 3717 rc = rte_kvargs_process(kvlist, ENA_DEVARG_MISS_TXC_TO, 3718 ena_process_uint_devarg, adapter); 3719 if (rc != 0) 3720 goto exit; 3721 rc = rte_kvargs_process(kvlist, ENA_DEVARG_ENABLE_LLQ, 3722 ena_process_bool_devarg, adapter); 3723 3724 exit: 3725 rte_kvargs_free(kvlist); 3726 3727 return rc; 3728 } 3729 3730 static int ena_setup_rx_intr(struct rte_eth_dev *dev) 3731 { 3732 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3733 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3734 int rc; 3735 uint16_t vectors_nb, i; 3736 bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq; 3737 3738 if (!rx_intr_requested) 3739 return 0; 3740 3741 if (!rte_intr_cap_multiple(intr_handle)) { 3742 PMD_DRV_LOG(ERR, 3743 "Rx interrupt requested, but it isn't supported by the PCI driver\n"); 3744 return -ENOTSUP; 3745 } 3746 3747 /* Disable interrupt mapping before the configuration starts. */ 3748 rte_intr_disable(intr_handle); 3749 3750 /* Verify if there are enough vectors available. */ 3751 vectors_nb = dev->data->nb_rx_queues; 3752 if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) { 3753 PMD_DRV_LOG(ERR, 3754 "Too many Rx interrupts requested, maximum number: %d\n", 3755 RTE_MAX_RXTX_INTR_VEC_ID); 3756 rc = -ENOTSUP; 3757 goto enable_intr; 3758 } 3759 3760 /* Allocate the vector list */ 3761 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 3762 dev->data->nb_rx_queues)) { 3763 PMD_DRV_LOG(ERR, 3764 "Failed to allocate interrupt vector for %d queues\n", 3765 dev->data->nb_rx_queues); 3766 rc = -ENOMEM; 3767 goto enable_intr; 3768 } 3769 3770 rc = rte_intr_efd_enable(intr_handle, vectors_nb); 3771 if (rc != 0) 3772 goto free_intr_vec; 3773 3774 if (!rte_intr_allow_others(intr_handle)) { 3775 PMD_DRV_LOG(ERR, 3776 "Not enough interrupts available to use both ENA Admin and Rx interrupts\n"); 3777 goto disable_intr_efd; 3778 } 3779 3780 for (i = 0; i < vectors_nb; ++i) 3781 if (rte_intr_vec_list_index_set(intr_handle, i, 3782 RTE_INTR_VEC_RXTX_OFFSET + i)) 3783 goto disable_intr_efd; 3784 3785 rte_intr_enable(intr_handle); 3786 return 0; 3787 3788 disable_intr_efd: 3789 rte_intr_efd_disable(intr_handle); 3790 free_intr_vec: 3791 rte_intr_vec_list_free(intr_handle); 3792 enable_intr: 3793 rte_intr_enable(intr_handle); 3794 return rc; 3795 } 3796 3797 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev, 3798 uint16_t queue_id, 3799 bool unmask) 3800 { 3801 struct ena_adapter *adapter = dev->data->dev_private; 3802 struct ena_ring *rxq = &adapter->rx_ring[queue_id]; 3803 struct ena_eth_io_intr_reg intr_reg; 3804 3805 ena_com_update_intr_reg(&intr_reg, 0, 0, unmask, 1); 3806 ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg); 3807 } 3808 3809 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, 3810 uint16_t queue_id) 3811 { 3812 ena_rx_queue_intr_set(dev, queue_id, true); 3813 3814 return 0; 3815 } 3816 3817 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, 3818 uint16_t queue_id) 3819 { 3820 ena_rx_queue_intr_set(dev, queue_id, false); 3821 3822 return 0; 3823 } 3824 3825 static int ena_configure_aenq(struct ena_adapter *adapter) 3826 { 3827 uint32_t aenq_groups = adapter->all_aenq_groups; 3828 int rc; 3829 3830 /* All_aenq_groups holds all AENQ functions supported by the device and 3831 * the HW, so at first we need to be sure the LSC request is valid. 3832 */ 3833 if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) { 3834 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) { 3835 PMD_DRV_LOG(ERR, 3836 "LSC requested, but it's not supported by the AENQ\n"); 3837 return -EINVAL; 3838 } 3839 } else { 3840 /* If LSC wasn't enabled by the app, let's enable all supported 3841 * AENQ procedures except the LSC. 3842 */ 3843 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE); 3844 } 3845 3846 rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups); 3847 if (rc != 0) { 3848 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc); 3849 return rc; 3850 } 3851 3852 adapter->active_aenq_groups = aenq_groups; 3853 3854 return 0; 3855 } 3856 3857 int ena_mp_indirect_table_set(struct ena_adapter *adapter) 3858 { 3859 return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev); 3860 } 3861 3862 int ena_mp_indirect_table_get(struct ena_adapter *adapter, 3863 uint32_t *indirect_table) 3864 { 3865 return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev, 3866 indirect_table); 3867 } 3868 3869 /********************************************************************* 3870 * ena_plat_dpdk.h functions implementations 3871 *********************************************************************/ 3872 3873 const struct rte_memzone * 3874 ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size, 3875 int socket_id, unsigned int alignment, void **virt_addr, 3876 dma_addr_t *phys_addr) 3877 { 3878 char z_name[RTE_MEMZONE_NAMESIZE]; 3879 struct ena_adapter *adapter = data->dev_private; 3880 const struct rte_memzone *memzone; 3881 int rc; 3882 3883 rc = snprintf(z_name, RTE_MEMZONE_NAMESIZE, "ena_p%d_mz%" PRIu64 "", 3884 data->port_id, adapter->memzone_cnt); 3885 if (rc >= RTE_MEMZONE_NAMESIZE) { 3886 PMD_DRV_LOG(ERR, 3887 "Name for the ena_com memzone is too long. Port: %d, mz_num: %" PRIu64 "\n", 3888 data->port_id, adapter->memzone_cnt); 3889 goto error; 3890 } 3891 adapter->memzone_cnt++; 3892 3893 memzone = rte_memzone_reserve_aligned(z_name, size, socket_id, 3894 RTE_MEMZONE_IOVA_CONTIG, alignment); 3895 if (memzone == NULL) { 3896 PMD_DRV_LOG(ERR, "Failed to allocate ena_com memzone: %s\n", 3897 z_name); 3898 goto error; 3899 } 3900 3901 memset(memzone->addr, 0, size); 3902 *virt_addr = memzone->addr; 3903 *phys_addr = memzone->iova; 3904 3905 return memzone; 3906 3907 error: 3908 *virt_addr = NULL; 3909 *phys_addr = 0; 3910 3911 return NULL; 3912 } 3913 3914 3915 /********************************************************************* 3916 * PMD configuration 3917 *********************************************************************/ 3918 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3919 struct rte_pci_device *pci_dev) 3920 { 3921 return rte_eth_dev_pci_generic_probe(pci_dev, 3922 sizeof(struct ena_adapter), eth_ena_dev_init); 3923 } 3924 3925 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 3926 { 3927 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 3928 } 3929 3930 static struct rte_pci_driver rte_ena_pmd = { 3931 .id_table = pci_id_ena_map, 3932 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 3933 RTE_PCI_DRV_WC_ACTIVATE, 3934 .probe = eth_ena_pci_probe, 3935 .remove = eth_ena_pci_remove, 3936 }; 3937 3938 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 3939 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 3940 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 3941 RTE_PMD_REGISTER_PARAM_STRING(net_ena, 3942 ENA_DEVARG_LARGE_LLQ_HDR "=<0|1> " 3943 ENA_DEVARG_ENABLE_LLQ "=<0|1> " 3944 ENA_DEVARG_MISS_TXC_TO "=<uint>"); 3945 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); 3946 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE); 3947 #ifdef RTE_ETHDEV_DEBUG_RX 3948 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG); 3949 #endif 3950 #ifdef RTE_ETHDEV_DEBUG_TX 3951 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG); 3952 #endif 3953 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING); 3954 3955 /****************************************************************************** 3956 ******************************** AENQ Handlers ******************************* 3957 *****************************************************************************/ 3958 static void ena_update_on_link_change(void *adapter_data, 3959 struct ena_admin_aenq_entry *aenq_e) 3960 { 3961 struct rte_eth_dev *eth_dev = adapter_data; 3962 struct ena_adapter *adapter = eth_dev->data->dev_private; 3963 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 3964 uint32_t status; 3965 3966 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3967 3968 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 3969 adapter->link_status = status; 3970 3971 ena_link_update(eth_dev, 0); 3972 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 3973 } 3974 3975 static void ena_notification(void *adapter_data, 3976 struct ena_admin_aenq_entry *aenq_e) 3977 { 3978 struct rte_eth_dev *eth_dev = adapter_data; 3979 struct ena_adapter *adapter = eth_dev->data->dev_private; 3980 struct ena_admin_ena_hw_hints *hints; 3981 3982 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 3983 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n", 3984 aenq_e->aenq_common_desc.group, 3985 ENA_ADMIN_NOTIFICATION); 3986 3987 switch (aenq_e->aenq_common_desc.syndrome) { 3988 case ENA_ADMIN_UPDATE_HINTS: 3989 hints = (struct ena_admin_ena_hw_hints *) 3990 (&aenq_e->inline_data_w4); 3991 ena_update_hints(adapter, hints); 3992 break; 3993 default: 3994 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n", 3995 aenq_e->aenq_common_desc.syndrome); 3996 } 3997 } 3998 3999 static void ena_keep_alive(void *adapter_data, 4000 __rte_unused struct ena_admin_aenq_entry *aenq_e) 4001 { 4002 struct rte_eth_dev *eth_dev = adapter_data; 4003 struct ena_adapter *adapter = eth_dev->data->dev_private; 4004 struct ena_admin_aenq_keep_alive_desc *desc; 4005 uint64_t rx_drops; 4006 uint64_t tx_drops; 4007 uint64_t rx_overruns; 4008 4009 adapter->timestamp_wd = rte_get_timer_cycles(); 4010 4011 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 4012 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 4013 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 4014 rx_overruns = ((uint64_t)desc->rx_overruns_high << 32) | desc->rx_overruns_low; 4015 4016 adapter->drv_stats->rx_drops = rx_drops; 4017 adapter->dev_stats.tx_drops = tx_drops; 4018 adapter->dev_stats.rx_overruns = rx_overruns; 4019 } 4020 4021 /** 4022 * This handler will called for unknown event group or unimplemented handlers 4023 **/ 4024 static void unimplemented_aenq_handler(__rte_unused void *data, 4025 __rte_unused struct ena_admin_aenq_entry *aenq_e) 4026 { 4027 PMD_DRV_LOG(ERR, 4028 "Unknown event was received or event with unimplemented handler\n"); 4029 } 4030 4031 static struct ena_aenq_handlers aenq_handlers = { 4032 .handlers = { 4033 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 4034 [ENA_ADMIN_NOTIFICATION] = ena_notification, 4035 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 4036 }, 4037 .unimplemented_handler = unimplemented_aenq_handler 4038 }; 4039 4040 /********************************************************************* 4041 * Multi-Process communication request handling (in primary) 4042 *********************************************************************/ 4043 static int 4044 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer) 4045 { 4046 const struct ena_mp_body *req = 4047 (const struct ena_mp_body *)mp_msg->param; 4048 struct ena_adapter *adapter; 4049 struct ena_com_dev *ena_dev; 4050 struct ena_mp_body *rsp; 4051 struct rte_mp_msg mp_rsp; 4052 struct rte_eth_dev *dev; 4053 int res = 0; 4054 4055 rsp = (struct ena_mp_body *)&mp_rsp.param; 4056 mp_msg_init(&mp_rsp, req->type, req->port_id); 4057 4058 if (!rte_eth_dev_is_valid_port(req->port_id)) { 4059 rte_errno = ENODEV; 4060 res = -rte_errno; 4061 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n", 4062 req->port_id, req->type); 4063 goto end; 4064 } 4065 dev = &rte_eth_devices[req->port_id]; 4066 adapter = dev->data->dev_private; 4067 ena_dev = &adapter->ena_dev; 4068 4069 switch (req->type) { 4070 case ENA_MP_DEV_STATS_GET: 4071 res = ena_com_get_dev_basic_stats(ena_dev, 4072 &adapter->basic_stats); 4073 break; 4074 case ENA_MP_ENI_STATS_GET: 4075 res = ena_com_get_eni_stats(ena_dev, 4076 (struct ena_admin_eni_stats *)&adapter->metrics_stats); 4077 break; 4078 case ENA_MP_MTU_SET: 4079 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu); 4080 break; 4081 case ENA_MP_IND_TBL_GET: 4082 res = ena_com_indirect_table_get(ena_dev, 4083 adapter->indirect_table); 4084 break; 4085 case ENA_MP_IND_TBL_SET: 4086 res = ena_com_indirect_table_set(ena_dev); 4087 break; 4088 case ENA_MP_CUSTOMER_METRICS_GET: 4089 res = ena_com_get_customer_metrics(ena_dev, 4090 (char *)adapter->metrics_stats, 4091 sizeof(uint64_t) * adapter->metrics_num); 4092 break; 4093 case ENA_MP_SRD_STATS_GET: 4094 res = ena_com_get_ena_srd_info(ena_dev, 4095 (struct ena_admin_ena_srd_info *)&adapter->srd_stats); 4096 break; 4097 default: 4098 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type); 4099 res = -EINVAL; 4100 break; 4101 } 4102 4103 end: 4104 /* Save processing result in the reply */ 4105 rsp->result = res; 4106 /* Return just IPC processing status */ 4107 return rte_mp_reply(&mp_rsp, peer); 4108 } 4109