1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 0 31 #define DRV_MODULE_VER_SUBMINOR 3 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 /* While processing submitted and completed descriptors (rx and tx path 39 * respectively) in a loop it is desired to: 40 * - perform batch submissions while populating sumbissmion queue 41 * - avoid blocking transmission of other packets during cleanup phase 42 * Hence the utilization ratio of 1/8 of a queue size. 43 */ 44 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 45 46 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 47 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 48 49 #define GET_L4_HDR_LEN(mbuf) \ 50 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 51 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 52 53 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 54 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 55 #define ENA_HASH_KEY_SIZE 40 56 #define ETH_GSTRING_LEN 32 57 58 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 59 60 #define ENA_MIN_RING_DESC 128 61 62 enum ethtool_stringset { 63 ETH_SS_TEST = 0, 64 ETH_SS_STATS, 65 }; 66 67 struct ena_stats { 68 char name[ETH_GSTRING_LEN]; 69 int stat_offset; 70 }; 71 72 #define ENA_STAT_ENTRY(stat, stat_type) { \ 73 .name = #stat, \ 74 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 75 } 76 77 #define ENA_STAT_RX_ENTRY(stat) \ 78 ENA_STAT_ENTRY(stat, rx) 79 80 #define ENA_STAT_TX_ENTRY(stat) \ 81 ENA_STAT_ENTRY(stat, tx) 82 83 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 84 ENA_STAT_ENTRY(stat, dev) 85 86 /* Device arguments */ 87 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 88 89 /* 90 * Each rte_memzone should have unique name. 91 * To satisfy it, count number of allocation and add it to name. 92 */ 93 rte_atomic32_t ena_alloc_cnt; 94 95 static const struct ena_stats ena_stats_global_strings[] = { 96 ENA_STAT_GLOBAL_ENTRY(wd_expired), 97 ENA_STAT_GLOBAL_ENTRY(dev_start), 98 ENA_STAT_GLOBAL_ENTRY(dev_stop), 99 ENA_STAT_GLOBAL_ENTRY(tx_drops), 100 }; 101 102 static const struct ena_stats ena_stats_tx_strings[] = { 103 ENA_STAT_TX_ENTRY(cnt), 104 ENA_STAT_TX_ENTRY(bytes), 105 ENA_STAT_TX_ENTRY(prepare_ctx_err), 106 ENA_STAT_TX_ENTRY(linearize), 107 ENA_STAT_TX_ENTRY(linearize_failed), 108 ENA_STAT_TX_ENTRY(tx_poll), 109 ENA_STAT_TX_ENTRY(doorbells), 110 ENA_STAT_TX_ENTRY(bad_req_id), 111 ENA_STAT_TX_ENTRY(available_desc), 112 }; 113 114 static const struct ena_stats ena_stats_rx_strings[] = { 115 ENA_STAT_RX_ENTRY(cnt), 116 ENA_STAT_RX_ENTRY(bytes), 117 ENA_STAT_RX_ENTRY(refill_partial), 118 ENA_STAT_RX_ENTRY(bad_csum), 119 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 120 ENA_STAT_RX_ENTRY(bad_desc_num), 121 ENA_STAT_RX_ENTRY(bad_req_id), 122 }; 123 124 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 125 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 126 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 127 128 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 129 DEV_TX_OFFLOAD_UDP_CKSUM |\ 130 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 131 DEV_TX_OFFLOAD_TCP_TSO) 132 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 133 PKT_TX_IP_CKSUM |\ 134 PKT_TX_TCP_SEG) 135 136 /** Vendor ID used by Amazon devices */ 137 #define PCI_VENDOR_ID_AMAZON 0x1D0F 138 /** Amazon devices */ 139 #define PCI_DEVICE_ID_ENA_VF 0xEC20 140 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 141 142 #define ENA_TX_OFFLOAD_MASK (\ 143 PKT_TX_L4_MASK | \ 144 PKT_TX_IPV6 | \ 145 PKT_TX_IPV4 | \ 146 PKT_TX_IP_CKSUM | \ 147 PKT_TX_TCP_SEG) 148 149 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 150 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 151 152 int ena_logtype_init; 153 int ena_logtype_driver; 154 155 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 156 int ena_logtype_rx; 157 #endif 158 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 159 int ena_logtype_tx; 160 #endif 161 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 162 int ena_logtype_tx_free; 163 #endif 164 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 165 int ena_logtype_com; 166 #endif 167 168 static const struct rte_pci_id pci_id_ena_map[] = { 169 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 170 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 171 { .device_id = 0 }, 172 }; 173 174 static struct ena_aenq_handlers aenq_handlers; 175 176 static int ena_device_init(struct ena_com_dev *ena_dev, 177 struct ena_com_dev_get_features_ctx *get_feat_ctx, 178 bool *wd_state); 179 static int ena_dev_configure(struct rte_eth_dev *dev); 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 181 uint16_t nb_pkts); 182 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 183 uint16_t nb_pkts); 184 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 185 uint16_t nb_desc, unsigned int socket_id, 186 const struct rte_eth_txconf *tx_conf); 187 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 188 uint16_t nb_desc, unsigned int socket_id, 189 const struct rte_eth_rxconf *rx_conf, 190 struct rte_mempool *mp); 191 static uint16_t eth_ena_recv_pkts(void *rx_queue, 192 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 193 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 194 static void ena_init_rings(struct ena_adapter *adapter); 195 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 196 static int ena_start(struct rte_eth_dev *dev); 197 static void ena_stop(struct rte_eth_dev *dev); 198 static void ena_close(struct rte_eth_dev *dev); 199 static int ena_dev_reset(struct rte_eth_dev *dev); 200 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 201 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 202 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 203 static void ena_rx_queue_release(void *queue); 204 static void ena_tx_queue_release(void *queue); 205 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 206 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 207 static int ena_link_update(struct rte_eth_dev *dev, 208 int wait_to_complete); 209 static int ena_create_io_queue(struct ena_ring *ring); 210 static void ena_queue_stop(struct ena_ring *ring); 211 static void ena_queue_stop_all(struct rte_eth_dev *dev, 212 enum ena_ring_type ring_type); 213 static int ena_queue_start(struct ena_ring *ring); 214 static int ena_queue_start_all(struct rte_eth_dev *dev, 215 enum ena_ring_type ring_type); 216 static void ena_stats_restart(struct rte_eth_dev *dev); 217 static int ena_infos_get(struct rte_eth_dev *dev, 218 struct rte_eth_dev_info *dev_info); 219 static int ena_rss_reta_update(struct rte_eth_dev *dev, 220 struct rte_eth_rss_reta_entry64 *reta_conf, 221 uint16_t reta_size); 222 static int ena_rss_reta_query(struct rte_eth_dev *dev, 223 struct rte_eth_rss_reta_entry64 *reta_conf, 224 uint16_t reta_size); 225 static void ena_interrupt_handler_rte(void *cb_arg); 226 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 227 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 228 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 229 static int ena_xstats_get_names(struct rte_eth_dev *dev, 230 struct rte_eth_xstat_name *xstats_names, 231 unsigned int n); 232 static int ena_xstats_get(struct rte_eth_dev *dev, 233 struct rte_eth_xstat *stats, 234 unsigned int n); 235 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 236 const uint64_t *ids, 237 uint64_t *values, 238 unsigned int n); 239 static int ena_process_bool_devarg(const char *key, 240 const char *value, 241 void *opaque); 242 static int ena_parse_devargs(struct ena_adapter *adapter, 243 struct rte_devargs *devargs); 244 245 static const struct eth_dev_ops ena_dev_ops = { 246 .dev_configure = ena_dev_configure, 247 .dev_infos_get = ena_infos_get, 248 .rx_queue_setup = ena_rx_queue_setup, 249 .tx_queue_setup = ena_tx_queue_setup, 250 .dev_start = ena_start, 251 .dev_stop = ena_stop, 252 .link_update = ena_link_update, 253 .stats_get = ena_stats_get, 254 .xstats_get_names = ena_xstats_get_names, 255 .xstats_get = ena_xstats_get, 256 .xstats_get_by_id = ena_xstats_get_by_id, 257 .mtu_set = ena_mtu_set, 258 .rx_queue_release = ena_rx_queue_release, 259 .tx_queue_release = ena_tx_queue_release, 260 .dev_close = ena_close, 261 .dev_reset = ena_dev_reset, 262 .reta_update = ena_rss_reta_update, 263 .reta_query = ena_rss_reta_query, 264 }; 265 266 void ena_rss_key_fill(void *key, size_t size) 267 { 268 static bool key_generated; 269 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 270 size_t i; 271 272 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 273 274 if (!key_generated) { 275 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 276 default_key[i] = rte_rand() & 0xff; 277 key_generated = true; 278 } 279 280 rte_memcpy(key, default_key, size); 281 } 282 283 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 284 struct ena_com_rx_ctx *ena_rx_ctx) 285 { 286 uint64_t ol_flags = 0; 287 uint32_t packet_type = 0; 288 289 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 290 packet_type |= RTE_PTYPE_L4_TCP; 291 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 292 packet_type |= RTE_PTYPE_L4_UDP; 293 294 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 295 packet_type |= RTE_PTYPE_L3_IPV4; 296 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 297 packet_type |= RTE_PTYPE_L3_IPV6; 298 299 if (!ena_rx_ctx->l4_csum_checked) 300 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 301 else 302 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 303 ol_flags |= PKT_RX_L4_CKSUM_BAD; 304 else 305 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 306 307 if (unlikely(ena_rx_ctx->l3_csum_err)) 308 ol_flags |= PKT_RX_IP_CKSUM_BAD; 309 310 mbuf->ol_flags = ol_flags; 311 mbuf->packet_type = packet_type; 312 } 313 314 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 315 struct ena_com_tx_ctx *ena_tx_ctx, 316 uint64_t queue_offloads) 317 { 318 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 319 320 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 321 (queue_offloads & QUEUE_OFFLOADS)) { 322 /* check if TSO is required */ 323 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 324 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 325 ena_tx_ctx->tso_enable = true; 326 327 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 328 } 329 330 /* check if L3 checksum is needed */ 331 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 332 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 333 ena_tx_ctx->l3_csum_enable = true; 334 335 if (mbuf->ol_flags & PKT_TX_IPV6) { 336 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 337 } else { 338 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 339 340 /* set don't fragment (DF) flag */ 341 if (mbuf->packet_type & 342 (RTE_PTYPE_L4_NONFRAG 343 | RTE_PTYPE_INNER_L4_NONFRAG)) 344 ena_tx_ctx->df = true; 345 } 346 347 /* check if L4 checksum is needed */ 348 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 349 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 350 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 351 ena_tx_ctx->l4_csum_enable = true; 352 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 353 PKT_TX_UDP_CKSUM) && 354 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 355 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 356 ena_tx_ctx->l4_csum_enable = true; 357 } else { 358 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 359 ena_tx_ctx->l4_csum_enable = false; 360 } 361 362 ena_meta->mss = mbuf->tso_segsz; 363 ena_meta->l3_hdr_len = mbuf->l3_len; 364 ena_meta->l3_hdr_offset = mbuf->l2_len; 365 366 ena_tx_ctx->meta_valid = true; 367 } else { 368 ena_tx_ctx->meta_valid = false; 369 } 370 } 371 372 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 373 { 374 if (likely(req_id < rx_ring->ring_size)) 375 return 0; 376 377 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 378 379 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 380 rx_ring->adapter->trigger_reset = true; 381 ++rx_ring->rx_stats.bad_req_id; 382 383 return -EFAULT; 384 } 385 386 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 387 { 388 struct ena_tx_buffer *tx_info = NULL; 389 390 if (likely(req_id < tx_ring->ring_size)) { 391 tx_info = &tx_ring->tx_buffer_info[req_id]; 392 if (likely(tx_info->mbuf)) 393 return 0; 394 } 395 396 if (tx_info) 397 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 398 else 399 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 400 401 /* Trigger device reset */ 402 ++tx_ring->tx_stats.bad_req_id; 403 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 404 tx_ring->adapter->trigger_reset = true; 405 return -EFAULT; 406 } 407 408 static void ena_config_host_info(struct ena_com_dev *ena_dev) 409 { 410 struct ena_admin_host_info *host_info; 411 int rc; 412 413 /* Allocate only the host info */ 414 rc = ena_com_allocate_host_info(ena_dev); 415 if (rc) { 416 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 417 return; 418 } 419 420 host_info = ena_dev->host_attr.host_info; 421 422 host_info->os_type = ENA_ADMIN_OS_DPDK; 423 host_info->kernel_ver = RTE_VERSION; 424 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 425 sizeof(host_info->kernel_ver_str)); 426 host_info->os_dist = RTE_VERSION; 427 strlcpy((char *)host_info->os_dist_str, rte_version(), 428 sizeof(host_info->os_dist_str)); 429 host_info->driver_version = 430 (DRV_MODULE_VER_MAJOR) | 431 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 432 (DRV_MODULE_VER_SUBMINOR << 433 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 434 host_info->num_cpus = rte_lcore_count(); 435 436 host_info->driver_supported_features = 437 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 438 439 rc = ena_com_set_host_attributes(ena_dev); 440 if (rc) { 441 if (rc == -ENA_COM_UNSUPPORTED) 442 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 443 else 444 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 445 446 goto err; 447 } 448 449 return; 450 451 err: 452 ena_com_delete_host_info(ena_dev); 453 } 454 455 /* This function calculates the number of xstats based on the current config */ 456 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 457 { 458 return ENA_STATS_ARRAY_GLOBAL + 459 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 460 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 461 } 462 463 static void ena_config_debug_area(struct ena_adapter *adapter) 464 { 465 u32 debug_area_size; 466 int rc, ss_count; 467 468 ss_count = ena_xstats_calc_num(adapter->rte_dev); 469 470 /* allocate 32 bytes for each string and 64bit for the value */ 471 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 472 473 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 474 if (rc) { 475 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 476 return; 477 } 478 479 rc = ena_com_set_host_attributes(&adapter->ena_dev); 480 if (rc) { 481 if (rc == -ENA_COM_UNSUPPORTED) 482 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 483 else 484 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 485 486 goto err; 487 } 488 489 return; 490 err: 491 ena_com_delete_debug_area(&adapter->ena_dev); 492 } 493 494 static void ena_close(struct rte_eth_dev *dev) 495 { 496 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 498 struct ena_adapter *adapter = dev->data->dev_private; 499 500 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 501 ena_stop(dev); 502 adapter->state = ENA_ADAPTER_STATE_CLOSED; 503 504 ena_rx_queue_release_all(dev); 505 ena_tx_queue_release_all(dev); 506 507 rte_free(adapter->drv_stats); 508 adapter->drv_stats = NULL; 509 510 rte_intr_disable(intr_handle); 511 rte_intr_callback_unregister(intr_handle, 512 ena_interrupt_handler_rte, 513 adapter); 514 515 /* 516 * MAC is not allocated dynamically. Setting NULL should prevent from 517 * release of the resource in the rte_eth_dev_release_port(). 518 */ 519 dev->data->mac_addrs = NULL; 520 } 521 522 static int 523 ena_dev_reset(struct rte_eth_dev *dev) 524 { 525 int rc = 0; 526 527 ena_destroy_device(dev); 528 rc = eth_ena_dev_init(dev); 529 if (rc) 530 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 531 532 return rc; 533 } 534 535 static int ena_rss_reta_update(struct rte_eth_dev *dev, 536 struct rte_eth_rss_reta_entry64 *reta_conf, 537 uint16_t reta_size) 538 { 539 struct ena_adapter *adapter = dev->data->dev_private; 540 struct ena_com_dev *ena_dev = &adapter->ena_dev; 541 int rc, i; 542 u16 entry_value; 543 int conf_idx; 544 int idx; 545 546 if ((reta_size == 0) || (reta_conf == NULL)) 547 return -EINVAL; 548 549 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 550 PMD_DRV_LOG(WARNING, 551 "indirection table %d is bigger than supported (%d)\n", 552 reta_size, ENA_RX_RSS_TABLE_SIZE); 553 return -EINVAL; 554 } 555 556 for (i = 0 ; i < reta_size ; i++) { 557 /* each reta_conf is for 64 entries. 558 * to support 128 we use 2 conf of 64 559 */ 560 conf_idx = i / RTE_RETA_GROUP_SIZE; 561 idx = i % RTE_RETA_GROUP_SIZE; 562 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 563 entry_value = 564 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 565 566 rc = ena_com_indirect_table_fill_entry(ena_dev, 567 i, 568 entry_value); 569 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 570 PMD_DRV_LOG(ERR, 571 "Cannot fill indirect table\n"); 572 return rc; 573 } 574 } 575 } 576 577 rc = ena_com_indirect_table_set(ena_dev); 578 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 579 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 580 return rc; 581 } 582 583 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 584 __func__, reta_size, adapter->rte_dev->data->port_id); 585 586 return 0; 587 } 588 589 /* Query redirection table. */ 590 static int ena_rss_reta_query(struct rte_eth_dev *dev, 591 struct rte_eth_rss_reta_entry64 *reta_conf, 592 uint16_t reta_size) 593 { 594 struct ena_adapter *adapter = dev->data->dev_private; 595 struct ena_com_dev *ena_dev = &adapter->ena_dev; 596 int rc; 597 int i; 598 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 599 int reta_conf_idx; 600 int reta_idx; 601 602 if (reta_size == 0 || reta_conf == NULL || 603 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 604 return -EINVAL; 605 606 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 607 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 608 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 609 return -ENOTSUP; 610 } 611 612 for (i = 0 ; i < reta_size ; i++) { 613 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 614 reta_idx = i % RTE_RETA_GROUP_SIZE; 615 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 616 reta_conf[reta_conf_idx].reta[reta_idx] = 617 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 618 } 619 620 return 0; 621 } 622 623 static int ena_rss_init_default(struct ena_adapter *adapter) 624 { 625 struct ena_com_dev *ena_dev = &adapter->ena_dev; 626 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 627 int rc, i; 628 u32 val; 629 630 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 631 if (unlikely(rc)) { 632 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 633 goto err_rss_init; 634 } 635 636 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 637 val = i % nb_rx_queues; 638 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 639 ENA_IO_RXQ_IDX(val)); 640 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 641 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 642 goto err_fill_indir; 643 } 644 } 645 646 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 647 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 648 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 649 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 650 goto err_fill_indir; 651 } 652 653 rc = ena_com_set_default_hash_ctrl(ena_dev); 654 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 655 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 656 goto err_fill_indir; 657 } 658 659 rc = ena_com_indirect_table_set(ena_dev); 660 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 661 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 662 goto err_fill_indir; 663 } 664 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 665 adapter->rte_dev->data->port_id); 666 667 return 0; 668 669 err_fill_indir: 670 ena_com_rss_destroy(ena_dev); 671 err_rss_init: 672 673 return rc; 674 } 675 676 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 677 { 678 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 679 int nb_queues = dev->data->nb_rx_queues; 680 int i; 681 682 for (i = 0; i < nb_queues; i++) 683 ena_rx_queue_release(queues[i]); 684 } 685 686 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 687 { 688 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 689 int nb_queues = dev->data->nb_tx_queues; 690 int i; 691 692 for (i = 0; i < nb_queues; i++) 693 ena_tx_queue_release(queues[i]); 694 } 695 696 static void ena_rx_queue_release(void *queue) 697 { 698 struct ena_ring *ring = (struct ena_ring *)queue; 699 700 /* Free ring resources */ 701 if (ring->rx_buffer_info) 702 rte_free(ring->rx_buffer_info); 703 ring->rx_buffer_info = NULL; 704 705 if (ring->rx_refill_buffer) 706 rte_free(ring->rx_refill_buffer); 707 ring->rx_refill_buffer = NULL; 708 709 if (ring->empty_rx_reqs) 710 rte_free(ring->empty_rx_reqs); 711 ring->empty_rx_reqs = NULL; 712 713 ring->configured = 0; 714 715 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 716 ring->port_id, ring->id); 717 } 718 719 static void ena_tx_queue_release(void *queue) 720 { 721 struct ena_ring *ring = (struct ena_ring *)queue; 722 723 /* Free ring resources */ 724 if (ring->push_buf_intermediate_buf) 725 rte_free(ring->push_buf_intermediate_buf); 726 727 if (ring->tx_buffer_info) 728 rte_free(ring->tx_buffer_info); 729 730 if (ring->empty_tx_reqs) 731 rte_free(ring->empty_tx_reqs); 732 733 ring->empty_tx_reqs = NULL; 734 ring->tx_buffer_info = NULL; 735 ring->push_buf_intermediate_buf = NULL; 736 737 ring->configured = 0; 738 739 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 740 ring->port_id, ring->id); 741 } 742 743 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 744 { 745 unsigned int i; 746 747 for (i = 0; i < ring->ring_size; ++i) 748 if (ring->rx_buffer_info[i]) { 749 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 750 ring->rx_buffer_info[i] = NULL; 751 } 752 } 753 754 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 755 { 756 unsigned int i; 757 758 for (i = 0; i < ring->ring_size; ++i) { 759 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 760 761 if (tx_buf->mbuf) 762 rte_pktmbuf_free(tx_buf->mbuf); 763 } 764 } 765 766 static int ena_link_update(struct rte_eth_dev *dev, 767 __rte_unused int wait_to_complete) 768 { 769 struct rte_eth_link *link = &dev->data->dev_link; 770 struct ena_adapter *adapter = dev->data->dev_private; 771 772 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 773 link->link_speed = ETH_SPEED_NUM_NONE; 774 link->link_duplex = ETH_LINK_FULL_DUPLEX; 775 776 return 0; 777 } 778 779 static int ena_queue_start_all(struct rte_eth_dev *dev, 780 enum ena_ring_type ring_type) 781 { 782 struct ena_adapter *adapter = dev->data->dev_private; 783 struct ena_ring *queues = NULL; 784 int nb_queues; 785 int i = 0; 786 int rc = 0; 787 788 if (ring_type == ENA_RING_TYPE_RX) { 789 queues = adapter->rx_ring; 790 nb_queues = dev->data->nb_rx_queues; 791 } else { 792 queues = adapter->tx_ring; 793 nb_queues = dev->data->nb_tx_queues; 794 } 795 for (i = 0; i < nb_queues; i++) { 796 if (queues[i].configured) { 797 if (ring_type == ENA_RING_TYPE_RX) { 798 ena_assert_msg( 799 dev->data->rx_queues[i] == &queues[i], 800 "Inconsistent state of rx queues\n"); 801 } else { 802 ena_assert_msg( 803 dev->data->tx_queues[i] == &queues[i], 804 "Inconsistent state of tx queues\n"); 805 } 806 807 rc = ena_queue_start(&queues[i]); 808 809 if (rc) { 810 PMD_INIT_LOG(ERR, 811 "failed to start queue %d type(%d)", 812 i, ring_type); 813 goto err; 814 } 815 } 816 } 817 818 return 0; 819 820 err: 821 while (i--) 822 if (queues[i].configured) 823 ena_queue_stop(&queues[i]); 824 825 return rc; 826 } 827 828 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 829 { 830 uint32_t max_frame_len = adapter->max_mtu; 831 832 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 833 DEV_RX_OFFLOAD_JUMBO_FRAME) 834 max_frame_len = 835 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 836 837 return max_frame_len; 838 } 839 840 static int ena_check_valid_conf(struct ena_adapter *adapter) 841 { 842 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 843 844 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 845 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 846 "max mtu: %d, min mtu: %d", 847 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 848 return ENA_COM_UNSUPPORTED; 849 } 850 851 return 0; 852 } 853 854 static int 855 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 856 bool use_large_llq_hdr) 857 { 858 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 859 struct ena_com_dev *ena_dev = ctx->ena_dev; 860 uint32_t max_tx_queue_size; 861 uint32_t max_rx_queue_size; 862 863 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 864 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 865 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 866 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 867 max_queue_ext->max_rx_sq_depth); 868 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 869 870 if (ena_dev->tx_mem_queue_type == 871 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 872 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 873 llq->max_llq_depth); 874 } else { 875 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 876 max_queue_ext->max_tx_sq_depth); 877 } 878 879 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 880 max_queue_ext->max_per_packet_rx_descs); 881 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 882 max_queue_ext->max_per_packet_tx_descs); 883 } else { 884 struct ena_admin_queue_feature_desc *max_queues = 885 &ctx->get_feat_ctx->max_queues; 886 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 887 max_queues->max_sq_depth); 888 max_tx_queue_size = max_queues->max_cq_depth; 889 890 if (ena_dev->tx_mem_queue_type == 891 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 892 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 893 llq->max_llq_depth); 894 } else { 895 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 896 max_queues->max_sq_depth); 897 } 898 899 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 900 max_queues->max_packet_rx_descs); 901 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 902 max_queues->max_packet_tx_descs); 903 } 904 905 /* Round down to the nearest power of 2 */ 906 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 907 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 908 909 if (use_large_llq_hdr) { 910 if ((llq->entry_size_ctrl_supported & 911 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 912 (ena_dev->tx_mem_queue_type == 913 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 914 max_tx_queue_size /= 2; 915 PMD_INIT_LOG(INFO, 916 "Forcing large headers and decreasing maximum TX queue size to %d\n", 917 max_tx_queue_size); 918 } else { 919 PMD_INIT_LOG(ERR, 920 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 921 } 922 } 923 924 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 925 PMD_INIT_LOG(ERR, "Invalid queue size"); 926 return -EFAULT; 927 } 928 929 ctx->max_tx_queue_size = max_tx_queue_size; 930 ctx->max_rx_queue_size = max_rx_queue_size; 931 932 return 0; 933 } 934 935 static void ena_stats_restart(struct rte_eth_dev *dev) 936 { 937 struct ena_adapter *adapter = dev->data->dev_private; 938 939 rte_atomic64_init(&adapter->drv_stats->ierrors); 940 rte_atomic64_init(&adapter->drv_stats->oerrors); 941 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 942 adapter->drv_stats->rx_drops = 0; 943 } 944 945 static int ena_stats_get(struct rte_eth_dev *dev, 946 struct rte_eth_stats *stats) 947 { 948 struct ena_admin_basic_stats ena_stats; 949 struct ena_adapter *adapter = dev->data->dev_private; 950 struct ena_com_dev *ena_dev = &adapter->ena_dev; 951 int rc; 952 int i; 953 int max_rings_stats; 954 955 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 956 return -ENOTSUP; 957 958 memset(&ena_stats, 0, sizeof(ena_stats)); 959 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 960 if (unlikely(rc)) { 961 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 962 return rc; 963 } 964 965 /* Set of basic statistics from ENA */ 966 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 967 ena_stats.rx_pkts_low); 968 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 969 ena_stats.tx_pkts_low); 970 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 971 ena_stats.rx_bytes_low); 972 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 973 ena_stats.tx_bytes_low); 974 975 /* Driver related stats */ 976 stats->imissed = adapter->drv_stats->rx_drops; 977 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 978 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 979 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 980 981 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 982 RTE_ETHDEV_QUEUE_STAT_CNTRS); 983 for (i = 0; i < max_rings_stats; ++i) { 984 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 985 986 stats->q_ibytes[i] = rx_stats->bytes; 987 stats->q_ipackets[i] = rx_stats->cnt; 988 stats->q_errors[i] = rx_stats->bad_desc_num + 989 rx_stats->bad_req_id; 990 } 991 992 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 993 RTE_ETHDEV_QUEUE_STAT_CNTRS); 994 for (i = 0; i < max_rings_stats; ++i) { 995 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 996 997 stats->q_obytes[i] = tx_stats->bytes; 998 stats->q_opackets[i] = tx_stats->cnt; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1005 { 1006 struct ena_adapter *adapter; 1007 struct ena_com_dev *ena_dev; 1008 int rc = 0; 1009 1010 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1011 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1012 adapter = dev->data->dev_private; 1013 1014 ena_dev = &adapter->ena_dev; 1015 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1016 1017 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1018 PMD_DRV_LOG(ERR, 1019 "Invalid MTU setting. new_mtu: %d " 1020 "max mtu: %d min mtu: %d\n", 1021 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1022 return -EINVAL; 1023 } 1024 1025 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1026 if (rc) 1027 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1028 else 1029 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1030 1031 return rc; 1032 } 1033 1034 static int ena_start(struct rte_eth_dev *dev) 1035 { 1036 struct ena_adapter *adapter = dev->data->dev_private; 1037 uint64_t ticks; 1038 int rc = 0; 1039 1040 rc = ena_check_valid_conf(adapter); 1041 if (rc) 1042 return rc; 1043 1044 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1045 if (rc) 1046 return rc; 1047 1048 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1049 if (rc) 1050 goto err_start_tx; 1051 1052 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1053 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1054 rc = ena_rss_init_default(adapter); 1055 if (rc) 1056 goto err_rss_init; 1057 } 1058 1059 ena_stats_restart(dev); 1060 1061 adapter->timestamp_wd = rte_get_timer_cycles(); 1062 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1063 1064 ticks = rte_get_timer_hz(); 1065 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1066 ena_timer_wd_callback, adapter); 1067 1068 ++adapter->dev_stats.dev_start; 1069 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1070 1071 return 0; 1072 1073 err_rss_init: 1074 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1075 err_start_tx: 1076 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1077 return rc; 1078 } 1079 1080 static void ena_stop(struct rte_eth_dev *dev) 1081 { 1082 struct ena_adapter *adapter = dev->data->dev_private; 1083 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1084 int rc; 1085 1086 rte_timer_stop_sync(&adapter->timer_wd); 1087 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1088 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1089 1090 if (adapter->trigger_reset) { 1091 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1092 if (rc) 1093 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1094 } 1095 1096 ++adapter->dev_stats.dev_stop; 1097 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1098 } 1099 1100 static int ena_create_io_queue(struct ena_ring *ring) 1101 { 1102 struct ena_adapter *adapter; 1103 struct ena_com_dev *ena_dev; 1104 struct ena_com_create_io_ctx ctx = 1105 /* policy set to _HOST just to satisfy icc compiler */ 1106 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1107 0, 0, 0, 0, 0 }; 1108 uint16_t ena_qid; 1109 unsigned int i; 1110 int rc; 1111 1112 adapter = ring->adapter; 1113 ena_dev = &adapter->ena_dev; 1114 1115 if (ring->type == ENA_RING_TYPE_TX) { 1116 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1117 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1118 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1119 for (i = 0; i < ring->ring_size; i++) 1120 ring->empty_tx_reqs[i] = i; 1121 } else { 1122 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1123 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1124 for (i = 0; i < ring->ring_size; i++) 1125 ring->empty_rx_reqs[i] = i; 1126 } 1127 ctx.queue_size = ring->ring_size; 1128 ctx.qid = ena_qid; 1129 ctx.msix_vector = -1; /* interrupts not used */ 1130 ctx.numa_node = ring->numa_socket_id; 1131 1132 rc = ena_com_create_io_queue(ena_dev, &ctx); 1133 if (rc) { 1134 PMD_DRV_LOG(ERR, 1135 "failed to create io queue #%d (qid:%d) rc: %d\n", 1136 ring->id, ena_qid, rc); 1137 return rc; 1138 } 1139 1140 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1141 &ring->ena_com_io_sq, 1142 &ring->ena_com_io_cq); 1143 if (rc) { 1144 PMD_DRV_LOG(ERR, 1145 "Failed to get io queue handlers. queue num %d rc: %d\n", 1146 ring->id, rc); 1147 ena_com_destroy_io_queue(ena_dev, ena_qid); 1148 return rc; 1149 } 1150 1151 if (ring->type == ENA_RING_TYPE_TX) 1152 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1153 1154 return 0; 1155 } 1156 1157 static void ena_queue_stop(struct ena_ring *ring) 1158 { 1159 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1160 1161 if (ring->type == ENA_RING_TYPE_RX) { 1162 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1163 ena_rx_queue_release_bufs(ring); 1164 } else { 1165 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1166 ena_tx_queue_release_bufs(ring); 1167 } 1168 } 1169 1170 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1171 enum ena_ring_type ring_type) 1172 { 1173 struct ena_adapter *adapter = dev->data->dev_private; 1174 struct ena_ring *queues = NULL; 1175 uint16_t nb_queues, i; 1176 1177 if (ring_type == ENA_RING_TYPE_RX) { 1178 queues = adapter->rx_ring; 1179 nb_queues = dev->data->nb_rx_queues; 1180 } else { 1181 queues = adapter->tx_ring; 1182 nb_queues = dev->data->nb_tx_queues; 1183 } 1184 1185 for (i = 0; i < nb_queues; ++i) 1186 if (queues[i].configured) 1187 ena_queue_stop(&queues[i]); 1188 } 1189 1190 static int ena_queue_start(struct ena_ring *ring) 1191 { 1192 int rc, bufs_num; 1193 1194 ena_assert_msg(ring->configured == 1, 1195 "Trying to start unconfigured queue\n"); 1196 1197 rc = ena_create_io_queue(ring); 1198 if (rc) { 1199 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1200 return rc; 1201 } 1202 1203 ring->next_to_clean = 0; 1204 ring->next_to_use = 0; 1205 1206 if (ring->type == ENA_RING_TYPE_TX) { 1207 ring->tx_stats.available_desc = 1208 ena_com_free_q_entries(ring->ena_com_io_sq); 1209 return 0; 1210 } 1211 1212 bufs_num = ring->ring_size - 1; 1213 rc = ena_populate_rx_queue(ring, bufs_num); 1214 if (rc != bufs_num) { 1215 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1216 ENA_IO_RXQ_IDX(ring->id)); 1217 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1218 return ENA_COM_FAULT; 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1225 uint16_t queue_idx, 1226 uint16_t nb_desc, 1227 unsigned int socket_id, 1228 const struct rte_eth_txconf *tx_conf) 1229 { 1230 struct ena_ring *txq = NULL; 1231 struct ena_adapter *adapter = dev->data->dev_private; 1232 unsigned int i; 1233 1234 txq = &adapter->tx_ring[queue_idx]; 1235 1236 if (txq->configured) { 1237 PMD_DRV_LOG(CRIT, 1238 "API violation. Queue %d is already configured\n", 1239 queue_idx); 1240 return ENA_COM_FAULT; 1241 } 1242 1243 if (!rte_is_power_of_2(nb_desc)) { 1244 PMD_DRV_LOG(ERR, 1245 "Unsupported size of TX queue: %d is not a power of 2.\n", 1246 nb_desc); 1247 return -EINVAL; 1248 } 1249 1250 if (nb_desc > adapter->max_tx_ring_size) { 1251 PMD_DRV_LOG(ERR, 1252 "Unsupported size of TX queue (max size: %d)\n", 1253 adapter->max_tx_ring_size); 1254 return -EINVAL; 1255 } 1256 1257 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1258 nb_desc = adapter->max_tx_ring_size; 1259 1260 txq->port_id = dev->data->port_id; 1261 txq->next_to_clean = 0; 1262 txq->next_to_use = 0; 1263 txq->ring_size = nb_desc; 1264 txq->numa_socket_id = socket_id; 1265 1266 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1267 sizeof(struct ena_tx_buffer) * 1268 txq->ring_size, 1269 RTE_CACHE_LINE_SIZE); 1270 if (!txq->tx_buffer_info) { 1271 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1272 return -ENOMEM; 1273 } 1274 1275 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1276 sizeof(u16) * txq->ring_size, 1277 RTE_CACHE_LINE_SIZE); 1278 if (!txq->empty_tx_reqs) { 1279 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1280 rte_free(txq->tx_buffer_info); 1281 return -ENOMEM; 1282 } 1283 1284 txq->push_buf_intermediate_buf = 1285 rte_zmalloc("txq->push_buf_intermediate_buf", 1286 txq->tx_max_header_size, 1287 RTE_CACHE_LINE_SIZE); 1288 if (!txq->push_buf_intermediate_buf) { 1289 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1290 rte_free(txq->tx_buffer_info); 1291 rte_free(txq->empty_tx_reqs); 1292 return -ENOMEM; 1293 } 1294 1295 for (i = 0; i < txq->ring_size; i++) 1296 txq->empty_tx_reqs[i] = i; 1297 1298 if (tx_conf != NULL) { 1299 txq->offloads = 1300 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1301 } 1302 /* Store pointer to this queue in upper layer */ 1303 txq->configured = 1; 1304 dev->data->tx_queues[queue_idx] = txq; 1305 1306 return 0; 1307 } 1308 1309 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1310 uint16_t queue_idx, 1311 uint16_t nb_desc, 1312 unsigned int socket_id, 1313 __rte_unused const struct rte_eth_rxconf *rx_conf, 1314 struct rte_mempool *mp) 1315 { 1316 struct ena_adapter *adapter = dev->data->dev_private; 1317 struct ena_ring *rxq = NULL; 1318 size_t buffer_size; 1319 int i; 1320 1321 rxq = &adapter->rx_ring[queue_idx]; 1322 if (rxq->configured) { 1323 PMD_DRV_LOG(CRIT, 1324 "API violation. Queue %d is already configured\n", 1325 queue_idx); 1326 return ENA_COM_FAULT; 1327 } 1328 1329 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1330 nb_desc = adapter->max_rx_ring_size; 1331 1332 if (!rte_is_power_of_2(nb_desc)) { 1333 PMD_DRV_LOG(ERR, 1334 "Unsupported size of RX queue: %d is not a power of 2.\n", 1335 nb_desc); 1336 return -EINVAL; 1337 } 1338 1339 if (nb_desc > adapter->max_rx_ring_size) { 1340 PMD_DRV_LOG(ERR, 1341 "Unsupported size of RX queue (max size: %d)\n", 1342 adapter->max_rx_ring_size); 1343 return -EINVAL; 1344 } 1345 1346 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1347 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1348 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1349 PMD_DRV_LOG(ERR, 1350 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1351 buffer_size, ENA_RX_BUF_MIN_SIZE); 1352 return -EINVAL; 1353 } 1354 1355 rxq->port_id = dev->data->port_id; 1356 rxq->next_to_clean = 0; 1357 rxq->next_to_use = 0; 1358 rxq->ring_size = nb_desc; 1359 rxq->numa_socket_id = socket_id; 1360 rxq->mb_pool = mp; 1361 1362 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1363 sizeof(struct rte_mbuf *) * nb_desc, 1364 RTE_CACHE_LINE_SIZE); 1365 if (!rxq->rx_buffer_info) { 1366 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1367 return -ENOMEM; 1368 } 1369 1370 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1371 sizeof(struct rte_mbuf *) * nb_desc, 1372 RTE_CACHE_LINE_SIZE); 1373 1374 if (!rxq->rx_refill_buffer) { 1375 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1376 rte_free(rxq->rx_buffer_info); 1377 rxq->rx_buffer_info = NULL; 1378 return -ENOMEM; 1379 } 1380 1381 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1382 sizeof(uint16_t) * nb_desc, 1383 RTE_CACHE_LINE_SIZE); 1384 if (!rxq->empty_rx_reqs) { 1385 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1386 rte_free(rxq->rx_buffer_info); 1387 rxq->rx_buffer_info = NULL; 1388 rte_free(rxq->rx_refill_buffer); 1389 rxq->rx_refill_buffer = NULL; 1390 return -ENOMEM; 1391 } 1392 1393 for (i = 0; i < nb_desc; i++) 1394 rxq->empty_rx_reqs[i] = i; 1395 1396 /* Store pointer to this queue in upper layer */ 1397 rxq->configured = 1; 1398 dev->data->rx_queues[queue_idx] = rxq; 1399 1400 return 0; 1401 } 1402 1403 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1404 { 1405 unsigned int i; 1406 int rc; 1407 uint16_t ring_size = rxq->ring_size; 1408 uint16_t ring_mask = ring_size - 1; 1409 uint16_t next_to_use = rxq->next_to_use; 1410 uint16_t in_use, req_id; 1411 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1412 1413 if (unlikely(!count)) 1414 return 0; 1415 1416 in_use = rxq->next_to_use - rxq->next_to_clean; 1417 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1418 1419 /* get resources for incoming packets */ 1420 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1421 if (unlikely(rc < 0)) { 1422 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1423 ++rxq->rx_stats.mbuf_alloc_fail; 1424 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1425 return 0; 1426 } 1427 1428 for (i = 0; i < count; i++) { 1429 uint16_t next_to_use_masked = next_to_use & ring_mask; 1430 struct rte_mbuf *mbuf = mbufs[i]; 1431 struct ena_com_buf ebuf; 1432 1433 if (likely((i + 4) < count)) 1434 rte_prefetch0(mbufs[i + 4]); 1435 1436 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1437 rc = validate_rx_req_id(rxq, req_id); 1438 if (unlikely(rc < 0)) 1439 break; 1440 rxq->rx_buffer_info[req_id] = mbuf; 1441 1442 /* prepare physical address for DMA transaction */ 1443 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1444 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1445 /* pass resource to device */ 1446 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1447 &ebuf, req_id); 1448 if (unlikely(rc)) { 1449 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1450 rxq->rx_buffer_info[req_id] = NULL; 1451 break; 1452 } 1453 next_to_use++; 1454 } 1455 1456 if (unlikely(i < count)) { 1457 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1458 "buffers (from %d)\n", rxq->id, i, count); 1459 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1460 count - i); 1461 ++rxq->rx_stats.refill_partial; 1462 } 1463 1464 /* When we submitted free recources to device... */ 1465 if (likely(i > 0)) { 1466 /* ...let HW know that it can fill buffers with data. */ 1467 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1468 1469 rxq->next_to_use = next_to_use; 1470 } 1471 1472 return i; 1473 } 1474 1475 static int ena_device_init(struct ena_com_dev *ena_dev, 1476 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1477 bool *wd_state) 1478 { 1479 uint32_t aenq_groups; 1480 int rc; 1481 bool readless_supported; 1482 1483 /* Initialize mmio registers */ 1484 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1485 if (rc) { 1486 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1487 return rc; 1488 } 1489 1490 /* The PCIe configuration space revision id indicate if mmio reg 1491 * read is disabled. 1492 */ 1493 readless_supported = 1494 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1495 & ENA_MMIO_DISABLE_REG_READ); 1496 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1497 1498 /* reset device */ 1499 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1500 if (rc) { 1501 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1502 goto err_mmio_read_less; 1503 } 1504 1505 /* check FW version */ 1506 rc = ena_com_validate_version(ena_dev); 1507 if (rc) { 1508 PMD_DRV_LOG(ERR, "device version is too low\n"); 1509 goto err_mmio_read_less; 1510 } 1511 1512 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1513 1514 /* ENA device administration layer init */ 1515 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1516 if (rc) { 1517 PMD_DRV_LOG(ERR, 1518 "cannot initialize ena admin queue with device\n"); 1519 goto err_mmio_read_less; 1520 } 1521 1522 /* To enable the msix interrupts the driver needs to know the number 1523 * of queues. So the driver uses polling mode to retrieve this 1524 * information. 1525 */ 1526 ena_com_set_admin_polling_mode(ena_dev, true); 1527 1528 ena_config_host_info(ena_dev); 1529 1530 /* Get Device Attributes and features */ 1531 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1532 if (rc) { 1533 PMD_DRV_LOG(ERR, 1534 "cannot get attribute for ena device rc= %d\n", rc); 1535 goto err_admin_init; 1536 } 1537 1538 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1539 BIT(ENA_ADMIN_NOTIFICATION) | 1540 BIT(ENA_ADMIN_KEEP_ALIVE) | 1541 BIT(ENA_ADMIN_FATAL_ERROR) | 1542 BIT(ENA_ADMIN_WARNING); 1543 1544 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1545 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1546 if (rc) { 1547 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1548 goto err_admin_init; 1549 } 1550 1551 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1552 1553 return 0; 1554 1555 err_admin_init: 1556 ena_com_admin_destroy(ena_dev); 1557 1558 err_mmio_read_less: 1559 ena_com_mmio_reg_read_request_destroy(ena_dev); 1560 1561 return rc; 1562 } 1563 1564 static void ena_interrupt_handler_rte(void *cb_arg) 1565 { 1566 struct ena_adapter *adapter = cb_arg; 1567 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1568 1569 ena_com_admin_q_comp_intr_handler(ena_dev); 1570 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1571 ena_com_aenq_intr_handler(ena_dev, adapter); 1572 } 1573 1574 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1575 { 1576 if (!adapter->wd_state) 1577 return; 1578 1579 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1580 return; 1581 1582 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1583 adapter->keep_alive_timeout)) { 1584 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1585 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1586 adapter->trigger_reset = true; 1587 ++adapter->dev_stats.wd_expired; 1588 } 1589 } 1590 1591 /* Check if admin queue is enabled */ 1592 static void check_for_admin_com_state(struct ena_adapter *adapter) 1593 { 1594 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1595 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1596 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1597 adapter->trigger_reset = true; 1598 } 1599 } 1600 1601 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1602 void *arg) 1603 { 1604 struct ena_adapter *adapter = arg; 1605 struct rte_eth_dev *dev = adapter->rte_dev; 1606 1607 check_for_missing_keep_alive(adapter); 1608 check_for_admin_com_state(adapter); 1609 1610 if (unlikely(adapter->trigger_reset)) { 1611 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1612 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1613 NULL); 1614 } 1615 } 1616 1617 static inline void 1618 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1619 struct ena_admin_feature_llq_desc *llq, 1620 bool use_large_llq_hdr) 1621 { 1622 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1623 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1624 llq_config->llq_num_decs_before_header = 1625 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1626 1627 if (use_large_llq_hdr && 1628 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1629 llq_config->llq_ring_entry_size = 1630 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1631 llq_config->llq_ring_entry_size_value = 256; 1632 } else { 1633 llq_config->llq_ring_entry_size = 1634 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1635 llq_config->llq_ring_entry_size_value = 128; 1636 } 1637 } 1638 1639 static int 1640 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1641 struct ena_com_dev *ena_dev, 1642 struct ena_admin_feature_llq_desc *llq, 1643 struct ena_llq_configurations *llq_default_configurations) 1644 { 1645 int rc; 1646 u32 llq_feature_mask; 1647 1648 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1649 if (!(ena_dev->supported_features & llq_feature_mask)) { 1650 PMD_DRV_LOG(INFO, 1651 "LLQ is not supported. Fallback to host mode policy.\n"); 1652 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1653 return 0; 1654 } 1655 1656 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1657 if (unlikely(rc)) { 1658 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1659 "Fallback to host mode policy."); 1660 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1661 return 0; 1662 } 1663 1664 /* Nothing to config, exit */ 1665 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1666 return 0; 1667 1668 if (!adapter->dev_mem_base) { 1669 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1670 "Fallback to host mode policy.\n."); 1671 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1672 return 0; 1673 } 1674 1675 ena_dev->mem_bar = adapter->dev_mem_base; 1676 1677 return 0; 1678 } 1679 1680 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1681 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1682 { 1683 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1684 1685 /* Regular queues capabilities */ 1686 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1687 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1688 &get_feat_ctx->max_queue_ext.max_queue_ext; 1689 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1690 max_queue_ext->max_rx_cq_num); 1691 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1692 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1693 } else { 1694 struct ena_admin_queue_feature_desc *max_queues = 1695 &get_feat_ctx->max_queues; 1696 io_tx_sq_num = max_queues->max_sq_num; 1697 io_tx_cq_num = max_queues->max_cq_num; 1698 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1699 } 1700 1701 /* In case of LLQ use the llq number in the get feature cmd */ 1702 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1703 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1704 1705 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1706 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1707 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1708 1709 if (unlikely(max_num_io_queues == 0)) { 1710 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1711 return -EFAULT; 1712 } 1713 1714 return max_num_io_queues; 1715 } 1716 1717 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1718 { 1719 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1720 struct rte_pci_device *pci_dev; 1721 struct rte_intr_handle *intr_handle; 1722 struct ena_adapter *adapter = eth_dev->data->dev_private; 1723 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1724 struct ena_com_dev_get_features_ctx get_feat_ctx; 1725 struct ena_llq_configurations llq_config; 1726 const char *queue_type_str; 1727 uint32_t max_num_io_queues; 1728 int rc; 1729 1730 static int adapters_found; 1731 bool wd_state; 1732 1733 eth_dev->dev_ops = &ena_dev_ops; 1734 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1735 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1736 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1737 1738 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1739 return 0; 1740 1741 memset(adapter, 0, sizeof(struct ena_adapter)); 1742 ena_dev = &adapter->ena_dev; 1743 1744 adapter->rte_eth_dev_data = eth_dev->data; 1745 adapter->rte_dev = eth_dev; 1746 1747 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1748 adapter->pdev = pci_dev; 1749 1750 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1751 pci_dev->addr.domain, 1752 pci_dev->addr.bus, 1753 pci_dev->addr.devid, 1754 pci_dev->addr.function); 1755 1756 intr_handle = &pci_dev->intr_handle; 1757 1758 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1759 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1760 1761 if (!adapter->regs) { 1762 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1763 ENA_REGS_BAR); 1764 return -ENXIO; 1765 } 1766 1767 ena_dev->reg_bar = adapter->regs; 1768 ena_dev->dmadev = adapter->pdev; 1769 1770 adapter->id_number = adapters_found; 1771 1772 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1773 adapter->id_number); 1774 1775 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1776 if (rc != 0) { 1777 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1778 goto err; 1779 } 1780 1781 /* device specific initialization routine */ 1782 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1783 if (rc) { 1784 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1785 goto err; 1786 } 1787 adapter->wd_state = wd_state; 1788 1789 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1790 adapter->use_large_llq_hdr); 1791 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1792 &get_feat_ctx.llq, &llq_config); 1793 if (unlikely(rc)) { 1794 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1795 return rc; 1796 } 1797 1798 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1799 queue_type_str = "Regular"; 1800 else 1801 queue_type_str = "Low latency"; 1802 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1803 1804 calc_queue_ctx.ena_dev = ena_dev; 1805 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1806 1807 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1808 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1809 adapter->use_large_llq_hdr); 1810 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1811 rc = -EFAULT; 1812 goto err_device_destroy; 1813 } 1814 1815 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1816 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1817 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1818 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1819 adapter->max_num_io_queues = max_num_io_queues; 1820 1821 /* prepare ring structures */ 1822 ena_init_rings(adapter); 1823 1824 ena_config_debug_area(adapter); 1825 1826 /* Set max MTU for this device */ 1827 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1828 1829 /* set device support for offloads */ 1830 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1831 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1832 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1833 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1834 adapter->offloads.rx_csum_supported = 1835 (get_feat_ctx.offload.rx_supported & 1836 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1837 1838 /* Copy MAC address and point DPDK to it */ 1839 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1840 rte_ether_addr_copy((struct rte_ether_addr *) 1841 get_feat_ctx.dev_attr.mac_addr, 1842 (struct rte_ether_addr *)adapter->mac_addr); 1843 1844 /* 1845 * Pass the information to the rte_eth_dev_close() that it should also 1846 * release the private port resources. 1847 */ 1848 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1849 1850 adapter->drv_stats = rte_zmalloc("adapter stats", 1851 sizeof(*adapter->drv_stats), 1852 RTE_CACHE_LINE_SIZE); 1853 if (!adapter->drv_stats) { 1854 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1855 rc = -ENOMEM; 1856 goto err_delete_debug_area; 1857 } 1858 1859 rte_intr_callback_register(intr_handle, 1860 ena_interrupt_handler_rte, 1861 adapter); 1862 rte_intr_enable(intr_handle); 1863 ena_com_set_admin_polling_mode(ena_dev, false); 1864 ena_com_admin_aenq_enable(ena_dev); 1865 1866 if (adapters_found == 0) 1867 rte_timer_subsystem_init(); 1868 rte_timer_init(&adapter->timer_wd); 1869 1870 adapters_found++; 1871 adapter->state = ENA_ADAPTER_STATE_INIT; 1872 1873 return 0; 1874 1875 err_delete_debug_area: 1876 ena_com_delete_debug_area(ena_dev); 1877 1878 err_device_destroy: 1879 ena_com_delete_host_info(ena_dev); 1880 ena_com_admin_destroy(ena_dev); 1881 1882 err: 1883 return rc; 1884 } 1885 1886 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1887 { 1888 struct ena_adapter *adapter = eth_dev->data->dev_private; 1889 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1890 1891 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1892 return; 1893 1894 ena_com_set_admin_running_state(ena_dev, false); 1895 1896 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1897 ena_close(eth_dev); 1898 1899 ena_com_delete_debug_area(ena_dev); 1900 ena_com_delete_host_info(ena_dev); 1901 1902 ena_com_abort_admin_commands(ena_dev); 1903 ena_com_wait_for_abort_completion(ena_dev); 1904 ena_com_admin_destroy(ena_dev); 1905 ena_com_mmio_reg_read_request_destroy(ena_dev); 1906 1907 adapter->state = ENA_ADAPTER_STATE_FREE; 1908 } 1909 1910 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1911 { 1912 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1913 return 0; 1914 1915 ena_destroy_device(eth_dev); 1916 1917 eth_dev->dev_ops = NULL; 1918 eth_dev->rx_pkt_burst = NULL; 1919 eth_dev->tx_pkt_burst = NULL; 1920 eth_dev->tx_pkt_prepare = NULL; 1921 1922 return 0; 1923 } 1924 1925 static int ena_dev_configure(struct rte_eth_dev *dev) 1926 { 1927 struct ena_adapter *adapter = dev->data->dev_private; 1928 1929 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1930 1931 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1932 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1933 return 0; 1934 } 1935 1936 static void ena_init_rings(struct ena_adapter *adapter) 1937 { 1938 size_t i; 1939 1940 for (i = 0; i < adapter->max_num_io_queues; i++) { 1941 struct ena_ring *ring = &adapter->tx_ring[i]; 1942 1943 ring->configured = 0; 1944 ring->type = ENA_RING_TYPE_TX; 1945 ring->adapter = adapter; 1946 ring->id = i; 1947 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1948 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1949 ring->sgl_size = adapter->max_tx_sgl_size; 1950 } 1951 1952 for (i = 0; i < adapter->max_num_io_queues; i++) { 1953 struct ena_ring *ring = &adapter->rx_ring[i]; 1954 1955 ring->configured = 0; 1956 ring->type = ENA_RING_TYPE_RX; 1957 ring->adapter = adapter; 1958 ring->id = i; 1959 ring->sgl_size = adapter->max_rx_sgl_size; 1960 } 1961 } 1962 1963 static int ena_infos_get(struct rte_eth_dev *dev, 1964 struct rte_eth_dev_info *dev_info) 1965 { 1966 struct ena_adapter *adapter; 1967 struct ena_com_dev *ena_dev; 1968 uint64_t rx_feat = 0, tx_feat = 0; 1969 1970 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1971 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1972 adapter = dev->data->dev_private; 1973 1974 ena_dev = &adapter->ena_dev; 1975 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1976 1977 dev_info->speed_capa = 1978 ETH_LINK_SPEED_1G | 1979 ETH_LINK_SPEED_2_5G | 1980 ETH_LINK_SPEED_5G | 1981 ETH_LINK_SPEED_10G | 1982 ETH_LINK_SPEED_25G | 1983 ETH_LINK_SPEED_40G | 1984 ETH_LINK_SPEED_50G | 1985 ETH_LINK_SPEED_100G; 1986 1987 /* Set Tx & Rx features available for device */ 1988 if (adapter->offloads.tso4_supported) 1989 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1990 1991 if (adapter->offloads.tx_csum_supported) 1992 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1993 DEV_TX_OFFLOAD_UDP_CKSUM | 1994 DEV_TX_OFFLOAD_TCP_CKSUM; 1995 1996 if (adapter->offloads.rx_csum_supported) 1997 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1998 DEV_RX_OFFLOAD_UDP_CKSUM | 1999 DEV_RX_OFFLOAD_TCP_CKSUM; 2000 2001 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2002 2003 /* Inform framework about available features */ 2004 dev_info->rx_offload_capa = rx_feat; 2005 dev_info->rx_queue_offload_capa = rx_feat; 2006 dev_info->tx_offload_capa = tx_feat; 2007 dev_info->tx_queue_offload_capa = tx_feat; 2008 2009 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2010 ETH_RSS_UDP; 2011 2012 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2013 dev_info->max_rx_pktlen = adapter->max_mtu; 2014 dev_info->max_mac_addrs = 1; 2015 2016 dev_info->max_rx_queues = adapter->max_num_io_queues; 2017 dev_info->max_tx_queues = adapter->max_num_io_queues; 2018 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2019 2020 adapter->tx_supported_offloads = tx_feat; 2021 adapter->rx_supported_offloads = rx_feat; 2022 2023 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2024 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2025 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2026 adapter->max_rx_sgl_size); 2027 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2028 adapter->max_rx_sgl_size); 2029 2030 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2031 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2032 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2033 adapter->max_tx_sgl_size); 2034 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2035 adapter->max_tx_sgl_size); 2036 2037 return 0; 2038 } 2039 2040 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2041 uint16_t nb_pkts) 2042 { 2043 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2044 unsigned int ring_size = rx_ring->ring_size; 2045 unsigned int ring_mask = ring_size - 1; 2046 uint16_t next_to_clean = rx_ring->next_to_clean; 2047 uint16_t desc_in_use = 0; 2048 uint16_t req_id; 2049 unsigned int recv_idx = 0; 2050 struct rte_mbuf *mbuf = NULL; 2051 struct rte_mbuf *mbuf_head = NULL; 2052 struct rte_mbuf *mbuf_prev = NULL; 2053 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2054 unsigned int completed; 2055 2056 struct ena_com_rx_ctx ena_rx_ctx; 2057 int rc = 0; 2058 2059 /* Check adapter state */ 2060 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2061 PMD_DRV_LOG(ALERT, 2062 "Trying to receive pkts while device is NOT running\n"); 2063 return 0; 2064 } 2065 2066 desc_in_use = rx_ring->next_to_use - next_to_clean; 2067 if (unlikely(nb_pkts > desc_in_use)) 2068 nb_pkts = desc_in_use; 2069 2070 for (completed = 0; completed < nb_pkts; completed++) { 2071 int segments = 0; 2072 2073 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2074 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2075 ena_rx_ctx.descs = 0; 2076 ena_rx_ctx.pkt_offset = 0; 2077 /* receive packet context */ 2078 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2079 rx_ring->ena_com_io_sq, 2080 &ena_rx_ctx); 2081 if (unlikely(rc)) { 2082 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2083 rx_ring->adapter->reset_reason = 2084 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2085 rx_ring->adapter->trigger_reset = true; 2086 ++rx_ring->rx_stats.bad_desc_num; 2087 return 0; 2088 } 2089 2090 if (unlikely(ena_rx_ctx.descs == 0)) 2091 break; 2092 2093 while (segments < ena_rx_ctx.descs) { 2094 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2095 rc = validate_rx_req_id(rx_ring, req_id); 2096 if (unlikely(rc)) { 2097 if (segments != 0) 2098 rte_mbuf_raw_free(mbuf_head); 2099 break; 2100 } 2101 2102 mbuf = rx_buff_info[req_id]; 2103 rx_buff_info[req_id] = NULL; 2104 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2105 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2106 mbuf->refcnt = 1; 2107 mbuf->next = NULL; 2108 if (unlikely(segments == 0)) { 2109 mbuf->nb_segs = ena_rx_ctx.descs; 2110 mbuf->port = rx_ring->port_id; 2111 mbuf->pkt_len = 0; 2112 mbuf->data_off += ena_rx_ctx.pkt_offset; 2113 mbuf_head = mbuf; 2114 } else { 2115 /* for multi-segment pkts create mbuf chain */ 2116 mbuf_prev->next = mbuf; 2117 } 2118 mbuf_head->pkt_len += mbuf->data_len; 2119 2120 mbuf_prev = mbuf; 2121 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2122 req_id; 2123 segments++; 2124 next_to_clean++; 2125 } 2126 if (unlikely(rc)) 2127 break; 2128 2129 /* fill mbuf attributes if any */ 2130 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2131 2132 if (unlikely(mbuf_head->ol_flags & 2133 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2134 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2135 ++rx_ring->rx_stats.bad_csum; 2136 } 2137 2138 mbuf_head->hash.rss = ena_rx_ctx.hash; 2139 2140 /* pass to DPDK application head mbuf */ 2141 rx_pkts[recv_idx] = mbuf_head; 2142 recv_idx++; 2143 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2144 } 2145 2146 rx_ring->rx_stats.cnt += recv_idx; 2147 rx_ring->next_to_clean = next_to_clean; 2148 2149 desc_in_use = desc_in_use - completed + 1; 2150 /* Burst refill to save doorbells, memory barriers, const interval */ 2151 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2152 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2153 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2154 } 2155 2156 return recv_idx; 2157 } 2158 2159 static uint16_t 2160 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2161 uint16_t nb_pkts) 2162 { 2163 int32_t ret; 2164 uint32_t i; 2165 struct rte_mbuf *m; 2166 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2167 struct rte_ipv4_hdr *ip_hdr; 2168 uint64_t ol_flags; 2169 uint16_t frag_field; 2170 2171 for (i = 0; i != nb_pkts; i++) { 2172 m = tx_pkts[i]; 2173 ol_flags = m->ol_flags; 2174 2175 if (!(ol_flags & PKT_TX_IPV4)) 2176 continue; 2177 2178 /* If there was not L2 header length specified, assume it is 2179 * length of the ethernet header. 2180 */ 2181 if (unlikely(m->l2_len == 0)) 2182 m->l2_len = sizeof(struct rte_ether_hdr); 2183 2184 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2185 m->l2_len); 2186 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2187 2188 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2189 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2190 2191 /* If IPv4 header has DF flag enabled and TSO support is 2192 * disabled, partial chcecksum should not be calculated. 2193 */ 2194 if (!tx_ring->adapter->offloads.tso4_supported) 2195 continue; 2196 } 2197 2198 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2199 (ol_flags & PKT_TX_L4_MASK) == 2200 PKT_TX_SCTP_CKSUM) { 2201 rte_errno = ENOTSUP; 2202 return i; 2203 } 2204 2205 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2206 ret = rte_validate_tx_offload(m); 2207 if (ret != 0) { 2208 rte_errno = -ret; 2209 return i; 2210 } 2211 #endif 2212 2213 /* In case we are supposed to TSO and have DF not set (DF=0) 2214 * hardware must be provided with partial checksum, otherwise 2215 * it will take care of necessary calculations. 2216 */ 2217 2218 ret = rte_net_intel_cksum_flags_prepare(m, 2219 ol_flags & ~PKT_TX_TCP_SEG); 2220 if (ret != 0) { 2221 rte_errno = -ret; 2222 return i; 2223 } 2224 } 2225 2226 return i; 2227 } 2228 2229 static void ena_update_hints(struct ena_adapter *adapter, 2230 struct ena_admin_ena_hw_hints *hints) 2231 { 2232 if (hints->admin_completion_tx_timeout) 2233 adapter->ena_dev.admin_queue.completion_timeout = 2234 hints->admin_completion_tx_timeout * 1000; 2235 2236 if (hints->mmio_read_timeout) 2237 /* convert to usec */ 2238 adapter->ena_dev.mmio_read.reg_read_to = 2239 hints->mmio_read_timeout * 1000; 2240 2241 if (hints->driver_watchdog_timeout) { 2242 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2243 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2244 else 2245 // Convert msecs to ticks 2246 adapter->keep_alive_timeout = 2247 (hints->driver_watchdog_timeout * 2248 rte_get_timer_hz()) / 1000; 2249 } 2250 } 2251 2252 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2253 struct rte_mbuf *mbuf) 2254 { 2255 struct ena_com_dev *ena_dev; 2256 int num_segments, header_len, rc; 2257 2258 ena_dev = &tx_ring->adapter->ena_dev; 2259 num_segments = mbuf->nb_segs; 2260 header_len = mbuf->data_len; 2261 2262 if (likely(num_segments < tx_ring->sgl_size)) 2263 return 0; 2264 2265 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2266 (num_segments == tx_ring->sgl_size) && 2267 (header_len < tx_ring->tx_max_header_size)) 2268 return 0; 2269 2270 ++tx_ring->tx_stats.linearize; 2271 rc = rte_pktmbuf_linearize(mbuf); 2272 if (unlikely(rc)) { 2273 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2274 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2275 ++tx_ring->tx_stats.linearize_failed; 2276 return rc; 2277 } 2278 2279 return rc; 2280 } 2281 2282 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2283 uint16_t nb_pkts) 2284 { 2285 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2286 uint16_t next_to_use = tx_ring->next_to_use; 2287 uint16_t next_to_clean = tx_ring->next_to_clean; 2288 struct rte_mbuf *mbuf; 2289 uint16_t seg_len; 2290 unsigned int ring_size = tx_ring->ring_size; 2291 unsigned int ring_mask = ring_size - 1; 2292 struct ena_com_tx_ctx ena_tx_ctx; 2293 struct ena_tx_buffer *tx_info; 2294 struct ena_com_buf *ebuf; 2295 uint16_t rc, req_id, total_tx_descs = 0; 2296 uint16_t sent_idx = 0, empty_tx_reqs; 2297 uint16_t push_len = 0; 2298 uint16_t delta = 0; 2299 int nb_hw_desc; 2300 uint32_t total_length; 2301 2302 /* Check adapter state */ 2303 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2304 PMD_DRV_LOG(ALERT, 2305 "Trying to xmit pkts while device is NOT running\n"); 2306 return 0; 2307 } 2308 2309 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2310 if (nb_pkts > empty_tx_reqs) 2311 nb_pkts = empty_tx_reqs; 2312 2313 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2314 mbuf = tx_pkts[sent_idx]; 2315 total_length = 0; 2316 2317 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2318 if (unlikely(rc)) 2319 break; 2320 2321 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2322 tx_info = &tx_ring->tx_buffer_info[req_id]; 2323 tx_info->mbuf = mbuf; 2324 tx_info->num_of_bufs = 0; 2325 ebuf = tx_info->bufs; 2326 2327 /* Prepare TX context */ 2328 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2329 memset(&ena_tx_ctx.ena_meta, 0x0, 2330 sizeof(struct ena_com_tx_meta)); 2331 ena_tx_ctx.ena_bufs = ebuf; 2332 ena_tx_ctx.req_id = req_id; 2333 2334 delta = 0; 2335 seg_len = mbuf->data_len; 2336 2337 if (tx_ring->tx_mem_queue_type == 2338 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2339 push_len = RTE_MIN(mbuf->pkt_len, 2340 tx_ring->tx_max_header_size); 2341 ena_tx_ctx.header_len = push_len; 2342 2343 if (likely(push_len <= seg_len)) { 2344 /* If the push header is in the single segment, 2345 * then just point it to the 1st mbuf data. 2346 */ 2347 ena_tx_ctx.push_header = 2348 rte_pktmbuf_mtod(mbuf, uint8_t *); 2349 } else { 2350 /* If the push header lays in the several 2351 * segments, copy it to the intermediate buffer. 2352 */ 2353 rte_pktmbuf_read(mbuf, 0, push_len, 2354 tx_ring->push_buf_intermediate_buf); 2355 ena_tx_ctx.push_header = 2356 tx_ring->push_buf_intermediate_buf; 2357 delta = push_len - seg_len; 2358 } 2359 } /* there's no else as we take advantage of memset zeroing */ 2360 2361 /* Set TX offloads flags, if applicable */ 2362 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2363 2364 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2365 2366 /* Process first segment taking into 2367 * consideration pushed header 2368 */ 2369 if (seg_len > push_len) { 2370 ebuf->paddr = mbuf->buf_iova + 2371 mbuf->data_off + 2372 push_len; 2373 ebuf->len = seg_len - push_len; 2374 ebuf++; 2375 tx_info->num_of_bufs++; 2376 } 2377 total_length += mbuf->data_len; 2378 2379 while ((mbuf = mbuf->next) != NULL) { 2380 seg_len = mbuf->data_len; 2381 2382 /* Skip mbufs if whole data is pushed as a header */ 2383 if (unlikely(delta > seg_len)) { 2384 delta -= seg_len; 2385 continue; 2386 } 2387 2388 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2389 ebuf->len = seg_len - delta; 2390 total_length += ebuf->len; 2391 ebuf++; 2392 tx_info->num_of_bufs++; 2393 2394 delta = 0; 2395 } 2396 2397 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2398 2399 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2400 &ena_tx_ctx)) { 2401 PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d" 2402 " achieved, writing doorbell to send burst\n", 2403 tx_ring->id); 2404 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2405 } 2406 2407 /* prepare the packet's descriptors to dma engine */ 2408 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2409 &ena_tx_ctx, &nb_hw_desc); 2410 if (unlikely(rc)) { 2411 ++tx_ring->tx_stats.prepare_ctx_err; 2412 break; 2413 } 2414 tx_info->tx_descs = nb_hw_desc; 2415 2416 next_to_use++; 2417 tx_ring->tx_stats.cnt++; 2418 tx_ring->tx_stats.bytes += total_length; 2419 } 2420 tx_ring->tx_stats.available_desc = 2421 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2422 2423 /* If there are ready packets to be xmitted... */ 2424 if (sent_idx > 0) { 2425 /* ...let HW do its best :-) */ 2426 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2427 tx_ring->tx_stats.doorbells++; 2428 tx_ring->next_to_use = next_to_use; 2429 } 2430 2431 /* Clear complete packets */ 2432 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2433 rc = validate_tx_req_id(tx_ring, req_id); 2434 if (rc) 2435 break; 2436 2437 /* Get Tx info & store how many descs were processed */ 2438 tx_info = &tx_ring->tx_buffer_info[req_id]; 2439 total_tx_descs += tx_info->tx_descs; 2440 2441 /* Free whole mbuf chain */ 2442 mbuf = tx_info->mbuf; 2443 rte_pktmbuf_free(mbuf); 2444 tx_info->mbuf = NULL; 2445 2446 /* Put back descriptor to the ring for reuse */ 2447 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2448 next_to_clean++; 2449 2450 /* If too many descs to clean, leave it for another run */ 2451 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2452 break; 2453 } 2454 tx_ring->tx_stats.available_desc = 2455 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2456 2457 if (total_tx_descs > 0) { 2458 /* acknowledge completion of sent packets */ 2459 tx_ring->next_to_clean = next_to_clean; 2460 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2461 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2462 } 2463 2464 tx_ring->tx_stats.tx_poll++; 2465 2466 return sent_idx; 2467 } 2468 2469 /** 2470 * DPDK callback to retrieve names of extended device statistics 2471 * 2472 * @param dev 2473 * Pointer to Ethernet device structure. 2474 * @param[out] xstats_names 2475 * Buffer to insert names into. 2476 * @param n 2477 * Number of names. 2478 * 2479 * @return 2480 * Number of xstats names. 2481 */ 2482 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2483 struct rte_eth_xstat_name *xstats_names, 2484 unsigned int n) 2485 { 2486 unsigned int xstats_count = ena_xstats_calc_num(dev); 2487 unsigned int stat, i, count = 0; 2488 2489 if (n < xstats_count || !xstats_names) 2490 return xstats_count; 2491 2492 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2493 strcpy(xstats_names[count].name, 2494 ena_stats_global_strings[stat].name); 2495 2496 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2497 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2498 snprintf(xstats_names[count].name, 2499 sizeof(xstats_names[count].name), 2500 "rx_q%d_%s", i, 2501 ena_stats_rx_strings[stat].name); 2502 2503 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2504 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2505 snprintf(xstats_names[count].name, 2506 sizeof(xstats_names[count].name), 2507 "tx_q%d_%s", i, 2508 ena_stats_tx_strings[stat].name); 2509 2510 return xstats_count; 2511 } 2512 2513 /** 2514 * DPDK callback to get extended device statistics. 2515 * 2516 * @param dev 2517 * Pointer to Ethernet device structure. 2518 * @param[out] stats 2519 * Stats table output buffer. 2520 * @param n 2521 * The size of the stats table. 2522 * 2523 * @return 2524 * Number of xstats on success, negative on failure. 2525 */ 2526 static int ena_xstats_get(struct rte_eth_dev *dev, 2527 struct rte_eth_xstat *xstats, 2528 unsigned int n) 2529 { 2530 struct ena_adapter *adapter = dev->data->dev_private; 2531 unsigned int xstats_count = ena_xstats_calc_num(dev); 2532 unsigned int stat, i, count = 0; 2533 int stat_offset; 2534 void *stats_begin; 2535 2536 if (n < xstats_count) 2537 return xstats_count; 2538 2539 if (!xstats) 2540 return 0; 2541 2542 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2543 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2544 stats_begin = &adapter->dev_stats; 2545 2546 xstats[count].id = count; 2547 xstats[count].value = *((uint64_t *) 2548 ((char *)stats_begin + stat_offset)); 2549 } 2550 2551 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2552 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2553 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2554 stats_begin = &adapter->rx_ring[i].rx_stats; 2555 2556 xstats[count].id = count; 2557 xstats[count].value = *((uint64_t *) 2558 ((char *)stats_begin + stat_offset)); 2559 } 2560 } 2561 2562 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2563 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2564 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2565 stats_begin = &adapter->tx_ring[i].rx_stats; 2566 2567 xstats[count].id = count; 2568 xstats[count].value = *((uint64_t *) 2569 ((char *)stats_begin + stat_offset)); 2570 } 2571 } 2572 2573 return count; 2574 } 2575 2576 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2577 const uint64_t *ids, 2578 uint64_t *values, 2579 unsigned int n) 2580 { 2581 struct ena_adapter *adapter = dev->data->dev_private; 2582 uint64_t id; 2583 uint64_t rx_entries, tx_entries; 2584 unsigned int i; 2585 int qid; 2586 int valid = 0; 2587 for (i = 0; i < n; ++i) { 2588 id = ids[i]; 2589 /* Check if id belongs to global statistics */ 2590 if (id < ENA_STATS_ARRAY_GLOBAL) { 2591 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2592 ++valid; 2593 continue; 2594 } 2595 2596 /* Check if id belongs to rx queue statistics */ 2597 id -= ENA_STATS_ARRAY_GLOBAL; 2598 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2599 if (id < rx_entries) { 2600 qid = id % dev->data->nb_rx_queues; 2601 id /= dev->data->nb_rx_queues; 2602 values[i] = *((uint64_t *) 2603 &adapter->rx_ring[qid].rx_stats + id); 2604 ++valid; 2605 continue; 2606 } 2607 /* Check if id belongs to rx queue statistics */ 2608 id -= rx_entries; 2609 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2610 if (id < tx_entries) { 2611 qid = id % dev->data->nb_tx_queues; 2612 id /= dev->data->nb_tx_queues; 2613 values[i] = *((uint64_t *) 2614 &adapter->tx_ring[qid].tx_stats + id); 2615 ++valid; 2616 continue; 2617 } 2618 } 2619 2620 return valid; 2621 } 2622 2623 static int ena_process_bool_devarg(const char *key, 2624 const char *value, 2625 void *opaque) 2626 { 2627 struct ena_adapter *adapter = opaque; 2628 bool bool_value; 2629 2630 /* Parse the value. */ 2631 if (strcmp(value, "1") == 0) { 2632 bool_value = true; 2633 } else if (strcmp(value, "0") == 0) { 2634 bool_value = false; 2635 } else { 2636 PMD_INIT_LOG(ERR, 2637 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2638 value, key); 2639 return -EINVAL; 2640 } 2641 2642 /* Now, assign it to the proper adapter field. */ 2643 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) 2644 adapter->use_large_llq_hdr = bool_value; 2645 2646 return 0; 2647 } 2648 2649 static int ena_parse_devargs(struct ena_adapter *adapter, 2650 struct rte_devargs *devargs) 2651 { 2652 static const char * const allowed_args[] = { 2653 ENA_DEVARG_LARGE_LLQ_HDR, 2654 }; 2655 struct rte_kvargs *kvlist; 2656 int rc; 2657 2658 if (devargs == NULL) 2659 return 0; 2660 2661 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2662 if (kvlist == NULL) { 2663 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2664 devargs->args); 2665 return -EINVAL; 2666 } 2667 2668 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2669 ena_process_bool_devarg, adapter); 2670 2671 rte_kvargs_free(kvlist); 2672 2673 return rc; 2674 } 2675 2676 /********************************************************************* 2677 * PMD configuration 2678 *********************************************************************/ 2679 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2680 struct rte_pci_device *pci_dev) 2681 { 2682 return rte_eth_dev_pci_generic_probe(pci_dev, 2683 sizeof(struct ena_adapter), eth_ena_dev_init); 2684 } 2685 2686 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2687 { 2688 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2689 } 2690 2691 static struct rte_pci_driver rte_ena_pmd = { 2692 .id_table = pci_id_ena_map, 2693 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2694 RTE_PCI_DRV_WC_ACTIVATE, 2695 .probe = eth_ena_pci_probe, 2696 .remove = eth_ena_pci_remove, 2697 }; 2698 2699 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2700 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2701 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2702 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2703 2704 RTE_INIT(ena_init_log) 2705 { 2706 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2707 if (ena_logtype_init >= 0) 2708 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2709 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2710 if (ena_logtype_driver >= 0) 2711 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2712 2713 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2714 ena_logtype_rx = rte_log_register("pmd.net.ena.rx"); 2715 if (ena_logtype_rx >= 0) 2716 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE); 2717 #endif 2718 2719 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2720 ena_logtype_tx = rte_log_register("pmd.net.ena.tx"); 2721 if (ena_logtype_tx >= 0) 2722 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE); 2723 #endif 2724 2725 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2726 ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free"); 2727 if (ena_logtype_tx_free >= 0) 2728 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE); 2729 #endif 2730 2731 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2732 ena_logtype_com = rte_log_register("pmd.net.ena.com"); 2733 if (ena_logtype_com >= 0) 2734 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE); 2735 #endif 2736 } 2737 2738 /****************************************************************************** 2739 ******************************** AENQ Handlers ******************************* 2740 *****************************************************************************/ 2741 static void ena_update_on_link_change(void *adapter_data, 2742 struct ena_admin_aenq_entry *aenq_e) 2743 { 2744 struct rte_eth_dev *eth_dev; 2745 struct ena_adapter *adapter; 2746 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2747 uint32_t status; 2748 2749 adapter = adapter_data; 2750 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2751 eth_dev = adapter->rte_dev; 2752 2753 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2754 adapter->link_status = status; 2755 2756 ena_link_update(eth_dev, 0); 2757 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2758 } 2759 2760 static void ena_notification(void *data, 2761 struct ena_admin_aenq_entry *aenq_e) 2762 { 2763 struct ena_adapter *adapter = data; 2764 struct ena_admin_ena_hw_hints *hints; 2765 2766 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2767 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2768 aenq_e->aenq_common_desc.group, 2769 ENA_ADMIN_NOTIFICATION); 2770 2771 switch (aenq_e->aenq_common_desc.syndrom) { 2772 case ENA_ADMIN_UPDATE_HINTS: 2773 hints = (struct ena_admin_ena_hw_hints *) 2774 (&aenq_e->inline_data_w4); 2775 ena_update_hints(adapter, hints); 2776 break; 2777 default: 2778 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2779 aenq_e->aenq_common_desc.syndrom); 2780 } 2781 } 2782 2783 static void ena_keep_alive(void *adapter_data, 2784 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2785 { 2786 struct ena_adapter *adapter = adapter_data; 2787 struct ena_admin_aenq_keep_alive_desc *desc; 2788 uint64_t rx_drops; 2789 uint64_t tx_drops; 2790 2791 adapter->timestamp_wd = rte_get_timer_cycles(); 2792 2793 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2794 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2795 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 2796 2797 adapter->drv_stats->rx_drops = rx_drops; 2798 adapter->dev_stats.tx_drops = tx_drops; 2799 } 2800 2801 /** 2802 * This handler will called for unknown event group or unimplemented handlers 2803 **/ 2804 static void unimplemented_aenq_handler(__rte_unused void *data, 2805 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2806 { 2807 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 2808 "unimplemented handler\n"); 2809 } 2810 2811 static struct ena_aenq_handlers aenq_handlers = { 2812 .handlers = { 2813 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2814 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2815 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2816 }, 2817 .unimplemented_handler = unimplemented_aenq_handler 2818 }; 2819