1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_errno.h> 8 #include <rte_version.h> 9 #include <rte_net.h> 10 #include <rte_kvargs.h> 11 12 #include "ena_ethdev.h" 13 #include "ena_logs.h" 14 #include "ena_platform.h" 15 #include "ena_com.h" 16 #include "ena_eth_com.h" 17 18 #include <ena_common_defs.h> 19 #include <ena_regs_defs.h> 20 #include <ena_admin_defs.h> 21 #include <ena_eth_io_defs.h> 22 23 #define DRV_MODULE_VER_MAJOR 2 24 #define DRV_MODULE_VER_MINOR 4 25 #define DRV_MODULE_VER_SUBMINOR 0 26 27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 28 29 #define GET_L4_HDR_LEN(mbuf) \ 30 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 31 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 32 33 #define ETH_GSTRING_LEN 32 34 35 #define ARRAY_SIZE(x) RTE_DIM(x) 36 37 #define ENA_MIN_RING_DESC 128 38 39 #define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP) 40 41 enum ethtool_stringset { 42 ETH_SS_TEST = 0, 43 ETH_SS_STATS, 44 }; 45 46 struct ena_stats { 47 char name[ETH_GSTRING_LEN]; 48 int stat_offset; 49 }; 50 51 #define ENA_STAT_ENTRY(stat, stat_type) { \ 52 .name = #stat, \ 53 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 54 } 55 56 #define ENA_STAT_RX_ENTRY(stat) \ 57 ENA_STAT_ENTRY(stat, rx) 58 59 #define ENA_STAT_TX_ENTRY(stat) \ 60 ENA_STAT_ENTRY(stat, tx) 61 62 #define ENA_STAT_ENI_ENTRY(stat) \ 63 ENA_STAT_ENTRY(stat, eni) 64 65 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 66 ENA_STAT_ENTRY(stat, dev) 67 68 /* Device arguments */ 69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 70 71 /* 72 * Each rte_memzone should have unique name. 73 * To satisfy it, count number of allocation and add it to name. 74 */ 75 rte_atomic64_t ena_alloc_cnt; 76 77 static const struct ena_stats ena_stats_global_strings[] = { 78 ENA_STAT_GLOBAL_ENTRY(wd_expired), 79 ENA_STAT_GLOBAL_ENTRY(dev_start), 80 ENA_STAT_GLOBAL_ENTRY(dev_stop), 81 ENA_STAT_GLOBAL_ENTRY(tx_drops), 82 }; 83 84 static const struct ena_stats ena_stats_eni_strings[] = { 85 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded), 86 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded), 87 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded), 88 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded), 89 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded), 90 }; 91 92 static const struct ena_stats ena_stats_tx_strings[] = { 93 ENA_STAT_TX_ENTRY(cnt), 94 ENA_STAT_TX_ENTRY(bytes), 95 ENA_STAT_TX_ENTRY(prepare_ctx_err), 96 ENA_STAT_TX_ENTRY(linearize), 97 ENA_STAT_TX_ENTRY(linearize_failed), 98 ENA_STAT_TX_ENTRY(tx_poll), 99 ENA_STAT_TX_ENTRY(doorbells), 100 ENA_STAT_TX_ENTRY(bad_req_id), 101 ENA_STAT_TX_ENTRY(available_desc), 102 }; 103 104 static const struct ena_stats ena_stats_rx_strings[] = { 105 ENA_STAT_RX_ENTRY(cnt), 106 ENA_STAT_RX_ENTRY(bytes), 107 ENA_STAT_RX_ENTRY(refill_partial), 108 ENA_STAT_RX_ENTRY(bad_csum), 109 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 110 ENA_STAT_RX_ENTRY(bad_desc_num), 111 ENA_STAT_RX_ENTRY(bad_req_id), 112 }; 113 114 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 115 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings) 116 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 117 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 118 119 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 120 DEV_TX_OFFLOAD_UDP_CKSUM |\ 121 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 122 DEV_TX_OFFLOAD_TCP_TSO) 123 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 124 PKT_TX_IP_CKSUM |\ 125 PKT_TX_TCP_SEG) 126 127 /** Vendor ID used by Amazon devices */ 128 #define PCI_VENDOR_ID_AMAZON 0x1D0F 129 /** Amazon devices */ 130 #define PCI_DEVICE_ID_ENA_VF 0xEC20 131 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21 132 133 #define ENA_TX_OFFLOAD_MASK (\ 134 PKT_TX_L4_MASK | \ 135 PKT_TX_IPV6 | \ 136 PKT_TX_IPV4 | \ 137 PKT_TX_IP_CKSUM | \ 138 PKT_TX_TCP_SEG) 139 140 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 141 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 142 143 static const struct rte_pci_id pci_id_ena_map[] = { 144 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) }, 146 { .device_id = 0 }, 147 }; 148 149 static struct ena_aenq_handlers aenq_handlers; 150 151 static int ena_device_init(struct ena_com_dev *ena_dev, 152 struct rte_pci_device *pdev, 153 struct ena_com_dev_get_features_ctx *get_feat_ctx, 154 bool *wd_state); 155 static int ena_dev_configure(struct rte_eth_dev *dev); 156 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 157 struct ena_tx_buffer *tx_info, 158 struct rte_mbuf *mbuf, 159 void **push_header, 160 uint16_t *header_len); 161 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 162 static void ena_tx_cleanup(struct ena_ring *tx_ring); 163 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 164 uint16_t nb_pkts); 165 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 166 uint16_t nb_pkts); 167 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 168 uint16_t nb_desc, unsigned int socket_id, 169 const struct rte_eth_txconf *tx_conf); 170 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 171 uint16_t nb_desc, unsigned int socket_id, 172 const struct rte_eth_rxconf *rx_conf, 173 struct rte_mempool *mp); 174 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 175 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 176 struct ena_com_rx_buf_info *ena_bufs, 177 uint32_t descs, 178 uint16_t *next_to_clean, 179 uint8_t offset); 180 static uint16_t eth_ena_recv_pkts(void *rx_queue, 181 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 182 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 183 struct rte_mbuf *mbuf, uint16_t id); 184 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 185 static void ena_init_rings(struct ena_adapter *adapter, 186 bool disable_meta_caching); 187 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 188 static int ena_start(struct rte_eth_dev *dev); 189 static int ena_stop(struct rte_eth_dev *dev); 190 static int ena_close(struct rte_eth_dev *dev); 191 static int ena_dev_reset(struct rte_eth_dev *dev); 192 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 193 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 194 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 195 static void ena_rx_queue_release(void *queue); 196 static void ena_tx_queue_release(void *queue); 197 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 198 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 199 static int ena_link_update(struct rte_eth_dev *dev, 200 int wait_to_complete); 201 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring); 202 static void ena_queue_stop(struct ena_ring *ring); 203 static void ena_queue_stop_all(struct rte_eth_dev *dev, 204 enum ena_ring_type ring_type); 205 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring); 206 static int ena_queue_start_all(struct rte_eth_dev *dev, 207 enum ena_ring_type ring_type); 208 static void ena_stats_restart(struct rte_eth_dev *dev); 209 static int ena_infos_get(struct rte_eth_dev *dev, 210 struct rte_eth_dev_info *dev_info); 211 static void ena_interrupt_handler_rte(void *cb_arg); 212 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 213 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 214 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 215 static int ena_xstats_get_names(struct rte_eth_dev *dev, 216 struct rte_eth_xstat_name *xstats_names, 217 unsigned int n); 218 static int ena_xstats_get(struct rte_eth_dev *dev, 219 struct rte_eth_xstat *stats, 220 unsigned int n); 221 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 222 const uint64_t *ids, 223 uint64_t *values, 224 unsigned int n); 225 static int ena_process_bool_devarg(const char *key, 226 const char *value, 227 void *opaque); 228 static int ena_parse_devargs(struct ena_adapter *adapter, 229 struct rte_devargs *devargs); 230 static int ena_copy_eni_stats(struct ena_adapter *adapter); 231 static int ena_setup_rx_intr(struct rte_eth_dev *dev); 232 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, 233 uint16_t queue_id); 234 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, 235 uint16_t queue_id); 236 237 static const struct eth_dev_ops ena_dev_ops = { 238 .dev_configure = ena_dev_configure, 239 .dev_infos_get = ena_infos_get, 240 .rx_queue_setup = ena_rx_queue_setup, 241 .tx_queue_setup = ena_tx_queue_setup, 242 .dev_start = ena_start, 243 .dev_stop = ena_stop, 244 .link_update = ena_link_update, 245 .stats_get = ena_stats_get, 246 .xstats_get_names = ena_xstats_get_names, 247 .xstats_get = ena_xstats_get, 248 .xstats_get_by_id = ena_xstats_get_by_id, 249 .mtu_set = ena_mtu_set, 250 .rx_queue_release = ena_rx_queue_release, 251 .tx_queue_release = ena_tx_queue_release, 252 .dev_close = ena_close, 253 .dev_reset = ena_dev_reset, 254 .reta_update = ena_rss_reta_update, 255 .reta_query = ena_rss_reta_query, 256 .rx_queue_intr_enable = ena_rx_queue_intr_enable, 257 .rx_queue_intr_disable = ena_rx_queue_intr_disable, 258 .rss_hash_update = ena_rss_hash_update, 259 .rss_hash_conf_get = ena_rss_hash_conf_get, 260 }; 261 262 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 263 struct ena_com_rx_ctx *ena_rx_ctx, 264 bool fill_hash) 265 { 266 uint64_t ol_flags = 0; 267 uint32_t packet_type = 0; 268 269 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 270 packet_type |= RTE_PTYPE_L4_TCP; 271 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 272 packet_type |= RTE_PTYPE_L4_UDP; 273 274 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 275 packet_type |= RTE_PTYPE_L3_IPV4; 276 if (unlikely(ena_rx_ctx->l3_csum_err)) 277 ol_flags |= PKT_RX_IP_CKSUM_BAD; 278 else 279 ol_flags |= PKT_RX_IP_CKSUM_GOOD; 280 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 281 packet_type |= RTE_PTYPE_L3_IPV6; 282 } 283 284 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) 285 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 286 else 287 if (unlikely(ena_rx_ctx->l4_csum_err)) 288 ol_flags |= PKT_RX_L4_CKSUM_BAD; 289 else 290 ol_flags |= PKT_RX_L4_CKSUM_GOOD; 291 292 if (fill_hash && 293 likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) { 294 ol_flags |= PKT_RX_RSS_HASH; 295 mbuf->hash.rss = ena_rx_ctx->hash; 296 } 297 298 mbuf->ol_flags = ol_flags; 299 mbuf->packet_type = packet_type; 300 } 301 302 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 303 struct ena_com_tx_ctx *ena_tx_ctx, 304 uint64_t queue_offloads, 305 bool disable_meta_caching) 306 { 307 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 308 309 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 310 (queue_offloads & QUEUE_OFFLOADS)) { 311 /* check if TSO is required */ 312 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 313 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 314 ena_tx_ctx->tso_enable = true; 315 316 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 317 } 318 319 /* check if L3 checksum is needed */ 320 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 321 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 322 ena_tx_ctx->l3_csum_enable = true; 323 324 if (mbuf->ol_flags & PKT_TX_IPV6) { 325 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 326 } else { 327 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 328 329 /* set don't fragment (DF) flag */ 330 if (mbuf->packet_type & 331 (RTE_PTYPE_L4_NONFRAG 332 | RTE_PTYPE_INNER_L4_NONFRAG)) 333 ena_tx_ctx->df = true; 334 } 335 336 /* check if L4 checksum is needed */ 337 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 339 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 340 ena_tx_ctx->l4_csum_enable = true; 341 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 342 PKT_TX_UDP_CKSUM) && 343 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 344 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 345 ena_tx_ctx->l4_csum_enable = true; 346 } else { 347 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 348 ena_tx_ctx->l4_csum_enable = false; 349 } 350 351 ena_meta->mss = mbuf->tso_segsz; 352 ena_meta->l3_hdr_len = mbuf->l3_len; 353 ena_meta->l3_hdr_offset = mbuf->l2_len; 354 355 ena_tx_ctx->meta_valid = true; 356 } else if (disable_meta_caching) { 357 memset(ena_meta, 0, sizeof(*ena_meta)); 358 ena_tx_ctx->meta_valid = true; 359 } else { 360 ena_tx_ctx->meta_valid = false; 361 } 362 } 363 364 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 365 { 366 struct ena_tx_buffer *tx_info = NULL; 367 368 if (likely(req_id < tx_ring->ring_size)) { 369 tx_info = &tx_ring->tx_buffer_info[req_id]; 370 if (likely(tx_info->mbuf)) 371 return 0; 372 } 373 374 if (tx_info) 375 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 376 else 377 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id); 378 379 /* Trigger device reset */ 380 ++tx_ring->tx_stats.bad_req_id; 381 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 382 tx_ring->adapter->trigger_reset = true; 383 return -EFAULT; 384 } 385 386 static void ena_config_host_info(struct ena_com_dev *ena_dev) 387 { 388 struct ena_admin_host_info *host_info; 389 int rc; 390 391 /* Allocate only the host info */ 392 rc = ena_com_allocate_host_info(ena_dev); 393 if (rc) { 394 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 395 return; 396 } 397 398 host_info = ena_dev->host_attr.host_info; 399 400 host_info->os_type = ENA_ADMIN_OS_DPDK; 401 host_info->kernel_ver = RTE_VERSION; 402 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 403 sizeof(host_info->kernel_ver_str)); 404 host_info->os_dist = RTE_VERSION; 405 strlcpy((char *)host_info->os_dist_str, rte_version(), 406 sizeof(host_info->os_dist_str)); 407 host_info->driver_version = 408 (DRV_MODULE_VER_MAJOR) | 409 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 410 (DRV_MODULE_VER_SUBMINOR << 411 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 412 host_info->num_cpus = rte_lcore_count(); 413 414 host_info->driver_supported_features = 415 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK | 416 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK; 417 418 rc = ena_com_set_host_attributes(ena_dev); 419 if (rc) { 420 if (rc == -ENA_COM_UNSUPPORTED) 421 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 422 else 423 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 424 425 goto err; 426 } 427 428 return; 429 430 err: 431 ena_com_delete_host_info(ena_dev); 432 } 433 434 /* This function calculates the number of xstats based on the current config */ 435 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data) 436 { 437 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + 438 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 439 (data->nb_rx_queues * ENA_STATS_ARRAY_RX); 440 } 441 442 static void ena_config_debug_area(struct ena_adapter *adapter) 443 { 444 u32 debug_area_size; 445 int rc, ss_count; 446 447 ss_count = ena_xstats_calc_num(adapter->edev_data); 448 449 /* allocate 32 bytes for each string and 64bit for the value */ 450 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 451 452 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 453 if (rc) { 454 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 455 return; 456 } 457 458 rc = ena_com_set_host_attributes(&adapter->ena_dev); 459 if (rc) { 460 if (rc == -ENA_COM_UNSUPPORTED) 461 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 462 else 463 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 464 465 goto err; 466 } 467 468 return; 469 err: 470 ena_com_delete_debug_area(&adapter->ena_dev); 471 } 472 473 static int ena_close(struct rte_eth_dev *dev) 474 { 475 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 476 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 477 struct ena_adapter *adapter = dev->data->dev_private; 478 int ret = 0; 479 480 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 481 return 0; 482 483 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 484 ret = ena_stop(dev); 485 adapter->state = ENA_ADAPTER_STATE_CLOSED; 486 487 ena_rx_queue_release_all(dev); 488 ena_tx_queue_release_all(dev); 489 490 rte_free(adapter->drv_stats); 491 adapter->drv_stats = NULL; 492 493 rte_intr_disable(intr_handle); 494 rte_intr_callback_unregister(intr_handle, 495 ena_interrupt_handler_rte, 496 dev); 497 498 /* 499 * MAC is not allocated dynamically. Setting NULL should prevent from 500 * release of the resource in the rte_eth_dev_release_port(). 501 */ 502 dev->data->mac_addrs = NULL; 503 504 return ret; 505 } 506 507 static int 508 ena_dev_reset(struct rte_eth_dev *dev) 509 { 510 int rc = 0; 511 512 /* Cannot release memory in secondary process */ 513 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 514 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n"); 515 return -EPERM; 516 } 517 518 ena_destroy_device(dev); 519 rc = eth_ena_dev_init(dev); 520 if (rc) 521 PMD_INIT_LOG(CRIT, "Cannot initialize device\n"); 522 523 return rc; 524 } 525 526 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 527 { 528 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 529 int nb_queues = dev->data->nb_rx_queues; 530 int i; 531 532 for (i = 0; i < nb_queues; i++) 533 ena_rx_queue_release(queues[i]); 534 } 535 536 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 537 { 538 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 539 int nb_queues = dev->data->nb_tx_queues; 540 int i; 541 542 for (i = 0; i < nb_queues; i++) 543 ena_tx_queue_release(queues[i]); 544 } 545 546 static void ena_rx_queue_release(void *queue) 547 { 548 struct ena_ring *ring = (struct ena_ring *)queue; 549 550 /* Free ring resources */ 551 if (ring->rx_buffer_info) 552 rte_free(ring->rx_buffer_info); 553 ring->rx_buffer_info = NULL; 554 555 if (ring->rx_refill_buffer) 556 rte_free(ring->rx_refill_buffer); 557 ring->rx_refill_buffer = NULL; 558 559 if (ring->empty_rx_reqs) 560 rte_free(ring->empty_rx_reqs); 561 ring->empty_rx_reqs = NULL; 562 563 ring->configured = 0; 564 565 PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n", 566 ring->port_id, ring->id); 567 } 568 569 static void ena_tx_queue_release(void *queue) 570 { 571 struct ena_ring *ring = (struct ena_ring *)queue; 572 573 /* Free ring resources */ 574 if (ring->push_buf_intermediate_buf) 575 rte_free(ring->push_buf_intermediate_buf); 576 577 if (ring->tx_buffer_info) 578 rte_free(ring->tx_buffer_info); 579 580 if (ring->empty_tx_reqs) 581 rte_free(ring->empty_tx_reqs); 582 583 ring->empty_tx_reqs = NULL; 584 ring->tx_buffer_info = NULL; 585 ring->push_buf_intermediate_buf = NULL; 586 587 ring->configured = 0; 588 589 PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n", 590 ring->port_id, ring->id); 591 } 592 593 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 594 { 595 unsigned int i; 596 597 for (i = 0; i < ring->ring_size; ++i) { 598 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 599 if (rx_info->mbuf) { 600 rte_mbuf_raw_free(rx_info->mbuf); 601 rx_info->mbuf = NULL; 602 } 603 } 604 } 605 606 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 607 { 608 unsigned int i; 609 610 for (i = 0; i < ring->ring_size; ++i) { 611 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 612 613 if (tx_buf->mbuf) { 614 rte_pktmbuf_free(tx_buf->mbuf); 615 tx_buf->mbuf = NULL; 616 } 617 } 618 } 619 620 static int ena_link_update(struct rte_eth_dev *dev, 621 __rte_unused int wait_to_complete) 622 { 623 struct rte_eth_link *link = &dev->data->dev_link; 624 struct ena_adapter *adapter = dev->data->dev_private; 625 626 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 627 link->link_speed = ETH_SPEED_NUM_NONE; 628 link->link_duplex = ETH_LINK_FULL_DUPLEX; 629 630 return 0; 631 } 632 633 static int ena_queue_start_all(struct rte_eth_dev *dev, 634 enum ena_ring_type ring_type) 635 { 636 struct ena_adapter *adapter = dev->data->dev_private; 637 struct ena_ring *queues = NULL; 638 int nb_queues; 639 int i = 0; 640 int rc = 0; 641 642 if (ring_type == ENA_RING_TYPE_RX) { 643 queues = adapter->rx_ring; 644 nb_queues = dev->data->nb_rx_queues; 645 } else { 646 queues = adapter->tx_ring; 647 nb_queues = dev->data->nb_tx_queues; 648 } 649 for (i = 0; i < nb_queues; i++) { 650 if (queues[i].configured) { 651 if (ring_type == ENA_RING_TYPE_RX) { 652 ena_assert_msg( 653 dev->data->rx_queues[i] == &queues[i], 654 "Inconsistent state of Rx queues\n"); 655 } else { 656 ena_assert_msg( 657 dev->data->tx_queues[i] == &queues[i], 658 "Inconsistent state of Tx queues\n"); 659 } 660 661 rc = ena_queue_start(dev, &queues[i]); 662 663 if (rc) { 664 PMD_INIT_LOG(ERR, 665 "Failed to start queue[%d] of type(%d)\n", 666 i, ring_type); 667 goto err; 668 } 669 } 670 } 671 672 return 0; 673 674 err: 675 while (i--) 676 if (queues[i].configured) 677 ena_queue_stop(&queues[i]); 678 679 return rc; 680 } 681 682 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 683 { 684 uint32_t max_frame_len = adapter->max_mtu; 685 686 if (adapter->edev_data->dev_conf.rxmode.offloads & 687 DEV_RX_OFFLOAD_JUMBO_FRAME) 688 max_frame_len = 689 adapter->edev_data->dev_conf.rxmode.max_rx_pkt_len; 690 691 return max_frame_len; 692 } 693 694 static int ena_check_valid_conf(struct ena_adapter *adapter) 695 { 696 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 697 698 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 699 PMD_INIT_LOG(ERR, 700 "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n", 701 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 702 return ENA_COM_UNSUPPORTED; 703 } 704 705 return 0; 706 } 707 708 static int 709 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 710 bool use_large_llq_hdr) 711 { 712 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 713 struct ena_com_dev *ena_dev = ctx->ena_dev; 714 uint32_t max_tx_queue_size; 715 uint32_t max_rx_queue_size; 716 717 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 718 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 719 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 720 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 721 max_queue_ext->max_rx_sq_depth); 722 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 723 724 if (ena_dev->tx_mem_queue_type == 725 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 726 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 727 llq->max_llq_depth); 728 } else { 729 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 730 max_queue_ext->max_tx_sq_depth); 731 } 732 733 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 734 max_queue_ext->max_per_packet_rx_descs); 735 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 736 max_queue_ext->max_per_packet_tx_descs); 737 } else { 738 struct ena_admin_queue_feature_desc *max_queues = 739 &ctx->get_feat_ctx->max_queues; 740 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 741 max_queues->max_sq_depth); 742 max_tx_queue_size = max_queues->max_cq_depth; 743 744 if (ena_dev->tx_mem_queue_type == 745 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 746 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 747 llq->max_llq_depth); 748 } else { 749 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 750 max_queues->max_sq_depth); 751 } 752 753 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 754 max_queues->max_packet_rx_descs); 755 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 756 max_queues->max_packet_tx_descs); 757 } 758 759 /* Round down to the nearest power of 2 */ 760 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 761 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 762 763 if (use_large_llq_hdr) { 764 if ((llq->entry_size_ctrl_supported & 765 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 766 (ena_dev->tx_mem_queue_type == 767 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 768 max_tx_queue_size /= 2; 769 PMD_INIT_LOG(INFO, 770 "Forcing large headers and decreasing maximum Tx queue size to %d\n", 771 max_tx_queue_size); 772 } else { 773 PMD_INIT_LOG(ERR, 774 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 775 } 776 } 777 778 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 779 PMD_INIT_LOG(ERR, "Invalid queue size\n"); 780 return -EFAULT; 781 } 782 783 ctx->max_tx_queue_size = max_tx_queue_size; 784 ctx->max_rx_queue_size = max_rx_queue_size; 785 786 return 0; 787 } 788 789 static void ena_stats_restart(struct rte_eth_dev *dev) 790 { 791 struct ena_adapter *adapter = dev->data->dev_private; 792 793 rte_atomic64_init(&adapter->drv_stats->ierrors); 794 rte_atomic64_init(&adapter->drv_stats->oerrors); 795 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 796 adapter->drv_stats->rx_drops = 0; 797 } 798 799 static int ena_stats_get(struct rte_eth_dev *dev, 800 struct rte_eth_stats *stats) 801 { 802 struct ena_admin_basic_stats ena_stats; 803 struct ena_adapter *adapter = dev->data->dev_private; 804 struct ena_com_dev *ena_dev = &adapter->ena_dev; 805 int rc; 806 int i; 807 int max_rings_stats; 808 809 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 810 return -ENOTSUP; 811 812 memset(&ena_stats, 0, sizeof(ena_stats)); 813 814 rte_spinlock_lock(&adapter->admin_lock); 815 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 816 rte_spinlock_unlock(&adapter->admin_lock); 817 if (unlikely(rc)) { 818 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 819 return rc; 820 } 821 822 /* Set of basic statistics from ENA */ 823 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 824 ena_stats.rx_pkts_low); 825 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 826 ena_stats.tx_pkts_low); 827 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 828 ena_stats.rx_bytes_low); 829 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 830 ena_stats.tx_bytes_low); 831 832 /* Driver related stats */ 833 stats->imissed = adapter->drv_stats->rx_drops; 834 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 835 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 836 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 837 838 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 839 RTE_ETHDEV_QUEUE_STAT_CNTRS); 840 for (i = 0; i < max_rings_stats; ++i) { 841 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 842 843 stats->q_ibytes[i] = rx_stats->bytes; 844 stats->q_ipackets[i] = rx_stats->cnt; 845 stats->q_errors[i] = rx_stats->bad_desc_num + 846 rx_stats->bad_req_id; 847 } 848 849 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 850 RTE_ETHDEV_QUEUE_STAT_CNTRS); 851 for (i = 0; i < max_rings_stats; ++i) { 852 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 853 854 stats->q_obytes[i] = tx_stats->bytes; 855 stats->q_opackets[i] = tx_stats->cnt; 856 } 857 858 return 0; 859 } 860 861 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 862 { 863 struct ena_adapter *adapter; 864 struct ena_com_dev *ena_dev; 865 int rc = 0; 866 867 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 868 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 869 adapter = dev->data->dev_private; 870 871 ena_dev = &adapter->ena_dev; 872 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 873 874 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 875 PMD_DRV_LOG(ERR, 876 "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n", 877 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 878 return -EINVAL; 879 } 880 881 rc = ena_com_set_dev_mtu(ena_dev, mtu); 882 if (rc) 883 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 884 else 885 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu); 886 887 return rc; 888 } 889 890 static int ena_start(struct rte_eth_dev *dev) 891 { 892 struct ena_adapter *adapter = dev->data->dev_private; 893 uint64_t ticks; 894 int rc = 0; 895 896 /* Cannot allocate memory in secondary process */ 897 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 898 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n"); 899 return -EPERM; 900 } 901 902 rc = ena_check_valid_conf(adapter); 903 if (rc) 904 return rc; 905 906 rc = ena_setup_rx_intr(dev); 907 if (rc) 908 return rc; 909 910 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 911 if (rc) 912 return rc; 913 914 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 915 if (rc) 916 goto err_start_tx; 917 918 if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 919 rc = ena_rss_configure(adapter); 920 if (rc) 921 goto err_rss_init; 922 } 923 924 ena_stats_restart(dev); 925 926 adapter->timestamp_wd = rte_get_timer_cycles(); 927 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 928 929 ticks = rte_get_timer_hz(); 930 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 931 ena_timer_wd_callback, dev); 932 933 ++adapter->dev_stats.dev_start; 934 adapter->state = ENA_ADAPTER_STATE_RUNNING; 935 936 return 0; 937 938 err_rss_init: 939 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 940 err_start_tx: 941 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 942 return rc; 943 } 944 945 static int ena_stop(struct rte_eth_dev *dev) 946 { 947 struct ena_adapter *adapter = dev->data->dev_private; 948 struct ena_com_dev *ena_dev = &adapter->ena_dev; 949 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 950 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 951 int rc; 952 953 /* Cannot free memory in secondary process */ 954 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 955 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n"); 956 return -EPERM; 957 } 958 959 rte_timer_stop_sync(&adapter->timer_wd); 960 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 961 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 962 963 if (adapter->trigger_reset) { 964 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 965 if (rc) 966 PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc); 967 } 968 969 rte_intr_disable(intr_handle); 970 971 rte_intr_efd_disable(intr_handle); 972 if (intr_handle->intr_vec != NULL) { 973 rte_free(intr_handle->intr_vec); 974 intr_handle->intr_vec = NULL; 975 } 976 977 rte_intr_enable(intr_handle); 978 979 ++adapter->dev_stats.dev_stop; 980 adapter->state = ENA_ADAPTER_STATE_STOPPED; 981 dev->data->dev_started = 0; 982 983 return 0; 984 } 985 986 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring) 987 { 988 struct ena_adapter *adapter = ring->adapter; 989 struct ena_com_dev *ena_dev = &adapter->ena_dev; 990 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 991 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 992 struct ena_com_create_io_ctx ctx = 993 /* policy set to _HOST just to satisfy icc compiler */ 994 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 995 0, 0, 0, 0, 0 }; 996 uint16_t ena_qid; 997 unsigned int i; 998 int rc; 999 1000 ctx.msix_vector = -1; 1001 if (ring->type == ENA_RING_TYPE_TX) { 1002 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1003 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1004 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1005 for (i = 0; i < ring->ring_size; i++) 1006 ring->empty_tx_reqs[i] = i; 1007 } else { 1008 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1009 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1010 if (rte_intr_dp_is_en(intr_handle)) 1011 ctx.msix_vector = intr_handle->intr_vec[ring->id]; 1012 for (i = 0; i < ring->ring_size; i++) 1013 ring->empty_rx_reqs[i] = i; 1014 } 1015 ctx.queue_size = ring->ring_size; 1016 ctx.qid = ena_qid; 1017 ctx.numa_node = ring->numa_socket_id; 1018 1019 rc = ena_com_create_io_queue(ena_dev, &ctx); 1020 if (rc) { 1021 PMD_DRV_LOG(ERR, 1022 "Failed to create IO queue[%d] (qid:%d), rc: %d\n", 1023 ring->id, ena_qid, rc); 1024 return rc; 1025 } 1026 1027 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1028 &ring->ena_com_io_sq, 1029 &ring->ena_com_io_cq); 1030 if (rc) { 1031 PMD_DRV_LOG(ERR, 1032 "Failed to get IO queue[%d] handlers, rc: %d\n", 1033 ring->id, rc); 1034 ena_com_destroy_io_queue(ena_dev, ena_qid); 1035 return rc; 1036 } 1037 1038 if (ring->type == ENA_RING_TYPE_TX) 1039 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1040 1041 /* Start with Rx interrupts being masked. */ 1042 if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle)) 1043 ena_rx_queue_intr_disable(dev, ring->id); 1044 1045 return 0; 1046 } 1047 1048 static void ena_queue_stop(struct ena_ring *ring) 1049 { 1050 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1051 1052 if (ring->type == ENA_RING_TYPE_RX) { 1053 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1054 ena_rx_queue_release_bufs(ring); 1055 } else { 1056 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1057 ena_tx_queue_release_bufs(ring); 1058 } 1059 } 1060 1061 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1062 enum ena_ring_type ring_type) 1063 { 1064 struct ena_adapter *adapter = dev->data->dev_private; 1065 struct ena_ring *queues = NULL; 1066 uint16_t nb_queues, i; 1067 1068 if (ring_type == ENA_RING_TYPE_RX) { 1069 queues = adapter->rx_ring; 1070 nb_queues = dev->data->nb_rx_queues; 1071 } else { 1072 queues = adapter->tx_ring; 1073 nb_queues = dev->data->nb_tx_queues; 1074 } 1075 1076 for (i = 0; i < nb_queues; ++i) 1077 if (queues[i].configured) 1078 ena_queue_stop(&queues[i]); 1079 } 1080 1081 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring) 1082 { 1083 int rc, bufs_num; 1084 1085 ena_assert_msg(ring->configured == 1, 1086 "Trying to start unconfigured queue\n"); 1087 1088 rc = ena_create_io_queue(dev, ring); 1089 if (rc) { 1090 PMD_INIT_LOG(ERR, "Failed to create IO queue\n"); 1091 return rc; 1092 } 1093 1094 ring->next_to_clean = 0; 1095 ring->next_to_use = 0; 1096 1097 if (ring->type == ENA_RING_TYPE_TX) { 1098 ring->tx_stats.available_desc = 1099 ena_com_free_q_entries(ring->ena_com_io_sq); 1100 return 0; 1101 } 1102 1103 bufs_num = ring->ring_size - 1; 1104 rc = ena_populate_rx_queue(ring, bufs_num); 1105 if (rc != bufs_num) { 1106 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1107 ENA_IO_RXQ_IDX(ring->id)); 1108 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n"); 1109 return ENA_COM_FAULT; 1110 } 1111 /* Flush per-core RX buffers pools cache as they can be used on other 1112 * cores as well. 1113 */ 1114 rte_mempool_cache_flush(NULL, ring->mb_pool); 1115 1116 return 0; 1117 } 1118 1119 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1120 uint16_t queue_idx, 1121 uint16_t nb_desc, 1122 unsigned int socket_id, 1123 const struct rte_eth_txconf *tx_conf) 1124 { 1125 struct ena_ring *txq = NULL; 1126 struct ena_adapter *adapter = dev->data->dev_private; 1127 unsigned int i; 1128 1129 txq = &adapter->tx_ring[queue_idx]; 1130 1131 if (txq->configured) { 1132 PMD_DRV_LOG(CRIT, 1133 "API violation. Queue[%d] is already configured\n", 1134 queue_idx); 1135 return ENA_COM_FAULT; 1136 } 1137 1138 if (!rte_is_power_of_2(nb_desc)) { 1139 PMD_DRV_LOG(ERR, 1140 "Unsupported size of Tx queue: %d is not a power of 2.\n", 1141 nb_desc); 1142 return -EINVAL; 1143 } 1144 1145 if (nb_desc > adapter->max_tx_ring_size) { 1146 PMD_DRV_LOG(ERR, 1147 "Unsupported size of Tx queue (max size: %d)\n", 1148 adapter->max_tx_ring_size); 1149 return -EINVAL; 1150 } 1151 1152 txq->port_id = dev->data->port_id; 1153 txq->next_to_clean = 0; 1154 txq->next_to_use = 0; 1155 txq->ring_size = nb_desc; 1156 txq->size_mask = nb_desc - 1; 1157 txq->numa_socket_id = socket_id; 1158 txq->pkts_without_db = false; 1159 1160 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1161 sizeof(struct ena_tx_buffer) * 1162 txq->ring_size, 1163 RTE_CACHE_LINE_SIZE); 1164 if (!txq->tx_buffer_info) { 1165 PMD_DRV_LOG(ERR, 1166 "Failed to allocate memory for Tx buffer info\n"); 1167 return -ENOMEM; 1168 } 1169 1170 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1171 sizeof(u16) * txq->ring_size, 1172 RTE_CACHE_LINE_SIZE); 1173 if (!txq->empty_tx_reqs) { 1174 PMD_DRV_LOG(ERR, 1175 "Failed to allocate memory for empty Tx requests\n"); 1176 rte_free(txq->tx_buffer_info); 1177 return -ENOMEM; 1178 } 1179 1180 txq->push_buf_intermediate_buf = 1181 rte_zmalloc("txq->push_buf_intermediate_buf", 1182 txq->tx_max_header_size, 1183 RTE_CACHE_LINE_SIZE); 1184 if (!txq->push_buf_intermediate_buf) { 1185 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n"); 1186 rte_free(txq->tx_buffer_info); 1187 rte_free(txq->empty_tx_reqs); 1188 return -ENOMEM; 1189 } 1190 1191 for (i = 0; i < txq->ring_size; i++) 1192 txq->empty_tx_reqs[i] = i; 1193 1194 if (tx_conf != NULL) { 1195 txq->offloads = 1196 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1197 } 1198 /* Store pointer to this queue in upper layer */ 1199 txq->configured = 1; 1200 dev->data->tx_queues[queue_idx] = txq; 1201 1202 return 0; 1203 } 1204 1205 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1206 uint16_t queue_idx, 1207 uint16_t nb_desc, 1208 unsigned int socket_id, 1209 const struct rte_eth_rxconf *rx_conf, 1210 struct rte_mempool *mp) 1211 { 1212 struct ena_adapter *adapter = dev->data->dev_private; 1213 struct ena_ring *rxq = NULL; 1214 size_t buffer_size; 1215 int i; 1216 1217 rxq = &adapter->rx_ring[queue_idx]; 1218 if (rxq->configured) { 1219 PMD_DRV_LOG(CRIT, 1220 "API violation. Queue[%d] is already configured\n", 1221 queue_idx); 1222 return ENA_COM_FAULT; 1223 } 1224 1225 if (!rte_is_power_of_2(nb_desc)) { 1226 PMD_DRV_LOG(ERR, 1227 "Unsupported size of Rx queue: %d is not a power of 2.\n", 1228 nb_desc); 1229 return -EINVAL; 1230 } 1231 1232 if (nb_desc > adapter->max_rx_ring_size) { 1233 PMD_DRV_LOG(ERR, 1234 "Unsupported size of Rx queue (max size: %d)\n", 1235 adapter->max_rx_ring_size); 1236 return -EINVAL; 1237 } 1238 1239 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1240 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1241 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1242 PMD_DRV_LOG(ERR, 1243 "Unsupported size of Rx buffer: %zu (min size: %d)\n", 1244 buffer_size, ENA_RX_BUF_MIN_SIZE); 1245 return -EINVAL; 1246 } 1247 1248 rxq->port_id = dev->data->port_id; 1249 rxq->next_to_clean = 0; 1250 rxq->next_to_use = 0; 1251 rxq->ring_size = nb_desc; 1252 rxq->size_mask = nb_desc - 1; 1253 rxq->numa_socket_id = socket_id; 1254 rxq->mb_pool = mp; 1255 1256 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1257 sizeof(struct ena_rx_buffer) * nb_desc, 1258 RTE_CACHE_LINE_SIZE); 1259 if (!rxq->rx_buffer_info) { 1260 PMD_DRV_LOG(ERR, 1261 "Failed to allocate memory for Rx buffer info\n"); 1262 return -ENOMEM; 1263 } 1264 1265 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1266 sizeof(struct rte_mbuf *) * nb_desc, 1267 RTE_CACHE_LINE_SIZE); 1268 1269 if (!rxq->rx_refill_buffer) { 1270 PMD_DRV_LOG(ERR, 1271 "Failed to allocate memory for Rx refill buffer\n"); 1272 rte_free(rxq->rx_buffer_info); 1273 rxq->rx_buffer_info = NULL; 1274 return -ENOMEM; 1275 } 1276 1277 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1278 sizeof(uint16_t) * nb_desc, 1279 RTE_CACHE_LINE_SIZE); 1280 if (!rxq->empty_rx_reqs) { 1281 PMD_DRV_LOG(ERR, 1282 "Failed to allocate memory for empty Rx requests\n"); 1283 rte_free(rxq->rx_buffer_info); 1284 rxq->rx_buffer_info = NULL; 1285 rte_free(rxq->rx_refill_buffer); 1286 rxq->rx_refill_buffer = NULL; 1287 return -ENOMEM; 1288 } 1289 1290 for (i = 0; i < nb_desc; i++) 1291 rxq->empty_rx_reqs[i] = i; 1292 1293 rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1294 1295 /* Store pointer to this queue in upper layer */ 1296 rxq->configured = 1; 1297 dev->data->rx_queues[queue_idx] = rxq; 1298 1299 return 0; 1300 } 1301 1302 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1303 struct rte_mbuf *mbuf, uint16_t id) 1304 { 1305 struct ena_com_buf ebuf; 1306 int rc; 1307 1308 /* prepare physical address for DMA transaction */ 1309 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1310 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1311 1312 /* pass resource to device */ 1313 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1314 if (unlikely(rc != 0)) 1315 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n"); 1316 1317 return rc; 1318 } 1319 1320 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1321 { 1322 unsigned int i; 1323 int rc; 1324 uint16_t next_to_use = rxq->next_to_use; 1325 uint16_t req_id; 1326 #ifdef RTE_ETHDEV_DEBUG_RX 1327 uint16_t in_use; 1328 #endif 1329 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1330 1331 if (unlikely(!count)) 1332 return 0; 1333 1334 #ifdef RTE_ETHDEV_DEBUG_RX 1335 in_use = rxq->ring_size - 1 - 1336 ena_com_free_q_entries(rxq->ena_com_io_sq); 1337 if (unlikely((in_use + count) >= rxq->ring_size)) 1338 PMD_RX_LOG(ERR, "Bad Rx ring state\n"); 1339 #endif 1340 1341 /* get resources for incoming packets */ 1342 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count); 1343 if (unlikely(rc < 0)) { 1344 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1345 ++rxq->rx_stats.mbuf_alloc_fail; 1346 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n"); 1347 return 0; 1348 } 1349 1350 for (i = 0; i < count; i++) { 1351 struct rte_mbuf *mbuf = mbufs[i]; 1352 struct ena_rx_buffer *rx_info; 1353 1354 if (likely((i + 4) < count)) 1355 rte_prefetch0(mbufs[i + 4]); 1356 1357 req_id = rxq->empty_rx_reqs[next_to_use]; 1358 rx_info = &rxq->rx_buffer_info[req_id]; 1359 1360 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1361 if (unlikely(rc != 0)) 1362 break; 1363 1364 rx_info->mbuf = mbuf; 1365 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1366 } 1367 1368 if (unlikely(i < count)) { 1369 PMD_RX_LOG(WARNING, 1370 "Refilled Rx queue[%d] with only %d/%d buffers\n", 1371 rxq->id, i, count); 1372 rte_pktmbuf_free_bulk(&mbufs[i], count - i); 1373 ++rxq->rx_stats.refill_partial; 1374 } 1375 1376 /* When we submitted free recources to device... */ 1377 if (likely(i > 0)) { 1378 /* ...let HW know that it can fill buffers with data. */ 1379 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1380 1381 rxq->next_to_use = next_to_use; 1382 } 1383 1384 return i; 1385 } 1386 1387 static int ena_device_init(struct ena_com_dev *ena_dev, 1388 struct rte_pci_device *pdev, 1389 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1390 bool *wd_state) 1391 { 1392 uint32_t aenq_groups; 1393 int rc; 1394 bool readless_supported; 1395 1396 /* Initialize mmio registers */ 1397 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1398 if (rc) { 1399 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n"); 1400 return rc; 1401 } 1402 1403 /* The PCIe configuration space revision id indicate if mmio reg 1404 * read is disabled. 1405 */ 1406 readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ); 1407 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1408 1409 /* reset device */ 1410 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1411 if (rc) { 1412 PMD_DRV_LOG(ERR, "Cannot reset device\n"); 1413 goto err_mmio_read_less; 1414 } 1415 1416 /* check FW version */ 1417 rc = ena_com_validate_version(ena_dev); 1418 if (rc) { 1419 PMD_DRV_LOG(ERR, "Device version is too low\n"); 1420 goto err_mmio_read_less; 1421 } 1422 1423 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1424 1425 /* ENA device administration layer init */ 1426 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1427 if (rc) { 1428 PMD_DRV_LOG(ERR, 1429 "Cannot initialize ENA admin queue\n"); 1430 goto err_mmio_read_less; 1431 } 1432 1433 /* To enable the msix interrupts the driver needs to know the number 1434 * of queues. So the driver uses polling mode to retrieve this 1435 * information. 1436 */ 1437 ena_com_set_admin_polling_mode(ena_dev, true); 1438 1439 ena_config_host_info(ena_dev); 1440 1441 /* Get Device Attributes and features */ 1442 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1443 if (rc) { 1444 PMD_DRV_LOG(ERR, 1445 "Cannot get attribute for ENA device, rc: %d\n", rc); 1446 goto err_admin_init; 1447 } 1448 1449 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1450 BIT(ENA_ADMIN_NOTIFICATION) | 1451 BIT(ENA_ADMIN_KEEP_ALIVE) | 1452 BIT(ENA_ADMIN_FATAL_ERROR) | 1453 BIT(ENA_ADMIN_WARNING); 1454 1455 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1456 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1457 if (rc) { 1458 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc); 1459 goto err_admin_init; 1460 } 1461 1462 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1463 1464 return 0; 1465 1466 err_admin_init: 1467 ena_com_admin_destroy(ena_dev); 1468 1469 err_mmio_read_less: 1470 ena_com_mmio_reg_read_request_destroy(ena_dev); 1471 1472 return rc; 1473 } 1474 1475 static void ena_interrupt_handler_rte(void *cb_arg) 1476 { 1477 struct rte_eth_dev *dev = cb_arg; 1478 struct ena_adapter *adapter = dev->data->dev_private; 1479 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1480 1481 ena_com_admin_q_comp_intr_handler(ena_dev); 1482 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1483 ena_com_aenq_intr_handler(ena_dev, dev); 1484 } 1485 1486 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1487 { 1488 if (!adapter->wd_state) 1489 return; 1490 1491 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1492 return; 1493 1494 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1495 adapter->keep_alive_timeout)) { 1496 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1497 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1498 adapter->trigger_reset = true; 1499 ++adapter->dev_stats.wd_expired; 1500 } 1501 } 1502 1503 /* Check if admin queue is enabled */ 1504 static void check_for_admin_com_state(struct ena_adapter *adapter) 1505 { 1506 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1507 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n"); 1508 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1509 adapter->trigger_reset = true; 1510 } 1511 } 1512 1513 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1514 void *arg) 1515 { 1516 struct rte_eth_dev *dev = arg; 1517 struct ena_adapter *adapter = dev->data->dev_private; 1518 1519 check_for_missing_keep_alive(adapter); 1520 check_for_admin_com_state(adapter); 1521 1522 if (unlikely(adapter->trigger_reset)) { 1523 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1524 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1525 NULL); 1526 } 1527 } 1528 1529 static inline void 1530 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1531 struct ena_admin_feature_llq_desc *llq, 1532 bool use_large_llq_hdr) 1533 { 1534 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1535 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1536 llq_config->llq_num_decs_before_header = 1537 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1538 1539 if (use_large_llq_hdr && 1540 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1541 llq_config->llq_ring_entry_size = 1542 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1543 llq_config->llq_ring_entry_size_value = 256; 1544 } else { 1545 llq_config->llq_ring_entry_size = 1546 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1547 llq_config->llq_ring_entry_size_value = 128; 1548 } 1549 } 1550 1551 static int 1552 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1553 struct ena_com_dev *ena_dev, 1554 struct ena_admin_feature_llq_desc *llq, 1555 struct ena_llq_configurations *llq_default_configurations) 1556 { 1557 int rc; 1558 u32 llq_feature_mask; 1559 1560 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1561 if (!(ena_dev->supported_features & llq_feature_mask)) { 1562 PMD_DRV_LOG(INFO, 1563 "LLQ is not supported. Fallback to host mode policy.\n"); 1564 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1565 return 0; 1566 } 1567 1568 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1569 if (unlikely(rc)) { 1570 PMD_INIT_LOG(WARNING, 1571 "Failed to config dev mode. Fallback to host mode policy.\n"); 1572 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1573 return 0; 1574 } 1575 1576 /* Nothing to config, exit */ 1577 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1578 return 0; 1579 1580 if (!adapter->dev_mem_base) { 1581 PMD_DRV_LOG(ERR, 1582 "Unable to access LLQ BAR resource. Fallback to host mode policy.\n"); 1583 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1584 return 0; 1585 } 1586 1587 ena_dev->mem_bar = adapter->dev_mem_base; 1588 1589 return 0; 1590 } 1591 1592 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1593 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1594 { 1595 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1596 1597 /* Regular queues capabilities */ 1598 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1599 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1600 &get_feat_ctx->max_queue_ext.max_queue_ext; 1601 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1602 max_queue_ext->max_rx_cq_num); 1603 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1604 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1605 } else { 1606 struct ena_admin_queue_feature_desc *max_queues = 1607 &get_feat_ctx->max_queues; 1608 io_tx_sq_num = max_queues->max_sq_num; 1609 io_tx_cq_num = max_queues->max_cq_num; 1610 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1611 } 1612 1613 /* In case of LLQ use the llq number in the get feature cmd */ 1614 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1615 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1616 1617 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1618 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1619 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1620 1621 if (unlikely(max_num_io_queues == 0)) { 1622 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n"); 1623 return -EFAULT; 1624 } 1625 1626 return max_num_io_queues; 1627 } 1628 1629 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1630 { 1631 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1632 struct rte_pci_device *pci_dev; 1633 struct rte_intr_handle *intr_handle; 1634 struct ena_adapter *adapter = eth_dev->data->dev_private; 1635 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1636 struct ena_com_dev_get_features_ctx get_feat_ctx; 1637 struct ena_llq_configurations llq_config; 1638 const char *queue_type_str; 1639 uint32_t max_num_io_queues; 1640 int rc; 1641 static int adapters_found; 1642 bool disable_meta_caching; 1643 bool wd_state = false; 1644 1645 eth_dev->dev_ops = &ena_dev_ops; 1646 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1647 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1648 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1649 1650 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1651 return 0; 1652 1653 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1654 1655 memset(adapter, 0, sizeof(struct ena_adapter)); 1656 ena_dev = &adapter->ena_dev; 1657 1658 adapter->edev_data = eth_dev->data; 1659 1660 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1661 1662 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n", 1663 pci_dev->addr.domain, 1664 pci_dev->addr.bus, 1665 pci_dev->addr.devid, 1666 pci_dev->addr.function); 1667 1668 intr_handle = &pci_dev->intr_handle; 1669 1670 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1671 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1672 1673 if (!adapter->regs) { 1674 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n", 1675 ENA_REGS_BAR); 1676 return -ENXIO; 1677 } 1678 1679 ena_dev->reg_bar = adapter->regs; 1680 /* This is a dummy pointer for ena_com functions. */ 1681 ena_dev->dmadev = adapter; 1682 1683 adapter->id_number = adapters_found; 1684 1685 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1686 adapter->id_number); 1687 1688 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1689 if (rc != 0) { 1690 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1691 goto err; 1692 } 1693 1694 /* device specific initialization routine */ 1695 rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state); 1696 if (rc) { 1697 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n"); 1698 goto err; 1699 } 1700 adapter->wd_state = wd_state; 1701 1702 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1703 adapter->use_large_llq_hdr); 1704 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1705 &get_feat_ctx.llq, &llq_config); 1706 if (unlikely(rc)) { 1707 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n"); 1708 return rc; 1709 } 1710 1711 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1712 queue_type_str = "Regular"; 1713 else 1714 queue_type_str = "Low latency"; 1715 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1716 1717 calc_queue_ctx.ena_dev = ena_dev; 1718 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1719 1720 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1721 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1722 adapter->use_large_llq_hdr); 1723 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1724 rc = -EFAULT; 1725 goto err_device_destroy; 1726 } 1727 1728 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1729 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1730 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1731 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1732 adapter->max_num_io_queues = max_num_io_queues; 1733 1734 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1735 disable_meta_caching = 1736 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 1737 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 1738 } else { 1739 disable_meta_caching = false; 1740 } 1741 1742 /* prepare ring structures */ 1743 ena_init_rings(adapter, disable_meta_caching); 1744 1745 ena_config_debug_area(adapter); 1746 1747 /* Set max MTU for this device */ 1748 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1749 1750 /* set device support for offloads */ 1751 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1752 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1753 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1754 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1755 adapter->offloads.rx_csum_supported = 1756 (get_feat_ctx.offload.rx_supported & 1757 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1758 adapter->offloads.rss_hash_supported = 1759 (get_feat_ctx.offload.rx_supported & 1760 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) != 0; 1761 1762 /* Copy MAC address and point DPDK to it */ 1763 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1764 rte_ether_addr_copy((struct rte_ether_addr *) 1765 get_feat_ctx.dev_attr.mac_addr, 1766 (struct rte_ether_addr *)adapter->mac_addr); 1767 1768 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 1769 if (unlikely(rc != 0)) { 1770 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n"); 1771 goto err_delete_debug_area; 1772 } 1773 1774 adapter->drv_stats = rte_zmalloc("adapter stats", 1775 sizeof(*adapter->drv_stats), 1776 RTE_CACHE_LINE_SIZE); 1777 if (!adapter->drv_stats) { 1778 PMD_DRV_LOG(ERR, 1779 "Failed to allocate memory for adapter statistics\n"); 1780 rc = -ENOMEM; 1781 goto err_rss_destroy; 1782 } 1783 1784 rte_spinlock_init(&adapter->admin_lock); 1785 1786 rte_intr_callback_register(intr_handle, 1787 ena_interrupt_handler_rte, 1788 eth_dev); 1789 rte_intr_enable(intr_handle); 1790 ena_com_set_admin_polling_mode(ena_dev, false); 1791 ena_com_admin_aenq_enable(ena_dev); 1792 1793 if (adapters_found == 0) 1794 rte_timer_subsystem_init(); 1795 rte_timer_init(&adapter->timer_wd); 1796 1797 adapters_found++; 1798 adapter->state = ENA_ADAPTER_STATE_INIT; 1799 1800 return 0; 1801 1802 err_rss_destroy: 1803 ena_com_rss_destroy(ena_dev); 1804 err_delete_debug_area: 1805 ena_com_delete_debug_area(ena_dev); 1806 1807 err_device_destroy: 1808 ena_com_delete_host_info(ena_dev); 1809 ena_com_admin_destroy(ena_dev); 1810 1811 err: 1812 return rc; 1813 } 1814 1815 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1816 { 1817 struct ena_adapter *adapter = eth_dev->data->dev_private; 1818 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1819 1820 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1821 return; 1822 1823 ena_com_set_admin_running_state(ena_dev, false); 1824 1825 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1826 ena_close(eth_dev); 1827 1828 ena_com_rss_destroy(ena_dev); 1829 1830 ena_com_delete_debug_area(ena_dev); 1831 ena_com_delete_host_info(ena_dev); 1832 1833 ena_com_abort_admin_commands(ena_dev); 1834 ena_com_wait_for_abort_completion(ena_dev); 1835 ena_com_admin_destroy(ena_dev); 1836 ena_com_mmio_reg_read_request_destroy(ena_dev); 1837 1838 adapter->state = ENA_ADAPTER_STATE_FREE; 1839 } 1840 1841 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1842 { 1843 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1844 return 0; 1845 1846 ena_destroy_device(eth_dev); 1847 1848 return 0; 1849 } 1850 1851 static int ena_dev_configure(struct rte_eth_dev *dev) 1852 { 1853 struct ena_adapter *adapter = dev->data->dev_private; 1854 1855 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1856 1857 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1858 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1859 dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS; 1860 1861 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1862 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1863 return 0; 1864 } 1865 1866 static void ena_init_rings(struct ena_adapter *adapter, 1867 bool disable_meta_caching) 1868 { 1869 size_t i; 1870 1871 for (i = 0; i < adapter->max_num_io_queues; i++) { 1872 struct ena_ring *ring = &adapter->tx_ring[i]; 1873 1874 ring->configured = 0; 1875 ring->type = ENA_RING_TYPE_TX; 1876 ring->adapter = adapter; 1877 ring->id = i; 1878 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1879 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1880 ring->sgl_size = adapter->max_tx_sgl_size; 1881 ring->disable_meta_caching = disable_meta_caching; 1882 } 1883 1884 for (i = 0; i < adapter->max_num_io_queues; i++) { 1885 struct ena_ring *ring = &adapter->rx_ring[i]; 1886 1887 ring->configured = 0; 1888 ring->type = ENA_RING_TYPE_RX; 1889 ring->adapter = adapter; 1890 ring->id = i; 1891 ring->sgl_size = adapter->max_rx_sgl_size; 1892 } 1893 } 1894 1895 static int ena_infos_get(struct rte_eth_dev *dev, 1896 struct rte_eth_dev_info *dev_info) 1897 { 1898 struct ena_adapter *adapter; 1899 struct ena_com_dev *ena_dev; 1900 uint64_t rx_feat = 0, tx_feat = 0; 1901 1902 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1903 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1904 adapter = dev->data->dev_private; 1905 1906 ena_dev = &adapter->ena_dev; 1907 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1908 1909 dev_info->speed_capa = 1910 ETH_LINK_SPEED_1G | 1911 ETH_LINK_SPEED_2_5G | 1912 ETH_LINK_SPEED_5G | 1913 ETH_LINK_SPEED_10G | 1914 ETH_LINK_SPEED_25G | 1915 ETH_LINK_SPEED_40G | 1916 ETH_LINK_SPEED_50G | 1917 ETH_LINK_SPEED_100G; 1918 1919 /* Set Tx & Rx features available for device */ 1920 if (adapter->offloads.tso4_supported) 1921 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1922 1923 if (adapter->offloads.tx_csum_supported) 1924 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1925 DEV_TX_OFFLOAD_UDP_CKSUM | 1926 DEV_TX_OFFLOAD_TCP_CKSUM; 1927 1928 if (adapter->offloads.rx_csum_supported) 1929 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1930 DEV_RX_OFFLOAD_UDP_CKSUM | 1931 DEV_RX_OFFLOAD_TCP_CKSUM; 1932 1933 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1934 tx_feat |= DEV_TX_OFFLOAD_MULTI_SEGS; 1935 1936 /* Inform framework about available features */ 1937 dev_info->rx_offload_capa = rx_feat; 1938 if (adapter->offloads.rss_hash_supported) 1939 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH; 1940 dev_info->rx_queue_offload_capa = rx_feat; 1941 dev_info->tx_offload_capa = tx_feat; 1942 dev_info->tx_queue_offload_capa = tx_feat; 1943 1944 dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF; 1945 dev_info->hash_key_size = ENA_HASH_KEY_SIZE; 1946 1947 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1948 dev_info->max_rx_pktlen = adapter->max_mtu; 1949 dev_info->max_mac_addrs = 1; 1950 1951 dev_info->max_rx_queues = adapter->max_num_io_queues; 1952 dev_info->max_tx_queues = adapter->max_num_io_queues; 1953 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1954 1955 adapter->tx_supported_offloads = tx_feat; 1956 adapter->rx_supported_offloads = rx_feat; 1957 1958 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 1959 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1960 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1961 adapter->max_rx_sgl_size); 1962 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1963 adapter->max_rx_sgl_size); 1964 1965 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 1966 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1967 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1968 adapter->max_tx_sgl_size); 1969 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1970 adapter->max_tx_sgl_size); 1971 1972 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; 1973 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; 1974 1975 return 0; 1976 } 1977 1978 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 1979 { 1980 mbuf->data_len = len; 1981 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 1982 mbuf->refcnt = 1; 1983 mbuf->next = NULL; 1984 } 1985 1986 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 1987 struct ena_com_rx_buf_info *ena_bufs, 1988 uint32_t descs, 1989 uint16_t *next_to_clean, 1990 uint8_t offset) 1991 { 1992 struct rte_mbuf *mbuf; 1993 struct rte_mbuf *mbuf_head; 1994 struct ena_rx_buffer *rx_info; 1995 int rc; 1996 uint16_t ntc, len, req_id, buf = 0; 1997 1998 if (unlikely(descs == 0)) 1999 return NULL; 2000 2001 ntc = *next_to_clean; 2002 2003 len = ena_bufs[buf].len; 2004 req_id = ena_bufs[buf].req_id; 2005 2006 rx_info = &rx_ring->rx_buffer_info[req_id]; 2007 2008 mbuf = rx_info->mbuf; 2009 RTE_ASSERT(mbuf != NULL); 2010 2011 ena_init_rx_mbuf(mbuf, len); 2012 2013 /* Fill the mbuf head with the data specific for 1st segment. */ 2014 mbuf_head = mbuf; 2015 mbuf_head->nb_segs = descs; 2016 mbuf_head->port = rx_ring->port_id; 2017 mbuf_head->pkt_len = len; 2018 mbuf_head->data_off += offset; 2019 2020 rx_info->mbuf = NULL; 2021 rx_ring->empty_rx_reqs[ntc] = req_id; 2022 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2023 2024 while (--descs) { 2025 ++buf; 2026 len = ena_bufs[buf].len; 2027 req_id = ena_bufs[buf].req_id; 2028 2029 rx_info = &rx_ring->rx_buffer_info[req_id]; 2030 RTE_ASSERT(rx_info->mbuf != NULL); 2031 2032 if (unlikely(len == 0)) { 2033 /* 2034 * Some devices can pass descriptor with the length 0. 2035 * To avoid confusion, the PMD is simply putting the 2036 * descriptor back, as it was never used. We'll avoid 2037 * mbuf allocation that way. 2038 */ 2039 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2040 rx_info->mbuf, req_id); 2041 if (unlikely(rc != 0)) { 2042 /* Free the mbuf in case of an error. */ 2043 rte_mbuf_raw_free(rx_info->mbuf); 2044 } else { 2045 /* 2046 * If there was no error, just exit the loop as 2047 * 0 length descriptor is always the last one. 2048 */ 2049 break; 2050 } 2051 } else { 2052 /* Create an mbuf chain. */ 2053 mbuf->next = rx_info->mbuf; 2054 mbuf = mbuf->next; 2055 2056 ena_init_rx_mbuf(mbuf, len); 2057 mbuf_head->pkt_len += len; 2058 } 2059 2060 /* 2061 * Mark the descriptor as depleted and perform necessary 2062 * cleanup. 2063 * This code will execute in two cases: 2064 * 1. Descriptor len was greater than 0 - normal situation. 2065 * 2. Descriptor len was 0 and we failed to add the descriptor 2066 * to the device. In that situation, we should try to add 2067 * the mbuf again in the populate routine and mark the 2068 * descriptor as used up by the device. 2069 */ 2070 rx_info->mbuf = NULL; 2071 rx_ring->empty_rx_reqs[ntc] = req_id; 2072 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2073 } 2074 2075 *next_to_clean = ntc; 2076 2077 return mbuf_head; 2078 } 2079 2080 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2081 uint16_t nb_pkts) 2082 { 2083 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2084 unsigned int free_queue_entries; 2085 unsigned int refill_threshold; 2086 uint16_t next_to_clean = rx_ring->next_to_clean; 2087 uint16_t descs_in_use; 2088 struct rte_mbuf *mbuf; 2089 uint16_t completed; 2090 struct ena_com_rx_ctx ena_rx_ctx; 2091 int i, rc = 0; 2092 bool fill_hash; 2093 2094 #ifdef RTE_ETHDEV_DEBUG_RX 2095 /* Check adapter state */ 2096 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2097 PMD_RX_LOG(ALERT, 2098 "Trying to receive pkts while device is NOT running\n"); 2099 return 0; 2100 } 2101 #endif 2102 2103 fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH; 2104 2105 descs_in_use = rx_ring->ring_size - 2106 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2107 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2108 2109 for (completed = 0; completed < nb_pkts; completed++) { 2110 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2111 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2112 ena_rx_ctx.descs = 0; 2113 ena_rx_ctx.pkt_offset = 0; 2114 /* receive packet context */ 2115 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2116 rx_ring->ena_com_io_sq, 2117 &ena_rx_ctx); 2118 if (unlikely(rc)) { 2119 PMD_RX_LOG(ERR, 2120 "Failed to get the packet from the device, rc: %d\n", 2121 rc); 2122 if (rc == ENA_COM_NO_SPACE) { 2123 ++rx_ring->rx_stats.bad_desc_num; 2124 rx_ring->adapter->reset_reason = 2125 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2126 } else { 2127 ++rx_ring->rx_stats.bad_req_id; 2128 rx_ring->adapter->reset_reason = 2129 ENA_REGS_RESET_INV_RX_REQ_ID; 2130 } 2131 rx_ring->adapter->trigger_reset = true; 2132 return 0; 2133 } 2134 2135 mbuf = ena_rx_mbuf(rx_ring, 2136 ena_rx_ctx.ena_bufs, 2137 ena_rx_ctx.descs, 2138 &next_to_clean, 2139 ena_rx_ctx.pkt_offset); 2140 if (unlikely(mbuf == NULL)) { 2141 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2142 rx_ring->empty_rx_reqs[next_to_clean] = 2143 rx_ring->ena_bufs[i].req_id; 2144 next_to_clean = ENA_IDX_NEXT_MASKED( 2145 next_to_clean, rx_ring->size_mask); 2146 } 2147 break; 2148 } 2149 2150 /* fill mbuf attributes if any */ 2151 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash); 2152 2153 if (unlikely(mbuf->ol_flags & 2154 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2155 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2156 ++rx_ring->rx_stats.bad_csum; 2157 } 2158 2159 rx_pkts[completed] = mbuf; 2160 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2161 } 2162 2163 rx_ring->rx_stats.cnt += completed; 2164 rx_ring->next_to_clean = next_to_clean; 2165 2166 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2167 refill_threshold = 2168 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2169 (unsigned int)ENA_REFILL_THRESH_PACKET); 2170 2171 /* Burst refill to save doorbells, memory barriers, const interval */ 2172 if (free_queue_entries > refill_threshold) { 2173 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2174 ena_populate_rx_queue(rx_ring, free_queue_entries); 2175 } 2176 2177 return completed; 2178 } 2179 2180 static uint16_t 2181 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2182 uint16_t nb_pkts) 2183 { 2184 int32_t ret; 2185 uint32_t i; 2186 struct rte_mbuf *m; 2187 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2188 struct rte_ipv4_hdr *ip_hdr; 2189 uint64_t ol_flags; 2190 uint16_t frag_field; 2191 2192 for (i = 0; i != nb_pkts; i++) { 2193 m = tx_pkts[i]; 2194 ol_flags = m->ol_flags; 2195 2196 if (!(ol_flags & PKT_TX_IPV4)) 2197 continue; 2198 2199 /* If there was not L2 header length specified, assume it is 2200 * length of the ethernet header. 2201 */ 2202 if (unlikely(m->l2_len == 0)) 2203 m->l2_len = sizeof(struct rte_ether_hdr); 2204 2205 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2206 m->l2_len); 2207 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2208 2209 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2210 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2211 2212 /* If IPv4 header has DF flag enabled and TSO support is 2213 * disabled, partial chcecksum should not be calculated. 2214 */ 2215 if (!tx_ring->adapter->offloads.tso4_supported) 2216 continue; 2217 } 2218 2219 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2220 (ol_flags & PKT_TX_L4_MASK) == 2221 PKT_TX_SCTP_CKSUM) { 2222 rte_errno = ENOTSUP; 2223 return i; 2224 } 2225 2226 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2227 ret = rte_validate_tx_offload(m); 2228 if (ret != 0) { 2229 rte_errno = -ret; 2230 return i; 2231 } 2232 #endif 2233 2234 /* In case we are supposed to TSO and have DF not set (DF=0) 2235 * hardware must be provided with partial checksum, otherwise 2236 * it will take care of necessary calculations. 2237 */ 2238 2239 ret = rte_net_intel_cksum_flags_prepare(m, 2240 ol_flags & ~PKT_TX_TCP_SEG); 2241 if (ret != 0) { 2242 rte_errno = -ret; 2243 return i; 2244 } 2245 } 2246 2247 return i; 2248 } 2249 2250 static void ena_update_hints(struct ena_adapter *adapter, 2251 struct ena_admin_ena_hw_hints *hints) 2252 { 2253 if (hints->admin_completion_tx_timeout) 2254 adapter->ena_dev.admin_queue.completion_timeout = 2255 hints->admin_completion_tx_timeout * 1000; 2256 2257 if (hints->mmio_read_timeout) 2258 /* convert to usec */ 2259 adapter->ena_dev.mmio_read.reg_read_to = 2260 hints->mmio_read_timeout * 1000; 2261 2262 if (hints->driver_watchdog_timeout) { 2263 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2264 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2265 else 2266 // Convert msecs to ticks 2267 adapter->keep_alive_timeout = 2268 (hints->driver_watchdog_timeout * 2269 rte_get_timer_hz()) / 1000; 2270 } 2271 } 2272 2273 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring, 2274 struct rte_mbuf *mbuf) 2275 { 2276 struct ena_com_dev *ena_dev; 2277 int num_segments, header_len, rc; 2278 2279 ena_dev = &tx_ring->adapter->ena_dev; 2280 num_segments = mbuf->nb_segs; 2281 header_len = mbuf->data_len; 2282 2283 if (likely(num_segments < tx_ring->sgl_size)) 2284 goto checkspace; 2285 2286 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2287 (num_segments == tx_ring->sgl_size) && 2288 (header_len < tx_ring->tx_max_header_size)) 2289 goto checkspace; 2290 2291 /* Checking for space for 2 additional metadata descriptors due to 2292 * possible header split and metadata descriptor. Linearization will 2293 * be needed so we reduce the segments number from num_segments to 1 2294 */ 2295 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) { 2296 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n"); 2297 return ENA_COM_NO_MEM; 2298 } 2299 ++tx_ring->tx_stats.linearize; 2300 rc = rte_pktmbuf_linearize(mbuf); 2301 if (unlikely(rc)) { 2302 PMD_TX_LOG(WARNING, "Mbuf linearize failed\n"); 2303 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2304 ++tx_ring->tx_stats.linearize_failed; 2305 return rc; 2306 } 2307 2308 return 0; 2309 2310 checkspace: 2311 /* Checking for space for 2 additional metadata descriptors due to 2312 * possible header split and metadata descriptor 2313 */ 2314 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 2315 num_segments + 2)) { 2316 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n"); 2317 return ENA_COM_NO_MEM; 2318 } 2319 2320 return 0; 2321 } 2322 2323 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2324 struct ena_tx_buffer *tx_info, 2325 struct rte_mbuf *mbuf, 2326 void **push_header, 2327 uint16_t *header_len) 2328 { 2329 struct ena_com_buf *ena_buf; 2330 uint16_t delta, seg_len, push_len; 2331 2332 delta = 0; 2333 seg_len = mbuf->data_len; 2334 2335 tx_info->mbuf = mbuf; 2336 ena_buf = tx_info->bufs; 2337 2338 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2339 /* 2340 * Tx header might be (and will be in most cases) smaller than 2341 * tx_max_header_size. But it's not an issue to send more data 2342 * to the device, than actually needed if the mbuf size is 2343 * greater than tx_max_header_size. 2344 */ 2345 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2346 *header_len = push_len; 2347 2348 if (likely(push_len <= seg_len)) { 2349 /* If the push header is in the single segment, then 2350 * just point it to the 1st mbuf data. 2351 */ 2352 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2353 } else { 2354 /* If the push header lays in the several segments, copy 2355 * it to the intermediate buffer. 2356 */ 2357 rte_pktmbuf_read(mbuf, 0, push_len, 2358 tx_ring->push_buf_intermediate_buf); 2359 *push_header = tx_ring->push_buf_intermediate_buf; 2360 delta = push_len - seg_len; 2361 } 2362 } else { 2363 *push_header = NULL; 2364 *header_len = 0; 2365 push_len = 0; 2366 } 2367 2368 /* Process first segment taking into consideration pushed header */ 2369 if (seg_len > push_len) { 2370 ena_buf->paddr = mbuf->buf_iova + 2371 mbuf->data_off + 2372 push_len; 2373 ena_buf->len = seg_len - push_len; 2374 ena_buf++; 2375 tx_info->num_of_bufs++; 2376 } 2377 2378 while ((mbuf = mbuf->next) != NULL) { 2379 seg_len = mbuf->data_len; 2380 2381 /* Skip mbufs if whole data is pushed as a header */ 2382 if (unlikely(delta > seg_len)) { 2383 delta -= seg_len; 2384 continue; 2385 } 2386 2387 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2388 ena_buf->len = seg_len - delta; 2389 ena_buf++; 2390 tx_info->num_of_bufs++; 2391 2392 delta = 0; 2393 } 2394 } 2395 2396 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 2397 { 2398 struct ena_tx_buffer *tx_info; 2399 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 2400 uint16_t next_to_use; 2401 uint16_t header_len; 2402 uint16_t req_id; 2403 void *push_header; 2404 int nb_hw_desc; 2405 int rc; 2406 2407 rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf); 2408 if (unlikely(rc)) 2409 return rc; 2410 2411 next_to_use = tx_ring->next_to_use; 2412 2413 req_id = tx_ring->empty_tx_reqs[next_to_use]; 2414 tx_info = &tx_ring->tx_buffer_info[req_id]; 2415 tx_info->num_of_bufs = 0; 2416 2417 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 2418 2419 ena_tx_ctx.ena_bufs = tx_info->bufs; 2420 ena_tx_ctx.push_header = push_header; 2421 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2422 ena_tx_ctx.req_id = req_id; 2423 ena_tx_ctx.header_len = header_len; 2424 2425 /* Set Tx offloads flags, if applicable */ 2426 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 2427 tx_ring->disable_meta_caching); 2428 2429 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2430 &ena_tx_ctx))) { 2431 PMD_TX_LOG(DEBUG, 2432 "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2433 tx_ring->id); 2434 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2435 tx_ring->tx_stats.doorbells++; 2436 tx_ring->pkts_without_db = false; 2437 } 2438 2439 /* prepare the packet's descriptors to dma engine */ 2440 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2441 &nb_hw_desc); 2442 if (unlikely(rc)) { 2443 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc); 2444 ++tx_ring->tx_stats.prepare_ctx_err; 2445 tx_ring->adapter->reset_reason = 2446 ENA_REGS_RESET_DRIVER_INVALID_STATE; 2447 tx_ring->adapter->trigger_reset = true; 2448 return rc; 2449 } 2450 2451 tx_info->tx_descs = nb_hw_desc; 2452 2453 tx_ring->tx_stats.cnt++; 2454 tx_ring->tx_stats.bytes += mbuf->pkt_len; 2455 2456 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 2457 tx_ring->size_mask); 2458 2459 return 0; 2460 } 2461 2462 static void ena_tx_cleanup(struct ena_ring *tx_ring) 2463 { 2464 unsigned int cleanup_budget; 2465 unsigned int total_tx_descs = 0; 2466 uint16_t next_to_clean = tx_ring->next_to_clean; 2467 2468 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2469 (unsigned int)ENA_REFILL_THRESH_PACKET); 2470 2471 while (likely(total_tx_descs < cleanup_budget)) { 2472 struct rte_mbuf *mbuf; 2473 struct ena_tx_buffer *tx_info; 2474 uint16_t req_id; 2475 2476 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 2477 break; 2478 2479 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 2480 break; 2481 2482 /* Get Tx info & store how many descs were processed */ 2483 tx_info = &tx_ring->tx_buffer_info[req_id]; 2484 2485 mbuf = tx_info->mbuf; 2486 rte_pktmbuf_free(mbuf); 2487 2488 tx_info->mbuf = NULL; 2489 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 2490 2491 total_tx_descs += tx_info->tx_descs; 2492 2493 /* Put back descriptor to the ring for reuse */ 2494 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 2495 tx_ring->size_mask); 2496 } 2497 2498 if (likely(total_tx_descs > 0)) { 2499 /* acknowledge completion of sent packets */ 2500 tx_ring->next_to_clean = next_to_clean; 2501 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2502 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2503 } 2504 } 2505 2506 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2507 uint16_t nb_pkts) 2508 { 2509 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2510 uint16_t sent_idx = 0; 2511 2512 #ifdef RTE_ETHDEV_DEBUG_TX 2513 /* Check adapter state */ 2514 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2515 PMD_TX_LOG(ALERT, 2516 "Trying to xmit pkts while device is NOT running\n"); 2517 return 0; 2518 } 2519 #endif 2520 2521 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2522 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 2523 break; 2524 tx_ring->pkts_without_db = true; 2525 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 2526 tx_ring->size_mask)]); 2527 } 2528 2529 tx_ring->tx_stats.available_desc = 2530 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2531 2532 /* If there are ready packets to be xmitted... */ 2533 if (likely(tx_ring->pkts_without_db)) { 2534 /* ...let HW do its best :-) */ 2535 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2536 tx_ring->tx_stats.doorbells++; 2537 tx_ring->pkts_without_db = false; 2538 } 2539 2540 ena_tx_cleanup(tx_ring); 2541 2542 tx_ring->tx_stats.available_desc = 2543 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2544 tx_ring->tx_stats.tx_poll++; 2545 2546 return sent_idx; 2547 } 2548 2549 int ena_copy_eni_stats(struct ena_adapter *adapter) 2550 { 2551 struct ena_admin_eni_stats admin_eni_stats; 2552 int rc; 2553 2554 rte_spinlock_lock(&adapter->admin_lock); 2555 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats); 2556 rte_spinlock_unlock(&adapter->admin_lock); 2557 if (rc != 0) { 2558 if (rc == ENA_COM_UNSUPPORTED) { 2559 PMD_DRV_LOG(DEBUG, 2560 "Retrieving ENI metrics is not supported\n"); 2561 } else { 2562 PMD_DRV_LOG(WARNING, 2563 "Failed to get ENI metrics, rc: %d\n", rc); 2564 } 2565 return rc; 2566 } 2567 2568 rte_memcpy(&adapter->eni_stats, &admin_eni_stats, 2569 sizeof(struct ena_stats_eni)); 2570 2571 return 0; 2572 } 2573 2574 /** 2575 * DPDK callback to retrieve names of extended device statistics 2576 * 2577 * @param dev 2578 * Pointer to Ethernet device structure. 2579 * @param[out] xstats_names 2580 * Buffer to insert names into. 2581 * @param n 2582 * Number of names. 2583 * 2584 * @return 2585 * Number of xstats names. 2586 */ 2587 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2588 struct rte_eth_xstat_name *xstats_names, 2589 unsigned int n) 2590 { 2591 unsigned int xstats_count = ena_xstats_calc_num(dev->data); 2592 unsigned int stat, i, count = 0; 2593 2594 if (n < xstats_count || !xstats_names) 2595 return xstats_count; 2596 2597 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2598 strcpy(xstats_names[count].name, 2599 ena_stats_global_strings[stat].name); 2600 2601 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) 2602 strcpy(xstats_names[count].name, 2603 ena_stats_eni_strings[stat].name); 2604 2605 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2606 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2607 snprintf(xstats_names[count].name, 2608 sizeof(xstats_names[count].name), 2609 "rx_q%d_%s", i, 2610 ena_stats_rx_strings[stat].name); 2611 2612 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2613 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2614 snprintf(xstats_names[count].name, 2615 sizeof(xstats_names[count].name), 2616 "tx_q%d_%s", i, 2617 ena_stats_tx_strings[stat].name); 2618 2619 return xstats_count; 2620 } 2621 2622 /** 2623 * DPDK callback to get extended device statistics. 2624 * 2625 * @param dev 2626 * Pointer to Ethernet device structure. 2627 * @param[out] stats 2628 * Stats table output buffer. 2629 * @param n 2630 * The size of the stats table. 2631 * 2632 * @return 2633 * Number of xstats on success, negative on failure. 2634 */ 2635 static int ena_xstats_get(struct rte_eth_dev *dev, 2636 struct rte_eth_xstat *xstats, 2637 unsigned int n) 2638 { 2639 struct ena_adapter *adapter = dev->data->dev_private; 2640 unsigned int xstats_count = ena_xstats_calc_num(dev->data); 2641 unsigned int stat, i, count = 0; 2642 int stat_offset; 2643 void *stats_begin; 2644 2645 if (n < xstats_count) 2646 return xstats_count; 2647 2648 if (!xstats) 2649 return 0; 2650 2651 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2652 stat_offset = ena_stats_global_strings[stat].stat_offset; 2653 stats_begin = &adapter->dev_stats; 2654 2655 xstats[count].id = count; 2656 xstats[count].value = *((uint64_t *) 2657 ((char *)stats_begin + stat_offset)); 2658 } 2659 2660 /* Even if the function below fails, we should copy previous (or initial 2661 * values) to keep structure of rte_eth_xstat consistent. 2662 */ 2663 ena_copy_eni_stats(adapter); 2664 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) { 2665 stat_offset = ena_stats_eni_strings[stat].stat_offset; 2666 stats_begin = &adapter->eni_stats; 2667 2668 xstats[count].id = count; 2669 xstats[count].value = *((uint64_t *) 2670 ((char *)stats_begin + stat_offset)); 2671 } 2672 2673 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2674 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2675 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2676 stats_begin = &adapter->rx_ring[i].rx_stats; 2677 2678 xstats[count].id = count; 2679 xstats[count].value = *((uint64_t *) 2680 ((char *)stats_begin + stat_offset)); 2681 } 2682 } 2683 2684 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2685 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2686 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2687 stats_begin = &adapter->tx_ring[i].rx_stats; 2688 2689 xstats[count].id = count; 2690 xstats[count].value = *((uint64_t *) 2691 ((char *)stats_begin + stat_offset)); 2692 } 2693 } 2694 2695 return count; 2696 } 2697 2698 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2699 const uint64_t *ids, 2700 uint64_t *values, 2701 unsigned int n) 2702 { 2703 struct ena_adapter *adapter = dev->data->dev_private; 2704 uint64_t id; 2705 uint64_t rx_entries, tx_entries; 2706 unsigned int i; 2707 int qid; 2708 int valid = 0; 2709 bool was_eni_copied = false; 2710 2711 for (i = 0; i < n; ++i) { 2712 id = ids[i]; 2713 /* Check if id belongs to global statistics */ 2714 if (id < ENA_STATS_ARRAY_GLOBAL) { 2715 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2716 ++valid; 2717 continue; 2718 } 2719 2720 /* Check if id belongs to ENI statistics */ 2721 id -= ENA_STATS_ARRAY_GLOBAL; 2722 if (id < ENA_STATS_ARRAY_ENI) { 2723 /* Avoid reading ENI stats multiple times in a single 2724 * function call, as it requires communication with the 2725 * admin queue. 2726 */ 2727 if (!was_eni_copied) { 2728 was_eni_copied = true; 2729 ena_copy_eni_stats(adapter); 2730 } 2731 values[i] = *((uint64_t *)&adapter->eni_stats + id); 2732 ++valid; 2733 continue; 2734 } 2735 2736 /* Check if id belongs to rx queue statistics */ 2737 id -= ENA_STATS_ARRAY_ENI; 2738 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2739 if (id < rx_entries) { 2740 qid = id % dev->data->nb_rx_queues; 2741 id /= dev->data->nb_rx_queues; 2742 values[i] = *((uint64_t *) 2743 &adapter->rx_ring[qid].rx_stats + id); 2744 ++valid; 2745 continue; 2746 } 2747 /* Check if id belongs to rx queue statistics */ 2748 id -= rx_entries; 2749 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2750 if (id < tx_entries) { 2751 qid = id % dev->data->nb_tx_queues; 2752 id /= dev->data->nb_tx_queues; 2753 values[i] = *((uint64_t *) 2754 &adapter->tx_ring[qid].tx_stats + id); 2755 ++valid; 2756 continue; 2757 } 2758 } 2759 2760 return valid; 2761 } 2762 2763 static int ena_process_bool_devarg(const char *key, 2764 const char *value, 2765 void *opaque) 2766 { 2767 struct ena_adapter *adapter = opaque; 2768 bool bool_value; 2769 2770 /* Parse the value. */ 2771 if (strcmp(value, "1") == 0) { 2772 bool_value = true; 2773 } else if (strcmp(value, "0") == 0) { 2774 bool_value = false; 2775 } else { 2776 PMD_INIT_LOG(ERR, 2777 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2778 value, key); 2779 return -EINVAL; 2780 } 2781 2782 /* Now, assign it to the proper adapter field. */ 2783 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) 2784 adapter->use_large_llq_hdr = bool_value; 2785 2786 return 0; 2787 } 2788 2789 static int ena_parse_devargs(struct ena_adapter *adapter, 2790 struct rte_devargs *devargs) 2791 { 2792 static const char * const allowed_args[] = { 2793 ENA_DEVARG_LARGE_LLQ_HDR, 2794 NULL, 2795 }; 2796 struct rte_kvargs *kvlist; 2797 int rc; 2798 2799 if (devargs == NULL) 2800 return 0; 2801 2802 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2803 if (kvlist == NULL) { 2804 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2805 devargs->args); 2806 return -EINVAL; 2807 } 2808 2809 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2810 ena_process_bool_devarg, adapter); 2811 2812 rte_kvargs_free(kvlist); 2813 2814 return rc; 2815 } 2816 2817 static int ena_setup_rx_intr(struct rte_eth_dev *dev) 2818 { 2819 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2820 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2821 int rc; 2822 uint16_t vectors_nb, i; 2823 bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq; 2824 2825 if (!rx_intr_requested) 2826 return 0; 2827 2828 if (!rte_intr_cap_multiple(intr_handle)) { 2829 PMD_DRV_LOG(ERR, 2830 "Rx interrupt requested, but it isn't supported by the PCI driver\n"); 2831 return -ENOTSUP; 2832 } 2833 2834 /* Disable interrupt mapping before the configuration starts. */ 2835 rte_intr_disable(intr_handle); 2836 2837 /* Verify if there are enough vectors available. */ 2838 vectors_nb = dev->data->nb_rx_queues; 2839 if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) { 2840 PMD_DRV_LOG(ERR, 2841 "Too many Rx interrupts requested, maximum number: %d\n", 2842 RTE_MAX_RXTX_INTR_VEC_ID); 2843 rc = -ENOTSUP; 2844 goto enable_intr; 2845 } 2846 2847 intr_handle->intr_vec = rte_zmalloc("intr_vec", 2848 dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0); 2849 if (intr_handle->intr_vec == NULL) { 2850 PMD_DRV_LOG(ERR, 2851 "Failed to allocate interrupt vector for %d queues\n", 2852 dev->data->nb_rx_queues); 2853 rc = -ENOMEM; 2854 goto enable_intr; 2855 } 2856 2857 rc = rte_intr_efd_enable(intr_handle, vectors_nb); 2858 if (rc != 0) 2859 goto free_intr_vec; 2860 2861 if (!rte_intr_allow_others(intr_handle)) { 2862 PMD_DRV_LOG(ERR, 2863 "Not enough interrupts available to use both ENA Admin and Rx interrupts\n"); 2864 goto disable_intr_efd; 2865 } 2866 2867 for (i = 0; i < vectors_nb; ++i) 2868 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i; 2869 2870 rte_intr_enable(intr_handle); 2871 return 0; 2872 2873 disable_intr_efd: 2874 rte_intr_efd_disable(intr_handle); 2875 free_intr_vec: 2876 rte_free(intr_handle->intr_vec); 2877 intr_handle->intr_vec = NULL; 2878 enable_intr: 2879 rte_intr_enable(intr_handle); 2880 return rc; 2881 } 2882 2883 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev, 2884 uint16_t queue_id, 2885 bool unmask) 2886 { 2887 struct ena_adapter *adapter = dev->data->dev_private; 2888 struct ena_ring *rxq = &adapter->rx_ring[queue_id]; 2889 struct ena_eth_io_intr_reg intr_reg; 2890 2891 ena_com_update_intr_reg(&intr_reg, 0, 0, unmask); 2892 ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg); 2893 } 2894 2895 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev, 2896 uint16_t queue_id) 2897 { 2898 ena_rx_queue_intr_set(dev, queue_id, true); 2899 2900 return 0; 2901 } 2902 2903 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, 2904 uint16_t queue_id) 2905 { 2906 ena_rx_queue_intr_set(dev, queue_id, false); 2907 2908 return 0; 2909 } 2910 2911 /********************************************************************* 2912 * PMD configuration 2913 *********************************************************************/ 2914 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2915 struct rte_pci_device *pci_dev) 2916 { 2917 return rte_eth_dev_pci_generic_probe(pci_dev, 2918 sizeof(struct ena_adapter), eth_ena_dev_init); 2919 } 2920 2921 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2922 { 2923 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2924 } 2925 2926 static struct rte_pci_driver rte_ena_pmd = { 2927 .id_table = pci_id_ena_map, 2928 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2929 RTE_PCI_DRV_WC_ACTIVATE, 2930 .probe = eth_ena_pci_probe, 2931 .remove = eth_ena_pci_remove, 2932 }; 2933 2934 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2935 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2936 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2937 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2938 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); 2939 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE); 2940 #ifdef RTE_ETHDEV_DEBUG_RX 2941 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG); 2942 #endif 2943 #ifdef RTE_ETHDEV_DEBUG_TX 2944 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG); 2945 #endif 2946 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING); 2947 2948 /****************************************************************************** 2949 ******************************** AENQ Handlers ******************************* 2950 *****************************************************************************/ 2951 static void ena_update_on_link_change(void *adapter_data, 2952 struct ena_admin_aenq_entry *aenq_e) 2953 { 2954 struct rte_eth_dev *eth_dev = adapter_data; 2955 struct ena_adapter *adapter = eth_dev->data->dev_private; 2956 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2957 uint32_t status; 2958 2959 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2960 2961 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2962 adapter->link_status = status; 2963 2964 ena_link_update(eth_dev, 0); 2965 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2966 } 2967 2968 static void ena_notification(void *adapter_data, 2969 struct ena_admin_aenq_entry *aenq_e) 2970 { 2971 struct rte_eth_dev *eth_dev = adapter_data; 2972 struct ena_adapter *adapter = eth_dev->data->dev_private; 2973 struct ena_admin_ena_hw_hints *hints; 2974 2975 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2976 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n", 2977 aenq_e->aenq_common_desc.group, 2978 ENA_ADMIN_NOTIFICATION); 2979 2980 switch (aenq_e->aenq_common_desc.syndrome) { 2981 case ENA_ADMIN_UPDATE_HINTS: 2982 hints = (struct ena_admin_ena_hw_hints *) 2983 (&aenq_e->inline_data_w4); 2984 ena_update_hints(adapter, hints); 2985 break; 2986 default: 2987 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n", 2988 aenq_e->aenq_common_desc.syndrome); 2989 } 2990 } 2991 2992 static void ena_keep_alive(void *adapter_data, 2993 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2994 { 2995 struct rte_eth_dev *eth_dev = adapter_data; 2996 struct ena_adapter *adapter = eth_dev->data->dev_private; 2997 struct ena_admin_aenq_keep_alive_desc *desc; 2998 uint64_t rx_drops; 2999 uint64_t tx_drops; 3000 3001 adapter->timestamp_wd = rte_get_timer_cycles(); 3002 3003 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3004 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3005 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 3006 3007 adapter->drv_stats->rx_drops = rx_drops; 3008 adapter->dev_stats.tx_drops = tx_drops; 3009 } 3010 3011 /** 3012 * This handler will called for unknown event group or unimplemented handlers 3013 **/ 3014 static void unimplemented_aenq_handler(__rte_unused void *data, 3015 __rte_unused struct ena_admin_aenq_entry *aenq_e) 3016 { 3017 PMD_DRV_LOG(ERR, 3018 "Unknown event was received or event with unimplemented handler\n"); 3019 } 3020 3021 static struct ena_aenq_handlers aenq_handlers = { 3022 .handlers = { 3023 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3024 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3025 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 3026 }, 3027 .unimplemented_handler = unimplemented_aenq_handler 3028 }; 3029