1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_ether.h> 35 #include <rte_ethdev_driver.h> 36 #include <rte_ethdev_pci.h> 37 #include <rte_tcp.h> 38 #include <rte_atomic.h> 39 #include <rte_dev.h> 40 #include <rte_errno.h> 41 #include <rte_version.h> 42 #include <rte_eal_memconfig.h> 43 #include <rte_net.h> 44 45 #include "ena_ethdev.h" 46 #include "ena_logs.h" 47 #include "ena_platform.h" 48 #include "ena_com.h" 49 #include "ena_eth_com.h" 50 51 #include <ena_common_defs.h> 52 #include <ena_regs_defs.h> 53 #include <ena_admin_defs.h> 54 #include <ena_eth_io_defs.h> 55 56 #define DRV_MODULE_VER_MAJOR 2 57 #define DRV_MODULE_VER_MINOR 0 58 #define DRV_MODULE_VER_SUBMINOR 0 59 60 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 62 /*reverse version of ENA_IO_RXQ_IDX*/ 63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 64 65 /* While processing submitted and completed descriptors (rx and tx path 66 * respectively) in a loop it is desired to: 67 * - perform batch submissions while populating sumbissmion queue 68 * - avoid blocking transmission of other packets during cleanup phase 69 * Hence the utilization ratio of 1/8 of a queue size. 70 */ 71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 72 73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 75 76 #define GET_L4_HDR_LEN(mbuf) \ 77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \ 78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 79 80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 82 #define ENA_HASH_KEY_SIZE 40 83 #define ETH_GSTRING_LEN 32 84 85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 86 87 #define ENA_MIN_RING_DESC 128 88 89 enum ethtool_stringset { 90 ETH_SS_TEST = 0, 91 ETH_SS_STATS, 92 }; 93 94 struct ena_stats { 95 char name[ETH_GSTRING_LEN]; 96 int stat_offset; 97 }; 98 99 #define ENA_STAT_ENTRY(stat, stat_type) { \ 100 .name = #stat, \ 101 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 102 } 103 104 #define ENA_STAT_RX_ENTRY(stat) \ 105 ENA_STAT_ENTRY(stat, rx) 106 107 #define ENA_STAT_TX_ENTRY(stat) \ 108 ENA_STAT_ENTRY(stat, tx) 109 110 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 111 ENA_STAT_ENTRY(stat, dev) 112 113 #define ENA_MAX_RING_SIZE_RX 8192 114 #define ENA_MAX_RING_SIZE_TX 1024 115 116 /* 117 * Each rte_memzone should have unique name. 118 * To satisfy it, count number of allocation and add it to name. 119 */ 120 uint32_t ena_alloc_cnt; 121 122 static const struct ena_stats ena_stats_global_strings[] = { 123 ENA_STAT_GLOBAL_ENTRY(wd_expired), 124 ENA_STAT_GLOBAL_ENTRY(dev_start), 125 ENA_STAT_GLOBAL_ENTRY(dev_stop), 126 }; 127 128 static const struct ena_stats ena_stats_tx_strings[] = { 129 ENA_STAT_TX_ENTRY(cnt), 130 ENA_STAT_TX_ENTRY(bytes), 131 ENA_STAT_TX_ENTRY(prepare_ctx_err), 132 ENA_STAT_TX_ENTRY(linearize), 133 ENA_STAT_TX_ENTRY(linearize_failed), 134 ENA_STAT_TX_ENTRY(tx_poll), 135 ENA_STAT_TX_ENTRY(doorbells), 136 ENA_STAT_TX_ENTRY(bad_req_id), 137 ENA_STAT_TX_ENTRY(available_desc), 138 }; 139 140 static const struct ena_stats ena_stats_rx_strings[] = { 141 ENA_STAT_RX_ENTRY(cnt), 142 ENA_STAT_RX_ENTRY(bytes), 143 ENA_STAT_RX_ENTRY(refill_partial), 144 ENA_STAT_RX_ENTRY(bad_csum), 145 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 146 ENA_STAT_RX_ENTRY(bad_desc_num), 147 ENA_STAT_RX_ENTRY(bad_req_id), 148 }; 149 150 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 151 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 152 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 153 154 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 155 DEV_TX_OFFLOAD_UDP_CKSUM |\ 156 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 157 DEV_TX_OFFLOAD_TCP_TSO) 158 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 159 PKT_TX_IP_CKSUM |\ 160 PKT_TX_TCP_SEG) 161 162 /** Vendor ID used by Amazon devices */ 163 #define PCI_VENDOR_ID_AMAZON 0x1D0F 164 /** Amazon devices */ 165 #define PCI_DEVICE_ID_ENA_VF 0xEC20 166 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 167 168 #define ENA_TX_OFFLOAD_MASK (\ 169 PKT_TX_L4_MASK | \ 170 PKT_TX_IPV6 | \ 171 PKT_TX_IPV4 | \ 172 PKT_TX_IP_CKSUM | \ 173 PKT_TX_TCP_SEG) 174 175 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 176 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 177 178 int ena_logtype_init; 179 int ena_logtype_driver; 180 181 static const struct rte_pci_id pci_id_ena_map[] = { 182 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 183 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 184 { .device_id = 0 }, 185 }; 186 187 static struct ena_aenq_handlers aenq_handlers; 188 189 static int ena_device_init(struct ena_com_dev *ena_dev, 190 struct ena_com_dev_get_features_ctx *get_feat_ctx, 191 bool *wd_state); 192 static int ena_dev_configure(struct rte_eth_dev *dev); 193 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 194 uint16_t nb_pkts); 195 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 196 uint16_t nb_pkts); 197 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 198 uint16_t nb_desc, unsigned int socket_id, 199 const struct rte_eth_txconf *tx_conf); 200 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 201 uint16_t nb_desc, unsigned int socket_id, 202 const struct rte_eth_rxconf *rx_conf, 203 struct rte_mempool *mp); 204 static uint16_t eth_ena_recv_pkts(void *rx_queue, 205 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 206 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 207 static void ena_init_rings(struct ena_adapter *adapter); 208 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 209 static int ena_start(struct rte_eth_dev *dev); 210 static void ena_stop(struct rte_eth_dev *dev); 211 static void ena_close(struct rte_eth_dev *dev); 212 static int ena_dev_reset(struct rte_eth_dev *dev); 213 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 214 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 215 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 216 static void ena_rx_queue_release(void *queue); 217 static void ena_tx_queue_release(void *queue); 218 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 219 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 220 static int ena_link_update(struct rte_eth_dev *dev, 221 int wait_to_complete); 222 static int ena_create_io_queue(struct ena_ring *ring); 223 static void ena_queue_stop(struct ena_ring *ring); 224 static void ena_queue_stop_all(struct rte_eth_dev *dev, 225 enum ena_ring_type ring_type); 226 static int ena_queue_start(struct ena_ring *ring); 227 static int ena_queue_start_all(struct rte_eth_dev *dev, 228 enum ena_ring_type ring_type); 229 static void ena_stats_restart(struct rte_eth_dev *dev); 230 static void ena_infos_get(struct rte_eth_dev *dev, 231 struct rte_eth_dev_info *dev_info); 232 static int ena_rss_reta_update(struct rte_eth_dev *dev, 233 struct rte_eth_rss_reta_entry64 *reta_conf, 234 uint16_t reta_size); 235 static int ena_rss_reta_query(struct rte_eth_dev *dev, 236 struct rte_eth_rss_reta_entry64 *reta_conf, 237 uint16_t reta_size); 238 static void ena_interrupt_handler_rte(void *cb_arg); 239 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 240 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 241 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 242 static int ena_xstats_get_names(struct rte_eth_dev *dev, 243 struct rte_eth_xstat_name *xstats_names, 244 unsigned int n); 245 static int ena_xstats_get(struct rte_eth_dev *dev, 246 struct rte_eth_xstat *stats, 247 unsigned int n); 248 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 249 const uint64_t *ids, 250 uint64_t *values, 251 unsigned int n); 252 253 static const struct eth_dev_ops ena_dev_ops = { 254 .dev_configure = ena_dev_configure, 255 .dev_infos_get = ena_infos_get, 256 .rx_queue_setup = ena_rx_queue_setup, 257 .tx_queue_setup = ena_tx_queue_setup, 258 .dev_start = ena_start, 259 .dev_stop = ena_stop, 260 .link_update = ena_link_update, 261 .stats_get = ena_stats_get, 262 .xstats_get_names = ena_xstats_get_names, 263 .xstats_get = ena_xstats_get, 264 .xstats_get_by_id = ena_xstats_get_by_id, 265 .mtu_set = ena_mtu_set, 266 .rx_queue_release = ena_rx_queue_release, 267 .tx_queue_release = ena_tx_queue_release, 268 .dev_close = ena_close, 269 .dev_reset = ena_dev_reset, 270 .reta_update = ena_rss_reta_update, 271 .reta_query = ena_rss_reta_query, 272 }; 273 274 #define NUMA_NO_NODE SOCKET_ID_ANY 275 276 static inline int ena_cpu_to_node(int cpu) 277 { 278 struct rte_config *config = rte_eal_get_configuration(); 279 struct rte_fbarray *arr = &config->mem_config->memzones; 280 const struct rte_memzone *mz; 281 282 if (unlikely(cpu >= RTE_MAX_MEMZONE)) 283 return NUMA_NO_NODE; 284 285 mz = rte_fbarray_get(arr, cpu); 286 287 return mz->socket_id; 288 } 289 290 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 291 struct ena_com_rx_ctx *ena_rx_ctx) 292 { 293 uint64_t ol_flags = 0; 294 uint32_t packet_type = 0; 295 296 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 297 packet_type |= RTE_PTYPE_L4_TCP; 298 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 299 packet_type |= RTE_PTYPE_L4_UDP; 300 301 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 302 packet_type |= RTE_PTYPE_L3_IPV4; 303 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 304 packet_type |= RTE_PTYPE_L3_IPV6; 305 306 if (unlikely(ena_rx_ctx->l4_csum_err)) 307 ol_flags |= PKT_RX_L4_CKSUM_BAD; 308 if (unlikely(ena_rx_ctx->l3_csum_err)) 309 ol_flags |= PKT_RX_IP_CKSUM_BAD; 310 311 mbuf->ol_flags = ol_flags; 312 mbuf->packet_type = packet_type; 313 } 314 315 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 316 struct ena_com_tx_ctx *ena_tx_ctx, 317 uint64_t queue_offloads) 318 { 319 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 320 321 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 322 (queue_offloads & QUEUE_OFFLOADS)) { 323 /* check if TSO is required */ 324 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 325 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 326 ena_tx_ctx->tso_enable = true; 327 328 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 329 } 330 331 /* check if L3 checksum is needed */ 332 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 333 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 334 ena_tx_ctx->l3_csum_enable = true; 335 336 if (mbuf->ol_flags & PKT_TX_IPV6) { 337 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 338 } else { 339 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 340 341 /* set don't fragment (DF) flag */ 342 if (mbuf->packet_type & 343 (RTE_PTYPE_L4_NONFRAG 344 | RTE_PTYPE_INNER_L4_NONFRAG)) 345 ena_tx_ctx->df = true; 346 } 347 348 /* check if L4 checksum is needed */ 349 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) && 350 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 351 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 352 ena_tx_ctx->l4_csum_enable = true; 353 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) && 354 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 355 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 356 ena_tx_ctx->l4_csum_enable = true; 357 } else { 358 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 359 ena_tx_ctx->l4_csum_enable = false; 360 } 361 362 ena_meta->mss = mbuf->tso_segsz; 363 ena_meta->l3_hdr_len = mbuf->l3_len; 364 ena_meta->l3_hdr_offset = mbuf->l2_len; 365 366 ena_tx_ctx->meta_valid = true; 367 } else { 368 ena_tx_ctx->meta_valid = false; 369 } 370 } 371 372 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 373 { 374 if (likely(req_id < rx_ring->ring_size)) 375 return 0; 376 377 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id); 378 379 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 380 rx_ring->adapter->trigger_reset = true; 381 ++rx_ring->rx_stats.bad_req_id; 382 383 return -EFAULT; 384 } 385 386 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 387 { 388 struct ena_tx_buffer *tx_info = NULL; 389 390 if (likely(req_id < tx_ring->ring_size)) { 391 tx_info = &tx_ring->tx_buffer_info[req_id]; 392 if (likely(tx_info->mbuf)) 393 return 0; 394 } 395 396 if (tx_info) 397 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n"); 398 else 399 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id); 400 401 /* Trigger device reset */ 402 ++tx_ring->tx_stats.bad_req_id; 403 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 404 tx_ring->adapter->trigger_reset = true; 405 return -EFAULT; 406 } 407 408 static void ena_config_host_info(struct ena_com_dev *ena_dev) 409 { 410 struct ena_admin_host_info *host_info; 411 int rc; 412 413 /* Allocate only the host info */ 414 rc = ena_com_allocate_host_info(ena_dev); 415 if (rc) { 416 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 417 return; 418 } 419 420 host_info = ena_dev->host_attr.host_info; 421 422 host_info->os_type = ENA_ADMIN_OS_DPDK; 423 host_info->kernel_ver = RTE_VERSION; 424 snprintf((char *)host_info->kernel_ver_str, 425 sizeof(host_info->kernel_ver_str), 426 "%s", rte_version()); 427 host_info->os_dist = RTE_VERSION; 428 snprintf((char *)host_info->os_dist_str, 429 sizeof(host_info->os_dist_str), 430 "%s", rte_version()); 431 host_info->driver_version = 432 (DRV_MODULE_VER_MAJOR) | 433 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 434 (DRV_MODULE_VER_SUBMINOR << 435 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 436 host_info->num_cpus = rte_lcore_count(); 437 438 rc = ena_com_set_host_attributes(ena_dev); 439 if (rc) { 440 if (rc == -ENA_COM_UNSUPPORTED) 441 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 442 else 443 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 444 445 goto err; 446 } 447 448 return; 449 450 err: 451 ena_com_delete_host_info(ena_dev); 452 } 453 454 /* This function calculates the number of xstats based on the current config */ 455 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 456 { 457 return ENA_STATS_ARRAY_GLOBAL + 458 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 459 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 460 } 461 462 static void ena_config_debug_area(struct ena_adapter *adapter) 463 { 464 u32 debug_area_size; 465 int rc, ss_count; 466 467 ss_count = ena_xstats_calc_num(adapter->rte_dev); 468 469 /* allocate 32 bytes for each string and 64bit for the value */ 470 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 471 472 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 473 if (rc) { 474 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 475 return; 476 } 477 478 rc = ena_com_set_host_attributes(&adapter->ena_dev); 479 if (rc) { 480 if (rc == -ENA_COM_UNSUPPORTED) 481 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 482 else 483 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 484 485 goto err; 486 } 487 488 return; 489 err: 490 ena_com_delete_debug_area(&adapter->ena_dev); 491 } 492 493 static void ena_close(struct rte_eth_dev *dev) 494 { 495 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 496 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 497 struct ena_adapter *adapter = 498 (struct ena_adapter *)(dev->data->dev_private); 499 500 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 501 ena_stop(dev); 502 adapter->state = ENA_ADAPTER_STATE_CLOSED; 503 504 ena_rx_queue_release_all(dev); 505 ena_tx_queue_release_all(dev); 506 507 rte_free(adapter->drv_stats); 508 adapter->drv_stats = NULL; 509 510 rte_intr_disable(intr_handle); 511 rte_intr_callback_unregister(intr_handle, 512 ena_interrupt_handler_rte, 513 adapter); 514 515 /* 516 * MAC is not allocated dynamically. Setting NULL should prevent from 517 * release of the resource in the rte_eth_dev_release_port(). 518 */ 519 dev->data->mac_addrs = NULL; 520 } 521 522 static int 523 ena_dev_reset(struct rte_eth_dev *dev) 524 { 525 int rc = 0; 526 527 ena_destroy_device(dev); 528 rc = eth_ena_dev_init(dev); 529 if (rc) 530 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 531 532 return rc; 533 } 534 535 static int ena_rss_reta_update(struct rte_eth_dev *dev, 536 struct rte_eth_rss_reta_entry64 *reta_conf, 537 uint16_t reta_size) 538 { 539 struct ena_adapter *adapter = 540 (struct ena_adapter *)(dev->data->dev_private); 541 struct ena_com_dev *ena_dev = &adapter->ena_dev; 542 int rc, i; 543 u16 entry_value; 544 int conf_idx; 545 int idx; 546 547 if ((reta_size == 0) || (reta_conf == NULL)) 548 return -EINVAL; 549 550 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 551 RTE_LOG(WARNING, PMD, 552 "indirection table %d is bigger than supported (%d)\n", 553 reta_size, ENA_RX_RSS_TABLE_SIZE); 554 return -EINVAL; 555 } 556 557 for (i = 0 ; i < reta_size ; i++) { 558 /* each reta_conf is for 64 entries. 559 * to support 128 we use 2 conf of 64 560 */ 561 conf_idx = i / RTE_RETA_GROUP_SIZE; 562 idx = i % RTE_RETA_GROUP_SIZE; 563 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 564 entry_value = 565 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 566 567 rc = ena_com_indirect_table_fill_entry(ena_dev, 568 i, 569 entry_value); 570 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 571 RTE_LOG(ERR, PMD, 572 "Cannot fill indirect table\n"); 573 return rc; 574 } 575 } 576 } 577 578 rc = ena_com_indirect_table_set(ena_dev); 579 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 580 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 581 return rc; 582 } 583 584 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 585 __func__, reta_size, adapter->rte_dev->data->port_id); 586 587 return 0; 588 } 589 590 /* Query redirection table. */ 591 static int ena_rss_reta_query(struct rte_eth_dev *dev, 592 struct rte_eth_rss_reta_entry64 *reta_conf, 593 uint16_t reta_size) 594 { 595 struct ena_adapter *adapter = 596 (struct ena_adapter *)(dev->data->dev_private); 597 struct ena_com_dev *ena_dev = &adapter->ena_dev; 598 int rc; 599 int i; 600 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 601 int reta_conf_idx; 602 int reta_idx; 603 604 if (reta_size == 0 || reta_conf == NULL || 605 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 606 return -EINVAL; 607 608 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 609 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 610 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 611 return -ENOTSUP; 612 } 613 614 for (i = 0 ; i < reta_size ; i++) { 615 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 616 reta_idx = i % RTE_RETA_GROUP_SIZE; 617 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 618 reta_conf[reta_conf_idx].reta[reta_idx] = 619 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 620 } 621 622 return 0; 623 } 624 625 static int ena_rss_init_default(struct ena_adapter *adapter) 626 { 627 struct ena_com_dev *ena_dev = &adapter->ena_dev; 628 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 629 int rc, i; 630 u32 val; 631 632 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 633 if (unlikely(rc)) { 634 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 635 goto err_rss_init; 636 } 637 638 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 639 val = i % nb_rx_queues; 640 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 641 ENA_IO_RXQ_IDX(val)); 642 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 643 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 644 goto err_fill_indir; 645 } 646 } 647 648 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 649 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 650 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 651 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 652 goto err_fill_indir; 653 } 654 655 rc = ena_com_set_default_hash_ctrl(ena_dev); 656 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 657 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 658 goto err_fill_indir; 659 } 660 661 rc = ena_com_indirect_table_set(ena_dev); 662 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 663 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 664 goto err_fill_indir; 665 } 666 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 667 adapter->rte_dev->data->port_id); 668 669 return 0; 670 671 err_fill_indir: 672 ena_com_rss_destroy(ena_dev); 673 err_rss_init: 674 675 return rc; 676 } 677 678 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 679 { 680 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 681 int nb_queues = dev->data->nb_rx_queues; 682 int i; 683 684 for (i = 0; i < nb_queues; i++) 685 ena_rx_queue_release(queues[i]); 686 } 687 688 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 689 { 690 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 691 int nb_queues = dev->data->nb_tx_queues; 692 int i; 693 694 for (i = 0; i < nb_queues; i++) 695 ena_tx_queue_release(queues[i]); 696 } 697 698 static void ena_rx_queue_release(void *queue) 699 { 700 struct ena_ring *ring = (struct ena_ring *)queue; 701 702 /* Free ring resources */ 703 if (ring->rx_buffer_info) 704 rte_free(ring->rx_buffer_info); 705 ring->rx_buffer_info = NULL; 706 707 if (ring->rx_refill_buffer) 708 rte_free(ring->rx_refill_buffer); 709 ring->rx_refill_buffer = NULL; 710 711 if (ring->empty_rx_reqs) 712 rte_free(ring->empty_rx_reqs); 713 ring->empty_rx_reqs = NULL; 714 715 ring->configured = 0; 716 717 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 718 ring->port_id, ring->id); 719 } 720 721 static void ena_tx_queue_release(void *queue) 722 { 723 struct ena_ring *ring = (struct ena_ring *)queue; 724 725 /* Free ring resources */ 726 if (ring->push_buf_intermediate_buf) 727 rte_free(ring->push_buf_intermediate_buf); 728 729 if (ring->tx_buffer_info) 730 rte_free(ring->tx_buffer_info); 731 732 if (ring->empty_tx_reqs) 733 rte_free(ring->empty_tx_reqs); 734 735 ring->empty_tx_reqs = NULL; 736 ring->tx_buffer_info = NULL; 737 ring->push_buf_intermediate_buf = NULL; 738 739 ring->configured = 0; 740 741 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 742 ring->port_id, ring->id); 743 } 744 745 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 746 { 747 unsigned int i; 748 749 for (i = 0; i < ring->ring_size; ++i) 750 if (ring->rx_buffer_info[i]) { 751 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 752 ring->rx_buffer_info[i] = NULL; 753 } 754 } 755 756 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 757 { 758 unsigned int i; 759 760 for (i = 0; i < ring->ring_size; ++i) { 761 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 762 763 if (tx_buf->mbuf) 764 rte_pktmbuf_free(tx_buf->mbuf); 765 } 766 } 767 768 static int ena_link_update(struct rte_eth_dev *dev, 769 __rte_unused int wait_to_complete) 770 { 771 struct rte_eth_link *link = &dev->data->dev_link; 772 struct ena_adapter *adapter; 773 774 adapter = (struct ena_adapter *)(dev->data->dev_private); 775 776 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 777 link->link_speed = ETH_SPEED_NUM_NONE; 778 link->link_duplex = ETH_LINK_FULL_DUPLEX; 779 780 return 0; 781 } 782 783 static int ena_queue_start_all(struct rte_eth_dev *dev, 784 enum ena_ring_type ring_type) 785 { 786 struct ena_adapter *adapter = 787 (struct ena_adapter *)(dev->data->dev_private); 788 struct ena_ring *queues = NULL; 789 int nb_queues; 790 int i = 0; 791 int rc = 0; 792 793 if (ring_type == ENA_RING_TYPE_RX) { 794 queues = adapter->rx_ring; 795 nb_queues = dev->data->nb_rx_queues; 796 } else { 797 queues = adapter->tx_ring; 798 nb_queues = dev->data->nb_tx_queues; 799 } 800 for (i = 0; i < nb_queues; i++) { 801 if (queues[i].configured) { 802 if (ring_type == ENA_RING_TYPE_RX) { 803 ena_assert_msg( 804 dev->data->rx_queues[i] == &queues[i], 805 "Inconsistent state of rx queues\n"); 806 } else { 807 ena_assert_msg( 808 dev->data->tx_queues[i] == &queues[i], 809 "Inconsistent state of tx queues\n"); 810 } 811 812 rc = ena_queue_start(&queues[i]); 813 814 if (rc) { 815 PMD_INIT_LOG(ERR, 816 "failed to start queue %d type(%d)", 817 i, ring_type); 818 goto err; 819 } 820 } 821 } 822 823 return 0; 824 825 err: 826 while (i--) 827 if (queues[i].configured) 828 ena_queue_stop(&queues[i]); 829 830 return rc; 831 } 832 833 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 834 { 835 uint32_t max_frame_len = adapter->max_mtu; 836 837 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 838 DEV_RX_OFFLOAD_JUMBO_FRAME) 839 max_frame_len = 840 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 841 842 return max_frame_len; 843 } 844 845 static int ena_check_valid_conf(struct ena_adapter *adapter) 846 { 847 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 848 849 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 850 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 851 "max mtu: %d, min mtu: %d", 852 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 853 return ENA_COM_UNSUPPORTED; 854 } 855 856 return 0; 857 } 858 859 static int 860 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) 861 { 862 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 863 struct ena_com_dev *ena_dev = ctx->ena_dev; 864 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; 865 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; 866 867 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 868 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 869 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 870 rx_queue_size = RTE_MIN(rx_queue_size, 871 max_queue_ext->max_rx_cq_depth); 872 rx_queue_size = RTE_MIN(rx_queue_size, 873 max_queue_ext->max_rx_sq_depth); 874 tx_queue_size = RTE_MIN(tx_queue_size, 875 max_queue_ext->max_tx_cq_depth); 876 877 if (ena_dev->tx_mem_queue_type == 878 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 879 tx_queue_size = RTE_MIN(tx_queue_size, 880 llq->max_llq_depth); 881 } else { 882 tx_queue_size = RTE_MIN(tx_queue_size, 883 max_queue_ext->max_tx_sq_depth); 884 } 885 886 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 887 max_queue_ext->max_per_packet_rx_descs); 888 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 889 max_queue_ext->max_per_packet_tx_descs); 890 } else { 891 struct ena_admin_queue_feature_desc *max_queues = 892 &ctx->get_feat_ctx->max_queues; 893 rx_queue_size = RTE_MIN(rx_queue_size, 894 max_queues->max_cq_depth); 895 rx_queue_size = RTE_MIN(rx_queue_size, 896 max_queues->max_sq_depth); 897 tx_queue_size = RTE_MIN(tx_queue_size, 898 max_queues->max_cq_depth); 899 900 if (ena_dev->tx_mem_queue_type == 901 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 902 tx_queue_size = RTE_MIN(tx_queue_size, 903 llq->max_llq_depth); 904 } else { 905 tx_queue_size = RTE_MIN(tx_queue_size, 906 max_queues->max_sq_depth); 907 } 908 909 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 910 max_queues->max_packet_tx_descs); 911 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 912 max_queues->max_packet_rx_descs); 913 } 914 915 /* Round down to the nearest power of 2 */ 916 rx_queue_size = rte_align32prevpow2(rx_queue_size); 917 tx_queue_size = rte_align32prevpow2(tx_queue_size); 918 919 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { 920 PMD_INIT_LOG(ERR, "Invalid queue size"); 921 return -EFAULT; 922 } 923 924 ctx->rx_queue_size = rx_queue_size; 925 ctx->tx_queue_size = tx_queue_size; 926 927 return 0; 928 } 929 930 static void ena_stats_restart(struct rte_eth_dev *dev) 931 { 932 struct ena_adapter *adapter = 933 (struct ena_adapter *)(dev->data->dev_private); 934 935 rte_atomic64_init(&adapter->drv_stats->ierrors); 936 rte_atomic64_init(&adapter->drv_stats->oerrors); 937 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 938 rte_atomic64_init(&adapter->drv_stats->rx_drops); 939 } 940 941 static int ena_stats_get(struct rte_eth_dev *dev, 942 struct rte_eth_stats *stats) 943 { 944 struct ena_admin_basic_stats ena_stats; 945 struct ena_adapter *adapter = 946 (struct ena_adapter *)(dev->data->dev_private); 947 struct ena_com_dev *ena_dev = &adapter->ena_dev; 948 int rc; 949 int i; 950 int max_rings_stats; 951 952 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 953 return -ENOTSUP; 954 955 memset(&ena_stats, 0, sizeof(ena_stats)); 956 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 957 if (unlikely(rc)) { 958 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n"); 959 return rc; 960 } 961 962 /* Set of basic statistics from ENA */ 963 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 964 ena_stats.rx_pkts_low); 965 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 966 ena_stats.tx_pkts_low); 967 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 968 ena_stats.rx_bytes_low); 969 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 970 ena_stats.tx_bytes_low); 971 972 /* Driver related stats */ 973 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 974 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 975 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 976 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 977 978 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 979 RTE_ETHDEV_QUEUE_STAT_CNTRS); 980 for (i = 0; i < max_rings_stats; ++i) { 981 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 982 983 stats->q_ibytes[i] = rx_stats->bytes; 984 stats->q_ipackets[i] = rx_stats->cnt; 985 stats->q_errors[i] = rx_stats->bad_desc_num + 986 rx_stats->bad_req_id; 987 } 988 989 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 990 RTE_ETHDEV_QUEUE_STAT_CNTRS); 991 for (i = 0; i < max_rings_stats; ++i) { 992 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 993 994 stats->q_obytes[i] = tx_stats->bytes; 995 stats->q_opackets[i] = tx_stats->cnt; 996 } 997 998 return 0; 999 } 1000 1001 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1002 { 1003 struct ena_adapter *adapter; 1004 struct ena_com_dev *ena_dev; 1005 int rc = 0; 1006 1007 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1008 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1009 adapter = (struct ena_adapter *)(dev->data->dev_private); 1010 1011 ena_dev = &adapter->ena_dev; 1012 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1013 1014 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1015 RTE_LOG(ERR, PMD, 1016 "Invalid MTU setting. new_mtu: %d " 1017 "max mtu: %d min mtu: %d\n", 1018 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1019 return -EINVAL; 1020 } 1021 1022 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1023 if (rc) 1024 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 1025 else 1026 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 1027 1028 return rc; 1029 } 1030 1031 static int ena_start(struct rte_eth_dev *dev) 1032 { 1033 struct ena_adapter *adapter = 1034 (struct ena_adapter *)(dev->data->dev_private); 1035 uint64_t ticks; 1036 int rc = 0; 1037 1038 rc = ena_check_valid_conf(adapter); 1039 if (rc) 1040 return rc; 1041 1042 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1043 if (rc) 1044 return rc; 1045 1046 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1047 if (rc) 1048 goto err_start_tx; 1049 1050 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1051 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1052 rc = ena_rss_init_default(adapter); 1053 if (rc) 1054 goto err_rss_init; 1055 } 1056 1057 ena_stats_restart(dev); 1058 1059 adapter->timestamp_wd = rte_get_timer_cycles(); 1060 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1061 1062 ticks = rte_get_timer_hz(); 1063 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1064 ena_timer_wd_callback, adapter); 1065 1066 ++adapter->dev_stats.dev_start; 1067 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1068 1069 return 0; 1070 1071 err_rss_init: 1072 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1073 err_start_tx: 1074 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1075 return rc; 1076 } 1077 1078 static void ena_stop(struct rte_eth_dev *dev) 1079 { 1080 struct ena_adapter *adapter = 1081 (struct ena_adapter *)(dev->data->dev_private); 1082 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1083 int rc; 1084 1085 rte_timer_stop_sync(&adapter->timer_wd); 1086 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1087 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1088 1089 if (adapter->trigger_reset) { 1090 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1091 if (rc) 1092 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc); 1093 } 1094 1095 ++adapter->dev_stats.dev_stop; 1096 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1097 } 1098 1099 static int ena_create_io_queue(struct ena_ring *ring) 1100 { 1101 struct ena_adapter *adapter; 1102 struct ena_com_dev *ena_dev; 1103 struct ena_com_create_io_ctx ctx = 1104 /* policy set to _HOST just to satisfy icc compiler */ 1105 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1106 0, 0, 0, 0, 0 }; 1107 uint16_t ena_qid; 1108 unsigned int i; 1109 int rc; 1110 1111 adapter = ring->adapter; 1112 ena_dev = &adapter->ena_dev; 1113 1114 if (ring->type == ENA_RING_TYPE_TX) { 1115 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1116 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1117 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1118 ctx.queue_size = adapter->tx_ring_size; 1119 for (i = 0; i < ring->ring_size; i++) 1120 ring->empty_tx_reqs[i] = i; 1121 } else { 1122 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1123 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1124 ctx.queue_size = adapter->rx_ring_size; 1125 for (i = 0; i < ring->ring_size; i++) 1126 ring->empty_rx_reqs[i] = i; 1127 } 1128 ctx.qid = ena_qid; 1129 ctx.msix_vector = -1; /* interrupts not used */ 1130 ctx.numa_node = ena_cpu_to_node(ring->id); 1131 1132 rc = ena_com_create_io_queue(ena_dev, &ctx); 1133 if (rc) { 1134 RTE_LOG(ERR, PMD, 1135 "failed to create io queue #%d (qid:%d) rc: %d\n", 1136 ring->id, ena_qid, rc); 1137 return rc; 1138 } 1139 1140 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1141 &ring->ena_com_io_sq, 1142 &ring->ena_com_io_cq); 1143 if (rc) { 1144 RTE_LOG(ERR, PMD, 1145 "Failed to get io queue handlers. queue num %d rc: %d\n", 1146 ring->id, rc); 1147 ena_com_destroy_io_queue(ena_dev, ena_qid); 1148 return rc; 1149 } 1150 1151 if (ring->type == ENA_RING_TYPE_TX) 1152 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1153 1154 return 0; 1155 } 1156 1157 static void ena_queue_stop(struct ena_ring *ring) 1158 { 1159 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1160 1161 if (ring->type == ENA_RING_TYPE_RX) { 1162 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1163 ena_rx_queue_release_bufs(ring); 1164 } else { 1165 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1166 ena_tx_queue_release_bufs(ring); 1167 } 1168 } 1169 1170 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1171 enum ena_ring_type ring_type) 1172 { 1173 struct ena_adapter *adapter = 1174 (struct ena_adapter *)(dev->data->dev_private); 1175 struct ena_ring *queues = NULL; 1176 uint16_t nb_queues, i; 1177 1178 if (ring_type == ENA_RING_TYPE_RX) { 1179 queues = adapter->rx_ring; 1180 nb_queues = dev->data->nb_rx_queues; 1181 } else { 1182 queues = adapter->tx_ring; 1183 nb_queues = dev->data->nb_tx_queues; 1184 } 1185 1186 for (i = 0; i < nb_queues; ++i) 1187 if (queues[i].configured) 1188 ena_queue_stop(&queues[i]); 1189 } 1190 1191 static int ena_queue_start(struct ena_ring *ring) 1192 { 1193 int rc, bufs_num; 1194 1195 ena_assert_msg(ring->configured == 1, 1196 "Trying to start unconfigured queue\n"); 1197 1198 rc = ena_create_io_queue(ring); 1199 if (rc) { 1200 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1201 return rc; 1202 } 1203 1204 ring->next_to_clean = 0; 1205 ring->next_to_use = 0; 1206 1207 if (ring->type == ENA_RING_TYPE_TX) { 1208 ring->tx_stats.available_desc = 1209 ena_com_free_desc(ring->ena_com_io_sq); 1210 return 0; 1211 } 1212 1213 bufs_num = ring->ring_size - 1; 1214 rc = ena_populate_rx_queue(ring, bufs_num); 1215 if (rc != bufs_num) { 1216 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1217 ENA_IO_RXQ_IDX(ring->id)); 1218 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1219 return ENA_COM_FAULT; 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1226 uint16_t queue_idx, 1227 uint16_t nb_desc, 1228 __rte_unused unsigned int socket_id, 1229 const struct rte_eth_txconf *tx_conf) 1230 { 1231 struct ena_ring *txq = NULL; 1232 struct ena_adapter *adapter = 1233 (struct ena_adapter *)(dev->data->dev_private); 1234 unsigned int i; 1235 1236 txq = &adapter->tx_ring[queue_idx]; 1237 1238 if (txq->configured) { 1239 RTE_LOG(CRIT, PMD, 1240 "API violation. Queue %d is already configured\n", 1241 queue_idx); 1242 return ENA_COM_FAULT; 1243 } 1244 1245 if (!rte_is_power_of_2(nb_desc)) { 1246 RTE_LOG(ERR, PMD, 1247 "Unsupported size of TX queue: %d is not a power of 2.\n", 1248 nb_desc); 1249 return -EINVAL; 1250 } 1251 1252 if (nb_desc > adapter->tx_ring_size) { 1253 RTE_LOG(ERR, PMD, 1254 "Unsupported size of TX queue (max size: %d)\n", 1255 adapter->tx_ring_size); 1256 return -EINVAL; 1257 } 1258 1259 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1260 nb_desc = adapter->tx_ring_size; 1261 1262 txq->port_id = dev->data->port_id; 1263 txq->next_to_clean = 0; 1264 txq->next_to_use = 0; 1265 txq->ring_size = nb_desc; 1266 1267 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1268 sizeof(struct ena_tx_buffer) * 1269 txq->ring_size, 1270 RTE_CACHE_LINE_SIZE); 1271 if (!txq->tx_buffer_info) { 1272 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1273 return -ENOMEM; 1274 } 1275 1276 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1277 sizeof(u16) * txq->ring_size, 1278 RTE_CACHE_LINE_SIZE); 1279 if (!txq->empty_tx_reqs) { 1280 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1281 rte_free(txq->tx_buffer_info); 1282 return -ENOMEM; 1283 } 1284 1285 txq->push_buf_intermediate_buf = 1286 rte_zmalloc("txq->push_buf_intermediate_buf", 1287 txq->tx_max_header_size, 1288 RTE_CACHE_LINE_SIZE); 1289 if (!txq->push_buf_intermediate_buf) { 1290 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n"); 1291 rte_free(txq->tx_buffer_info); 1292 rte_free(txq->empty_tx_reqs); 1293 return -ENOMEM; 1294 } 1295 1296 for (i = 0; i < txq->ring_size; i++) 1297 txq->empty_tx_reqs[i] = i; 1298 1299 if (tx_conf != NULL) { 1300 txq->offloads = 1301 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1302 } 1303 /* Store pointer to this queue in upper layer */ 1304 txq->configured = 1; 1305 dev->data->tx_queues[queue_idx] = txq; 1306 1307 return 0; 1308 } 1309 1310 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1311 uint16_t queue_idx, 1312 uint16_t nb_desc, 1313 __rte_unused unsigned int socket_id, 1314 __rte_unused const struct rte_eth_rxconf *rx_conf, 1315 struct rte_mempool *mp) 1316 { 1317 struct ena_adapter *adapter = 1318 (struct ena_adapter *)(dev->data->dev_private); 1319 struct ena_ring *rxq = NULL; 1320 int i; 1321 1322 rxq = &adapter->rx_ring[queue_idx]; 1323 if (rxq->configured) { 1324 RTE_LOG(CRIT, PMD, 1325 "API violation. Queue %d is already configured\n", 1326 queue_idx); 1327 return ENA_COM_FAULT; 1328 } 1329 1330 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1331 nb_desc = adapter->rx_ring_size; 1332 1333 if (!rte_is_power_of_2(nb_desc)) { 1334 RTE_LOG(ERR, PMD, 1335 "Unsupported size of RX queue: %d is not a power of 2.\n", 1336 nb_desc); 1337 return -EINVAL; 1338 } 1339 1340 if (nb_desc > adapter->rx_ring_size) { 1341 RTE_LOG(ERR, PMD, 1342 "Unsupported size of RX queue (max size: %d)\n", 1343 adapter->rx_ring_size); 1344 return -EINVAL; 1345 } 1346 1347 rxq->port_id = dev->data->port_id; 1348 rxq->next_to_clean = 0; 1349 rxq->next_to_use = 0; 1350 rxq->ring_size = nb_desc; 1351 rxq->mb_pool = mp; 1352 1353 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1354 sizeof(struct rte_mbuf *) * nb_desc, 1355 RTE_CACHE_LINE_SIZE); 1356 if (!rxq->rx_buffer_info) { 1357 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1358 return -ENOMEM; 1359 } 1360 1361 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1362 sizeof(struct rte_mbuf *) * nb_desc, 1363 RTE_CACHE_LINE_SIZE); 1364 1365 if (!rxq->rx_refill_buffer) { 1366 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n"); 1367 rte_free(rxq->rx_buffer_info); 1368 rxq->rx_buffer_info = NULL; 1369 return -ENOMEM; 1370 } 1371 1372 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1373 sizeof(uint16_t) * nb_desc, 1374 RTE_CACHE_LINE_SIZE); 1375 if (!rxq->empty_rx_reqs) { 1376 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n"); 1377 rte_free(rxq->rx_buffer_info); 1378 rxq->rx_buffer_info = NULL; 1379 rte_free(rxq->rx_refill_buffer); 1380 rxq->rx_refill_buffer = NULL; 1381 return -ENOMEM; 1382 } 1383 1384 for (i = 0; i < nb_desc; i++) 1385 rxq->empty_rx_reqs[i] = i; 1386 1387 /* Store pointer to this queue in upper layer */ 1388 rxq->configured = 1; 1389 dev->data->rx_queues[queue_idx] = rxq; 1390 1391 return 0; 1392 } 1393 1394 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1395 { 1396 unsigned int i; 1397 int rc; 1398 uint16_t ring_size = rxq->ring_size; 1399 uint16_t ring_mask = ring_size - 1; 1400 uint16_t next_to_use = rxq->next_to_use; 1401 uint16_t in_use, req_id; 1402 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1403 1404 if (unlikely(!count)) 1405 return 0; 1406 1407 in_use = rxq->next_to_use - rxq->next_to_clean; 1408 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1409 1410 /* get resources for incoming packets */ 1411 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1412 if (unlikely(rc < 0)) { 1413 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1414 ++rxq->rx_stats.mbuf_alloc_fail; 1415 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1416 return 0; 1417 } 1418 1419 for (i = 0; i < count; i++) { 1420 uint16_t next_to_use_masked = next_to_use & ring_mask; 1421 struct rte_mbuf *mbuf = mbufs[i]; 1422 struct ena_com_buf ebuf; 1423 1424 if (likely((i + 4) < count)) 1425 rte_prefetch0(mbufs[i + 4]); 1426 1427 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1428 rc = validate_rx_req_id(rxq, req_id); 1429 if (unlikely(rc < 0)) 1430 break; 1431 rxq->rx_buffer_info[req_id] = mbuf; 1432 1433 /* prepare physical address for DMA transaction */ 1434 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1435 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1436 /* pass resource to device */ 1437 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1438 &ebuf, req_id); 1439 if (unlikely(rc)) { 1440 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1441 rxq->rx_buffer_info[req_id] = NULL; 1442 break; 1443 } 1444 next_to_use++; 1445 } 1446 1447 if (unlikely(i < count)) { 1448 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d " 1449 "buffers (from %d)\n", rxq->id, i, count); 1450 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1451 count - i); 1452 ++rxq->rx_stats.refill_partial; 1453 } 1454 1455 /* When we submitted free recources to device... */ 1456 if (likely(i > 0)) { 1457 /* ...let HW know that it can fill buffers with data 1458 * 1459 * Add memory barrier to make sure the desc were written before 1460 * issue a doorbell 1461 */ 1462 rte_wmb(); 1463 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1464 1465 rxq->next_to_use = next_to_use; 1466 } 1467 1468 return i; 1469 } 1470 1471 static int ena_device_init(struct ena_com_dev *ena_dev, 1472 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1473 bool *wd_state) 1474 { 1475 uint32_t aenq_groups; 1476 int rc; 1477 bool readless_supported; 1478 1479 /* Initialize mmio registers */ 1480 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1481 if (rc) { 1482 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1483 return rc; 1484 } 1485 1486 /* The PCIe configuration space revision id indicate if mmio reg 1487 * read is disabled. 1488 */ 1489 readless_supported = 1490 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1491 & ENA_MMIO_DISABLE_REG_READ); 1492 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1493 1494 /* reset device */ 1495 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1496 if (rc) { 1497 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1498 goto err_mmio_read_less; 1499 } 1500 1501 /* check FW version */ 1502 rc = ena_com_validate_version(ena_dev); 1503 if (rc) { 1504 RTE_LOG(ERR, PMD, "device version is too low\n"); 1505 goto err_mmio_read_less; 1506 } 1507 1508 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1509 1510 /* ENA device administration layer init */ 1511 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1512 if (rc) { 1513 RTE_LOG(ERR, PMD, 1514 "cannot initialize ena admin queue with device\n"); 1515 goto err_mmio_read_less; 1516 } 1517 1518 /* To enable the msix interrupts the driver needs to know the number 1519 * of queues. So the driver uses polling mode to retrieve this 1520 * information. 1521 */ 1522 ena_com_set_admin_polling_mode(ena_dev, true); 1523 1524 ena_config_host_info(ena_dev); 1525 1526 /* Get Device Attributes and features */ 1527 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1528 if (rc) { 1529 RTE_LOG(ERR, PMD, 1530 "cannot get attribute for ena device rc= %d\n", rc); 1531 goto err_admin_init; 1532 } 1533 1534 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1535 BIT(ENA_ADMIN_NOTIFICATION) | 1536 BIT(ENA_ADMIN_KEEP_ALIVE) | 1537 BIT(ENA_ADMIN_FATAL_ERROR) | 1538 BIT(ENA_ADMIN_WARNING); 1539 1540 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1541 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1542 if (rc) { 1543 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc); 1544 goto err_admin_init; 1545 } 1546 1547 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1548 1549 return 0; 1550 1551 err_admin_init: 1552 ena_com_admin_destroy(ena_dev); 1553 1554 err_mmio_read_less: 1555 ena_com_mmio_reg_read_request_destroy(ena_dev); 1556 1557 return rc; 1558 } 1559 1560 static void ena_interrupt_handler_rte(void *cb_arg) 1561 { 1562 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg; 1563 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1564 1565 ena_com_admin_q_comp_intr_handler(ena_dev); 1566 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1567 ena_com_aenq_intr_handler(ena_dev, adapter); 1568 } 1569 1570 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1571 { 1572 if (!adapter->wd_state) 1573 return; 1574 1575 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1576 return; 1577 1578 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1579 adapter->keep_alive_timeout)) { 1580 RTE_LOG(ERR, PMD, "Keep alive timeout\n"); 1581 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1582 adapter->trigger_reset = true; 1583 ++adapter->dev_stats.wd_expired; 1584 } 1585 } 1586 1587 /* Check if admin queue is enabled */ 1588 static void check_for_admin_com_state(struct ena_adapter *adapter) 1589 { 1590 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1591 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n"); 1592 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1593 adapter->trigger_reset = true; 1594 } 1595 } 1596 1597 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1598 void *arg) 1599 { 1600 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1601 struct rte_eth_dev *dev = adapter->rte_dev; 1602 1603 check_for_missing_keep_alive(adapter); 1604 check_for_admin_com_state(adapter); 1605 1606 if (unlikely(adapter->trigger_reset)) { 1607 RTE_LOG(ERR, PMD, "Trigger reset is on\n"); 1608 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1609 NULL); 1610 } 1611 } 1612 1613 static inline void 1614 set_default_llq_configurations(struct ena_llq_configurations *llq_config) 1615 { 1616 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1617 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1618 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1619 llq_config->llq_num_decs_before_header = 1620 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1621 llq_config->llq_ring_entry_size_value = 128; 1622 } 1623 1624 static int 1625 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1626 struct ena_com_dev *ena_dev, 1627 struct ena_admin_feature_llq_desc *llq, 1628 struct ena_llq_configurations *llq_default_configurations) 1629 { 1630 int rc; 1631 u32 llq_feature_mask; 1632 1633 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1634 if (!(ena_dev->supported_features & llq_feature_mask)) { 1635 RTE_LOG(INFO, PMD, 1636 "LLQ is not supported. Fallback to host mode policy.\n"); 1637 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1638 return 0; 1639 } 1640 1641 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1642 if (unlikely(rc)) { 1643 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1644 "Fallback to host mode policy."); 1645 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1646 return 0; 1647 } 1648 1649 /* Nothing to config, exit */ 1650 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1651 return 0; 1652 1653 if (!adapter->dev_mem_base) { 1654 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. " 1655 "Fallback to host mode policy.\n."); 1656 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1657 return 0; 1658 } 1659 1660 ena_dev->mem_bar = adapter->dev_mem_base; 1661 1662 return 0; 1663 } 1664 1665 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, 1666 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1667 { 1668 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; 1669 1670 /* Regular queues capabilities */ 1671 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1672 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1673 &get_feat_ctx->max_queue_ext.max_queue_ext; 1674 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1675 max_queue_ext->max_rx_cq_num); 1676 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1677 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1678 } else { 1679 struct ena_admin_queue_feature_desc *max_queues = 1680 &get_feat_ctx->max_queues; 1681 io_tx_sq_num = max_queues->max_sq_num; 1682 io_tx_cq_num = max_queues->max_cq_num; 1683 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1684 } 1685 1686 /* In case of LLQ use the llq number in the get feature cmd */ 1687 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1688 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1689 1690 io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES); 1691 io_queue_num = RTE_MIN(io_queue_num, io_rx_num); 1692 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); 1693 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); 1694 1695 if (unlikely(io_queue_num == 0)) { 1696 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n"); 1697 return -EFAULT; 1698 } 1699 1700 return io_queue_num; 1701 } 1702 1703 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1704 { 1705 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1706 struct rte_pci_device *pci_dev; 1707 struct rte_intr_handle *intr_handle; 1708 struct ena_adapter *adapter = 1709 (struct ena_adapter *)(eth_dev->data->dev_private); 1710 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1711 struct ena_com_dev_get_features_ctx get_feat_ctx; 1712 struct ena_llq_configurations llq_config; 1713 const char *queue_type_str; 1714 int rc; 1715 1716 static int adapters_found; 1717 bool wd_state; 1718 1719 memset(adapter, 0, sizeof(struct ena_adapter)); 1720 ena_dev = &adapter->ena_dev; 1721 1722 eth_dev->dev_ops = &ena_dev_ops; 1723 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1724 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1725 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1726 adapter->rte_eth_dev_data = eth_dev->data; 1727 adapter->rte_dev = eth_dev; 1728 1729 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1730 return 0; 1731 1732 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1733 adapter->pdev = pci_dev; 1734 1735 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1736 pci_dev->addr.domain, 1737 pci_dev->addr.bus, 1738 pci_dev->addr.devid, 1739 pci_dev->addr.function); 1740 1741 intr_handle = &pci_dev->intr_handle; 1742 1743 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1744 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1745 1746 if (!adapter->regs) { 1747 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1748 ENA_REGS_BAR); 1749 return -ENXIO; 1750 } 1751 1752 ena_dev->reg_bar = adapter->regs; 1753 ena_dev->dmadev = adapter->pdev; 1754 1755 adapter->id_number = adapters_found; 1756 1757 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1758 adapter->id_number); 1759 1760 /* device specific initialization routine */ 1761 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1762 if (rc) { 1763 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1764 goto err; 1765 } 1766 adapter->wd_state = wd_state; 1767 1768 set_default_llq_configurations(&llq_config); 1769 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1770 &get_feat_ctx.llq, &llq_config); 1771 if (unlikely(rc)) { 1772 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1773 return rc; 1774 } 1775 1776 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1777 queue_type_str = "Regular"; 1778 else 1779 queue_type_str = "Low latency"; 1780 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str); 1781 1782 calc_queue_ctx.ena_dev = ena_dev; 1783 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1784 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1785 &get_feat_ctx); 1786 1787 rc = ena_calc_queue_size(&calc_queue_ctx); 1788 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { 1789 rc = -EFAULT; 1790 goto err_device_destroy; 1791 } 1792 1793 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; 1794 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; 1795 1796 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1797 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1798 1799 /* prepare ring structures */ 1800 ena_init_rings(adapter); 1801 1802 ena_config_debug_area(adapter); 1803 1804 /* Set max MTU for this device */ 1805 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1806 1807 /* set device support for TSO */ 1808 adapter->tso4_supported = get_feat_ctx.offload.tx & 1809 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1810 1811 /* Copy MAC address and point DPDK to it */ 1812 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr; 1813 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr, 1814 (struct ether_addr *)adapter->mac_addr); 1815 1816 /* 1817 * Pass the information to the rte_eth_dev_close() that it should also 1818 * release the private port resources. 1819 */ 1820 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1821 1822 adapter->drv_stats = rte_zmalloc("adapter stats", 1823 sizeof(*adapter->drv_stats), 1824 RTE_CACHE_LINE_SIZE); 1825 if (!adapter->drv_stats) { 1826 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1827 rc = -ENOMEM; 1828 goto err_delete_debug_area; 1829 } 1830 1831 rte_intr_callback_register(intr_handle, 1832 ena_interrupt_handler_rte, 1833 adapter); 1834 rte_intr_enable(intr_handle); 1835 ena_com_set_admin_polling_mode(ena_dev, false); 1836 ena_com_admin_aenq_enable(ena_dev); 1837 1838 if (adapters_found == 0) 1839 rte_timer_subsystem_init(); 1840 rte_timer_init(&adapter->timer_wd); 1841 1842 adapters_found++; 1843 adapter->state = ENA_ADAPTER_STATE_INIT; 1844 1845 return 0; 1846 1847 err_delete_debug_area: 1848 ena_com_delete_debug_area(ena_dev); 1849 1850 err_device_destroy: 1851 ena_com_delete_host_info(ena_dev); 1852 ena_com_admin_destroy(ena_dev); 1853 1854 err: 1855 return rc; 1856 } 1857 1858 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1859 { 1860 struct ena_adapter *adapter = 1861 (struct ena_adapter *)(eth_dev->data->dev_private); 1862 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1863 1864 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1865 return; 1866 1867 ena_com_set_admin_running_state(ena_dev, false); 1868 1869 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1870 ena_close(eth_dev); 1871 1872 ena_com_delete_debug_area(ena_dev); 1873 ena_com_delete_host_info(ena_dev); 1874 1875 ena_com_abort_admin_commands(ena_dev); 1876 ena_com_wait_for_abort_completion(ena_dev); 1877 ena_com_admin_destroy(ena_dev); 1878 ena_com_mmio_reg_read_request_destroy(ena_dev); 1879 1880 adapter->state = ENA_ADAPTER_STATE_FREE; 1881 } 1882 1883 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1884 { 1885 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1886 return 0; 1887 1888 ena_destroy_device(eth_dev); 1889 1890 eth_dev->dev_ops = NULL; 1891 eth_dev->rx_pkt_burst = NULL; 1892 eth_dev->tx_pkt_burst = NULL; 1893 eth_dev->tx_pkt_prepare = NULL; 1894 1895 return 0; 1896 } 1897 1898 static int ena_dev_configure(struct rte_eth_dev *dev) 1899 { 1900 struct ena_adapter *adapter = 1901 (struct ena_adapter *)(dev->data->dev_private); 1902 1903 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1904 1905 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1906 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1907 return 0; 1908 } 1909 1910 static void ena_init_rings(struct ena_adapter *adapter) 1911 { 1912 int i; 1913 1914 for (i = 0; i < adapter->num_queues; i++) { 1915 struct ena_ring *ring = &adapter->tx_ring[i]; 1916 1917 ring->configured = 0; 1918 ring->type = ENA_RING_TYPE_TX; 1919 ring->adapter = adapter; 1920 ring->id = i; 1921 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1922 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1923 ring->sgl_size = adapter->max_tx_sgl_size; 1924 } 1925 1926 for (i = 0; i < adapter->num_queues; i++) { 1927 struct ena_ring *ring = &adapter->rx_ring[i]; 1928 1929 ring->configured = 0; 1930 ring->type = ENA_RING_TYPE_RX; 1931 ring->adapter = adapter; 1932 ring->id = i; 1933 ring->sgl_size = adapter->max_rx_sgl_size; 1934 } 1935 } 1936 1937 static void ena_infos_get(struct rte_eth_dev *dev, 1938 struct rte_eth_dev_info *dev_info) 1939 { 1940 struct ena_adapter *adapter; 1941 struct ena_com_dev *ena_dev; 1942 struct ena_com_dev_get_features_ctx feat; 1943 uint64_t rx_feat = 0, tx_feat = 0; 1944 int rc = 0; 1945 1946 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1947 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1948 adapter = (struct ena_adapter *)(dev->data->dev_private); 1949 1950 ena_dev = &adapter->ena_dev; 1951 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1952 1953 dev_info->speed_capa = 1954 ETH_LINK_SPEED_1G | 1955 ETH_LINK_SPEED_2_5G | 1956 ETH_LINK_SPEED_5G | 1957 ETH_LINK_SPEED_10G | 1958 ETH_LINK_SPEED_25G | 1959 ETH_LINK_SPEED_40G | 1960 ETH_LINK_SPEED_50G | 1961 ETH_LINK_SPEED_100G; 1962 1963 /* Get supported features from HW */ 1964 rc = ena_com_get_dev_attr_feat(ena_dev, &feat); 1965 if (unlikely(rc)) { 1966 RTE_LOG(ERR, PMD, 1967 "Cannot get attribute for ena device rc= %d\n", rc); 1968 return; 1969 } 1970 1971 /* Set Tx & Rx features available for device */ 1972 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 1973 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1974 1975 if (feat.offload.tx & 1976 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 1977 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1978 DEV_TX_OFFLOAD_UDP_CKSUM | 1979 DEV_TX_OFFLOAD_TCP_CKSUM; 1980 1981 if (feat.offload.rx_supported & 1982 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 1983 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1984 DEV_RX_OFFLOAD_UDP_CKSUM | 1985 DEV_RX_OFFLOAD_TCP_CKSUM; 1986 1987 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1988 1989 /* Inform framework about available features */ 1990 dev_info->rx_offload_capa = rx_feat; 1991 dev_info->rx_queue_offload_capa = rx_feat; 1992 dev_info->tx_offload_capa = tx_feat; 1993 dev_info->tx_queue_offload_capa = tx_feat; 1994 1995 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1996 ETH_RSS_UDP; 1997 1998 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1999 dev_info->max_rx_pktlen = adapter->max_mtu; 2000 dev_info->max_mac_addrs = 1; 2001 2002 dev_info->max_rx_queues = adapter->num_queues; 2003 dev_info->max_tx_queues = adapter->num_queues; 2004 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2005 2006 adapter->tx_supported_offloads = tx_feat; 2007 adapter->rx_supported_offloads = rx_feat; 2008 2009 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; 2010 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2011 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2012 adapter->max_rx_sgl_size); 2013 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2014 adapter->max_rx_sgl_size); 2015 2016 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; 2017 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2018 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2019 adapter->max_tx_sgl_size); 2020 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2021 adapter->max_tx_sgl_size); 2022 } 2023 2024 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2025 uint16_t nb_pkts) 2026 { 2027 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2028 unsigned int ring_size = rx_ring->ring_size; 2029 unsigned int ring_mask = ring_size - 1; 2030 uint16_t next_to_clean = rx_ring->next_to_clean; 2031 uint16_t desc_in_use = 0; 2032 uint16_t req_id; 2033 unsigned int recv_idx = 0; 2034 struct rte_mbuf *mbuf = NULL; 2035 struct rte_mbuf *mbuf_head = NULL; 2036 struct rte_mbuf *mbuf_prev = NULL; 2037 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2038 unsigned int completed; 2039 2040 struct ena_com_rx_ctx ena_rx_ctx; 2041 int rc = 0; 2042 2043 /* Check adapter state */ 2044 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2045 RTE_LOG(ALERT, PMD, 2046 "Trying to receive pkts while device is NOT running\n"); 2047 return 0; 2048 } 2049 2050 desc_in_use = rx_ring->next_to_use - next_to_clean; 2051 if (unlikely(nb_pkts > desc_in_use)) 2052 nb_pkts = desc_in_use; 2053 2054 for (completed = 0; completed < nb_pkts; completed++) { 2055 int segments = 0; 2056 2057 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2058 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2059 ena_rx_ctx.descs = 0; 2060 /* receive packet context */ 2061 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2062 rx_ring->ena_com_io_sq, 2063 &ena_rx_ctx); 2064 if (unlikely(rc)) { 2065 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 2066 rx_ring->adapter->reset_reason = 2067 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2068 rx_ring->adapter->trigger_reset = true; 2069 ++rx_ring->rx_stats.bad_desc_num; 2070 return 0; 2071 } 2072 2073 if (unlikely(ena_rx_ctx.descs == 0)) 2074 break; 2075 2076 while (segments < ena_rx_ctx.descs) { 2077 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2078 rc = validate_rx_req_id(rx_ring, req_id); 2079 if (unlikely(rc)) { 2080 if (segments != 0) 2081 rte_mbuf_raw_free(mbuf_head); 2082 break; 2083 } 2084 2085 mbuf = rx_buff_info[req_id]; 2086 rx_buff_info[req_id] = NULL; 2087 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2088 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2089 mbuf->refcnt = 1; 2090 mbuf->next = NULL; 2091 if (unlikely(segments == 0)) { 2092 mbuf->nb_segs = ena_rx_ctx.descs; 2093 mbuf->port = rx_ring->port_id; 2094 mbuf->pkt_len = 0; 2095 mbuf_head = mbuf; 2096 } else { 2097 /* for multi-segment pkts create mbuf chain */ 2098 mbuf_prev->next = mbuf; 2099 } 2100 mbuf_head->pkt_len += mbuf->data_len; 2101 2102 mbuf_prev = mbuf; 2103 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2104 req_id; 2105 segments++; 2106 next_to_clean++; 2107 } 2108 if (unlikely(rc)) 2109 break; 2110 2111 /* fill mbuf attributes if any */ 2112 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2113 2114 if (unlikely(mbuf_head->ol_flags & 2115 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) 2116 ++rx_ring->rx_stats.bad_csum; 2117 2118 mbuf_head->hash.rss = ena_rx_ctx.hash; 2119 2120 /* pass to DPDK application head mbuf */ 2121 rx_pkts[recv_idx] = mbuf_head; 2122 recv_idx++; 2123 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2124 } 2125 2126 rx_ring->rx_stats.cnt += recv_idx; 2127 rx_ring->next_to_clean = next_to_clean; 2128 2129 desc_in_use = desc_in_use - completed + 1; 2130 /* Burst refill to save doorbells, memory barriers, const interval */ 2131 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2132 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2133 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2134 } 2135 2136 return recv_idx; 2137 } 2138 2139 static uint16_t 2140 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2141 uint16_t nb_pkts) 2142 { 2143 int32_t ret; 2144 uint32_t i; 2145 struct rte_mbuf *m; 2146 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2147 struct ipv4_hdr *ip_hdr; 2148 uint64_t ol_flags; 2149 uint16_t frag_field; 2150 2151 for (i = 0; i != nb_pkts; i++) { 2152 m = tx_pkts[i]; 2153 ol_flags = m->ol_flags; 2154 2155 if (!(ol_flags & PKT_TX_IPV4)) 2156 continue; 2157 2158 /* If there was not L2 header length specified, assume it is 2159 * length of the ethernet header. 2160 */ 2161 if (unlikely(m->l2_len == 0)) 2162 m->l2_len = sizeof(struct ether_hdr); 2163 2164 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, 2165 m->l2_len); 2166 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2167 2168 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) { 2169 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2170 2171 /* If IPv4 header has DF flag enabled and TSO support is 2172 * disabled, partial chcecksum should not be calculated. 2173 */ 2174 if (!tx_ring->adapter->tso4_supported) 2175 continue; 2176 } 2177 2178 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2179 (ol_flags & PKT_TX_L4_MASK) == 2180 PKT_TX_SCTP_CKSUM) { 2181 rte_errno = -ENOTSUP; 2182 return i; 2183 } 2184 2185 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2186 ret = rte_validate_tx_offload(m); 2187 if (ret != 0) { 2188 rte_errno = ret; 2189 return i; 2190 } 2191 #endif 2192 2193 /* In case we are supposed to TSO and have DF not set (DF=0) 2194 * hardware must be provided with partial checksum, otherwise 2195 * it will take care of necessary calculations. 2196 */ 2197 2198 ret = rte_net_intel_cksum_flags_prepare(m, 2199 ol_flags & ~PKT_TX_TCP_SEG); 2200 if (ret != 0) { 2201 rte_errno = ret; 2202 return i; 2203 } 2204 } 2205 2206 return i; 2207 } 2208 2209 static void ena_update_hints(struct ena_adapter *adapter, 2210 struct ena_admin_ena_hw_hints *hints) 2211 { 2212 if (hints->admin_completion_tx_timeout) 2213 adapter->ena_dev.admin_queue.completion_timeout = 2214 hints->admin_completion_tx_timeout * 1000; 2215 2216 if (hints->mmio_read_timeout) 2217 /* convert to usec */ 2218 adapter->ena_dev.mmio_read.reg_read_to = 2219 hints->mmio_read_timeout * 1000; 2220 2221 if (hints->driver_watchdog_timeout) { 2222 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2223 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2224 else 2225 // Convert msecs to ticks 2226 adapter->keep_alive_timeout = 2227 (hints->driver_watchdog_timeout * 2228 rte_get_timer_hz()) / 1000; 2229 } 2230 } 2231 2232 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2233 struct rte_mbuf *mbuf) 2234 { 2235 struct ena_com_dev *ena_dev; 2236 int num_segments, header_len, rc; 2237 2238 ena_dev = &tx_ring->adapter->ena_dev; 2239 num_segments = mbuf->nb_segs; 2240 header_len = mbuf->data_len; 2241 2242 if (likely(num_segments < tx_ring->sgl_size)) 2243 return 0; 2244 2245 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2246 (num_segments == tx_ring->sgl_size) && 2247 (header_len < tx_ring->tx_max_header_size)) 2248 return 0; 2249 2250 ++tx_ring->tx_stats.linearize; 2251 rc = rte_pktmbuf_linearize(mbuf); 2252 if (unlikely(rc)) { 2253 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n"); 2254 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2255 ++tx_ring->tx_stats.linearize_failed; 2256 return rc; 2257 } 2258 2259 return rc; 2260 } 2261 2262 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2263 uint16_t nb_pkts) 2264 { 2265 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2266 uint16_t next_to_use = tx_ring->next_to_use; 2267 uint16_t next_to_clean = tx_ring->next_to_clean; 2268 struct rte_mbuf *mbuf; 2269 uint16_t seg_len; 2270 unsigned int ring_size = tx_ring->ring_size; 2271 unsigned int ring_mask = ring_size - 1; 2272 struct ena_com_tx_ctx ena_tx_ctx; 2273 struct ena_tx_buffer *tx_info; 2274 struct ena_com_buf *ebuf; 2275 uint16_t rc, req_id, total_tx_descs = 0; 2276 uint16_t sent_idx = 0, empty_tx_reqs; 2277 uint16_t push_len = 0; 2278 uint16_t delta = 0; 2279 int nb_hw_desc; 2280 uint32_t total_length; 2281 2282 /* Check adapter state */ 2283 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2284 RTE_LOG(ALERT, PMD, 2285 "Trying to xmit pkts while device is NOT running\n"); 2286 return 0; 2287 } 2288 2289 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2290 if (nb_pkts > empty_tx_reqs) 2291 nb_pkts = empty_tx_reqs; 2292 2293 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2294 mbuf = tx_pkts[sent_idx]; 2295 total_length = 0; 2296 2297 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2298 if (unlikely(rc)) 2299 break; 2300 2301 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2302 tx_info = &tx_ring->tx_buffer_info[req_id]; 2303 tx_info->mbuf = mbuf; 2304 tx_info->num_of_bufs = 0; 2305 ebuf = tx_info->bufs; 2306 2307 /* Prepare TX context */ 2308 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2309 memset(&ena_tx_ctx.ena_meta, 0x0, 2310 sizeof(struct ena_com_tx_meta)); 2311 ena_tx_ctx.ena_bufs = ebuf; 2312 ena_tx_ctx.req_id = req_id; 2313 2314 delta = 0; 2315 seg_len = mbuf->data_len; 2316 2317 if (tx_ring->tx_mem_queue_type == 2318 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2319 push_len = RTE_MIN(mbuf->pkt_len, 2320 tx_ring->tx_max_header_size); 2321 ena_tx_ctx.header_len = push_len; 2322 2323 if (likely(push_len <= seg_len)) { 2324 /* If the push header is in the single segment, 2325 * then just point it to the 1st mbuf data. 2326 */ 2327 ena_tx_ctx.push_header = 2328 rte_pktmbuf_mtod(mbuf, uint8_t *); 2329 } else { 2330 /* If the push header lays in the several 2331 * segments, copy it to the intermediate buffer. 2332 */ 2333 rte_pktmbuf_read(mbuf, 0, push_len, 2334 tx_ring->push_buf_intermediate_buf); 2335 ena_tx_ctx.push_header = 2336 tx_ring->push_buf_intermediate_buf; 2337 delta = push_len - seg_len; 2338 } 2339 } /* there's no else as we take advantage of memset zeroing */ 2340 2341 /* Set TX offloads flags, if applicable */ 2342 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2343 2344 if (unlikely(mbuf->ol_flags & 2345 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD))) 2346 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2347 2348 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2349 2350 /* Process first segment taking into 2351 * consideration pushed header 2352 */ 2353 if (seg_len > push_len) { 2354 ebuf->paddr = mbuf->buf_iova + 2355 mbuf->data_off + 2356 push_len; 2357 ebuf->len = seg_len - push_len; 2358 ebuf++; 2359 tx_info->num_of_bufs++; 2360 } 2361 total_length += mbuf->data_len; 2362 2363 while ((mbuf = mbuf->next) != NULL) { 2364 seg_len = mbuf->data_len; 2365 2366 /* Skip mbufs if whole data is pushed as a header */ 2367 if (unlikely(delta > seg_len)) { 2368 delta -= seg_len; 2369 continue; 2370 } 2371 2372 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2373 ebuf->len = seg_len - delta; 2374 total_length += ebuf->len; 2375 ebuf++; 2376 tx_info->num_of_bufs++; 2377 2378 delta = 0; 2379 } 2380 2381 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2382 2383 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2384 &ena_tx_ctx)) { 2385 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d" 2386 " achieved, writing doorbell to send burst\n", 2387 tx_ring->id); 2388 rte_wmb(); 2389 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2390 } 2391 2392 /* prepare the packet's descriptors to dma engine */ 2393 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2394 &ena_tx_ctx, &nb_hw_desc); 2395 if (unlikely(rc)) { 2396 ++tx_ring->tx_stats.prepare_ctx_err; 2397 break; 2398 } 2399 tx_info->tx_descs = nb_hw_desc; 2400 2401 next_to_use++; 2402 tx_ring->tx_stats.cnt += tx_info->num_of_bufs; 2403 tx_ring->tx_stats.bytes += total_length; 2404 } 2405 tx_ring->tx_stats.available_desc = 2406 ena_com_free_desc(tx_ring->ena_com_io_sq); 2407 2408 /* If there are ready packets to be xmitted... */ 2409 if (sent_idx > 0) { 2410 /* ...let HW do its best :-) */ 2411 rte_wmb(); 2412 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2413 tx_ring->tx_stats.doorbells++; 2414 tx_ring->next_to_use = next_to_use; 2415 } 2416 2417 /* Clear complete packets */ 2418 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2419 rc = validate_tx_req_id(tx_ring, req_id); 2420 if (rc) 2421 break; 2422 2423 /* Get Tx info & store how many descs were processed */ 2424 tx_info = &tx_ring->tx_buffer_info[req_id]; 2425 total_tx_descs += tx_info->tx_descs; 2426 2427 /* Free whole mbuf chain */ 2428 mbuf = tx_info->mbuf; 2429 rte_pktmbuf_free(mbuf); 2430 tx_info->mbuf = NULL; 2431 2432 /* Put back descriptor to the ring for reuse */ 2433 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2434 next_to_clean++; 2435 2436 /* If too many descs to clean, leave it for another run */ 2437 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2438 break; 2439 } 2440 tx_ring->tx_stats.available_desc = 2441 ena_com_free_desc(tx_ring->ena_com_io_sq); 2442 2443 if (total_tx_descs > 0) { 2444 /* acknowledge completion of sent packets */ 2445 tx_ring->next_to_clean = next_to_clean; 2446 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2447 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2448 } 2449 2450 tx_ring->tx_stats.tx_poll++; 2451 2452 return sent_idx; 2453 } 2454 2455 /** 2456 * DPDK callback to retrieve names of extended device statistics 2457 * 2458 * @param dev 2459 * Pointer to Ethernet device structure. 2460 * @param[out] xstats_names 2461 * Buffer to insert names into. 2462 * @param n 2463 * Number of names. 2464 * 2465 * @return 2466 * Number of xstats names. 2467 */ 2468 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2469 struct rte_eth_xstat_name *xstats_names, 2470 unsigned int n) 2471 { 2472 unsigned int xstats_count = ena_xstats_calc_num(dev); 2473 unsigned int stat, i, count = 0; 2474 2475 if (n < xstats_count || !xstats_names) 2476 return xstats_count; 2477 2478 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2479 strcpy(xstats_names[count].name, 2480 ena_stats_global_strings[stat].name); 2481 2482 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2483 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2484 snprintf(xstats_names[count].name, 2485 sizeof(xstats_names[count].name), 2486 "rx_q%d_%s", i, 2487 ena_stats_rx_strings[stat].name); 2488 2489 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2490 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2491 snprintf(xstats_names[count].name, 2492 sizeof(xstats_names[count].name), 2493 "tx_q%d_%s", i, 2494 ena_stats_tx_strings[stat].name); 2495 2496 return xstats_count; 2497 } 2498 2499 /** 2500 * DPDK callback to get extended device statistics. 2501 * 2502 * @param dev 2503 * Pointer to Ethernet device structure. 2504 * @param[out] stats 2505 * Stats table output buffer. 2506 * @param n 2507 * The size of the stats table. 2508 * 2509 * @return 2510 * Number of xstats on success, negative on failure. 2511 */ 2512 static int ena_xstats_get(struct rte_eth_dev *dev, 2513 struct rte_eth_xstat *xstats, 2514 unsigned int n) 2515 { 2516 struct ena_adapter *adapter = 2517 (struct ena_adapter *)(dev->data->dev_private); 2518 unsigned int xstats_count = ena_xstats_calc_num(dev); 2519 unsigned int stat, i, count = 0; 2520 int stat_offset; 2521 void *stats_begin; 2522 2523 if (n < xstats_count) 2524 return xstats_count; 2525 2526 if (!xstats) 2527 return 0; 2528 2529 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2530 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2531 stats_begin = &adapter->dev_stats; 2532 2533 xstats[count].id = count; 2534 xstats[count].value = *((uint64_t *) 2535 ((char *)stats_begin + stat_offset)); 2536 } 2537 2538 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2539 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2540 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2541 stats_begin = &adapter->rx_ring[i].rx_stats; 2542 2543 xstats[count].id = count; 2544 xstats[count].value = *((uint64_t *) 2545 ((char *)stats_begin + stat_offset)); 2546 } 2547 } 2548 2549 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2550 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2551 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2552 stats_begin = &adapter->tx_ring[i].rx_stats; 2553 2554 xstats[count].id = count; 2555 xstats[count].value = *((uint64_t *) 2556 ((char *)stats_begin + stat_offset)); 2557 } 2558 } 2559 2560 return count; 2561 } 2562 2563 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2564 const uint64_t *ids, 2565 uint64_t *values, 2566 unsigned int n) 2567 { 2568 struct ena_adapter *adapter = 2569 (struct ena_adapter *)(dev->data->dev_private); 2570 uint64_t id; 2571 uint64_t rx_entries, tx_entries; 2572 unsigned int i; 2573 int qid; 2574 int valid = 0; 2575 for (i = 0; i < n; ++i) { 2576 id = ids[i]; 2577 /* Check if id belongs to global statistics */ 2578 if (id < ENA_STATS_ARRAY_GLOBAL) { 2579 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2580 ++valid; 2581 continue; 2582 } 2583 2584 /* Check if id belongs to rx queue statistics */ 2585 id -= ENA_STATS_ARRAY_GLOBAL; 2586 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2587 if (id < rx_entries) { 2588 qid = id % dev->data->nb_rx_queues; 2589 id /= dev->data->nb_rx_queues; 2590 values[i] = *((uint64_t *) 2591 &adapter->rx_ring[qid].rx_stats + id); 2592 ++valid; 2593 continue; 2594 } 2595 /* Check if id belongs to rx queue statistics */ 2596 id -= rx_entries; 2597 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2598 if (id < tx_entries) { 2599 qid = id % dev->data->nb_tx_queues; 2600 id /= dev->data->nb_tx_queues; 2601 values[i] = *((uint64_t *) 2602 &adapter->tx_ring[qid].tx_stats + id); 2603 ++valid; 2604 continue; 2605 } 2606 } 2607 2608 return valid; 2609 } 2610 2611 /********************************************************************* 2612 * PMD configuration 2613 *********************************************************************/ 2614 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2615 struct rte_pci_device *pci_dev) 2616 { 2617 return rte_eth_dev_pci_generic_probe(pci_dev, 2618 sizeof(struct ena_adapter), eth_ena_dev_init); 2619 } 2620 2621 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2622 { 2623 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2624 } 2625 2626 static struct rte_pci_driver rte_ena_pmd = { 2627 .id_table = pci_id_ena_map, 2628 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2629 RTE_PCI_DRV_WC_ACTIVATE, 2630 .probe = eth_ena_pci_probe, 2631 .remove = eth_ena_pci_remove, 2632 }; 2633 2634 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2635 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2636 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2637 2638 RTE_INIT(ena_init_log) 2639 { 2640 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2641 if (ena_logtype_init >= 0) 2642 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2643 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2644 if (ena_logtype_driver >= 0) 2645 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2646 } 2647 2648 /****************************************************************************** 2649 ******************************** AENQ Handlers ******************************* 2650 *****************************************************************************/ 2651 static void ena_update_on_link_change(void *adapter_data, 2652 struct ena_admin_aenq_entry *aenq_e) 2653 { 2654 struct rte_eth_dev *eth_dev; 2655 struct ena_adapter *adapter; 2656 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2657 uint32_t status; 2658 2659 adapter = (struct ena_adapter *)adapter_data; 2660 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2661 eth_dev = adapter->rte_dev; 2662 2663 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2664 adapter->link_status = status; 2665 2666 ena_link_update(eth_dev, 0); 2667 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2668 } 2669 2670 static void ena_notification(void *data, 2671 struct ena_admin_aenq_entry *aenq_e) 2672 { 2673 struct ena_adapter *adapter = (struct ena_adapter *)data; 2674 struct ena_admin_ena_hw_hints *hints; 2675 2676 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2677 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n", 2678 aenq_e->aenq_common_desc.group, 2679 ENA_ADMIN_NOTIFICATION); 2680 2681 switch (aenq_e->aenq_common_desc.syndrom) { 2682 case ENA_ADMIN_UPDATE_HINTS: 2683 hints = (struct ena_admin_ena_hw_hints *) 2684 (&aenq_e->inline_data_w4); 2685 ena_update_hints(adapter, hints); 2686 break; 2687 default: 2688 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n", 2689 aenq_e->aenq_common_desc.syndrom); 2690 } 2691 } 2692 2693 static void ena_keep_alive(void *adapter_data, 2694 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2695 { 2696 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 2697 struct ena_admin_aenq_keep_alive_desc *desc; 2698 uint64_t rx_drops; 2699 2700 adapter->timestamp_wd = rte_get_timer_cycles(); 2701 2702 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2703 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2704 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2705 } 2706 2707 /** 2708 * This handler will called for unknown event group or unimplemented handlers 2709 **/ 2710 static void unimplemented_aenq_handler(__rte_unused void *data, 2711 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2712 { 2713 RTE_LOG(ERR, PMD, "Unknown event was received or event with " 2714 "unimplemented handler\n"); 2715 } 2716 2717 static struct ena_aenq_handlers aenq_handlers = { 2718 .handlers = { 2719 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2720 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2721 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2722 }, 2723 .unimplemented_handler = unimplemented_aenq_handler 2724 }; 2725