1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 1 31 #define DRV_MODULE_VER_SUBMINOR 0 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 40 41 #define GET_L4_HDR_LEN(mbuf) \ 42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 44 45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 47 #define ENA_HASH_KEY_SIZE 40 48 #define ETH_GSTRING_LEN 32 49 50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 51 52 #define ENA_MIN_RING_DESC 128 53 54 enum ethtool_stringset { 55 ETH_SS_TEST = 0, 56 ETH_SS_STATS, 57 }; 58 59 struct ena_stats { 60 char name[ETH_GSTRING_LEN]; 61 int stat_offset; 62 }; 63 64 #define ENA_STAT_ENTRY(stat, stat_type) { \ 65 .name = #stat, \ 66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 67 } 68 69 #define ENA_STAT_RX_ENTRY(stat) \ 70 ENA_STAT_ENTRY(stat, rx) 71 72 #define ENA_STAT_TX_ENTRY(stat) \ 73 ENA_STAT_ENTRY(stat, tx) 74 75 #define ENA_STAT_ENI_ENTRY(stat) \ 76 ENA_STAT_ENTRY(stat, eni) 77 78 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 79 ENA_STAT_ENTRY(stat, dev) 80 81 /* Device arguments */ 82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 83 84 /* 85 * Each rte_memzone should have unique name. 86 * To satisfy it, count number of allocation and add it to name. 87 */ 88 rte_atomic32_t ena_alloc_cnt; 89 90 static const struct ena_stats ena_stats_global_strings[] = { 91 ENA_STAT_GLOBAL_ENTRY(wd_expired), 92 ENA_STAT_GLOBAL_ENTRY(dev_start), 93 ENA_STAT_GLOBAL_ENTRY(dev_stop), 94 ENA_STAT_GLOBAL_ENTRY(tx_drops), 95 }; 96 97 static const struct ena_stats ena_stats_eni_strings[] = { 98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded), 99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded), 100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded), 101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded), 102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded), 103 }; 104 105 static const struct ena_stats ena_stats_tx_strings[] = { 106 ENA_STAT_TX_ENTRY(cnt), 107 ENA_STAT_TX_ENTRY(bytes), 108 ENA_STAT_TX_ENTRY(prepare_ctx_err), 109 ENA_STAT_TX_ENTRY(linearize), 110 ENA_STAT_TX_ENTRY(linearize_failed), 111 ENA_STAT_TX_ENTRY(tx_poll), 112 ENA_STAT_TX_ENTRY(doorbells), 113 ENA_STAT_TX_ENTRY(bad_req_id), 114 ENA_STAT_TX_ENTRY(available_desc), 115 }; 116 117 static const struct ena_stats ena_stats_rx_strings[] = { 118 ENA_STAT_RX_ENTRY(cnt), 119 ENA_STAT_RX_ENTRY(bytes), 120 ENA_STAT_RX_ENTRY(refill_partial), 121 ENA_STAT_RX_ENTRY(bad_csum), 122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 123 ENA_STAT_RX_ENTRY(bad_desc_num), 124 ENA_STAT_RX_ENTRY(bad_req_id), 125 }; 126 127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings) 129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 131 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 133 DEV_TX_OFFLOAD_UDP_CKSUM |\ 134 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 135 DEV_TX_OFFLOAD_TCP_TSO) 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 137 PKT_TX_IP_CKSUM |\ 138 PKT_TX_TCP_SEG) 139 140 /** Vendor ID used by Amazon devices */ 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F 142 /** Amazon devices */ 143 #define PCI_DEVICE_ID_ENA_VF 0xEC20 144 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 145 146 #define ENA_TX_OFFLOAD_MASK (\ 147 PKT_TX_L4_MASK | \ 148 PKT_TX_IPV6 | \ 149 PKT_TX_IPV4 | \ 150 PKT_TX_IP_CKSUM | \ 151 PKT_TX_TCP_SEG) 152 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 155 156 static const struct rte_pci_id pci_id_ena_map[] = { 157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 159 { .device_id = 0 }, 160 }; 161 162 static struct ena_aenq_handlers aenq_handlers; 163 164 static int ena_device_init(struct ena_com_dev *ena_dev, 165 struct ena_com_dev_get_features_ctx *get_feat_ctx, 166 bool *wd_state); 167 static int ena_dev_configure(struct rte_eth_dev *dev); 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 169 struct ena_tx_buffer *tx_info, 170 struct rte_mbuf *mbuf, 171 void **push_header, 172 uint16_t *header_len); 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 174 static void ena_tx_cleanup(struct ena_ring *tx_ring); 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 176 uint16_t nb_pkts); 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 178 uint16_t nb_pkts); 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 180 uint16_t nb_desc, unsigned int socket_id, 181 const struct rte_eth_txconf *tx_conf); 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 183 uint16_t nb_desc, unsigned int socket_id, 184 const struct rte_eth_rxconf *rx_conf, 185 struct rte_mempool *mp); 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 188 struct ena_com_rx_buf_info *ena_bufs, 189 uint32_t descs, 190 uint16_t *next_to_clean, 191 uint8_t offset); 192 static uint16_t eth_ena_recv_pkts(void *rx_queue, 193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 195 struct rte_mbuf *mbuf, uint16_t id); 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 197 static void ena_init_rings(struct ena_adapter *adapter, 198 bool disable_meta_caching); 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 200 static int ena_start(struct rte_eth_dev *dev); 201 static void ena_stop(struct rte_eth_dev *dev); 202 static int ena_close(struct rte_eth_dev *dev); 203 static int ena_dev_reset(struct rte_eth_dev *dev); 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 207 static void ena_rx_queue_release(void *queue); 208 static void ena_tx_queue_release(void *queue); 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 211 static int ena_link_update(struct rte_eth_dev *dev, 212 int wait_to_complete); 213 static int ena_create_io_queue(struct ena_ring *ring); 214 static void ena_queue_stop(struct ena_ring *ring); 215 static void ena_queue_stop_all(struct rte_eth_dev *dev, 216 enum ena_ring_type ring_type); 217 static int ena_queue_start(struct ena_ring *ring); 218 static int ena_queue_start_all(struct rte_eth_dev *dev, 219 enum ena_ring_type ring_type); 220 static void ena_stats_restart(struct rte_eth_dev *dev); 221 static int ena_infos_get(struct rte_eth_dev *dev, 222 struct rte_eth_dev_info *dev_info); 223 static int ena_rss_reta_update(struct rte_eth_dev *dev, 224 struct rte_eth_rss_reta_entry64 *reta_conf, 225 uint16_t reta_size); 226 static int ena_rss_reta_query(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 static void ena_interrupt_handler_rte(void *cb_arg); 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 233 static int ena_xstats_get_names(struct rte_eth_dev *dev, 234 struct rte_eth_xstat_name *xstats_names, 235 unsigned int n); 236 static int ena_xstats_get(struct rte_eth_dev *dev, 237 struct rte_eth_xstat *stats, 238 unsigned int n); 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 240 const uint64_t *ids, 241 uint64_t *values, 242 unsigned int n); 243 static int ena_process_bool_devarg(const char *key, 244 const char *value, 245 void *opaque); 246 static int ena_parse_devargs(struct ena_adapter *adapter, 247 struct rte_devargs *devargs); 248 static int ena_copy_eni_stats(struct ena_adapter *adapter); 249 250 static const struct eth_dev_ops ena_dev_ops = { 251 .dev_configure = ena_dev_configure, 252 .dev_infos_get = ena_infos_get, 253 .rx_queue_setup = ena_rx_queue_setup, 254 .tx_queue_setup = ena_tx_queue_setup, 255 .dev_start = ena_start, 256 .dev_stop = ena_stop, 257 .link_update = ena_link_update, 258 .stats_get = ena_stats_get, 259 .xstats_get_names = ena_xstats_get_names, 260 .xstats_get = ena_xstats_get, 261 .xstats_get_by_id = ena_xstats_get_by_id, 262 .mtu_set = ena_mtu_set, 263 .rx_queue_release = ena_rx_queue_release, 264 .tx_queue_release = ena_tx_queue_release, 265 .dev_close = ena_close, 266 .dev_reset = ena_dev_reset, 267 .reta_update = ena_rss_reta_update, 268 .reta_query = ena_rss_reta_query, 269 }; 270 271 void ena_rss_key_fill(void *key, size_t size) 272 { 273 static bool key_generated; 274 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 275 size_t i; 276 277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 278 279 if (!key_generated) { 280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 281 default_key[i] = rte_rand() & 0xff; 282 key_generated = true; 283 } 284 285 rte_memcpy(key, default_key, size); 286 } 287 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 289 struct ena_com_rx_ctx *ena_rx_ctx) 290 { 291 uint64_t ol_flags = 0; 292 uint32_t packet_type = 0; 293 294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 295 packet_type |= RTE_PTYPE_L4_TCP; 296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 297 packet_type |= RTE_PTYPE_L4_UDP; 298 299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 300 packet_type |= RTE_PTYPE_L3_IPV4; 301 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 302 packet_type |= RTE_PTYPE_L3_IPV6; 303 304 if (!ena_rx_ctx->l4_csum_checked) 305 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 306 else 307 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 308 ol_flags |= PKT_RX_L4_CKSUM_BAD; 309 else 310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 311 312 if (unlikely(ena_rx_ctx->l3_csum_err)) 313 ol_flags |= PKT_RX_IP_CKSUM_BAD; 314 315 mbuf->ol_flags = ol_flags; 316 mbuf->packet_type = packet_type; 317 } 318 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 320 struct ena_com_tx_ctx *ena_tx_ctx, 321 uint64_t queue_offloads, 322 bool disable_meta_caching) 323 { 324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 325 326 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 327 (queue_offloads & QUEUE_OFFLOADS)) { 328 /* check if TSO is required */ 329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 331 ena_tx_ctx->tso_enable = true; 332 333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 334 } 335 336 /* check if L3 checksum is needed */ 337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 339 ena_tx_ctx->l3_csum_enable = true; 340 341 if (mbuf->ol_flags & PKT_TX_IPV6) { 342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 343 } else { 344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 345 346 /* set don't fragment (DF) flag */ 347 if (mbuf->packet_type & 348 (RTE_PTYPE_L4_NONFRAG 349 | RTE_PTYPE_INNER_L4_NONFRAG)) 350 ena_tx_ctx->df = true; 351 } 352 353 /* check if L4 checksum is needed */ 354 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 357 ena_tx_ctx->l4_csum_enable = true; 358 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 359 PKT_TX_UDP_CKSUM) && 360 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 362 ena_tx_ctx->l4_csum_enable = true; 363 } else { 364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 365 ena_tx_ctx->l4_csum_enable = false; 366 } 367 368 ena_meta->mss = mbuf->tso_segsz; 369 ena_meta->l3_hdr_len = mbuf->l3_len; 370 ena_meta->l3_hdr_offset = mbuf->l2_len; 371 372 ena_tx_ctx->meta_valid = true; 373 } else if (disable_meta_caching) { 374 memset(ena_meta, 0, sizeof(*ena_meta)); 375 ena_tx_ctx->meta_valid = true; 376 } else { 377 ena_tx_ctx->meta_valid = false; 378 } 379 } 380 381 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 382 { 383 if (likely(req_id < rx_ring->ring_size)) 384 return 0; 385 386 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 387 388 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 389 rx_ring->adapter->trigger_reset = true; 390 ++rx_ring->rx_stats.bad_req_id; 391 392 return -EFAULT; 393 } 394 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 396 { 397 struct ena_tx_buffer *tx_info = NULL; 398 399 if (likely(req_id < tx_ring->ring_size)) { 400 tx_info = &tx_ring->tx_buffer_info[req_id]; 401 if (likely(tx_info->mbuf)) 402 return 0; 403 } 404 405 if (tx_info) 406 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 407 else 408 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 409 410 /* Trigger device reset */ 411 ++tx_ring->tx_stats.bad_req_id; 412 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 413 tx_ring->adapter->trigger_reset = true; 414 return -EFAULT; 415 } 416 417 static void ena_config_host_info(struct ena_com_dev *ena_dev) 418 { 419 struct ena_admin_host_info *host_info; 420 int rc; 421 422 /* Allocate only the host info */ 423 rc = ena_com_allocate_host_info(ena_dev); 424 if (rc) { 425 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 426 return; 427 } 428 429 host_info = ena_dev->host_attr.host_info; 430 431 host_info->os_type = ENA_ADMIN_OS_DPDK; 432 host_info->kernel_ver = RTE_VERSION; 433 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 434 sizeof(host_info->kernel_ver_str)); 435 host_info->os_dist = RTE_VERSION; 436 strlcpy((char *)host_info->os_dist_str, rte_version(), 437 sizeof(host_info->os_dist_str)); 438 host_info->driver_version = 439 (DRV_MODULE_VER_MAJOR) | 440 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 441 (DRV_MODULE_VER_SUBMINOR << 442 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 443 host_info->num_cpus = rte_lcore_count(); 444 445 host_info->driver_supported_features = 446 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 447 448 rc = ena_com_set_host_attributes(ena_dev); 449 if (rc) { 450 if (rc == -ENA_COM_UNSUPPORTED) 451 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 452 else 453 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 454 455 goto err; 456 } 457 458 return; 459 460 err: 461 ena_com_delete_host_info(ena_dev); 462 } 463 464 /* This function calculates the number of xstats based on the current config */ 465 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 466 { 467 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + 468 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 469 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 470 } 471 472 static void ena_config_debug_area(struct ena_adapter *adapter) 473 { 474 u32 debug_area_size; 475 int rc, ss_count; 476 477 ss_count = ena_xstats_calc_num(adapter->rte_dev); 478 479 /* allocate 32 bytes for each string and 64bit for the value */ 480 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 481 482 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 483 if (rc) { 484 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 485 return; 486 } 487 488 rc = ena_com_set_host_attributes(&adapter->ena_dev); 489 if (rc) { 490 if (rc == -ENA_COM_UNSUPPORTED) 491 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 492 else 493 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 494 495 goto err; 496 } 497 498 return; 499 err: 500 ena_com_delete_debug_area(&adapter->ena_dev); 501 } 502 503 static int ena_close(struct rte_eth_dev *dev) 504 { 505 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 507 struct ena_adapter *adapter = dev->data->dev_private; 508 509 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 510 return 0; 511 512 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 513 ena_stop(dev); 514 adapter->state = ENA_ADAPTER_STATE_CLOSED; 515 516 ena_rx_queue_release_all(dev); 517 ena_tx_queue_release_all(dev); 518 519 rte_free(adapter->drv_stats); 520 adapter->drv_stats = NULL; 521 522 rte_intr_disable(intr_handle); 523 rte_intr_callback_unregister(intr_handle, 524 ena_interrupt_handler_rte, 525 adapter); 526 527 /* 528 * MAC is not allocated dynamically. Setting NULL should prevent from 529 * release of the resource in the rte_eth_dev_release_port(). 530 */ 531 dev->data->mac_addrs = NULL; 532 533 return 0; 534 } 535 536 static int 537 ena_dev_reset(struct rte_eth_dev *dev) 538 { 539 int rc = 0; 540 541 ena_destroy_device(dev); 542 rc = eth_ena_dev_init(dev); 543 if (rc) 544 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 545 546 return rc; 547 } 548 549 static int ena_rss_reta_update(struct rte_eth_dev *dev, 550 struct rte_eth_rss_reta_entry64 *reta_conf, 551 uint16_t reta_size) 552 { 553 struct ena_adapter *adapter = dev->data->dev_private; 554 struct ena_com_dev *ena_dev = &adapter->ena_dev; 555 int rc, i; 556 u16 entry_value; 557 int conf_idx; 558 int idx; 559 560 if ((reta_size == 0) || (reta_conf == NULL)) 561 return -EINVAL; 562 563 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 564 PMD_DRV_LOG(WARNING, 565 "indirection table %d is bigger than supported (%d)\n", 566 reta_size, ENA_RX_RSS_TABLE_SIZE); 567 return -EINVAL; 568 } 569 570 for (i = 0 ; i < reta_size ; i++) { 571 /* each reta_conf is for 64 entries. 572 * to support 128 we use 2 conf of 64 573 */ 574 conf_idx = i / RTE_RETA_GROUP_SIZE; 575 idx = i % RTE_RETA_GROUP_SIZE; 576 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 577 entry_value = 578 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 579 580 rc = ena_com_indirect_table_fill_entry(ena_dev, 581 i, 582 entry_value); 583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 584 PMD_DRV_LOG(ERR, 585 "Cannot fill indirect table\n"); 586 return rc; 587 } 588 } 589 } 590 591 rte_spinlock_lock(&adapter->admin_lock); 592 rc = ena_com_indirect_table_set(ena_dev); 593 rte_spinlock_unlock(&adapter->admin_lock); 594 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 595 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 596 return rc; 597 } 598 599 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 600 __func__, reta_size, adapter->rte_dev->data->port_id); 601 602 return 0; 603 } 604 605 /* Query redirection table. */ 606 static int ena_rss_reta_query(struct rte_eth_dev *dev, 607 struct rte_eth_rss_reta_entry64 *reta_conf, 608 uint16_t reta_size) 609 { 610 struct ena_adapter *adapter = dev->data->dev_private; 611 struct ena_com_dev *ena_dev = &adapter->ena_dev; 612 int rc; 613 int i; 614 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 615 int reta_conf_idx; 616 int reta_idx; 617 618 if (reta_size == 0 || reta_conf == NULL || 619 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 620 return -EINVAL; 621 622 rte_spinlock_lock(&adapter->admin_lock); 623 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 624 rte_spinlock_unlock(&adapter->admin_lock); 625 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 626 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 627 return -ENOTSUP; 628 } 629 630 for (i = 0 ; i < reta_size ; i++) { 631 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 632 reta_idx = i % RTE_RETA_GROUP_SIZE; 633 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 634 reta_conf[reta_conf_idx].reta[reta_idx] = 635 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 636 } 637 638 return 0; 639 } 640 641 static int ena_rss_init_default(struct ena_adapter *adapter) 642 { 643 struct ena_com_dev *ena_dev = &adapter->ena_dev; 644 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 645 int rc, i; 646 u32 val; 647 648 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 649 if (unlikely(rc)) { 650 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 651 goto err_rss_init; 652 } 653 654 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 655 val = i % nb_rx_queues; 656 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 657 ENA_IO_RXQ_IDX(val)); 658 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 659 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 660 goto err_fill_indir; 661 } 662 } 663 664 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 665 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 666 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 667 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 668 goto err_fill_indir; 669 } 670 671 rc = ena_com_set_default_hash_ctrl(ena_dev); 672 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 673 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 674 goto err_fill_indir; 675 } 676 677 rc = ena_com_indirect_table_set(ena_dev); 678 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 679 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 680 goto err_fill_indir; 681 } 682 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 683 adapter->rte_dev->data->port_id); 684 685 return 0; 686 687 err_fill_indir: 688 ena_com_rss_destroy(ena_dev); 689 err_rss_init: 690 691 return rc; 692 } 693 694 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 695 { 696 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 697 int nb_queues = dev->data->nb_rx_queues; 698 int i; 699 700 for (i = 0; i < nb_queues; i++) 701 ena_rx_queue_release(queues[i]); 702 } 703 704 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 705 { 706 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 707 int nb_queues = dev->data->nb_tx_queues; 708 int i; 709 710 for (i = 0; i < nb_queues; i++) 711 ena_tx_queue_release(queues[i]); 712 } 713 714 static void ena_rx_queue_release(void *queue) 715 { 716 struct ena_ring *ring = (struct ena_ring *)queue; 717 718 /* Free ring resources */ 719 if (ring->rx_buffer_info) 720 rte_free(ring->rx_buffer_info); 721 ring->rx_buffer_info = NULL; 722 723 if (ring->rx_refill_buffer) 724 rte_free(ring->rx_refill_buffer); 725 ring->rx_refill_buffer = NULL; 726 727 if (ring->empty_rx_reqs) 728 rte_free(ring->empty_rx_reqs); 729 ring->empty_rx_reqs = NULL; 730 731 ring->configured = 0; 732 733 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 734 ring->port_id, ring->id); 735 } 736 737 static void ena_tx_queue_release(void *queue) 738 { 739 struct ena_ring *ring = (struct ena_ring *)queue; 740 741 /* Free ring resources */ 742 if (ring->push_buf_intermediate_buf) 743 rte_free(ring->push_buf_intermediate_buf); 744 745 if (ring->tx_buffer_info) 746 rte_free(ring->tx_buffer_info); 747 748 if (ring->empty_tx_reqs) 749 rte_free(ring->empty_tx_reqs); 750 751 ring->empty_tx_reqs = NULL; 752 ring->tx_buffer_info = NULL; 753 ring->push_buf_intermediate_buf = NULL; 754 755 ring->configured = 0; 756 757 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 758 ring->port_id, ring->id); 759 } 760 761 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 762 { 763 unsigned int i; 764 765 for (i = 0; i < ring->ring_size; ++i) { 766 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 767 if (rx_info->mbuf) { 768 rte_mbuf_raw_free(rx_info->mbuf); 769 rx_info->mbuf = NULL; 770 } 771 } 772 } 773 774 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 775 { 776 unsigned int i; 777 778 for (i = 0; i < ring->ring_size; ++i) { 779 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 780 781 if (tx_buf->mbuf) 782 rte_pktmbuf_free(tx_buf->mbuf); 783 } 784 } 785 786 static int ena_link_update(struct rte_eth_dev *dev, 787 __rte_unused int wait_to_complete) 788 { 789 struct rte_eth_link *link = &dev->data->dev_link; 790 struct ena_adapter *adapter = dev->data->dev_private; 791 792 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 793 link->link_speed = ETH_SPEED_NUM_NONE; 794 link->link_duplex = ETH_LINK_FULL_DUPLEX; 795 796 return 0; 797 } 798 799 static int ena_queue_start_all(struct rte_eth_dev *dev, 800 enum ena_ring_type ring_type) 801 { 802 struct ena_adapter *adapter = dev->data->dev_private; 803 struct ena_ring *queues = NULL; 804 int nb_queues; 805 int i = 0; 806 int rc = 0; 807 808 if (ring_type == ENA_RING_TYPE_RX) { 809 queues = adapter->rx_ring; 810 nb_queues = dev->data->nb_rx_queues; 811 } else { 812 queues = adapter->tx_ring; 813 nb_queues = dev->data->nb_tx_queues; 814 } 815 for (i = 0; i < nb_queues; i++) { 816 if (queues[i].configured) { 817 if (ring_type == ENA_RING_TYPE_RX) { 818 ena_assert_msg( 819 dev->data->rx_queues[i] == &queues[i], 820 "Inconsistent state of rx queues\n"); 821 } else { 822 ena_assert_msg( 823 dev->data->tx_queues[i] == &queues[i], 824 "Inconsistent state of tx queues\n"); 825 } 826 827 rc = ena_queue_start(&queues[i]); 828 829 if (rc) { 830 PMD_INIT_LOG(ERR, 831 "failed to start queue %d type(%d)", 832 i, ring_type); 833 goto err; 834 } 835 } 836 } 837 838 return 0; 839 840 err: 841 while (i--) 842 if (queues[i].configured) 843 ena_queue_stop(&queues[i]); 844 845 return rc; 846 } 847 848 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 849 { 850 uint32_t max_frame_len = adapter->max_mtu; 851 852 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 853 DEV_RX_OFFLOAD_JUMBO_FRAME) 854 max_frame_len = 855 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 856 857 return max_frame_len; 858 } 859 860 static int ena_check_valid_conf(struct ena_adapter *adapter) 861 { 862 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 863 864 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 865 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 866 "max mtu: %d, min mtu: %d", 867 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 868 return ENA_COM_UNSUPPORTED; 869 } 870 871 return 0; 872 } 873 874 static int 875 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 876 bool use_large_llq_hdr) 877 { 878 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 879 struct ena_com_dev *ena_dev = ctx->ena_dev; 880 uint32_t max_tx_queue_size; 881 uint32_t max_rx_queue_size; 882 883 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 884 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 885 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 886 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 887 max_queue_ext->max_rx_sq_depth); 888 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 889 890 if (ena_dev->tx_mem_queue_type == 891 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 892 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 893 llq->max_llq_depth); 894 } else { 895 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 896 max_queue_ext->max_tx_sq_depth); 897 } 898 899 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 900 max_queue_ext->max_per_packet_rx_descs); 901 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 902 max_queue_ext->max_per_packet_tx_descs); 903 } else { 904 struct ena_admin_queue_feature_desc *max_queues = 905 &ctx->get_feat_ctx->max_queues; 906 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 907 max_queues->max_sq_depth); 908 max_tx_queue_size = max_queues->max_cq_depth; 909 910 if (ena_dev->tx_mem_queue_type == 911 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 912 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 913 llq->max_llq_depth); 914 } else { 915 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 916 max_queues->max_sq_depth); 917 } 918 919 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 920 max_queues->max_packet_rx_descs); 921 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 922 max_queues->max_packet_tx_descs); 923 } 924 925 /* Round down to the nearest power of 2 */ 926 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 927 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 928 929 if (use_large_llq_hdr) { 930 if ((llq->entry_size_ctrl_supported & 931 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 932 (ena_dev->tx_mem_queue_type == 933 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 934 max_tx_queue_size /= 2; 935 PMD_INIT_LOG(INFO, 936 "Forcing large headers and decreasing maximum TX queue size to %d\n", 937 max_tx_queue_size); 938 } else { 939 PMD_INIT_LOG(ERR, 940 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 941 } 942 } 943 944 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 945 PMD_INIT_LOG(ERR, "Invalid queue size"); 946 return -EFAULT; 947 } 948 949 ctx->max_tx_queue_size = max_tx_queue_size; 950 ctx->max_rx_queue_size = max_rx_queue_size; 951 952 return 0; 953 } 954 955 static void ena_stats_restart(struct rte_eth_dev *dev) 956 { 957 struct ena_adapter *adapter = dev->data->dev_private; 958 959 rte_atomic64_init(&adapter->drv_stats->ierrors); 960 rte_atomic64_init(&adapter->drv_stats->oerrors); 961 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 962 adapter->drv_stats->rx_drops = 0; 963 } 964 965 static int ena_stats_get(struct rte_eth_dev *dev, 966 struct rte_eth_stats *stats) 967 { 968 struct ena_admin_basic_stats ena_stats; 969 struct ena_adapter *adapter = dev->data->dev_private; 970 struct ena_com_dev *ena_dev = &adapter->ena_dev; 971 int rc; 972 int i; 973 int max_rings_stats; 974 975 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 976 return -ENOTSUP; 977 978 memset(&ena_stats, 0, sizeof(ena_stats)); 979 980 rte_spinlock_lock(&adapter->admin_lock); 981 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 982 rte_spinlock_unlock(&adapter->admin_lock); 983 if (unlikely(rc)) { 984 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 985 return rc; 986 } 987 988 /* Set of basic statistics from ENA */ 989 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 990 ena_stats.rx_pkts_low); 991 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 992 ena_stats.tx_pkts_low); 993 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 994 ena_stats.rx_bytes_low); 995 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 996 ena_stats.tx_bytes_low); 997 998 /* Driver related stats */ 999 stats->imissed = adapter->drv_stats->rx_drops; 1000 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 1001 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 1002 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 1003 1004 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 1005 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1006 for (i = 0; i < max_rings_stats; ++i) { 1007 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 1008 1009 stats->q_ibytes[i] = rx_stats->bytes; 1010 stats->q_ipackets[i] = rx_stats->cnt; 1011 stats->q_errors[i] = rx_stats->bad_desc_num + 1012 rx_stats->bad_req_id; 1013 } 1014 1015 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 1016 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1017 for (i = 0; i < max_rings_stats; ++i) { 1018 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 1019 1020 stats->q_obytes[i] = tx_stats->bytes; 1021 stats->q_opackets[i] = tx_stats->cnt; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1028 { 1029 struct ena_adapter *adapter; 1030 struct ena_com_dev *ena_dev; 1031 int rc = 0; 1032 1033 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1034 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1035 adapter = dev->data->dev_private; 1036 1037 ena_dev = &adapter->ena_dev; 1038 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1039 1040 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1041 PMD_DRV_LOG(ERR, 1042 "Invalid MTU setting. new_mtu: %d " 1043 "max mtu: %d min mtu: %d\n", 1044 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1045 return -EINVAL; 1046 } 1047 1048 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1049 if (rc) 1050 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1051 else 1052 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1053 1054 return rc; 1055 } 1056 1057 static int ena_start(struct rte_eth_dev *dev) 1058 { 1059 struct ena_adapter *adapter = dev->data->dev_private; 1060 uint64_t ticks; 1061 int rc = 0; 1062 1063 rc = ena_check_valid_conf(adapter); 1064 if (rc) 1065 return rc; 1066 1067 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1068 if (rc) 1069 return rc; 1070 1071 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1072 if (rc) 1073 goto err_start_tx; 1074 1075 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1076 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1077 rc = ena_rss_init_default(adapter); 1078 if (rc) 1079 goto err_rss_init; 1080 } 1081 1082 ena_stats_restart(dev); 1083 1084 adapter->timestamp_wd = rte_get_timer_cycles(); 1085 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1086 1087 ticks = rte_get_timer_hz(); 1088 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1089 ena_timer_wd_callback, adapter); 1090 1091 ++adapter->dev_stats.dev_start; 1092 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1093 1094 return 0; 1095 1096 err_rss_init: 1097 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1098 err_start_tx: 1099 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1100 return rc; 1101 } 1102 1103 static void ena_stop(struct rte_eth_dev *dev) 1104 { 1105 struct ena_adapter *adapter = dev->data->dev_private; 1106 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1107 int rc; 1108 1109 rte_timer_stop_sync(&adapter->timer_wd); 1110 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1111 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1112 1113 if (adapter->trigger_reset) { 1114 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1115 if (rc) 1116 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1117 } 1118 1119 ++adapter->dev_stats.dev_stop; 1120 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1121 dev->data->dev_started = 0; 1122 } 1123 1124 static int ena_create_io_queue(struct ena_ring *ring) 1125 { 1126 struct ena_adapter *adapter; 1127 struct ena_com_dev *ena_dev; 1128 struct ena_com_create_io_ctx ctx = 1129 /* policy set to _HOST just to satisfy icc compiler */ 1130 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1131 0, 0, 0, 0, 0 }; 1132 uint16_t ena_qid; 1133 unsigned int i; 1134 int rc; 1135 1136 adapter = ring->adapter; 1137 ena_dev = &adapter->ena_dev; 1138 1139 if (ring->type == ENA_RING_TYPE_TX) { 1140 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1141 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1142 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1143 for (i = 0; i < ring->ring_size; i++) 1144 ring->empty_tx_reqs[i] = i; 1145 } else { 1146 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1147 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1148 for (i = 0; i < ring->ring_size; i++) 1149 ring->empty_rx_reqs[i] = i; 1150 } 1151 ctx.queue_size = ring->ring_size; 1152 ctx.qid = ena_qid; 1153 ctx.msix_vector = -1; /* interrupts not used */ 1154 ctx.numa_node = ring->numa_socket_id; 1155 1156 rc = ena_com_create_io_queue(ena_dev, &ctx); 1157 if (rc) { 1158 PMD_DRV_LOG(ERR, 1159 "failed to create io queue #%d (qid:%d) rc: %d\n", 1160 ring->id, ena_qid, rc); 1161 return rc; 1162 } 1163 1164 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1165 &ring->ena_com_io_sq, 1166 &ring->ena_com_io_cq); 1167 if (rc) { 1168 PMD_DRV_LOG(ERR, 1169 "Failed to get io queue handlers. queue num %d rc: %d\n", 1170 ring->id, rc); 1171 ena_com_destroy_io_queue(ena_dev, ena_qid); 1172 return rc; 1173 } 1174 1175 if (ring->type == ENA_RING_TYPE_TX) 1176 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1177 1178 return 0; 1179 } 1180 1181 static void ena_queue_stop(struct ena_ring *ring) 1182 { 1183 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1184 1185 if (ring->type == ENA_RING_TYPE_RX) { 1186 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1187 ena_rx_queue_release_bufs(ring); 1188 } else { 1189 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1190 ena_tx_queue_release_bufs(ring); 1191 } 1192 } 1193 1194 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1195 enum ena_ring_type ring_type) 1196 { 1197 struct ena_adapter *adapter = dev->data->dev_private; 1198 struct ena_ring *queues = NULL; 1199 uint16_t nb_queues, i; 1200 1201 if (ring_type == ENA_RING_TYPE_RX) { 1202 queues = adapter->rx_ring; 1203 nb_queues = dev->data->nb_rx_queues; 1204 } else { 1205 queues = adapter->tx_ring; 1206 nb_queues = dev->data->nb_tx_queues; 1207 } 1208 1209 for (i = 0; i < nb_queues; ++i) 1210 if (queues[i].configured) 1211 ena_queue_stop(&queues[i]); 1212 } 1213 1214 static int ena_queue_start(struct ena_ring *ring) 1215 { 1216 int rc, bufs_num; 1217 1218 ena_assert_msg(ring->configured == 1, 1219 "Trying to start unconfigured queue\n"); 1220 1221 rc = ena_create_io_queue(ring); 1222 if (rc) { 1223 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1224 return rc; 1225 } 1226 1227 ring->next_to_clean = 0; 1228 ring->next_to_use = 0; 1229 1230 if (ring->type == ENA_RING_TYPE_TX) { 1231 ring->tx_stats.available_desc = 1232 ena_com_free_q_entries(ring->ena_com_io_sq); 1233 return 0; 1234 } 1235 1236 bufs_num = ring->ring_size - 1; 1237 rc = ena_populate_rx_queue(ring, bufs_num); 1238 if (rc != bufs_num) { 1239 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1240 ENA_IO_RXQ_IDX(ring->id)); 1241 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1242 return ENA_COM_FAULT; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1249 uint16_t queue_idx, 1250 uint16_t nb_desc, 1251 unsigned int socket_id, 1252 const struct rte_eth_txconf *tx_conf) 1253 { 1254 struct ena_ring *txq = NULL; 1255 struct ena_adapter *adapter = dev->data->dev_private; 1256 unsigned int i; 1257 1258 txq = &adapter->tx_ring[queue_idx]; 1259 1260 if (txq->configured) { 1261 PMD_DRV_LOG(CRIT, 1262 "API violation. Queue %d is already configured\n", 1263 queue_idx); 1264 return ENA_COM_FAULT; 1265 } 1266 1267 if (!rte_is_power_of_2(nb_desc)) { 1268 PMD_DRV_LOG(ERR, 1269 "Unsupported size of TX queue: %d is not a power of 2.\n", 1270 nb_desc); 1271 return -EINVAL; 1272 } 1273 1274 if (nb_desc > adapter->max_tx_ring_size) { 1275 PMD_DRV_LOG(ERR, 1276 "Unsupported size of TX queue (max size: %d)\n", 1277 adapter->max_tx_ring_size); 1278 return -EINVAL; 1279 } 1280 1281 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1282 nb_desc = adapter->max_tx_ring_size; 1283 1284 txq->port_id = dev->data->port_id; 1285 txq->next_to_clean = 0; 1286 txq->next_to_use = 0; 1287 txq->ring_size = nb_desc; 1288 txq->size_mask = nb_desc - 1; 1289 txq->numa_socket_id = socket_id; 1290 1291 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1292 sizeof(struct ena_tx_buffer) * 1293 txq->ring_size, 1294 RTE_CACHE_LINE_SIZE); 1295 if (!txq->tx_buffer_info) { 1296 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1297 return -ENOMEM; 1298 } 1299 1300 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1301 sizeof(u16) * txq->ring_size, 1302 RTE_CACHE_LINE_SIZE); 1303 if (!txq->empty_tx_reqs) { 1304 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1305 rte_free(txq->tx_buffer_info); 1306 return -ENOMEM; 1307 } 1308 1309 txq->push_buf_intermediate_buf = 1310 rte_zmalloc("txq->push_buf_intermediate_buf", 1311 txq->tx_max_header_size, 1312 RTE_CACHE_LINE_SIZE); 1313 if (!txq->push_buf_intermediate_buf) { 1314 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1315 rte_free(txq->tx_buffer_info); 1316 rte_free(txq->empty_tx_reqs); 1317 return -ENOMEM; 1318 } 1319 1320 for (i = 0; i < txq->ring_size; i++) 1321 txq->empty_tx_reqs[i] = i; 1322 1323 if (tx_conf != NULL) { 1324 txq->offloads = 1325 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1326 } 1327 /* Store pointer to this queue in upper layer */ 1328 txq->configured = 1; 1329 dev->data->tx_queues[queue_idx] = txq; 1330 1331 return 0; 1332 } 1333 1334 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1335 uint16_t queue_idx, 1336 uint16_t nb_desc, 1337 unsigned int socket_id, 1338 __rte_unused const struct rte_eth_rxconf *rx_conf, 1339 struct rte_mempool *mp) 1340 { 1341 struct ena_adapter *adapter = dev->data->dev_private; 1342 struct ena_ring *rxq = NULL; 1343 size_t buffer_size; 1344 int i; 1345 1346 rxq = &adapter->rx_ring[queue_idx]; 1347 if (rxq->configured) { 1348 PMD_DRV_LOG(CRIT, 1349 "API violation. Queue %d is already configured\n", 1350 queue_idx); 1351 return ENA_COM_FAULT; 1352 } 1353 1354 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1355 nb_desc = adapter->max_rx_ring_size; 1356 1357 if (!rte_is_power_of_2(nb_desc)) { 1358 PMD_DRV_LOG(ERR, 1359 "Unsupported size of RX queue: %d is not a power of 2.\n", 1360 nb_desc); 1361 return -EINVAL; 1362 } 1363 1364 if (nb_desc > adapter->max_rx_ring_size) { 1365 PMD_DRV_LOG(ERR, 1366 "Unsupported size of RX queue (max size: %d)\n", 1367 adapter->max_rx_ring_size); 1368 return -EINVAL; 1369 } 1370 1371 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1372 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1373 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1374 PMD_DRV_LOG(ERR, 1375 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1376 buffer_size, ENA_RX_BUF_MIN_SIZE); 1377 return -EINVAL; 1378 } 1379 1380 rxq->port_id = dev->data->port_id; 1381 rxq->next_to_clean = 0; 1382 rxq->next_to_use = 0; 1383 rxq->ring_size = nb_desc; 1384 rxq->size_mask = nb_desc - 1; 1385 rxq->numa_socket_id = socket_id; 1386 rxq->mb_pool = mp; 1387 1388 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1389 sizeof(struct ena_rx_buffer) * nb_desc, 1390 RTE_CACHE_LINE_SIZE); 1391 if (!rxq->rx_buffer_info) { 1392 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1393 return -ENOMEM; 1394 } 1395 1396 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1397 sizeof(struct rte_mbuf *) * nb_desc, 1398 RTE_CACHE_LINE_SIZE); 1399 1400 if (!rxq->rx_refill_buffer) { 1401 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1402 rte_free(rxq->rx_buffer_info); 1403 rxq->rx_buffer_info = NULL; 1404 return -ENOMEM; 1405 } 1406 1407 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1408 sizeof(uint16_t) * nb_desc, 1409 RTE_CACHE_LINE_SIZE); 1410 if (!rxq->empty_rx_reqs) { 1411 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1412 rte_free(rxq->rx_buffer_info); 1413 rxq->rx_buffer_info = NULL; 1414 rte_free(rxq->rx_refill_buffer); 1415 rxq->rx_refill_buffer = NULL; 1416 return -ENOMEM; 1417 } 1418 1419 for (i = 0; i < nb_desc; i++) 1420 rxq->empty_rx_reqs[i] = i; 1421 1422 /* Store pointer to this queue in upper layer */ 1423 rxq->configured = 1; 1424 dev->data->rx_queues[queue_idx] = rxq; 1425 1426 return 0; 1427 } 1428 1429 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1430 struct rte_mbuf *mbuf, uint16_t id) 1431 { 1432 struct ena_com_buf ebuf; 1433 int rc; 1434 1435 /* prepare physical address for DMA transaction */ 1436 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1437 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1438 1439 /* pass resource to device */ 1440 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1441 if (unlikely(rc != 0)) 1442 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1443 1444 return rc; 1445 } 1446 1447 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1448 { 1449 unsigned int i; 1450 int rc; 1451 uint16_t next_to_use = rxq->next_to_use; 1452 uint16_t in_use, req_id; 1453 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1454 1455 if (unlikely(!count)) 1456 return 0; 1457 1458 in_use = rxq->ring_size - 1 - 1459 ena_com_free_q_entries(rxq->ena_com_io_sq); 1460 ena_assert_msg(((in_use + count) < rxq->ring_size), 1461 "bad ring state\n"); 1462 1463 /* get resources for incoming packets */ 1464 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1465 if (unlikely(rc < 0)) { 1466 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1467 ++rxq->rx_stats.mbuf_alloc_fail; 1468 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1469 return 0; 1470 } 1471 1472 for (i = 0; i < count; i++) { 1473 struct rte_mbuf *mbuf = mbufs[i]; 1474 struct ena_rx_buffer *rx_info; 1475 1476 if (likely((i + 4) < count)) 1477 rte_prefetch0(mbufs[i + 4]); 1478 1479 req_id = rxq->empty_rx_reqs[next_to_use]; 1480 rc = validate_rx_req_id(rxq, req_id); 1481 if (unlikely(rc)) 1482 break; 1483 1484 rx_info = &rxq->rx_buffer_info[req_id]; 1485 1486 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1487 if (unlikely(rc != 0)) 1488 break; 1489 1490 rx_info->mbuf = mbuf; 1491 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1492 } 1493 1494 if (unlikely(i < count)) { 1495 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1496 "buffers (from %d)\n", rxq->id, i, count); 1497 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1498 count - i); 1499 ++rxq->rx_stats.refill_partial; 1500 } 1501 1502 /* When we submitted free recources to device... */ 1503 if (likely(i > 0)) { 1504 /* ...let HW know that it can fill buffers with data. */ 1505 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1506 1507 rxq->next_to_use = next_to_use; 1508 } 1509 1510 return i; 1511 } 1512 1513 static int ena_device_init(struct ena_com_dev *ena_dev, 1514 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1515 bool *wd_state) 1516 { 1517 uint32_t aenq_groups; 1518 int rc; 1519 bool readless_supported; 1520 1521 /* Initialize mmio registers */ 1522 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1523 if (rc) { 1524 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1525 return rc; 1526 } 1527 1528 /* The PCIe configuration space revision id indicate if mmio reg 1529 * read is disabled. 1530 */ 1531 readless_supported = 1532 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1533 & ENA_MMIO_DISABLE_REG_READ); 1534 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1535 1536 /* reset device */ 1537 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1538 if (rc) { 1539 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1540 goto err_mmio_read_less; 1541 } 1542 1543 /* check FW version */ 1544 rc = ena_com_validate_version(ena_dev); 1545 if (rc) { 1546 PMD_DRV_LOG(ERR, "device version is too low\n"); 1547 goto err_mmio_read_less; 1548 } 1549 1550 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1551 1552 /* ENA device administration layer init */ 1553 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1554 if (rc) { 1555 PMD_DRV_LOG(ERR, 1556 "cannot initialize ena admin queue with device\n"); 1557 goto err_mmio_read_less; 1558 } 1559 1560 /* To enable the msix interrupts the driver needs to know the number 1561 * of queues. So the driver uses polling mode to retrieve this 1562 * information. 1563 */ 1564 ena_com_set_admin_polling_mode(ena_dev, true); 1565 1566 ena_config_host_info(ena_dev); 1567 1568 /* Get Device Attributes and features */ 1569 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1570 if (rc) { 1571 PMD_DRV_LOG(ERR, 1572 "cannot get attribute for ena device rc= %d\n", rc); 1573 goto err_admin_init; 1574 } 1575 1576 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1577 BIT(ENA_ADMIN_NOTIFICATION) | 1578 BIT(ENA_ADMIN_KEEP_ALIVE) | 1579 BIT(ENA_ADMIN_FATAL_ERROR) | 1580 BIT(ENA_ADMIN_WARNING); 1581 1582 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1583 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1584 if (rc) { 1585 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1586 goto err_admin_init; 1587 } 1588 1589 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1590 1591 return 0; 1592 1593 err_admin_init: 1594 ena_com_admin_destroy(ena_dev); 1595 1596 err_mmio_read_less: 1597 ena_com_mmio_reg_read_request_destroy(ena_dev); 1598 1599 return rc; 1600 } 1601 1602 static void ena_interrupt_handler_rte(void *cb_arg) 1603 { 1604 struct ena_adapter *adapter = cb_arg; 1605 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1606 1607 ena_com_admin_q_comp_intr_handler(ena_dev); 1608 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1609 ena_com_aenq_intr_handler(ena_dev, adapter); 1610 } 1611 1612 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1613 { 1614 if (!adapter->wd_state) 1615 return; 1616 1617 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1618 return; 1619 1620 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1621 adapter->keep_alive_timeout)) { 1622 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1623 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1624 adapter->trigger_reset = true; 1625 ++adapter->dev_stats.wd_expired; 1626 } 1627 } 1628 1629 /* Check if admin queue is enabled */ 1630 static void check_for_admin_com_state(struct ena_adapter *adapter) 1631 { 1632 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1633 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1634 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1635 adapter->trigger_reset = true; 1636 } 1637 } 1638 1639 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1640 void *arg) 1641 { 1642 struct ena_adapter *adapter = arg; 1643 struct rte_eth_dev *dev = adapter->rte_dev; 1644 1645 check_for_missing_keep_alive(adapter); 1646 check_for_admin_com_state(adapter); 1647 1648 if (unlikely(adapter->trigger_reset)) { 1649 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1650 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1651 NULL); 1652 } 1653 } 1654 1655 static inline void 1656 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1657 struct ena_admin_feature_llq_desc *llq, 1658 bool use_large_llq_hdr) 1659 { 1660 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1661 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1662 llq_config->llq_num_decs_before_header = 1663 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1664 1665 if (use_large_llq_hdr && 1666 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1667 llq_config->llq_ring_entry_size = 1668 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1669 llq_config->llq_ring_entry_size_value = 256; 1670 } else { 1671 llq_config->llq_ring_entry_size = 1672 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1673 llq_config->llq_ring_entry_size_value = 128; 1674 } 1675 } 1676 1677 static int 1678 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1679 struct ena_com_dev *ena_dev, 1680 struct ena_admin_feature_llq_desc *llq, 1681 struct ena_llq_configurations *llq_default_configurations) 1682 { 1683 int rc; 1684 u32 llq_feature_mask; 1685 1686 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1687 if (!(ena_dev->supported_features & llq_feature_mask)) { 1688 PMD_DRV_LOG(INFO, 1689 "LLQ is not supported. Fallback to host mode policy.\n"); 1690 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1691 return 0; 1692 } 1693 1694 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1695 if (unlikely(rc)) { 1696 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1697 "Fallback to host mode policy."); 1698 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1699 return 0; 1700 } 1701 1702 /* Nothing to config, exit */ 1703 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1704 return 0; 1705 1706 if (!adapter->dev_mem_base) { 1707 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1708 "Fallback to host mode policy.\n."); 1709 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1710 return 0; 1711 } 1712 1713 ena_dev->mem_bar = adapter->dev_mem_base; 1714 1715 return 0; 1716 } 1717 1718 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1719 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1720 { 1721 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1722 1723 /* Regular queues capabilities */ 1724 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1725 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1726 &get_feat_ctx->max_queue_ext.max_queue_ext; 1727 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1728 max_queue_ext->max_rx_cq_num); 1729 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1730 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1731 } else { 1732 struct ena_admin_queue_feature_desc *max_queues = 1733 &get_feat_ctx->max_queues; 1734 io_tx_sq_num = max_queues->max_sq_num; 1735 io_tx_cq_num = max_queues->max_cq_num; 1736 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1737 } 1738 1739 /* In case of LLQ use the llq number in the get feature cmd */ 1740 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1741 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1742 1743 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1744 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1745 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1746 1747 if (unlikely(max_num_io_queues == 0)) { 1748 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1749 return -EFAULT; 1750 } 1751 1752 return max_num_io_queues; 1753 } 1754 1755 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1756 { 1757 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1758 struct rte_pci_device *pci_dev; 1759 struct rte_intr_handle *intr_handle; 1760 struct ena_adapter *adapter = eth_dev->data->dev_private; 1761 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1762 struct ena_com_dev_get_features_ctx get_feat_ctx; 1763 struct ena_llq_configurations llq_config; 1764 const char *queue_type_str; 1765 uint32_t max_num_io_queues; 1766 int rc; 1767 static int adapters_found; 1768 bool disable_meta_caching; 1769 bool wd_state = false; 1770 1771 eth_dev->dev_ops = &ena_dev_ops; 1772 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1773 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1774 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1775 1776 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1777 return 0; 1778 1779 memset(adapter, 0, sizeof(struct ena_adapter)); 1780 ena_dev = &adapter->ena_dev; 1781 1782 adapter->rte_eth_dev_data = eth_dev->data; 1783 adapter->rte_dev = eth_dev; 1784 1785 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1786 adapter->pdev = pci_dev; 1787 1788 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1789 pci_dev->addr.domain, 1790 pci_dev->addr.bus, 1791 pci_dev->addr.devid, 1792 pci_dev->addr.function); 1793 1794 intr_handle = &pci_dev->intr_handle; 1795 1796 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1797 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1798 1799 if (!adapter->regs) { 1800 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1801 ENA_REGS_BAR); 1802 return -ENXIO; 1803 } 1804 1805 ena_dev->reg_bar = adapter->regs; 1806 ena_dev->dmadev = adapter->pdev; 1807 1808 adapter->id_number = adapters_found; 1809 1810 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1811 adapter->id_number); 1812 1813 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1814 if (rc != 0) { 1815 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1816 goto err; 1817 } 1818 1819 /* device specific initialization routine */ 1820 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1821 if (rc) { 1822 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1823 goto err; 1824 } 1825 adapter->wd_state = wd_state; 1826 1827 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1828 adapter->use_large_llq_hdr); 1829 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1830 &get_feat_ctx.llq, &llq_config); 1831 if (unlikely(rc)) { 1832 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1833 return rc; 1834 } 1835 1836 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1837 queue_type_str = "Regular"; 1838 else 1839 queue_type_str = "Low latency"; 1840 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1841 1842 calc_queue_ctx.ena_dev = ena_dev; 1843 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1844 1845 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1846 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1847 adapter->use_large_llq_hdr); 1848 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1849 rc = -EFAULT; 1850 goto err_device_destroy; 1851 } 1852 1853 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1854 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1855 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1856 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1857 adapter->max_num_io_queues = max_num_io_queues; 1858 1859 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1860 disable_meta_caching = 1861 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 1862 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 1863 } else { 1864 disable_meta_caching = false; 1865 } 1866 1867 /* prepare ring structures */ 1868 ena_init_rings(adapter, disable_meta_caching); 1869 1870 ena_config_debug_area(adapter); 1871 1872 /* Set max MTU for this device */ 1873 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1874 1875 /* set device support for offloads */ 1876 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1877 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1878 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1879 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1880 adapter->offloads.rx_csum_supported = 1881 (get_feat_ctx.offload.rx_supported & 1882 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1883 1884 /* Copy MAC address and point DPDK to it */ 1885 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1886 rte_ether_addr_copy((struct rte_ether_addr *) 1887 get_feat_ctx.dev_attr.mac_addr, 1888 (struct rte_ether_addr *)adapter->mac_addr); 1889 1890 adapter->drv_stats = rte_zmalloc("adapter stats", 1891 sizeof(*adapter->drv_stats), 1892 RTE_CACHE_LINE_SIZE); 1893 if (!adapter->drv_stats) { 1894 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1895 rc = -ENOMEM; 1896 goto err_delete_debug_area; 1897 } 1898 1899 rte_spinlock_init(&adapter->admin_lock); 1900 1901 rte_intr_callback_register(intr_handle, 1902 ena_interrupt_handler_rte, 1903 adapter); 1904 rte_intr_enable(intr_handle); 1905 ena_com_set_admin_polling_mode(ena_dev, false); 1906 ena_com_admin_aenq_enable(ena_dev); 1907 1908 if (adapters_found == 0) 1909 rte_timer_subsystem_init(); 1910 rte_timer_init(&adapter->timer_wd); 1911 1912 adapters_found++; 1913 adapter->state = ENA_ADAPTER_STATE_INIT; 1914 1915 return 0; 1916 1917 err_delete_debug_area: 1918 ena_com_delete_debug_area(ena_dev); 1919 1920 err_device_destroy: 1921 ena_com_delete_host_info(ena_dev); 1922 ena_com_admin_destroy(ena_dev); 1923 1924 err: 1925 return rc; 1926 } 1927 1928 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1929 { 1930 struct ena_adapter *adapter = eth_dev->data->dev_private; 1931 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1932 1933 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1934 return; 1935 1936 ena_com_set_admin_running_state(ena_dev, false); 1937 1938 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1939 ena_close(eth_dev); 1940 1941 ena_com_delete_debug_area(ena_dev); 1942 ena_com_delete_host_info(ena_dev); 1943 1944 ena_com_abort_admin_commands(ena_dev); 1945 ena_com_wait_for_abort_completion(ena_dev); 1946 ena_com_admin_destroy(ena_dev); 1947 ena_com_mmio_reg_read_request_destroy(ena_dev); 1948 1949 adapter->state = ENA_ADAPTER_STATE_FREE; 1950 } 1951 1952 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1953 { 1954 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1955 return 0; 1956 1957 ena_destroy_device(eth_dev); 1958 1959 eth_dev->dev_ops = NULL; 1960 eth_dev->rx_pkt_burst = NULL; 1961 eth_dev->tx_pkt_burst = NULL; 1962 eth_dev->tx_pkt_prepare = NULL; 1963 1964 return 0; 1965 } 1966 1967 static int ena_dev_configure(struct rte_eth_dev *dev) 1968 { 1969 struct ena_adapter *adapter = dev->data->dev_private; 1970 1971 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1972 1973 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1974 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1975 return 0; 1976 } 1977 1978 static void ena_init_rings(struct ena_adapter *adapter, 1979 bool disable_meta_caching) 1980 { 1981 size_t i; 1982 1983 for (i = 0; i < adapter->max_num_io_queues; i++) { 1984 struct ena_ring *ring = &adapter->tx_ring[i]; 1985 1986 ring->configured = 0; 1987 ring->type = ENA_RING_TYPE_TX; 1988 ring->adapter = adapter; 1989 ring->id = i; 1990 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1991 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1992 ring->sgl_size = adapter->max_tx_sgl_size; 1993 ring->disable_meta_caching = disable_meta_caching; 1994 } 1995 1996 for (i = 0; i < adapter->max_num_io_queues; i++) { 1997 struct ena_ring *ring = &adapter->rx_ring[i]; 1998 1999 ring->configured = 0; 2000 ring->type = ENA_RING_TYPE_RX; 2001 ring->adapter = adapter; 2002 ring->id = i; 2003 ring->sgl_size = adapter->max_rx_sgl_size; 2004 } 2005 } 2006 2007 static int ena_infos_get(struct rte_eth_dev *dev, 2008 struct rte_eth_dev_info *dev_info) 2009 { 2010 struct ena_adapter *adapter; 2011 struct ena_com_dev *ena_dev; 2012 uint64_t rx_feat = 0, tx_feat = 0; 2013 2014 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 2015 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 2016 adapter = dev->data->dev_private; 2017 2018 ena_dev = &adapter->ena_dev; 2019 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 2020 2021 dev_info->speed_capa = 2022 ETH_LINK_SPEED_1G | 2023 ETH_LINK_SPEED_2_5G | 2024 ETH_LINK_SPEED_5G | 2025 ETH_LINK_SPEED_10G | 2026 ETH_LINK_SPEED_25G | 2027 ETH_LINK_SPEED_40G | 2028 ETH_LINK_SPEED_50G | 2029 ETH_LINK_SPEED_100G; 2030 2031 /* Set Tx & Rx features available for device */ 2032 if (adapter->offloads.tso4_supported) 2033 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 2034 2035 if (adapter->offloads.tx_csum_supported) 2036 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 2037 DEV_TX_OFFLOAD_UDP_CKSUM | 2038 DEV_TX_OFFLOAD_TCP_CKSUM; 2039 2040 if (adapter->offloads.rx_csum_supported) 2041 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 2042 DEV_RX_OFFLOAD_UDP_CKSUM | 2043 DEV_RX_OFFLOAD_TCP_CKSUM; 2044 2045 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2046 2047 /* Inform framework about available features */ 2048 dev_info->rx_offload_capa = rx_feat; 2049 dev_info->rx_queue_offload_capa = rx_feat; 2050 dev_info->tx_offload_capa = tx_feat; 2051 dev_info->tx_queue_offload_capa = tx_feat; 2052 2053 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2054 ETH_RSS_UDP; 2055 2056 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2057 dev_info->max_rx_pktlen = adapter->max_mtu; 2058 dev_info->max_mac_addrs = 1; 2059 2060 dev_info->max_rx_queues = adapter->max_num_io_queues; 2061 dev_info->max_tx_queues = adapter->max_num_io_queues; 2062 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2063 2064 adapter->tx_supported_offloads = tx_feat; 2065 adapter->rx_supported_offloads = rx_feat; 2066 2067 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2068 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2069 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2070 adapter->max_rx_sgl_size); 2071 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2072 adapter->max_rx_sgl_size); 2073 2074 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2075 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2076 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2077 adapter->max_tx_sgl_size); 2078 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2079 adapter->max_tx_sgl_size); 2080 2081 return 0; 2082 } 2083 2084 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 2085 { 2086 mbuf->data_len = len; 2087 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2088 mbuf->refcnt = 1; 2089 mbuf->next = NULL; 2090 } 2091 2092 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 2093 struct ena_com_rx_buf_info *ena_bufs, 2094 uint32_t descs, 2095 uint16_t *next_to_clean, 2096 uint8_t offset) 2097 { 2098 struct rte_mbuf *mbuf; 2099 struct rte_mbuf *mbuf_head; 2100 struct ena_rx_buffer *rx_info; 2101 int rc; 2102 uint16_t ntc, len, req_id, buf = 0; 2103 2104 if (unlikely(descs == 0)) 2105 return NULL; 2106 2107 ntc = *next_to_clean; 2108 2109 len = ena_bufs[buf].len; 2110 req_id = ena_bufs[buf].req_id; 2111 if (unlikely(validate_rx_req_id(rx_ring, req_id))) 2112 return NULL; 2113 2114 rx_info = &rx_ring->rx_buffer_info[req_id]; 2115 2116 mbuf = rx_info->mbuf; 2117 RTE_ASSERT(mbuf != NULL); 2118 2119 ena_init_rx_mbuf(mbuf, len); 2120 2121 /* Fill the mbuf head with the data specific for 1st segment. */ 2122 mbuf_head = mbuf; 2123 mbuf_head->nb_segs = descs; 2124 mbuf_head->port = rx_ring->port_id; 2125 mbuf_head->pkt_len = len; 2126 mbuf_head->data_off += offset; 2127 2128 rx_info->mbuf = NULL; 2129 rx_ring->empty_rx_reqs[ntc] = req_id; 2130 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2131 2132 while (--descs) { 2133 ++buf; 2134 len = ena_bufs[buf].len; 2135 req_id = ena_bufs[buf].req_id; 2136 if (unlikely(validate_rx_req_id(rx_ring, req_id))) { 2137 rte_mbuf_raw_free(mbuf_head); 2138 return NULL; 2139 } 2140 2141 rx_info = &rx_ring->rx_buffer_info[req_id]; 2142 RTE_ASSERT(rx_info->mbuf != NULL); 2143 2144 if (unlikely(len == 0)) { 2145 /* 2146 * Some devices can pass descriptor with the length 0. 2147 * To avoid confusion, the PMD is simply putting the 2148 * descriptor back, as it was never used. We'll avoid 2149 * mbuf allocation that way. 2150 */ 2151 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2152 rx_info->mbuf, req_id); 2153 if (unlikely(rc != 0)) { 2154 /* Free the mbuf in case of an error. */ 2155 rte_mbuf_raw_free(rx_info->mbuf); 2156 } else { 2157 /* 2158 * If there was no error, just exit the loop as 2159 * 0 length descriptor is always the last one. 2160 */ 2161 break; 2162 } 2163 } else { 2164 /* Create an mbuf chain. */ 2165 mbuf->next = rx_info->mbuf; 2166 mbuf = mbuf->next; 2167 2168 ena_init_rx_mbuf(mbuf, len); 2169 mbuf_head->pkt_len += len; 2170 } 2171 2172 /* 2173 * Mark the descriptor as depleted and perform necessary 2174 * cleanup. 2175 * This code will execute in two cases: 2176 * 1. Descriptor len was greater than 0 - normal situation. 2177 * 2. Descriptor len was 0 and we failed to add the descriptor 2178 * to the device. In that situation, we should try to add 2179 * the mbuf again in the populate routine and mark the 2180 * descriptor as used up by the device. 2181 */ 2182 rx_info->mbuf = NULL; 2183 rx_ring->empty_rx_reqs[ntc] = req_id; 2184 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2185 } 2186 2187 *next_to_clean = ntc; 2188 2189 return mbuf_head; 2190 } 2191 2192 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2193 uint16_t nb_pkts) 2194 { 2195 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2196 unsigned int free_queue_entries; 2197 unsigned int refill_threshold; 2198 uint16_t next_to_clean = rx_ring->next_to_clean; 2199 uint16_t descs_in_use; 2200 struct rte_mbuf *mbuf; 2201 uint16_t completed; 2202 struct ena_com_rx_ctx ena_rx_ctx; 2203 int i, rc = 0; 2204 2205 /* Check adapter state */ 2206 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2207 PMD_DRV_LOG(ALERT, 2208 "Trying to receive pkts while device is NOT running\n"); 2209 return 0; 2210 } 2211 2212 descs_in_use = rx_ring->ring_size - 2213 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2214 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2215 2216 for (completed = 0; completed < nb_pkts; completed++) { 2217 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2218 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2219 ena_rx_ctx.descs = 0; 2220 ena_rx_ctx.pkt_offset = 0; 2221 /* receive packet context */ 2222 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2223 rx_ring->ena_com_io_sq, 2224 &ena_rx_ctx); 2225 if (unlikely(rc)) { 2226 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2227 rx_ring->adapter->reset_reason = 2228 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2229 rx_ring->adapter->trigger_reset = true; 2230 ++rx_ring->rx_stats.bad_desc_num; 2231 return 0; 2232 } 2233 2234 mbuf = ena_rx_mbuf(rx_ring, 2235 ena_rx_ctx.ena_bufs, 2236 ena_rx_ctx.descs, 2237 &next_to_clean, 2238 ena_rx_ctx.pkt_offset); 2239 if (unlikely(mbuf == NULL)) { 2240 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2241 rx_ring->empty_rx_reqs[next_to_clean] = 2242 rx_ring->ena_bufs[i].req_id; 2243 next_to_clean = ENA_IDX_NEXT_MASKED( 2244 next_to_clean, rx_ring->size_mask); 2245 } 2246 break; 2247 } 2248 2249 /* fill mbuf attributes if any */ 2250 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); 2251 2252 if (unlikely(mbuf->ol_flags & 2253 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2254 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2255 ++rx_ring->rx_stats.bad_csum; 2256 } 2257 2258 mbuf->hash.rss = ena_rx_ctx.hash; 2259 2260 rx_pkts[completed] = mbuf; 2261 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2262 } 2263 2264 rx_ring->rx_stats.cnt += completed; 2265 rx_ring->next_to_clean = next_to_clean; 2266 2267 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2268 refill_threshold = 2269 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2270 (unsigned int)ENA_REFILL_THRESH_PACKET); 2271 2272 /* Burst refill to save doorbells, memory barriers, const interval */ 2273 if (free_queue_entries > refill_threshold) { 2274 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2275 ena_populate_rx_queue(rx_ring, free_queue_entries); 2276 } 2277 2278 return completed; 2279 } 2280 2281 static uint16_t 2282 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2283 uint16_t nb_pkts) 2284 { 2285 int32_t ret; 2286 uint32_t i; 2287 struct rte_mbuf *m; 2288 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2289 struct rte_ipv4_hdr *ip_hdr; 2290 uint64_t ol_flags; 2291 uint16_t frag_field; 2292 2293 for (i = 0; i != nb_pkts; i++) { 2294 m = tx_pkts[i]; 2295 ol_flags = m->ol_flags; 2296 2297 if (!(ol_flags & PKT_TX_IPV4)) 2298 continue; 2299 2300 /* If there was not L2 header length specified, assume it is 2301 * length of the ethernet header. 2302 */ 2303 if (unlikely(m->l2_len == 0)) 2304 m->l2_len = sizeof(struct rte_ether_hdr); 2305 2306 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2307 m->l2_len); 2308 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2309 2310 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2311 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2312 2313 /* If IPv4 header has DF flag enabled and TSO support is 2314 * disabled, partial chcecksum should not be calculated. 2315 */ 2316 if (!tx_ring->adapter->offloads.tso4_supported) 2317 continue; 2318 } 2319 2320 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2321 (ol_flags & PKT_TX_L4_MASK) == 2322 PKT_TX_SCTP_CKSUM) { 2323 rte_errno = ENOTSUP; 2324 return i; 2325 } 2326 2327 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2328 ret = rte_validate_tx_offload(m); 2329 if (ret != 0) { 2330 rte_errno = -ret; 2331 return i; 2332 } 2333 #endif 2334 2335 /* In case we are supposed to TSO and have DF not set (DF=0) 2336 * hardware must be provided with partial checksum, otherwise 2337 * it will take care of necessary calculations. 2338 */ 2339 2340 ret = rte_net_intel_cksum_flags_prepare(m, 2341 ol_flags & ~PKT_TX_TCP_SEG); 2342 if (ret != 0) { 2343 rte_errno = -ret; 2344 return i; 2345 } 2346 } 2347 2348 return i; 2349 } 2350 2351 static void ena_update_hints(struct ena_adapter *adapter, 2352 struct ena_admin_ena_hw_hints *hints) 2353 { 2354 if (hints->admin_completion_tx_timeout) 2355 adapter->ena_dev.admin_queue.completion_timeout = 2356 hints->admin_completion_tx_timeout * 1000; 2357 2358 if (hints->mmio_read_timeout) 2359 /* convert to usec */ 2360 adapter->ena_dev.mmio_read.reg_read_to = 2361 hints->mmio_read_timeout * 1000; 2362 2363 if (hints->driver_watchdog_timeout) { 2364 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2365 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2366 else 2367 // Convert msecs to ticks 2368 adapter->keep_alive_timeout = 2369 (hints->driver_watchdog_timeout * 2370 rte_get_timer_hz()) / 1000; 2371 } 2372 } 2373 2374 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2375 struct rte_mbuf *mbuf) 2376 { 2377 struct ena_com_dev *ena_dev; 2378 int num_segments, header_len, rc; 2379 2380 ena_dev = &tx_ring->adapter->ena_dev; 2381 num_segments = mbuf->nb_segs; 2382 header_len = mbuf->data_len; 2383 2384 if (likely(num_segments < tx_ring->sgl_size)) 2385 return 0; 2386 2387 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2388 (num_segments == tx_ring->sgl_size) && 2389 (header_len < tx_ring->tx_max_header_size)) 2390 return 0; 2391 2392 ++tx_ring->tx_stats.linearize; 2393 rc = rte_pktmbuf_linearize(mbuf); 2394 if (unlikely(rc)) { 2395 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2396 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2397 ++tx_ring->tx_stats.linearize_failed; 2398 return rc; 2399 } 2400 2401 return rc; 2402 } 2403 2404 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2405 struct ena_tx_buffer *tx_info, 2406 struct rte_mbuf *mbuf, 2407 void **push_header, 2408 uint16_t *header_len) 2409 { 2410 struct ena_com_buf *ena_buf; 2411 uint16_t delta, seg_len, push_len; 2412 2413 delta = 0; 2414 seg_len = mbuf->data_len; 2415 2416 tx_info->mbuf = mbuf; 2417 ena_buf = tx_info->bufs; 2418 2419 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2420 /* 2421 * Tx header might be (and will be in most cases) smaller than 2422 * tx_max_header_size. But it's not an issue to send more data 2423 * to the device, than actually needed if the mbuf size is 2424 * greater than tx_max_header_size. 2425 */ 2426 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2427 *header_len = push_len; 2428 2429 if (likely(push_len <= seg_len)) { 2430 /* If the push header is in the single segment, then 2431 * just point it to the 1st mbuf data. 2432 */ 2433 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2434 } else { 2435 /* If the push header lays in the several segments, copy 2436 * it to the intermediate buffer. 2437 */ 2438 rte_pktmbuf_read(mbuf, 0, push_len, 2439 tx_ring->push_buf_intermediate_buf); 2440 *push_header = tx_ring->push_buf_intermediate_buf; 2441 delta = push_len - seg_len; 2442 } 2443 } else { 2444 *push_header = NULL; 2445 *header_len = 0; 2446 push_len = 0; 2447 } 2448 2449 /* Process first segment taking into consideration pushed header */ 2450 if (seg_len > push_len) { 2451 ena_buf->paddr = mbuf->buf_iova + 2452 mbuf->data_off + 2453 push_len; 2454 ena_buf->len = seg_len - push_len; 2455 ena_buf++; 2456 tx_info->num_of_bufs++; 2457 } 2458 2459 while ((mbuf = mbuf->next) != NULL) { 2460 seg_len = mbuf->data_len; 2461 2462 /* Skip mbufs if whole data is pushed as a header */ 2463 if (unlikely(delta > seg_len)) { 2464 delta -= seg_len; 2465 continue; 2466 } 2467 2468 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2469 ena_buf->len = seg_len - delta; 2470 ena_buf++; 2471 tx_info->num_of_bufs++; 2472 2473 delta = 0; 2474 } 2475 } 2476 2477 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 2478 { 2479 struct ena_tx_buffer *tx_info; 2480 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 2481 uint16_t next_to_use; 2482 uint16_t header_len; 2483 uint16_t req_id; 2484 void *push_header; 2485 int nb_hw_desc; 2486 int rc; 2487 2488 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2489 if (unlikely(rc)) 2490 return rc; 2491 2492 next_to_use = tx_ring->next_to_use; 2493 2494 req_id = tx_ring->empty_tx_reqs[next_to_use]; 2495 tx_info = &tx_ring->tx_buffer_info[req_id]; 2496 tx_info->num_of_bufs = 0; 2497 2498 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 2499 2500 ena_tx_ctx.ena_bufs = tx_info->bufs; 2501 ena_tx_ctx.push_header = push_header; 2502 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2503 ena_tx_ctx.req_id = req_id; 2504 ena_tx_ctx.header_len = header_len; 2505 2506 /* Set Tx offloads flags, if applicable */ 2507 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 2508 tx_ring->disable_meta_caching); 2509 2510 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2511 &ena_tx_ctx))) { 2512 PMD_DRV_LOG(DEBUG, 2513 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2514 tx_ring->id); 2515 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2516 } 2517 2518 /* prepare the packet's descriptors to dma engine */ 2519 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2520 &nb_hw_desc); 2521 if (unlikely(rc)) { 2522 ++tx_ring->tx_stats.prepare_ctx_err; 2523 return rc; 2524 } 2525 2526 tx_info->tx_descs = nb_hw_desc; 2527 2528 tx_ring->tx_stats.cnt++; 2529 tx_ring->tx_stats.bytes += mbuf->pkt_len; 2530 2531 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 2532 tx_ring->size_mask); 2533 2534 return 0; 2535 } 2536 2537 static void ena_tx_cleanup(struct ena_ring *tx_ring) 2538 { 2539 unsigned int cleanup_budget; 2540 unsigned int total_tx_descs = 0; 2541 uint16_t next_to_clean = tx_ring->next_to_clean; 2542 2543 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2544 (unsigned int)ENA_REFILL_THRESH_PACKET); 2545 2546 while (likely(total_tx_descs < cleanup_budget)) { 2547 struct rte_mbuf *mbuf; 2548 struct ena_tx_buffer *tx_info; 2549 uint16_t req_id; 2550 2551 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 2552 break; 2553 2554 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 2555 break; 2556 2557 /* Get Tx info & store how many descs were processed */ 2558 tx_info = &tx_ring->tx_buffer_info[req_id]; 2559 2560 mbuf = tx_info->mbuf; 2561 rte_pktmbuf_free(mbuf); 2562 2563 tx_info->mbuf = NULL; 2564 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 2565 2566 total_tx_descs += tx_info->tx_descs; 2567 2568 /* Put back descriptor to the ring for reuse */ 2569 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 2570 tx_ring->size_mask); 2571 } 2572 2573 if (likely(total_tx_descs > 0)) { 2574 /* acknowledge completion of sent packets */ 2575 tx_ring->next_to_clean = next_to_clean; 2576 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2577 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2578 } 2579 } 2580 2581 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2582 uint16_t nb_pkts) 2583 { 2584 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2585 uint16_t sent_idx = 0; 2586 2587 /* Check adapter state */ 2588 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2589 PMD_DRV_LOG(ALERT, 2590 "Trying to xmit pkts while device is NOT running\n"); 2591 return 0; 2592 } 2593 2594 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq), 2595 nb_pkts); 2596 2597 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2598 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 2599 break; 2600 2601 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 2602 tx_ring->size_mask)]); 2603 } 2604 2605 tx_ring->tx_stats.available_desc = 2606 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2607 2608 /* If there are ready packets to be xmitted... */ 2609 if (sent_idx > 0) { 2610 /* ...let HW do its best :-) */ 2611 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2612 tx_ring->tx_stats.doorbells++; 2613 } 2614 2615 ena_tx_cleanup(tx_ring); 2616 2617 tx_ring->tx_stats.available_desc = 2618 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2619 tx_ring->tx_stats.tx_poll++; 2620 2621 return sent_idx; 2622 } 2623 2624 int ena_copy_eni_stats(struct ena_adapter *adapter) 2625 { 2626 struct ena_admin_eni_stats admin_eni_stats; 2627 int rc; 2628 2629 rte_spinlock_lock(&adapter->admin_lock); 2630 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats); 2631 rte_spinlock_unlock(&adapter->admin_lock); 2632 if (rc != 0) { 2633 if (rc == ENA_COM_UNSUPPORTED) { 2634 PMD_DRV_LOG(DEBUG, 2635 "Retrieving ENI metrics is not supported.\n"); 2636 } else { 2637 PMD_DRV_LOG(WARNING, 2638 "Failed to get ENI metrics: %d\n", rc); 2639 } 2640 return rc; 2641 } 2642 2643 rte_memcpy(&adapter->eni_stats, &admin_eni_stats, 2644 sizeof(struct ena_stats_eni)); 2645 2646 return 0; 2647 } 2648 2649 /** 2650 * DPDK callback to retrieve names of extended device statistics 2651 * 2652 * @param dev 2653 * Pointer to Ethernet device structure. 2654 * @param[out] xstats_names 2655 * Buffer to insert names into. 2656 * @param n 2657 * Number of names. 2658 * 2659 * @return 2660 * Number of xstats names. 2661 */ 2662 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2663 struct rte_eth_xstat_name *xstats_names, 2664 unsigned int n) 2665 { 2666 unsigned int xstats_count = ena_xstats_calc_num(dev); 2667 unsigned int stat, i, count = 0; 2668 2669 if (n < xstats_count || !xstats_names) 2670 return xstats_count; 2671 2672 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2673 strcpy(xstats_names[count].name, 2674 ena_stats_global_strings[stat].name); 2675 2676 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) 2677 strcpy(xstats_names[count].name, 2678 ena_stats_eni_strings[stat].name); 2679 2680 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2681 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2682 snprintf(xstats_names[count].name, 2683 sizeof(xstats_names[count].name), 2684 "rx_q%d_%s", i, 2685 ena_stats_rx_strings[stat].name); 2686 2687 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2688 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2689 snprintf(xstats_names[count].name, 2690 sizeof(xstats_names[count].name), 2691 "tx_q%d_%s", i, 2692 ena_stats_tx_strings[stat].name); 2693 2694 return xstats_count; 2695 } 2696 2697 /** 2698 * DPDK callback to get extended device statistics. 2699 * 2700 * @param dev 2701 * Pointer to Ethernet device structure. 2702 * @param[out] stats 2703 * Stats table output buffer. 2704 * @param n 2705 * The size of the stats table. 2706 * 2707 * @return 2708 * Number of xstats on success, negative on failure. 2709 */ 2710 static int ena_xstats_get(struct rte_eth_dev *dev, 2711 struct rte_eth_xstat *xstats, 2712 unsigned int n) 2713 { 2714 struct ena_adapter *adapter = dev->data->dev_private; 2715 unsigned int xstats_count = ena_xstats_calc_num(dev); 2716 unsigned int stat, i, count = 0; 2717 int stat_offset; 2718 void *stats_begin; 2719 2720 if (n < xstats_count) 2721 return xstats_count; 2722 2723 if (!xstats) 2724 return 0; 2725 2726 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2727 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2728 stats_begin = &adapter->dev_stats; 2729 2730 xstats[count].id = count; 2731 xstats[count].value = *((uint64_t *) 2732 ((char *)stats_begin + stat_offset)); 2733 } 2734 2735 /* Even if the function below fails, we should copy previous (or initial 2736 * values) to keep structure of rte_eth_xstat consistent. 2737 */ 2738 ena_copy_eni_stats(adapter); 2739 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) { 2740 stat_offset = ena_stats_eni_strings[stat].stat_offset; 2741 stats_begin = &adapter->eni_stats; 2742 2743 xstats[count].id = count; 2744 xstats[count].value = *((uint64_t *) 2745 ((char *)stats_begin + stat_offset)); 2746 } 2747 2748 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2749 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2750 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2751 stats_begin = &adapter->rx_ring[i].rx_stats; 2752 2753 xstats[count].id = count; 2754 xstats[count].value = *((uint64_t *) 2755 ((char *)stats_begin + stat_offset)); 2756 } 2757 } 2758 2759 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2760 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2761 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2762 stats_begin = &adapter->tx_ring[i].rx_stats; 2763 2764 xstats[count].id = count; 2765 xstats[count].value = *((uint64_t *) 2766 ((char *)stats_begin + stat_offset)); 2767 } 2768 } 2769 2770 return count; 2771 } 2772 2773 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2774 const uint64_t *ids, 2775 uint64_t *values, 2776 unsigned int n) 2777 { 2778 struct ena_adapter *adapter = dev->data->dev_private; 2779 uint64_t id; 2780 uint64_t rx_entries, tx_entries; 2781 unsigned int i; 2782 int qid; 2783 int valid = 0; 2784 bool was_eni_copied = false; 2785 2786 for (i = 0; i < n; ++i) { 2787 id = ids[i]; 2788 /* Check if id belongs to global statistics */ 2789 if (id < ENA_STATS_ARRAY_GLOBAL) { 2790 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2791 ++valid; 2792 continue; 2793 } 2794 2795 /* Check if id belongs to ENI statistics */ 2796 id -= ENA_STATS_ARRAY_GLOBAL; 2797 if (id < ENA_STATS_ARRAY_ENI) { 2798 /* Avoid reading ENI stats multiple times in a single 2799 * function call, as it requires communication with the 2800 * admin queue. 2801 */ 2802 if (!was_eni_copied) { 2803 was_eni_copied = true; 2804 ena_copy_eni_stats(adapter); 2805 } 2806 values[i] = *((uint64_t *)&adapter->eni_stats + id); 2807 ++valid; 2808 continue; 2809 } 2810 2811 /* Check if id belongs to rx queue statistics */ 2812 id -= ENA_STATS_ARRAY_ENI; 2813 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2814 if (id < rx_entries) { 2815 qid = id % dev->data->nb_rx_queues; 2816 id /= dev->data->nb_rx_queues; 2817 values[i] = *((uint64_t *) 2818 &adapter->rx_ring[qid].rx_stats + id); 2819 ++valid; 2820 continue; 2821 } 2822 /* Check if id belongs to rx queue statistics */ 2823 id -= rx_entries; 2824 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2825 if (id < tx_entries) { 2826 qid = id % dev->data->nb_tx_queues; 2827 id /= dev->data->nb_tx_queues; 2828 values[i] = *((uint64_t *) 2829 &adapter->tx_ring[qid].tx_stats + id); 2830 ++valid; 2831 continue; 2832 } 2833 } 2834 2835 return valid; 2836 } 2837 2838 static int ena_process_bool_devarg(const char *key, 2839 const char *value, 2840 void *opaque) 2841 { 2842 struct ena_adapter *adapter = opaque; 2843 bool bool_value; 2844 2845 /* Parse the value. */ 2846 if (strcmp(value, "1") == 0) { 2847 bool_value = true; 2848 } else if (strcmp(value, "0") == 0) { 2849 bool_value = false; 2850 } else { 2851 PMD_INIT_LOG(ERR, 2852 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2853 value, key); 2854 return -EINVAL; 2855 } 2856 2857 /* Now, assign it to the proper adapter field. */ 2858 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) 2859 adapter->use_large_llq_hdr = bool_value; 2860 2861 return 0; 2862 } 2863 2864 static int ena_parse_devargs(struct ena_adapter *adapter, 2865 struct rte_devargs *devargs) 2866 { 2867 static const char * const allowed_args[] = { 2868 ENA_DEVARG_LARGE_LLQ_HDR, 2869 }; 2870 struct rte_kvargs *kvlist; 2871 int rc; 2872 2873 if (devargs == NULL) 2874 return 0; 2875 2876 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2877 if (kvlist == NULL) { 2878 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2879 devargs->args); 2880 return -EINVAL; 2881 } 2882 2883 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2884 ena_process_bool_devarg, adapter); 2885 2886 rte_kvargs_free(kvlist); 2887 2888 return rc; 2889 } 2890 2891 /********************************************************************* 2892 * PMD configuration 2893 *********************************************************************/ 2894 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2895 struct rte_pci_device *pci_dev) 2896 { 2897 return rte_eth_dev_pci_generic_probe(pci_dev, 2898 sizeof(struct ena_adapter), eth_ena_dev_init); 2899 } 2900 2901 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2902 { 2903 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2904 } 2905 2906 static struct rte_pci_driver rte_ena_pmd = { 2907 .id_table = pci_id_ena_map, 2908 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2909 RTE_PCI_DRV_WC_ACTIVATE, 2910 .probe = eth_ena_pci_probe, 2911 .remove = eth_ena_pci_remove, 2912 }; 2913 2914 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2915 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2916 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2917 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2918 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE); 2919 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE); 2920 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2921 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE); 2922 #endif 2923 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2924 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE); 2925 #endif 2926 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2927 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE); 2928 #endif 2929 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2930 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE); 2931 #endif 2932 2933 /****************************************************************************** 2934 ******************************** AENQ Handlers ******************************* 2935 *****************************************************************************/ 2936 static void ena_update_on_link_change(void *adapter_data, 2937 struct ena_admin_aenq_entry *aenq_e) 2938 { 2939 struct rte_eth_dev *eth_dev; 2940 struct ena_adapter *adapter; 2941 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2942 uint32_t status; 2943 2944 adapter = adapter_data; 2945 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2946 eth_dev = adapter->rte_dev; 2947 2948 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2949 adapter->link_status = status; 2950 2951 ena_link_update(eth_dev, 0); 2952 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2953 } 2954 2955 static void ena_notification(void *data, 2956 struct ena_admin_aenq_entry *aenq_e) 2957 { 2958 struct ena_adapter *adapter = data; 2959 struct ena_admin_ena_hw_hints *hints; 2960 2961 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2962 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2963 aenq_e->aenq_common_desc.group, 2964 ENA_ADMIN_NOTIFICATION); 2965 2966 switch (aenq_e->aenq_common_desc.syndrom) { 2967 case ENA_ADMIN_UPDATE_HINTS: 2968 hints = (struct ena_admin_ena_hw_hints *) 2969 (&aenq_e->inline_data_w4); 2970 ena_update_hints(adapter, hints); 2971 break; 2972 default: 2973 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2974 aenq_e->aenq_common_desc.syndrom); 2975 } 2976 } 2977 2978 static void ena_keep_alive(void *adapter_data, 2979 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2980 { 2981 struct ena_adapter *adapter = adapter_data; 2982 struct ena_admin_aenq_keep_alive_desc *desc; 2983 uint64_t rx_drops; 2984 uint64_t tx_drops; 2985 2986 adapter->timestamp_wd = rte_get_timer_cycles(); 2987 2988 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2989 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2990 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 2991 2992 adapter->drv_stats->rx_drops = rx_drops; 2993 adapter->dev_stats.tx_drops = tx_drops; 2994 } 2995 2996 /** 2997 * This handler will called for unknown event group or unimplemented handlers 2998 **/ 2999 static void unimplemented_aenq_handler(__rte_unused void *data, 3000 __rte_unused struct ena_admin_aenq_entry *aenq_e) 3001 { 3002 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 3003 "unimplemented handler\n"); 3004 } 3005 3006 static struct ena_aenq_handlers aenq_handlers = { 3007 .handlers = { 3008 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3009 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3010 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 3011 }, 3012 .unimplemented_handler = unimplemented_aenq_handler 3013 }; 3014