1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <ethdev_driver.h> 9 #include <ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 2 31 #define DRV_MODULE_VER_SUBMINOR 1 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 40 41 #define GET_L4_HDR_LEN(mbuf) \ 42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 44 45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 47 #define ENA_HASH_KEY_SIZE 40 48 #define ETH_GSTRING_LEN 32 49 50 #define ARRAY_SIZE(x) RTE_DIM(x) 51 52 #define ENA_MIN_RING_DESC 128 53 54 enum ethtool_stringset { 55 ETH_SS_TEST = 0, 56 ETH_SS_STATS, 57 }; 58 59 struct ena_stats { 60 char name[ETH_GSTRING_LEN]; 61 int stat_offset; 62 }; 63 64 #define ENA_STAT_ENTRY(stat, stat_type) { \ 65 .name = #stat, \ 66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 67 } 68 69 #define ENA_STAT_RX_ENTRY(stat) \ 70 ENA_STAT_ENTRY(stat, rx) 71 72 #define ENA_STAT_TX_ENTRY(stat) \ 73 ENA_STAT_ENTRY(stat, tx) 74 75 #define ENA_STAT_ENI_ENTRY(stat) \ 76 ENA_STAT_ENTRY(stat, eni) 77 78 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 79 ENA_STAT_ENTRY(stat, dev) 80 81 /* Device arguments */ 82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 83 84 /* 85 * Each rte_memzone should have unique name. 86 * To satisfy it, count number of allocation and add it to name. 87 */ 88 rte_atomic64_t ena_alloc_cnt; 89 90 static const struct ena_stats ena_stats_global_strings[] = { 91 ENA_STAT_GLOBAL_ENTRY(wd_expired), 92 ENA_STAT_GLOBAL_ENTRY(dev_start), 93 ENA_STAT_GLOBAL_ENTRY(dev_stop), 94 ENA_STAT_GLOBAL_ENTRY(tx_drops), 95 }; 96 97 static const struct ena_stats ena_stats_eni_strings[] = { 98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded), 99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded), 100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded), 101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded), 102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded), 103 }; 104 105 static const struct ena_stats ena_stats_tx_strings[] = { 106 ENA_STAT_TX_ENTRY(cnt), 107 ENA_STAT_TX_ENTRY(bytes), 108 ENA_STAT_TX_ENTRY(prepare_ctx_err), 109 ENA_STAT_TX_ENTRY(linearize), 110 ENA_STAT_TX_ENTRY(linearize_failed), 111 ENA_STAT_TX_ENTRY(tx_poll), 112 ENA_STAT_TX_ENTRY(doorbells), 113 ENA_STAT_TX_ENTRY(bad_req_id), 114 ENA_STAT_TX_ENTRY(available_desc), 115 }; 116 117 static const struct ena_stats ena_stats_rx_strings[] = { 118 ENA_STAT_RX_ENTRY(cnt), 119 ENA_STAT_RX_ENTRY(bytes), 120 ENA_STAT_RX_ENTRY(refill_partial), 121 ENA_STAT_RX_ENTRY(bad_csum), 122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 123 ENA_STAT_RX_ENTRY(bad_desc_num), 124 ENA_STAT_RX_ENTRY(bad_req_id), 125 }; 126 127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings) 129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 131 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 133 DEV_TX_OFFLOAD_UDP_CKSUM |\ 134 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 135 DEV_TX_OFFLOAD_TCP_TSO) 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 137 PKT_TX_IP_CKSUM |\ 138 PKT_TX_TCP_SEG) 139 140 /** Vendor ID used by Amazon devices */ 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F 142 /** Amazon devices */ 143 #define PCI_DEVICE_ID_ENA_VF 0xEC20 144 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21 145 146 #define ENA_TX_OFFLOAD_MASK (\ 147 PKT_TX_L4_MASK | \ 148 PKT_TX_IPV6 | \ 149 PKT_TX_IPV4 | \ 150 PKT_TX_IP_CKSUM | \ 151 PKT_TX_TCP_SEG) 152 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 155 156 static const struct rte_pci_id pci_id_ena_map[] = { 157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) }, 159 { .device_id = 0 }, 160 }; 161 162 static struct ena_aenq_handlers aenq_handlers; 163 164 static int ena_device_init(struct ena_com_dev *ena_dev, 165 struct ena_com_dev_get_features_ctx *get_feat_ctx, 166 bool *wd_state); 167 static int ena_dev_configure(struct rte_eth_dev *dev); 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 169 struct ena_tx_buffer *tx_info, 170 struct rte_mbuf *mbuf, 171 void **push_header, 172 uint16_t *header_len); 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf); 174 static void ena_tx_cleanup(struct ena_ring *tx_ring); 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 176 uint16_t nb_pkts); 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 178 uint16_t nb_pkts); 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 180 uint16_t nb_desc, unsigned int socket_id, 181 const struct rte_eth_txconf *tx_conf); 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 183 uint16_t nb_desc, unsigned int socket_id, 184 const struct rte_eth_rxconf *rx_conf, 185 struct rte_mempool *mp); 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len); 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 188 struct ena_com_rx_buf_info *ena_bufs, 189 uint32_t descs, 190 uint16_t *next_to_clean, 191 uint8_t offset); 192 static uint16_t eth_ena_recv_pkts(void *rx_queue, 193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 195 struct rte_mbuf *mbuf, uint16_t id); 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 197 static void ena_init_rings(struct ena_adapter *adapter, 198 bool disable_meta_caching); 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 200 static int ena_start(struct rte_eth_dev *dev); 201 static int ena_stop(struct rte_eth_dev *dev); 202 static int ena_close(struct rte_eth_dev *dev); 203 static int ena_dev_reset(struct rte_eth_dev *dev); 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 207 static void ena_rx_queue_release(void *queue); 208 static void ena_tx_queue_release(void *queue); 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 211 static int ena_link_update(struct rte_eth_dev *dev, 212 int wait_to_complete); 213 static int ena_create_io_queue(struct ena_ring *ring); 214 static void ena_queue_stop(struct ena_ring *ring); 215 static void ena_queue_stop_all(struct rte_eth_dev *dev, 216 enum ena_ring_type ring_type); 217 static int ena_queue_start(struct ena_ring *ring); 218 static int ena_queue_start_all(struct rte_eth_dev *dev, 219 enum ena_ring_type ring_type); 220 static void ena_stats_restart(struct rte_eth_dev *dev); 221 static int ena_infos_get(struct rte_eth_dev *dev, 222 struct rte_eth_dev_info *dev_info); 223 static int ena_rss_reta_update(struct rte_eth_dev *dev, 224 struct rte_eth_rss_reta_entry64 *reta_conf, 225 uint16_t reta_size); 226 static int ena_rss_reta_query(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 static void ena_interrupt_handler_rte(void *cb_arg); 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 233 static int ena_xstats_get_names(struct rte_eth_dev *dev, 234 struct rte_eth_xstat_name *xstats_names, 235 unsigned int n); 236 static int ena_xstats_get(struct rte_eth_dev *dev, 237 struct rte_eth_xstat *stats, 238 unsigned int n); 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 240 const uint64_t *ids, 241 uint64_t *values, 242 unsigned int n); 243 static int ena_process_bool_devarg(const char *key, 244 const char *value, 245 void *opaque); 246 static int ena_parse_devargs(struct ena_adapter *adapter, 247 struct rte_devargs *devargs); 248 static int ena_copy_eni_stats(struct ena_adapter *adapter); 249 250 static const struct eth_dev_ops ena_dev_ops = { 251 .dev_configure = ena_dev_configure, 252 .dev_infos_get = ena_infos_get, 253 .rx_queue_setup = ena_rx_queue_setup, 254 .tx_queue_setup = ena_tx_queue_setup, 255 .dev_start = ena_start, 256 .dev_stop = ena_stop, 257 .link_update = ena_link_update, 258 .stats_get = ena_stats_get, 259 .xstats_get_names = ena_xstats_get_names, 260 .xstats_get = ena_xstats_get, 261 .xstats_get_by_id = ena_xstats_get_by_id, 262 .mtu_set = ena_mtu_set, 263 .rx_queue_release = ena_rx_queue_release, 264 .tx_queue_release = ena_tx_queue_release, 265 .dev_close = ena_close, 266 .dev_reset = ena_dev_reset, 267 .reta_update = ena_rss_reta_update, 268 .reta_query = ena_rss_reta_query, 269 }; 270 271 void ena_rss_key_fill(void *key, size_t size) 272 { 273 static bool key_generated; 274 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 275 size_t i; 276 277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 278 279 if (!key_generated) { 280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 281 default_key[i] = rte_rand() & 0xff; 282 key_generated = true; 283 } 284 285 rte_memcpy(key, default_key, size); 286 } 287 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 289 struct ena_com_rx_ctx *ena_rx_ctx) 290 { 291 uint64_t ol_flags = 0; 292 uint32_t packet_type = 0; 293 294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 295 packet_type |= RTE_PTYPE_L4_TCP; 296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 297 packet_type |= RTE_PTYPE_L4_UDP; 298 299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 300 packet_type |= RTE_PTYPE_L3_IPV4; 301 if (unlikely(ena_rx_ctx->l3_csum_err)) 302 ol_flags |= PKT_RX_IP_CKSUM_BAD; 303 else 304 ol_flags |= PKT_RX_IP_CKSUM_GOOD; 305 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 306 packet_type |= RTE_PTYPE_L3_IPV6; 307 } 308 309 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) 310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 311 else 312 if (unlikely(ena_rx_ctx->l4_csum_err)) 313 ol_flags |= PKT_RX_L4_CKSUM_BAD; 314 else 315 ol_flags |= PKT_RX_L4_CKSUM_GOOD; 316 317 mbuf->ol_flags = ol_flags; 318 mbuf->packet_type = packet_type; 319 } 320 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 322 struct ena_com_tx_ctx *ena_tx_ctx, 323 uint64_t queue_offloads, 324 bool disable_meta_caching) 325 { 326 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 327 328 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 329 (queue_offloads & QUEUE_OFFLOADS)) { 330 /* check if TSO is required */ 331 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 332 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 333 ena_tx_ctx->tso_enable = true; 334 335 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 336 } 337 338 /* check if L3 checksum is needed */ 339 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 340 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 341 ena_tx_ctx->l3_csum_enable = true; 342 343 if (mbuf->ol_flags & PKT_TX_IPV6) { 344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 345 } else { 346 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 347 348 /* set don't fragment (DF) flag */ 349 if (mbuf->packet_type & 350 (RTE_PTYPE_L4_NONFRAG 351 | RTE_PTYPE_INNER_L4_NONFRAG)) 352 ena_tx_ctx->df = true; 353 } 354 355 /* check if L4 checksum is needed */ 356 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 357 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 358 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 359 ena_tx_ctx->l4_csum_enable = true; 360 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 361 PKT_TX_UDP_CKSUM) && 362 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 363 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 364 ena_tx_ctx->l4_csum_enable = true; 365 } else { 366 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 367 ena_tx_ctx->l4_csum_enable = false; 368 } 369 370 ena_meta->mss = mbuf->tso_segsz; 371 ena_meta->l3_hdr_len = mbuf->l3_len; 372 ena_meta->l3_hdr_offset = mbuf->l2_len; 373 374 ena_tx_ctx->meta_valid = true; 375 } else if (disable_meta_caching) { 376 memset(ena_meta, 0, sizeof(*ena_meta)); 377 ena_tx_ctx->meta_valid = true; 378 } else { 379 ena_tx_ctx->meta_valid = false; 380 } 381 } 382 383 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 384 { 385 struct ena_tx_buffer *tx_info = NULL; 386 387 if (likely(req_id < tx_ring->ring_size)) { 388 tx_info = &tx_ring->tx_buffer_info[req_id]; 389 if (likely(tx_info->mbuf)) 390 return 0; 391 } 392 393 if (tx_info) 394 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 395 else 396 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 397 398 /* Trigger device reset */ 399 ++tx_ring->tx_stats.bad_req_id; 400 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 401 tx_ring->adapter->trigger_reset = true; 402 return -EFAULT; 403 } 404 405 static void ena_config_host_info(struct ena_com_dev *ena_dev) 406 { 407 struct ena_admin_host_info *host_info; 408 int rc; 409 410 /* Allocate only the host info */ 411 rc = ena_com_allocate_host_info(ena_dev); 412 if (rc) { 413 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 414 return; 415 } 416 417 host_info = ena_dev->host_attr.host_info; 418 419 host_info->os_type = ENA_ADMIN_OS_DPDK; 420 host_info->kernel_ver = RTE_VERSION; 421 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 422 sizeof(host_info->kernel_ver_str)); 423 host_info->os_dist = RTE_VERSION; 424 strlcpy((char *)host_info->os_dist_str, rte_version(), 425 sizeof(host_info->os_dist_str)); 426 host_info->driver_version = 427 (DRV_MODULE_VER_MAJOR) | 428 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 429 (DRV_MODULE_VER_SUBMINOR << 430 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 431 host_info->num_cpus = rte_lcore_count(); 432 433 host_info->driver_supported_features = 434 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 435 436 rc = ena_com_set_host_attributes(ena_dev); 437 if (rc) { 438 if (rc == -ENA_COM_UNSUPPORTED) 439 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 440 else 441 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 442 443 goto err; 444 } 445 446 return; 447 448 err: 449 ena_com_delete_host_info(ena_dev); 450 } 451 452 /* This function calculates the number of xstats based on the current config */ 453 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 454 { 455 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + 456 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 457 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 458 } 459 460 static void ena_config_debug_area(struct ena_adapter *adapter) 461 { 462 u32 debug_area_size; 463 int rc, ss_count; 464 465 ss_count = ena_xstats_calc_num(adapter->rte_dev); 466 467 /* allocate 32 bytes for each string and 64bit for the value */ 468 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 469 470 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 471 if (rc) { 472 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 473 return; 474 } 475 476 rc = ena_com_set_host_attributes(&adapter->ena_dev); 477 if (rc) { 478 if (rc == -ENA_COM_UNSUPPORTED) 479 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 480 else 481 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 482 483 goto err; 484 } 485 486 return; 487 err: 488 ena_com_delete_debug_area(&adapter->ena_dev); 489 } 490 491 static int ena_close(struct rte_eth_dev *dev) 492 { 493 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 494 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 495 struct ena_adapter *adapter = dev->data->dev_private; 496 int ret = 0; 497 498 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 499 return 0; 500 501 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 502 ret = ena_stop(dev); 503 adapter->state = ENA_ADAPTER_STATE_CLOSED; 504 505 ena_rx_queue_release_all(dev); 506 ena_tx_queue_release_all(dev); 507 508 rte_free(adapter->drv_stats); 509 adapter->drv_stats = NULL; 510 511 rte_intr_disable(intr_handle); 512 rte_intr_callback_unregister(intr_handle, 513 ena_interrupt_handler_rte, 514 adapter); 515 516 /* 517 * MAC is not allocated dynamically. Setting NULL should prevent from 518 * release of the resource in the rte_eth_dev_release_port(). 519 */ 520 dev->data->mac_addrs = NULL; 521 522 return ret; 523 } 524 525 static int 526 ena_dev_reset(struct rte_eth_dev *dev) 527 { 528 int rc = 0; 529 530 ena_destroy_device(dev); 531 rc = eth_ena_dev_init(dev); 532 if (rc) 533 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 534 535 return rc; 536 } 537 538 static int ena_rss_reta_update(struct rte_eth_dev *dev, 539 struct rte_eth_rss_reta_entry64 *reta_conf, 540 uint16_t reta_size) 541 { 542 struct ena_adapter *adapter = dev->data->dev_private; 543 struct ena_com_dev *ena_dev = &adapter->ena_dev; 544 int rc, i; 545 u16 entry_value; 546 int conf_idx; 547 int idx; 548 549 if ((reta_size == 0) || (reta_conf == NULL)) 550 return -EINVAL; 551 552 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 553 PMD_DRV_LOG(WARNING, 554 "indirection table %d is bigger than supported (%d)\n", 555 reta_size, ENA_RX_RSS_TABLE_SIZE); 556 return -EINVAL; 557 } 558 559 for (i = 0 ; i < reta_size ; i++) { 560 /* each reta_conf is for 64 entries. 561 * to support 128 we use 2 conf of 64 562 */ 563 conf_idx = i / RTE_RETA_GROUP_SIZE; 564 idx = i % RTE_RETA_GROUP_SIZE; 565 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 566 entry_value = 567 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 568 569 rc = ena_com_indirect_table_fill_entry(ena_dev, 570 i, 571 entry_value); 572 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 573 PMD_DRV_LOG(ERR, 574 "Cannot fill indirect table\n"); 575 return rc; 576 } 577 } 578 } 579 580 rte_spinlock_lock(&adapter->admin_lock); 581 rc = ena_com_indirect_table_set(ena_dev); 582 rte_spinlock_unlock(&adapter->admin_lock); 583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 584 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 585 return rc; 586 } 587 588 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 589 __func__, reta_size, adapter->rte_dev->data->port_id); 590 591 return 0; 592 } 593 594 /* Query redirection table. */ 595 static int ena_rss_reta_query(struct rte_eth_dev *dev, 596 struct rte_eth_rss_reta_entry64 *reta_conf, 597 uint16_t reta_size) 598 { 599 struct ena_adapter *adapter = dev->data->dev_private; 600 struct ena_com_dev *ena_dev = &adapter->ena_dev; 601 int rc; 602 int i; 603 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 604 int reta_conf_idx; 605 int reta_idx; 606 607 if (reta_size == 0 || reta_conf == NULL || 608 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 609 return -EINVAL; 610 611 rte_spinlock_lock(&adapter->admin_lock); 612 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 613 rte_spinlock_unlock(&adapter->admin_lock); 614 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 615 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 616 return -ENOTSUP; 617 } 618 619 for (i = 0 ; i < reta_size ; i++) { 620 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 621 reta_idx = i % RTE_RETA_GROUP_SIZE; 622 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 623 reta_conf[reta_conf_idx].reta[reta_idx] = 624 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 625 } 626 627 return 0; 628 } 629 630 static int ena_rss_init_default(struct ena_adapter *adapter) 631 { 632 struct ena_com_dev *ena_dev = &adapter->ena_dev; 633 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 634 int rc, i; 635 u32 val; 636 637 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 638 if (unlikely(rc)) { 639 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 640 goto err_rss_init; 641 } 642 643 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 644 val = i % nb_rx_queues; 645 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 646 ENA_IO_RXQ_IDX(val)); 647 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 648 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 649 goto err_fill_indir; 650 } 651 } 652 653 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 654 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 655 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 656 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 657 goto err_fill_indir; 658 } 659 660 rc = ena_com_set_default_hash_ctrl(ena_dev); 661 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 662 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 663 goto err_fill_indir; 664 } 665 666 rc = ena_com_indirect_table_set(ena_dev); 667 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 668 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 669 goto err_fill_indir; 670 } 671 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 672 adapter->rte_dev->data->port_id); 673 674 return 0; 675 676 err_fill_indir: 677 ena_com_rss_destroy(ena_dev); 678 err_rss_init: 679 680 return rc; 681 } 682 683 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 684 { 685 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 686 int nb_queues = dev->data->nb_rx_queues; 687 int i; 688 689 for (i = 0; i < nb_queues; i++) 690 ena_rx_queue_release(queues[i]); 691 } 692 693 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 694 { 695 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 696 int nb_queues = dev->data->nb_tx_queues; 697 int i; 698 699 for (i = 0; i < nb_queues; i++) 700 ena_tx_queue_release(queues[i]); 701 } 702 703 static void ena_rx_queue_release(void *queue) 704 { 705 struct ena_ring *ring = (struct ena_ring *)queue; 706 707 /* Free ring resources */ 708 if (ring->rx_buffer_info) 709 rte_free(ring->rx_buffer_info); 710 ring->rx_buffer_info = NULL; 711 712 if (ring->rx_refill_buffer) 713 rte_free(ring->rx_refill_buffer); 714 ring->rx_refill_buffer = NULL; 715 716 if (ring->empty_rx_reqs) 717 rte_free(ring->empty_rx_reqs); 718 ring->empty_rx_reqs = NULL; 719 720 ring->configured = 0; 721 722 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 723 ring->port_id, ring->id); 724 } 725 726 static void ena_tx_queue_release(void *queue) 727 { 728 struct ena_ring *ring = (struct ena_ring *)queue; 729 730 /* Free ring resources */ 731 if (ring->push_buf_intermediate_buf) 732 rte_free(ring->push_buf_intermediate_buf); 733 734 if (ring->tx_buffer_info) 735 rte_free(ring->tx_buffer_info); 736 737 if (ring->empty_tx_reqs) 738 rte_free(ring->empty_tx_reqs); 739 740 ring->empty_tx_reqs = NULL; 741 ring->tx_buffer_info = NULL; 742 ring->push_buf_intermediate_buf = NULL; 743 744 ring->configured = 0; 745 746 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 747 ring->port_id, ring->id); 748 } 749 750 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 751 { 752 unsigned int i; 753 754 for (i = 0; i < ring->ring_size; ++i) { 755 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i]; 756 if (rx_info->mbuf) { 757 rte_mbuf_raw_free(rx_info->mbuf); 758 rx_info->mbuf = NULL; 759 } 760 } 761 } 762 763 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 764 { 765 unsigned int i; 766 767 for (i = 0; i < ring->ring_size; ++i) { 768 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 769 770 if (tx_buf->mbuf) { 771 rte_pktmbuf_free(tx_buf->mbuf); 772 tx_buf->mbuf = NULL; 773 } 774 } 775 } 776 777 static int ena_link_update(struct rte_eth_dev *dev, 778 __rte_unused int wait_to_complete) 779 { 780 struct rte_eth_link *link = &dev->data->dev_link; 781 struct ena_adapter *adapter = dev->data->dev_private; 782 783 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 784 link->link_speed = ETH_SPEED_NUM_NONE; 785 link->link_duplex = ETH_LINK_FULL_DUPLEX; 786 787 return 0; 788 } 789 790 static int ena_queue_start_all(struct rte_eth_dev *dev, 791 enum ena_ring_type ring_type) 792 { 793 struct ena_adapter *adapter = dev->data->dev_private; 794 struct ena_ring *queues = NULL; 795 int nb_queues; 796 int i = 0; 797 int rc = 0; 798 799 if (ring_type == ENA_RING_TYPE_RX) { 800 queues = adapter->rx_ring; 801 nb_queues = dev->data->nb_rx_queues; 802 } else { 803 queues = adapter->tx_ring; 804 nb_queues = dev->data->nb_tx_queues; 805 } 806 for (i = 0; i < nb_queues; i++) { 807 if (queues[i].configured) { 808 if (ring_type == ENA_RING_TYPE_RX) { 809 ena_assert_msg( 810 dev->data->rx_queues[i] == &queues[i], 811 "Inconsistent state of rx queues\n"); 812 } else { 813 ena_assert_msg( 814 dev->data->tx_queues[i] == &queues[i], 815 "Inconsistent state of tx queues\n"); 816 } 817 818 rc = ena_queue_start(&queues[i]); 819 820 if (rc) { 821 PMD_INIT_LOG(ERR, 822 "failed to start queue %d type(%d)", 823 i, ring_type); 824 goto err; 825 } 826 } 827 } 828 829 return 0; 830 831 err: 832 while (i--) 833 if (queues[i].configured) 834 ena_queue_stop(&queues[i]); 835 836 return rc; 837 } 838 839 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 840 { 841 uint32_t max_frame_len = adapter->max_mtu; 842 843 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 844 DEV_RX_OFFLOAD_JUMBO_FRAME) 845 max_frame_len = 846 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 847 848 return max_frame_len; 849 } 850 851 static int ena_check_valid_conf(struct ena_adapter *adapter) 852 { 853 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 854 855 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 856 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 857 "max mtu: %d, min mtu: %d", 858 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 859 return ENA_COM_UNSUPPORTED; 860 } 861 862 return 0; 863 } 864 865 static int 866 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 867 bool use_large_llq_hdr) 868 { 869 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 870 struct ena_com_dev *ena_dev = ctx->ena_dev; 871 uint32_t max_tx_queue_size; 872 uint32_t max_rx_queue_size; 873 874 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 875 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 876 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 877 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 878 max_queue_ext->max_rx_sq_depth); 879 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 880 881 if (ena_dev->tx_mem_queue_type == 882 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 883 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 884 llq->max_llq_depth); 885 } else { 886 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 887 max_queue_ext->max_tx_sq_depth); 888 } 889 890 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 891 max_queue_ext->max_per_packet_rx_descs); 892 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 893 max_queue_ext->max_per_packet_tx_descs); 894 } else { 895 struct ena_admin_queue_feature_desc *max_queues = 896 &ctx->get_feat_ctx->max_queues; 897 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 898 max_queues->max_sq_depth); 899 max_tx_queue_size = max_queues->max_cq_depth; 900 901 if (ena_dev->tx_mem_queue_type == 902 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 903 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 904 llq->max_llq_depth); 905 } else { 906 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 907 max_queues->max_sq_depth); 908 } 909 910 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 911 max_queues->max_packet_rx_descs); 912 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 913 max_queues->max_packet_tx_descs); 914 } 915 916 /* Round down to the nearest power of 2 */ 917 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 918 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 919 920 if (use_large_llq_hdr) { 921 if ((llq->entry_size_ctrl_supported & 922 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 923 (ena_dev->tx_mem_queue_type == 924 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 925 max_tx_queue_size /= 2; 926 PMD_INIT_LOG(INFO, 927 "Forcing large headers and decreasing maximum TX queue size to %d\n", 928 max_tx_queue_size); 929 } else { 930 PMD_INIT_LOG(ERR, 931 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 932 } 933 } 934 935 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 936 PMD_INIT_LOG(ERR, "Invalid queue size"); 937 return -EFAULT; 938 } 939 940 ctx->max_tx_queue_size = max_tx_queue_size; 941 ctx->max_rx_queue_size = max_rx_queue_size; 942 943 return 0; 944 } 945 946 static void ena_stats_restart(struct rte_eth_dev *dev) 947 { 948 struct ena_adapter *adapter = dev->data->dev_private; 949 950 rte_atomic64_init(&adapter->drv_stats->ierrors); 951 rte_atomic64_init(&adapter->drv_stats->oerrors); 952 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 953 adapter->drv_stats->rx_drops = 0; 954 } 955 956 static int ena_stats_get(struct rte_eth_dev *dev, 957 struct rte_eth_stats *stats) 958 { 959 struct ena_admin_basic_stats ena_stats; 960 struct ena_adapter *adapter = dev->data->dev_private; 961 struct ena_com_dev *ena_dev = &adapter->ena_dev; 962 int rc; 963 int i; 964 int max_rings_stats; 965 966 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 967 return -ENOTSUP; 968 969 memset(&ena_stats, 0, sizeof(ena_stats)); 970 971 rte_spinlock_lock(&adapter->admin_lock); 972 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 973 rte_spinlock_unlock(&adapter->admin_lock); 974 if (unlikely(rc)) { 975 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 976 return rc; 977 } 978 979 /* Set of basic statistics from ENA */ 980 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 981 ena_stats.rx_pkts_low); 982 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 983 ena_stats.tx_pkts_low); 984 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 985 ena_stats.rx_bytes_low); 986 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 987 ena_stats.tx_bytes_low); 988 989 /* Driver related stats */ 990 stats->imissed = adapter->drv_stats->rx_drops; 991 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 992 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 993 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 994 995 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 996 RTE_ETHDEV_QUEUE_STAT_CNTRS); 997 for (i = 0; i < max_rings_stats; ++i) { 998 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 999 1000 stats->q_ibytes[i] = rx_stats->bytes; 1001 stats->q_ipackets[i] = rx_stats->cnt; 1002 stats->q_errors[i] = rx_stats->bad_desc_num + 1003 rx_stats->bad_req_id; 1004 } 1005 1006 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 1007 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1008 for (i = 0; i < max_rings_stats; ++i) { 1009 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 1010 1011 stats->q_obytes[i] = tx_stats->bytes; 1012 stats->q_opackets[i] = tx_stats->cnt; 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1019 { 1020 struct ena_adapter *adapter; 1021 struct ena_com_dev *ena_dev; 1022 int rc = 0; 1023 1024 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1025 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1026 adapter = dev->data->dev_private; 1027 1028 ena_dev = &adapter->ena_dev; 1029 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1030 1031 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1032 PMD_DRV_LOG(ERR, 1033 "Invalid MTU setting. new_mtu: %d " 1034 "max mtu: %d min mtu: %d\n", 1035 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1036 return -EINVAL; 1037 } 1038 1039 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1040 if (rc) 1041 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1042 else 1043 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1044 1045 return rc; 1046 } 1047 1048 static int ena_start(struct rte_eth_dev *dev) 1049 { 1050 struct ena_adapter *adapter = dev->data->dev_private; 1051 uint64_t ticks; 1052 int rc = 0; 1053 1054 rc = ena_check_valid_conf(adapter); 1055 if (rc) 1056 return rc; 1057 1058 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1059 if (rc) 1060 return rc; 1061 1062 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1063 if (rc) 1064 goto err_start_tx; 1065 1066 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1067 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1068 rc = ena_rss_init_default(adapter); 1069 if (rc) 1070 goto err_rss_init; 1071 } 1072 1073 ena_stats_restart(dev); 1074 1075 adapter->timestamp_wd = rte_get_timer_cycles(); 1076 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1077 1078 ticks = rte_get_timer_hz(); 1079 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1080 ena_timer_wd_callback, adapter); 1081 1082 ++adapter->dev_stats.dev_start; 1083 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1084 1085 return 0; 1086 1087 err_rss_init: 1088 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1089 err_start_tx: 1090 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1091 return rc; 1092 } 1093 1094 static int ena_stop(struct rte_eth_dev *dev) 1095 { 1096 struct ena_adapter *adapter = dev->data->dev_private; 1097 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1098 int rc; 1099 1100 rte_timer_stop_sync(&adapter->timer_wd); 1101 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1102 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1103 1104 if (adapter->trigger_reset) { 1105 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1106 if (rc) 1107 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1108 } 1109 1110 ++adapter->dev_stats.dev_stop; 1111 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1112 dev->data->dev_started = 0; 1113 1114 return 0; 1115 } 1116 1117 static int ena_create_io_queue(struct ena_ring *ring) 1118 { 1119 struct ena_adapter *adapter; 1120 struct ena_com_dev *ena_dev; 1121 struct ena_com_create_io_ctx ctx = 1122 /* policy set to _HOST just to satisfy icc compiler */ 1123 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1124 0, 0, 0, 0, 0 }; 1125 uint16_t ena_qid; 1126 unsigned int i; 1127 int rc; 1128 1129 adapter = ring->adapter; 1130 ena_dev = &adapter->ena_dev; 1131 1132 if (ring->type == ENA_RING_TYPE_TX) { 1133 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1134 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1135 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1136 for (i = 0; i < ring->ring_size; i++) 1137 ring->empty_tx_reqs[i] = i; 1138 } else { 1139 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1140 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1141 for (i = 0; i < ring->ring_size; i++) 1142 ring->empty_rx_reqs[i] = i; 1143 } 1144 ctx.queue_size = ring->ring_size; 1145 ctx.qid = ena_qid; 1146 ctx.msix_vector = -1; /* interrupts not used */ 1147 ctx.numa_node = ring->numa_socket_id; 1148 1149 rc = ena_com_create_io_queue(ena_dev, &ctx); 1150 if (rc) { 1151 PMD_DRV_LOG(ERR, 1152 "failed to create io queue #%d (qid:%d) rc: %d\n", 1153 ring->id, ena_qid, rc); 1154 return rc; 1155 } 1156 1157 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1158 &ring->ena_com_io_sq, 1159 &ring->ena_com_io_cq); 1160 if (rc) { 1161 PMD_DRV_LOG(ERR, 1162 "Failed to get io queue handlers. queue num %d rc: %d\n", 1163 ring->id, rc); 1164 ena_com_destroy_io_queue(ena_dev, ena_qid); 1165 return rc; 1166 } 1167 1168 if (ring->type == ENA_RING_TYPE_TX) 1169 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1170 1171 return 0; 1172 } 1173 1174 static void ena_queue_stop(struct ena_ring *ring) 1175 { 1176 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1177 1178 if (ring->type == ENA_RING_TYPE_RX) { 1179 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1180 ena_rx_queue_release_bufs(ring); 1181 } else { 1182 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1183 ena_tx_queue_release_bufs(ring); 1184 } 1185 } 1186 1187 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1188 enum ena_ring_type ring_type) 1189 { 1190 struct ena_adapter *adapter = dev->data->dev_private; 1191 struct ena_ring *queues = NULL; 1192 uint16_t nb_queues, i; 1193 1194 if (ring_type == ENA_RING_TYPE_RX) { 1195 queues = adapter->rx_ring; 1196 nb_queues = dev->data->nb_rx_queues; 1197 } else { 1198 queues = adapter->tx_ring; 1199 nb_queues = dev->data->nb_tx_queues; 1200 } 1201 1202 for (i = 0; i < nb_queues; ++i) 1203 if (queues[i].configured) 1204 ena_queue_stop(&queues[i]); 1205 } 1206 1207 static int ena_queue_start(struct ena_ring *ring) 1208 { 1209 int rc, bufs_num; 1210 1211 ena_assert_msg(ring->configured == 1, 1212 "Trying to start unconfigured queue\n"); 1213 1214 rc = ena_create_io_queue(ring); 1215 if (rc) { 1216 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1217 return rc; 1218 } 1219 1220 ring->next_to_clean = 0; 1221 ring->next_to_use = 0; 1222 1223 if (ring->type == ENA_RING_TYPE_TX) { 1224 ring->tx_stats.available_desc = 1225 ena_com_free_q_entries(ring->ena_com_io_sq); 1226 return 0; 1227 } 1228 1229 bufs_num = ring->ring_size - 1; 1230 rc = ena_populate_rx_queue(ring, bufs_num); 1231 if (rc != bufs_num) { 1232 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1233 ENA_IO_RXQ_IDX(ring->id)); 1234 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1235 return ENA_COM_FAULT; 1236 } 1237 /* Flush per-core RX buffers pools cache as they can be used on other 1238 * cores as well. 1239 */ 1240 rte_mempool_cache_flush(NULL, ring->mb_pool); 1241 1242 return 0; 1243 } 1244 1245 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1246 uint16_t queue_idx, 1247 uint16_t nb_desc, 1248 unsigned int socket_id, 1249 const struct rte_eth_txconf *tx_conf) 1250 { 1251 struct ena_ring *txq = NULL; 1252 struct ena_adapter *adapter = dev->data->dev_private; 1253 unsigned int i; 1254 1255 txq = &adapter->tx_ring[queue_idx]; 1256 1257 if (txq->configured) { 1258 PMD_DRV_LOG(CRIT, 1259 "API violation. Queue %d is already configured\n", 1260 queue_idx); 1261 return ENA_COM_FAULT; 1262 } 1263 1264 if (!rte_is_power_of_2(nb_desc)) { 1265 PMD_DRV_LOG(ERR, 1266 "Unsupported size of TX queue: %d is not a power of 2.\n", 1267 nb_desc); 1268 return -EINVAL; 1269 } 1270 1271 if (nb_desc > adapter->max_tx_ring_size) { 1272 PMD_DRV_LOG(ERR, 1273 "Unsupported size of TX queue (max size: %d)\n", 1274 adapter->max_tx_ring_size); 1275 return -EINVAL; 1276 } 1277 1278 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1279 nb_desc = adapter->max_tx_ring_size; 1280 1281 txq->port_id = dev->data->port_id; 1282 txq->next_to_clean = 0; 1283 txq->next_to_use = 0; 1284 txq->ring_size = nb_desc; 1285 txq->size_mask = nb_desc - 1; 1286 txq->numa_socket_id = socket_id; 1287 txq->pkts_without_db = false; 1288 1289 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1290 sizeof(struct ena_tx_buffer) * 1291 txq->ring_size, 1292 RTE_CACHE_LINE_SIZE); 1293 if (!txq->tx_buffer_info) { 1294 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1295 return -ENOMEM; 1296 } 1297 1298 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1299 sizeof(u16) * txq->ring_size, 1300 RTE_CACHE_LINE_SIZE); 1301 if (!txq->empty_tx_reqs) { 1302 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1303 rte_free(txq->tx_buffer_info); 1304 return -ENOMEM; 1305 } 1306 1307 txq->push_buf_intermediate_buf = 1308 rte_zmalloc("txq->push_buf_intermediate_buf", 1309 txq->tx_max_header_size, 1310 RTE_CACHE_LINE_SIZE); 1311 if (!txq->push_buf_intermediate_buf) { 1312 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1313 rte_free(txq->tx_buffer_info); 1314 rte_free(txq->empty_tx_reqs); 1315 return -ENOMEM; 1316 } 1317 1318 for (i = 0; i < txq->ring_size; i++) 1319 txq->empty_tx_reqs[i] = i; 1320 1321 if (tx_conf != NULL) { 1322 txq->offloads = 1323 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1324 } 1325 /* Store pointer to this queue in upper layer */ 1326 txq->configured = 1; 1327 dev->data->tx_queues[queue_idx] = txq; 1328 1329 return 0; 1330 } 1331 1332 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1333 uint16_t queue_idx, 1334 uint16_t nb_desc, 1335 unsigned int socket_id, 1336 __rte_unused const struct rte_eth_rxconf *rx_conf, 1337 struct rte_mempool *mp) 1338 { 1339 struct ena_adapter *adapter = dev->data->dev_private; 1340 struct ena_ring *rxq = NULL; 1341 size_t buffer_size; 1342 int i; 1343 1344 rxq = &adapter->rx_ring[queue_idx]; 1345 if (rxq->configured) { 1346 PMD_DRV_LOG(CRIT, 1347 "API violation. Queue %d is already configured\n", 1348 queue_idx); 1349 return ENA_COM_FAULT; 1350 } 1351 1352 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1353 nb_desc = adapter->max_rx_ring_size; 1354 1355 if (!rte_is_power_of_2(nb_desc)) { 1356 PMD_DRV_LOG(ERR, 1357 "Unsupported size of RX queue: %d is not a power of 2.\n", 1358 nb_desc); 1359 return -EINVAL; 1360 } 1361 1362 if (nb_desc > adapter->max_rx_ring_size) { 1363 PMD_DRV_LOG(ERR, 1364 "Unsupported size of RX queue (max size: %d)\n", 1365 adapter->max_rx_ring_size); 1366 return -EINVAL; 1367 } 1368 1369 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1370 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1371 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1372 PMD_DRV_LOG(ERR, 1373 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1374 buffer_size, ENA_RX_BUF_MIN_SIZE); 1375 return -EINVAL; 1376 } 1377 1378 rxq->port_id = dev->data->port_id; 1379 rxq->next_to_clean = 0; 1380 rxq->next_to_use = 0; 1381 rxq->ring_size = nb_desc; 1382 rxq->size_mask = nb_desc - 1; 1383 rxq->numa_socket_id = socket_id; 1384 rxq->mb_pool = mp; 1385 1386 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1387 sizeof(struct ena_rx_buffer) * nb_desc, 1388 RTE_CACHE_LINE_SIZE); 1389 if (!rxq->rx_buffer_info) { 1390 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1391 return -ENOMEM; 1392 } 1393 1394 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1395 sizeof(struct rte_mbuf *) * nb_desc, 1396 RTE_CACHE_LINE_SIZE); 1397 1398 if (!rxq->rx_refill_buffer) { 1399 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1400 rte_free(rxq->rx_buffer_info); 1401 rxq->rx_buffer_info = NULL; 1402 return -ENOMEM; 1403 } 1404 1405 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1406 sizeof(uint16_t) * nb_desc, 1407 RTE_CACHE_LINE_SIZE); 1408 if (!rxq->empty_rx_reqs) { 1409 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1410 rte_free(rxq->rx_buffer_info); 1411 rxq->rx_buffer_info = NULL; 1412 rte_free(rxq->rx_refill_buffer); 1413 rxq->rx_refill_buffer = NULL; 1414 return -ENOMEM; 1415 } 1416 1417 for (i = 0; i < nb_desc; i++) 1418 rxq->empty_rx_reqs[i] = i; 1419 1420 /* Store pointer to this queue in upper layer */ 1421 rxq->configured = 1; 1422 dev->data->rx_queues[queue_idx] = rxq; 1423 1424 return 0; 1425 } 1426 1427 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq, 1428 struct rte_mbuf *mbuf, uint16_t id) 1429 { 1430 struct ena_com_buf ebuf; 1431 int rc; 1432 1433 /* prepare physical address for DMA transaction */ 1434 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1435 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1436 1437 /* pass resource to device */ 1438 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id); 1439 if (unlikely(rc != 0)) 1440 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1441 1442 return rc; 1443 } 1444 1445 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1446 { 1447 unsigned int i; 1448 int rc; 1449 uint16_t next_to_use = rxq->next_to_use; 1450 uint16_t in_use, req_id; 1451 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1452 1453 if (unlikely(!count)) 1454 return 0; 1455 1456 in_use = rxq->ring_size - 1 - 1457 ena_com_free_q_entries(rxq->ena_com_io_sq); 1458 ena_assert_msg(((in_use + count) < rxq->ring_size), 1459 "bad ring state\n"); 1460 1461 /* get resources for incoming packets */ 1462 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count); 1463 if (unlikely(rc < 0)) { 1464 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1465 ++rxq->rx_stats.mbuf_alloc_fail; 1466 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1467 return 0; 1468 } 1469 1470 for (i = 0; i < count; i++) { 1471 struct rte_mbuf *mbuf = mbufs[i]; 1472 struct ena_rx_buffer *rx_info; 1473 1474 if (likely((i + 4) < count)) 1475 rte_prefetch0(mbufs[i + 4]); 1476 1477 req_id = rxq->empty_rx_reqs[next_to_use]; 1478 rx_info = &rxq->rx_buffer_info[req_id]; 1479 1480 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id); 1481 if (unlikely(rc != 0)) 1482 break; 1483 1484 rx_info->mbuf = mbuf; 1485 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask); 1486 } 1487 1488 if (unlikely(i < count)) { 1489 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1490 "buffers (from %d)\n", rxq->id, i, count); 1491 rte_pktmbuf_free_bulk(&mbufs[i], count - i); 1492 ++rxq->rx_stats.refill_partial; 1493 } 1494 1495 /* When we submitted free recources to device... */ 1496 if (likely(i > 0)) { 1497 /* ...let HW know that it can fill buffers with data. */ 1498 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1499 1500 rxq->next_to_use = next_to_use; 1501 } 1502 1503 return i; 1504 } 1505 1506 static int ena_device_init(struct ena_com_dev *ena_dev, 1507 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1508 bool *wd_state) 1509 { 1510 uint32_t aenq_groups; 1511 int rc; 1512 bool readless_supported; 1513 1514 /* Initialize mmio registers */ 1515 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1516 if (rc) { 1517 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1518 return rc; 1519 } 1520 1521 /* The PCIe configuration space revision id indicate if mmio reg 1522 * read is disabled. 1523 */ 1524 readless_supported = 1525 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1526 & ENA_MMIO_DISABLE_REG_READ); 1527 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1528 1529 /* reset device */ 1530 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1531 if (rc) { 1532 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1533 goto err_mmio_read_less; 1534 } 1535 1536 /* check FW version */ 1537 rc = ena_com_validate_version(ena_dev); 1538 if (rc) { 1539 PMD_DRV_LOG(ERR, "device version is too low\n"); 1540 goto err_mmio_read_less; 1541 } 1542 1543 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1544 1545 /* ENA device administration layer init */ 1546 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1547 if (rc) { 1548 PMD_DRV_LOG(ERR, 1549 "cannot initialize ena admin queue with device\n"); 1550 goto err_mmio_read_less; 1551 } 1552 1553 /* To enable the msix interrupts the driver needs to know the number 1554 * of queues. So the driver uses polling mode to retrieve this 1555 * information. 1556 */ 1557 ena_com_set_admin_polling_mode(ena_dev, true); 1558 1559 ena_config_host_info(ena_dev); 1560 1561 /* Get Device Attributes and features */ 1562 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1563 if (rc) { 1564 PMD_DRV_LOG(ERR, 1565 "cannot get attribute for ena device rc= %d\n", rc); 1566 goto err_admin_init; 1567 } 1568 1569 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1570 BIT(ENA_ADMIN_NOTIFICATION) | 1571 BIT(ENA_ADMIN_KEEP_ALIVE) | 1572 BIT(ENA_ADMIN_FATAL_ERROR) | 1573 BIT(ENA_ADMIN_WARNING); 1574 1575 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1576 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1577 if (rc) { 1578 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1579 goto err_admin_init; 1580 } 1581 1582 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1583 1584 return 0; 1585 1586 err_admin_init: 1587 ena_com_admin_destroy(ena_dev); 1588 1589 err_mmio_read_less: 1590 ena_com_mmio_reg_read_request_destroy(ena_dev); 1591 1592 return rc; 1593 } 1594 1595 static void ena_interrupt_handler_rte(void *cb_arg) 1596 { 1597 struct ena_adapter *adapter = cb_arg; 1598 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1599 1600 ena_com_admin_q_comp_intr_handler(ena_dev); 1601 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1602 ena_com_aenq_intr_handler(ena_dev, adapter); 1603 } 1604 1605 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1606 { 1607 if (!adapter->wd_state) 1608 return; 1609 1610 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1611 return; 1612 1613 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1614 adapter->keep_alive_timeout)) { 1615 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1616 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1617 adapter->trigger_reset = true; 1618 ++adapter->dev_stats.wd_expired; 1619 } 1620 } 1621 1622 /* Check if admin queue is enabled */ 1623 static void check_for_admin_com_state(struct ena_adapter *adapter) 1624 { 1625 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1626 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1627 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1628 adapter->trigger_reset = true; 1629 } 1630 } 1631 1632 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1633 void *arg) 1634 { 1635 struct ena_adapter *adapter = arg; 1636 struct rte_eth_dev *dev = adapter->rte_dev; 1637 1638 check_for_missing_keep_alive(adapter); 1639 check_for_admin_com_state(adapter); 1640 1641 if (unlikely(adapter->trigger_reset)) { 1642 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1643 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1644 NULL); 1645 } 1646 } 1647 1648 static inline void 1649 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1650 struct ena_admin_feature_llq_desc *llq, 1651 bool use_large_llq_hdr) 1652 { 1653 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1654 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1655 llq_config->llq_num_decs_before_header = 1656 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1657 1658 if (use_large_llq_hdr && 1659 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1660 llq_config->llq_ring_entry_size = 1661 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1662 llq_config->llq_ring_entry_size_value = 256; 1663 } else { 1664 llq_config->llq_ring_entry_size = 1665 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1666 llq_config->llq_ring_entry_size_value = 128; 1667 } 1668 } 1669 1670 static int 1671 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1672 struct ena_com_dev *ena_dev, 1673 struct ena_admin_feature_llq_desc *llq, 1674 struct ena_llq_configurations *llq_default_configurations) 1675 { 1676 int rc; 1677 u32 llq_feature_mask; 1678 1679 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1680 if (!(ena_dev->supported_features & llq_feature_mask)) { 1681 PMD_DRV_LOG(INFO, 1682 "LLQ is not supported. Fallback to host mode policy.\n"); 1683 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1684 return 0; 1685 } 1686 1687 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1688 if (unlikely(rc)) { 1689 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1690 "Fallback to host mode policy."); 1691 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1692 return 0; 1693 } 1694 1695 /* Nothing to config, exit */ 1696 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1697 return 0; 1698 1699 if (!adapter->dev_mem_base) { 1700 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1701 "Fallback to host mode policy.\n."); 1702 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1703 return 0; 1704 } 1705 1706 ena_dev->mem_bar = adapter->dev_mem_base; 1707 1708 return 0; 1709 } 1710 1711 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1712 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1713 { 1714 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1715 1716 /* Regular queues capabilities */ 1717 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1718 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1719 &get_feat_ctx->max_queue_ext.max_queue_ext; 1720 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1721 max_queue_ext->max_rx_cq_num); 1722 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1723 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1724 } else { 1725 struct ena_admin_queue_feature_desc *max_queues = 1726 &get_feat_ctx->max_queues; 1727 io_tx_sq_num = max_queues->max_sq_num; 1728 io_tx_cq_num = max_queues->max_cq_num; 1729 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1730 } 1731 1732 /* In case of LLQ use the llq number in the get feature cmd */ 1733 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1734 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1735 1736 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1737 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1738 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1739 1740 if (unlikely(max_num_io_queues == 0)) { 1741 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1742 return -EFAULT; 1743 } 1744 1745 return max_num_io_queues; 1746 } 1747 1748 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1749 { 1750 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1751 struct rte_pci_device *pci_dev; 1752 struct rte_intr_handle *intr_handle; 1753 struct ena_adapter *adapter = eth_dev->data->dev_private; 1754 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1755 struct ena_com_dev_get_features_ctx get_feat_ctx; 1756 struct ena_llq_configurations llq_config; 1757 const char *queue_type_str; 1758 uint32_t max_num_io_queues; 1759 int rc; 1760 static int adapters_found; 1761 bool disable_meta_caching; 1762 bool wd_state = false; 1763 1764 eth_dev->dev_ops = &ena_dev_ops; 1765 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1766 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1767 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1768 1769 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1770 return 0; 1771 1772 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1773 1774 memset(adapter, 0, sizeof(struct ena_adapter)); 1775 ena_dev = &adapter->ena_dev; 1776 1777 adapter->rte_eth_dev_data = eth_dev->data; 1778 adapter->rte_dev = eth_dev; 1779 1780 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1781 adapter->pdev = pci_dev; 1782 1783 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1784 pci_dev->addr.domain, 1785 pci_dev->addr.bus, 1786 pci_dev->addr.devid, 1787 pci_dev->addr.function); 1788 1789 intr_handle = &pci_dev->intr_handle; 1790 1791 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1792 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1793 1794 if (!adapter->regs) { 1795 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1796 ENA_REGS_BAR); 1797 return -ENXIO; 1798 } 1799 1800 ena_dev->reg_bar = adapter->regs; 1801 ena_dev->dmadev = adapter->pdev; 1802 1803 adapter->id_number = adapters_found; 1804 1805 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1806 adapter->id_number); 1807 1808 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1809 if (rc != 0) { 1810 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1811 goto err; 1812 } 1813 1814 /* device specific initialization routine */ 1815 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1816 if (rc) { 1817 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1818 goto err; 1819 } 1820 adapter->wd_state = wd_state; 1821 1822 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1823 adapter->use_large_llq_hdr); 1824 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1825 &get_feat_ctx.llq, &llq_config); 1826 if (unlikely(rc)) { 1827 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1828 return rc; 1829 } 1830 1831 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1832 queue_type_str = "Regular"; 1833 else 1834 queue_type_str = "Low latency"; 1835 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1836 1837 calc_queue_ctx.ena_dev = ena_dev; 1838 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1839 1840 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1841 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1842 adapter->use_large_llq_hdr); 1843 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1844 rc = -EFAULT; 1845 goto err_device_destroy; 1846 } 1847 1848 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1849 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1850 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1851 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1852 adapter->max_num_io_queues = max_num_io_queues; 1853 1854 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1855 disable_meta_caching = 1856 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags & 1857 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 1858 } else { 1859 disable_meta_caching = false; 1860 } 1861 1862 /* prepare ring structures */ 1863 ena_init_rings(adapter, disable_meta_caching); 1864 1865 ena_config_debug_area(adapter); 1866 1867 /* Set max MTU for this device */ 1868 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1869 1870 /* set device support for offloads */ 1871 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1872 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1873 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1874 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1875 adapter->offloads.rx_csum_supported = 1876 (get_feat_ctx.offload.rx_supported & 1877 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1878 1879 /* Copy MAC address and point DPDK to it */ 1880 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1881 rte_ether_addr_copy((struct rte_ether_addr *) 1882 get_feat_ctx.dev_attr.mac_addr, 1883 (struct rte_ether_addr *)adapter->mac_addr); 1884 1885 adapter->drv_stats = rte_zmalloc("adapter stats", 1886 sizeof(*adapter->drv_stats), 1887 RTE_CACHE_LINE_SIZE); 1888 if (!adapter->drv_stats) { 1889 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1890 rc = -ENOMEM; 1891 goto err_delete_debug_area; 1892 } 1893 1894 rte_spinlock_init(&adapter->admin_lock); 1895 1896 rte_intr_callback_register(intr_handle, 1897 ena_interrupt_handler_rte, 1898 adapter); 1899 rte_intr_enable(intr_handle); 1900 ena_com_set_admin_polling_mode(ena_dev, false); 1901 ena_com_admin_aenq_enable(ena_dev); 1902 1903 if (adapters_found == 0) 1904 rte_timer_subsystem_init(); 1905 rte_timer_init(&adapter->timer_wd); 1906 1907 adapters_found++; 1908 adapter->state = ENA_ADAPTER_STATE_INIT; 1909 1910 return 0; 1911 1912 err_delete_debug_area: 1913 ena_com_delete_debug_area(ena_dev); 1914 1915 err_device_destroy: 1916 ena_com_delete_host_info(ena_dev); 1917 ena_com_admin_destroy(ena_dev); 1918 1919 err: 1920 return rc; 1921 } 1922 1923 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1924 { 1925 struct ena_adapter *adapter = eth_dev->data->dev_private; 1926 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1927 1928 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1929 return; 1930 1931 ena_com_set_admin_running_state(ena_dev, false); 1932 1933 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1934 ena_close(eth_dev); 1935 1936 ena_com_delete_debug_area(ena_dev); 1937 ena_com_delete_host_info(ena_dev); 1938 1939 ena_com_abort_admin_commands(ena_dev); 1940 ena_com_wait_for_abort_completion(ena_dev); 1941 ena_com_admin_destroy(ena_dev); 1942 ena_com_mmio_reg_read_request_destroy(ena_dev); 1943 1944 adapter->state = ENA_ADAPTER_STATE_FREE; 1945 } 1946 1947 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1948 { 1949 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1950 return 0; 1951 1952 ena_destroy_device(eth_dev); 1953 1954 return 0; 1955 } 1956 1957 static int ena_dev_configure(struct rte_eth_dev *dev) 1958 { 1959 struct ena_adapter *adapter = dev->data->dev_private; 1960 1961 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1962 1963 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1964 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1965 return 0; 1966 } 1967 1968 static void ena_init_rings(struct ena_adapter *adapter, 1969 bool disable_meta_caching) 1970 { 1971 size_t i; 1972 1973 for (i = 0; i < adapter->max_num_io_queues; i++) { 1974 struct ena_ring *ring = &adapter->tx_ring[i]; 1975 1976 ring->configured = 0; 1977 ring->type = ENA_RING_TYPE_TX; 1978 ring->adapter = adapter; 1979 ring->id = i; 1980 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1981 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1982 ring->sgl_size = adapter->max_tx_sgl_size; 1983 ring->disable_meta_caching = disable_meta_caching; 1984 } 1985 1986 for (i = 0; i < adapter->max_num_io_queues; i++) { 1987 struct ena_ring *ring = &adapter->rx_ring[i]; 1988 1989 ring->configured = 0; 1990 ring->type = ENA_RING_TYPE_RX; 1991 ring->adapter = adapter; 1992 ring->id = i; 1993 ring->sgl_size = adapter->max_rx_sgl_size; 1994 } 1995 } 1996 1997 static int ena_infos_get(struct rte_eth_dev *dev, 1998 struct rte_eth_dev_info *dev_info) 1999 { 2000 struct ena_adapter *adapter; 2001 struct ena_com_dev *ena_dev; 2002 uint64_t rx_feat = 0, tx_feat = 0; 2003 2004 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 2005 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 2006 adapter = dev->data->dev_private; 2007 2008 ena_dev = &adapter->ena_dev; 2009 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 2010 2011 dev_info->speed_capa = 2012 ETH_LINK_SPEED_1G | 2013 ETH_LINK_SPEED_2_5G | 2014 ETH_LINK_SPEED_5G | 2015 ETH_LINK_SPEED_10G | 2016 ETH_LINK_SPEED_25G | 2017 ETH_LINK_SPEED_40G | 2018 ETH_LINK_SPEED_50G | 2019 ETH_LINK_SPEED_100G; 2020 2021 /* Set Tx & Rx features available for device */ 2022 if (adapter->offloads.tso4_supported) 2023 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 2024 2025 if (adapter->offloads.tx_csum_supported) 2026 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 2027 DEV_TX_OFFLOAD_UDP_CKSUM | 2028 DEV_TX_OFFLOAD_TCP_CKSUM; 2029 2030 if (adapter->offloads.rx_csum_supported) 2031 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 2032 DEV_RX_OFFLOAD_UDP_CKSUM | 2033 DEV_RX_OFFLOAD_TCP_CKSUM; 2034 2035 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2036 2037 /* Inform framework about available features */ 2038 dev_info->rx_offload_capa = rx_feat; 2039 dev_info->rx_queue_offload_capa = rx_feat; 2040 dev_info->tx_offload_capa = tx_feat; 2041 dev_info->tx_queue_offload_capa = tx_feat; 2042 2043 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2044 ETH_RSS_UDP; 2045 2046 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2047 dev_info->max_rx_pktlen = adapter->max_mtu; 2048 dev_info->max_mac_addrs = 1; 2049 2050 dev_info->max_rx_queues = adapter->max_num_io_queues; 2051 dev_info->max_tx_queues = adapter->max_num_io_queues; 2052 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2053 2054 adapter->tx_supported_offloads = tx_feat; 2055 adapter->rx_supported_offloads = rx_feat; 2056 2057 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2058 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2059 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2060 adapter->max_rx_sgl_size); 2061 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2062 adapter->max_rx_sgl_size); 2063 2064 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2065 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2066 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2067 adapter->max_tx_sgl_size); 2068 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2069 adapter->max_tx_sgl_size); 2070 2071 return 0; 2072 } 2073 2074 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len) 2075 { 2076 mbuf->data_len = len; 2077 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2078 mbuf->refcnt = 1; 2079 mbuf->next = NULL; 2080 } 2081 2082 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring, 2083 struct ena_com_rx_buf_info *ena_bufs, 2084 uint32_t descs, 2085 uint16_t *next_to_clean, 2086 uint8_t offset) 2087 { 2088 struct rte_mbuf *mbuf; 2089 struct rte_mbuf *mbuf_head; 2090 struct ena_rx_buffer *rx_info; 2091 int rc; 2092 uint16_t ntc, len, req_id, buf = 0; 2093 2094 if (unlikely(descs == 0)) 2095 return NULL; 2096 2097 ntc = *next_to_clean; 2098 2099 len = ena_bufs[buf].len; 2100 req_id = ena_bufs[buf].req_id; 2101 2102 rx_info = &rx_ring->rx_buffer_info[req_id]; 2103 2104 mbuf = rx_info->mbuf; 2105 RTE_ASSERT(mbuf != NULL); 2106 2107 ena_init_rx_mbuf(mbuf, len); 2108 2109 /* Fill the mbuf head with the data specific for 1st segment. */ 2110 mbuf_head = mbuf; 2111 mbuf_head->nb_segs = descs; 2112 mbuf_head->port = rx_ring->port_id; 2113 mbuf_head->pkt_len = len; 2114 mbuf_head->data_off += offset; 2115 2116 rx_info->mbuf = NULL; 2117 rx_ring->empty_rx_reqs[ntc] = req_id; 2118 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2119 2120 while (--descs) { 2121 ++buf; 2122 len = ena_bufs[buf].len; 2123 req_id = ena_bufs[buf].req_id; 2124 2125 rx_info = &rx_ring->rx_buffer_info[req_id]; 2126 RTE_ASSERT(rx_info->mbuf != NULL); 2127 2128 if (unlikely(len == 0)) { 2129 /* 2130 * Some devices can pass descriptor with the length 0. 2131 * To avoid confusion, the PMD is simply putting the 2132 * descriptor back, as it was never used. We'll avoid 2133 * mbuf allocation that way. 2134 */ 2135 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq, 2136 rx_info->mbuf, req_id); 2137 if (unlikely(rc != 0)) { 2138 /* Free the mbuf in case of an error. */ 2139 rte_mbuf_raw_free(rx_info->mbuf); 2140 } else { 2141 /* 2142 * If there was no error, just exit the loop as 2143 * 0 length descriptor is always the last one. 2144 */ 2145 break; 2146 } 2147 } else { 2148 /* Create an mbuf chain. */ 2149 mbuf->next = rx_info->mbuf; 2150 mbuf = mbuf->next; 2151 2152 ena_init_rx_mbuf(mbuf, len); 2153 mbuf_head->pkt_len += len; 2154 } 2155 2156 /* 2157 * Mark the descriptor as depleted and perform necessary 2158 * cleanup. 2159 * This code will execute in two cases: 2160 * 1. Descriptor len was greater than 0 - normal situation. 2161 * 2. Descriptor len was 0 and we failed to add the descriptor 2162 * to the device. In that situation, we should try to add 2163 * the mbuf again in the populate routine and mark the 2164 * descriptor as used up by the device. 2165 */ 2166 rx_info->mbuf = NULL; 2167 rx_ring->empty_rx_reqs[ntc] = req_id; 2168 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask); 2169 } 2170 2171 *next_to_clean = ntc; 2172 2173 return mbuf_head; 2174 } 2175 2176 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2177 uint16_t nb_pkts) 2178 { 2179 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2180 unsigned int free_queue_entries; 2181 unsigned int refill_threshold; 2182 uint16_t next_to_clean = rx_ring->next_to_clean; 2183 uint16_t descs_in_use; 2184 struct rte_mbuf *mbuf; 2185 uint16_t completed; 2186 struct ena_com_rx_ctx ena_rx_ctx; 2187 int i, rc = 0; 2188 2189 /* Check adapter state */ 2190 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2191 PMD_DRV_LOG(ALERT, 2192 "Trying to receive pkts while device is NOT running\n"); 2193 return 0; 2194 } 2195 2196 descs_in_use = rx_ring->ring_size - 2197 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1; 2198 nb_pkts = RTE_MIN(descs_in_use, nb_pkts); 2199 2200 for (completed = 0; completed < nb_pkts; completed++) { 2201 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2202 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2203 ena_rx_ctx.descs = 0; 2204 ena_rx_ctx.pkt_offset = 0; 2205 /* receive packet context */ 2206 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2207 rx_ring->ena_com_io_sq, 2208 &ena_rx_ctx); 2209 if (unlikely(rc)) { 2210 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2211 if (rc == ENA_COM_NO_SPACE) { 2212 ++rx_ring->rx_stats.bad_desc_num; 2213 rx_ring->adapter->reset_reason = 2214 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2215 } else { 2216 ++rx_ring->rx_stats.bad_req_id; 2217 rx_ring->adapter->reset_reason = 2218 ENA_REGS_RESET_INV_RX_REQ_ID; 2219 } 2220 rx_ring->adapter->trigger_reset = true; 2221 return 0; 2222 } 2223 2224 mbuf = ena_rx_mbuf(rx_ring, 2225 ena_rx_ctx.ena_bufs, 2226 ena_rx_ctx.descs, 2227 &next_to_clean, 2228 ena_rx_ctx.pkt_offset); 2229 if (unlikely(mbuf == NULL)) { 2230 for (i = 0; i < ena_rx_ctx.descs; ++i) { 2231 rx_ring->empty_rx_reqs[next_to_clean] = 2232 rx_ring->ena_bufs[i].req_id; 2233 next_to_clean = ENA_IDX_NEXT_MASKED( 2234 next_to_clean, rx_ring->size_mask); 2235 } 2236 break; 2237 } 2238 2239 /* fill mbuf attributes if any */ 2240 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx); 2241 2242 if (unlikely(mbuf->ol_flags & 2243 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2244 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2245 ++rx_ring->rx_stats.bad_csum; 2246 } 2247 2248 mbuf->hash.rss = ena_rx_ctx.hash; 2249 2250 rx_pkts[completed] = mbuf; 2251 rx_ring->rx_stats.bytes += mbuf->pkt_len; 2252 } 2253 2254 rx_ring->rx_stats.cnt += completed; 2255 rx_ring->next_to_clean = next_to_clean; 2256 2257 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq); 2258 refill_threshold = 2259 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2260 (unsigned int)ENA_REFILL_THRESH_PACKET); 2261 2262 /* Burst refill to save doorbells, memory barriers, const interval */ 2263 if (free_queue_entries > refill_threshold) { 2264 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2265 ena_populate_rx_queue(rx_ring, free_queue_entries); 2266 } 2267 2268 return completed; 2269 } 2270 2271 static uint16_t 2272 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2273 uint16_t nb_pkts) 2274 { 2275 int32_t ret; 2276 uint32_t i; 2277 struct rte_mbuf *m; 2278 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2279 struct rte_ipv4_hdr *ip_hdr; 2280 uint64_t ol_flags; 2281 uint16_t frag_field; 2282 2283 for (i = 0; i != nb_pkts; i++) { 2284 m = tx_pkts[i]; 2285 ol_flags = m->ol_flags; 2286 2287 if (!(ol_flags & PKT_TX_IPV4)) 2288 continue; 2289 2290 /* If there was not L2 header length specified, assume it is 2291 * length of the ethernet header. 2292 */ 2293 if (unlikely(m->l2_len == 0)) 2294 m->l2_len = sizeof(struct rte_ether_hdr); 2295 2296 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2297 m->l2_len); 2298 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2299 2300 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2301 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2302 2303 /* If IPv4 header has DF flag enabled and TSO support is 2304 * disabled, partial chcecksum should not be calculated. 2305 */ 2306 if (!tx_ring->adapter->offloads.tso4_supported) 2307 continue; 2308 } 2309 2310 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2311 (ol_flags & PKT_TX_L4_MASK) == 2312 PKT_TX_SCTP_CKSUM) { 2313 rte_errno = ENOTSUP; 2314 return i; 2315 } 2316 2317 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2318 ret = rte_validate_tx_offload(m); 2319 if (ret != 0) { 2320 rte_errno = -ret; 2321 return i; 2322 } 2323 #endif 2324 2325 /* In case we are supposed to TSO and have DF not set (DF=0) 2326 * hardware must be provided with partial checksum, otherwise 2327 * it will take care of necessary calculations. 2328 */ 2329 2330 ret = rte_net_intel_cksum_flags_prepare(m, 2331 ol_flags & ~PKT_TX_TCP_SEG); 2332 if (ret != 0) { 2333 rte_errno = -ret; 2334 return i; 2335 } 2336 } 2337 2338 return i; 2339 } 2340 2341 static void ena_update_hints(struct ena_adapter *adapter, 2342 struct ena_admin_ena_hw_hints *hints) 2343 { 2344 if (hints->admin_completion_tx_timeout) 2345 adapter->ena_dev.admin_queue.completion_timeout = 2346 hints->admin_completion_tx_timeout * 1000; 2347 2348 if (hints->mmio_read_timeout) 2349 /* convert to usec */ 2350 adapter->ena_dev.mmio_read.reg_read_to = 2351 hints->mmio_read_timeout * 1000; 2352 2353 if (hints->driver_watchdog_timeout) { 2354 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2355 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2356 else 2357 // Convert msecs to ticks 2358 adapter->keep_alive_timeout = 2359 (hints->driver_watchdog_timeout * 2360 rte_get_timer_hz()) / 1000; 2361 } 2362 } 2363 2364 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring, 2365 struct rte_mbuf *mbuf) 2366 { 2367 struct ena_com_dev *ena_dev; 2368 int num_segments, header_len, rc; 2369 2370 ena_dev = &tx_ring->adapter->ena_dev; 2371 num_segments = mbuf->nb_segs; 2372 header_len = mbuf->data_len; 2373 2374 if (likely(num_segments < tx_ring->sgl_size)) 2375 goto checkspace; 2376 2377 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2378 (num_segments == tx_ring->sgl_size) && 2379 (header_len < tx_ring->tx_max_header_size)) 2380 goto checkspace; 2381 2382 /* Checking for space for 2 additional metadata descriptors due to 2383 * possible header split and metadata descriptor. Linearization will 2384 * be needed so we reduce the segments number from num_segments to 1 2385 */ 2386 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) { 2387 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n"); 2388 return ENA_COM_NO_MEM; 2389 } 2390 ++tx_ring->tx_stats.linearize; 2391 rc = rte_pktmbuf_linearize(mbuf); 2392 if (unlikely(rc)) { 2393 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2394 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2395 ++tx_ring->tx_stats.linearize_failed; 2396 return rc; 2397 } 2398 2399 return 0; 2400 2401 checkspace: 2402 /* Checking for space for 2 additional metadata descriptors due to 2403 * possible header split and metadata descriptor 2404 */ 2405 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 2406 num_segments + 2)) { 2407 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n"); 2408 return ENA_COM_NO_MEM; 2409 } 2410 2411 return 0; 2412 } 2413 2414 static void ena_tx_map_mbuf(struct ena_ring *tx_ring, 2415 struct ena_tx_buffer *tx_info, 2416 struct rte_mbuf *mbuf, 2417 void **push_header, 2418 uint16_t *header_len) 2419 { 2420 struct ena_com_buf *ena_buf; 2421 uint16_t delta, seg_len, push_len; 2422 2423 delta = 0; 2424 seg_len = mbuf->data_len; 2425 2426 tx_info->mbuf = mbuf; 2427 ena_buf = tx_info->bufs; 2428 2429 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2430 /* 2431 * Tx header might be (and will be in most cases) smaller than 2432 * tx_max_header_size. But it's not an issue to send more data 2433 * to the device, than actually needed if the mbuf size is 2434 * greater than tx_max_header_size. 2435 */ 2436 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size); 2437 *header_len = push_len; 2438 2439 if (likely(push_len <= seg_len)) { 2440 /* If the push header is in the single segment, then 2441 * just point it to the 1st mbuf data. 2442 */ 2443 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *); 2444 } else { 2445 /* If the push header lays in the several segments, copy 2446 * it to the intermediate buffer. 2447 */ 2448 rte_pktmbuf_read(mbuf, 0, push_len, 2449 tx_ring->push_buf_intermediate_buf); 2450 *push_header = tx_ring->push_buf_intermediate_buf; 2451 delta = push_len - seg_len; 2452 } 2453 } else { 2454 *push_header = NULL; 2455 *header_len = 0; 2456 push_len = 0; 2457 } 2458 2459 /* Process first segment taking into consideration pushed header */ 2460 if (seg_len > push_len) { 2461 ena_buf->paddr = mbuf->buf_iova + 2462 mbuf->data_off + 2463 push_len; 2464 ena_buf->len = seg_len - push_len; 2465 ena_buf++; 2466 tx_info->num_of_bufs++; 2467 } 2468 2469 while ((mbuf = mbuf->next) != NULL) { 2470 seg_len = mbuf->data_len; 2471 2472 /* Skip mbufs if whole data is pushed as a header */ 2473 if (unlikely(delta > seg_len)) { 2474 delta -= seg_len; 2475 continue; 2476 } 2477 2478 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2479 ena_buf->len = seg_len - delta; 2480 ena_buf++; 2481 tx_info->num_of_bufs++; 2482 2483 delta = 0; 2484 } 2485 } 2486 2487 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf) 2488 { 2489 struct ena_tx_buffer *tx_info; 2490 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } }; 2491 uint16_t next_to_use; 2492 uint16_t header_len; 2493 uint16_t req_id; 2494 void *push_header; 2495 int nb_hw_desc; 2496 int rc; 2497 2498 rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf); 2499 if (unlikely(rc)) 2500 return rc; 2501 2502 next_to_use = tx_ring->next_to_use; 2503 2504 req_id = tx_ring->empty_tx_reqs[next_to_use]; 2505 tx_info = &tx_ring->tx_buffer_info[req_id]; 2506 tx_info->num_of_bufs = 0; 2507 2508 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len); 2509 2510 ena_tx_ctx.ena_bufs = tx_info->bufs; 2511 ena_tx_ctx.push_header = push_header; 2512 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2513 ena_tx_ctx.req_id = req_id; 2514 ena_tx_ctx.header_len = header_len; 2515 2516 /* Set Tx offloads flags, if applicable */ 2517 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads, 2518 tx_ring->disable_meta_caching); 2519 2520 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2521 &ena_tx_ctx))) { 2522 PMD_DRV_LOG(DEBUG, 2523 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2524 tx_ring->id); 2525 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2526 tx_ring->tx_stats.doorbells++; 2527 tx_ring->pkts_without_db = false; 2528 } 2529 2530 /* prepare the packet's descriptors to dma engine */ 2531 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2532 &nb_hw_desc); 2533 if (unlikely(rc)) { 2534 ++tx_ring->tx_stats.prepare_ctx_err; 2535 return rc; 2536 } 2537 2538 tx_info->tx_descs = nb_hw_desc; 2539 2540 tx_ring->tx_stats.cnt++; 2541 tx_ring->tx_stats.bytes += mbuf->pkt_len; 2542 2543 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, 2544 tx_ring->size_mask); 2545 2546 return 0; 2547 } 2548 2549 static void ena_tx_cleanup(struct ena_ring *tx_ring) 2550 { 2551 unsigned int cleanup_budget; 2552 unsigned int total_tx_descs = 0; 2553 uint16_t next_to_clean = tx_ring->next_to_clean; 2554 2555 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER, 2556 (unsigned int)ENA_REFILL_THRESH_PACKET); 2557 2558 while (likely(total_tx_descs < cleanup_budget)) { 2559 struct rte_mbuf *mbuf; 2560 struct ena_tx_buffer *tx_info; 2561 uint16_t req_id; 2562 2563 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0) 2564 break; 2565 2566 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0)) 2567 break; 2568 2569 /* Get Tx info & store how many descs were processed */ 2570 tx_info = &tx_ring->tx_buffer_info[req_id]; 2571 2572 mbuf = tx_info->mbuf; 2573 rte_pktmbuf_free(mbuf); 2574 2575 tx_info->mbuf = NULL; 2576 tx_ring->empty_tx_reqs[next_to_clean] = req_id; 2577 2578 total_tx_descs += tx_info->tx_descs; 2579 2580 /* Put back descriptor to the ring for reuse */ 2581 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean, 2582 tx_ring->size_mask); 2583 } 2584 2585 if (likely(total_tx_descs > 0)) { 2586 /* acknowledge completion of sent packets */ 2587 tx_ring->next_to_clean = next_to_clean; 2588 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2589 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2590 } 2591 } 2592 2593 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2594 uint16_t nb_pkts) 2595 { 2596 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2597 uint16_t sent_idx = 0; 2598 2599 /* Check adapter state */ 2600 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2601 PMD_DRV_LOG(ALERT, 2602 "Trying to xmit pkts while device is NOT running\n"); 2603 return 0; 2604 } 2605 2606 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2607 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx])) 2608 break; 2609 tx_ring->pkts_without_db = true; 2610 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4, 2611 tx_ring->size_mask)]); 2612 } 2613 2614 tx_ring->tx_stats.available_desc = 2615 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2616 2617 /* If there are ready packets to be xmitted... */ 2618 if (likely(tx_ring->pkts_without_db)) { 2619 /* ...let HW do its best :-) */ 2620 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2621 tx_ring->tx_stats.doorbells++; 2622 tx_ring->pkts_without_db = false; 2623 } 2624 2625 ena_tx_cleanup(tx_ring); 2626 2627 tx_ring->tx_stats.available_desc = 2628 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2629 tx_ring->tx_stats.tx_poll++; 2630 2631 return sent_idx; 2632 } 2633 2634 int ena_copy_eni_stats(struct ena_adapter *adapter) 2635 { 2636 struct ena_admin_eni_stats admin_eni_stats; 2637 int rc; 2638 2639 rte_spinlock_lock(&adapter->admin_lock); 2640 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats); 2641 rte_spinlock_unlock(&adapter->admin_lock); 2642 if (rc != 0) { 2643 if (rc == ENA_COM_UNSUPPORTED) { 2644 PMD_DRV_LOG(DEBUG, 2645 "Retrieving ENI metrics is not supported.\n"); 2646 } else { 2647 PMD_DRV_LOG(WARNING, 2648 "Failed to get ENI metrics: %d\n", rc); 2649 } 2650 return rc; 2651 } 2652 2653 rte_memcpy(&adapter->eni_stats, &admin_eni_stats, 2654 sizeof(struct ena_stats_eni)); 2655 2656 return 0; 2657 } 2658 2659 /** 2660 * DPDK callback to retrieve names of extended device statistics 2661 * 2662 * @param dev 2663 * Pointer to Ethernet device structure. 2664 * @param[out] xstats_names 2665 * Buffer to insert names into. 2666 * @param n 2667 * Number of names. 2668 * 2669 * @return 2670 * Number of xstats names. 2671 */ 2672 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2673 struct rte_eth_xstat_name *xstats_names, 2674 unsigned int n) 2675 { 2676 unsigned int xstats_count = ena_xstats_calc_num(dev); 2677 unsigned int stat, i, count = 0; 2678 2679 if (n < xstats_count || !xstats_names) 2680 return xstats_count; 2681 2682 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2683 strcpy(xstats_names[count].name, 2684 ena_stats_global_strings[stat].name); 2685 2686 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) 2687 strcpy(xstats_names[count].name, 2688 ena_stats_eni_strings[stat].name); 2689 2690 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2691 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2692 snprintf(xstats_names[count].name, 2693 sizeof(xstats_names[count].name), 2694 "rx_q%d_%s", i, 2695 ena_stats_rx_strings[stat].name); 2696 2697 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2698 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2699 snprintf(xstats_names[count].name, 2700 sizeof(xstats_names[count].name), 2701 "tx_q%d_%s", i, 2702 ena_stats_tx_strings[stat].name); 2703 2704 return xstats_count; 2705 } 2706 2707 /** 2708 * DPDK callback to get extended device statistics. 2709 * 2710 * @param dev 2711 * Pointer to Ethernet device structure. 2712 * @param[out] stats 2713 * Stats table output buffer. 2714 * @param n 2715 * The size of the stats table. 2716 * 2717 * @return 2718 * Number of xstats on success, negative on failure. 2719 */ 2720 static int ena_xstats_get(struct rte_eth_dev *dev, 2721 struct rte_eth_xstat *xstats, 2722 unsigned int n) 2723 { 2724 struct ena_adapter *adapter = dev->data->dev_private; 2725 unsigned int xstats_count = ena_xstats_calc_num(dev); 2726 unsigned int stat, i, count = 0; 2727 int stat_offset; 2728 void *stats_begin; 2729 2730 if (n < xstats_count) 2731 return xstats_count; 2732 2733 if (!xstats) 2734 return 0; 2735 2736 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2737 stat_offset = ena_stats_global_strings[stat].stat_offset; 2738 stats_begin = &adapter->dev_stats; 2739 2740 xstats[count].id = count; 2741 xstats[count].value = *((uint64_t *) 2742 ((char *)stats_begin + stat_offset)); 2743 } 2744 2745 /* Even if the function below fails, we should copy previous (or initial 2746 * values) to keep structure of rte_eth_xstat consistent. 2747 */ 2748 ena_copy_eni_stats(adapter); 2749 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) { 2750 stat_offset = ena_stats_eni_strings[stat].stat_offset; 2751 stats_begin = &adapter->eni_stats; 2752 2753 xstats[count].id = count; 2754 xstats[count].value = *((uint64_t *) 2755 ((char *)stats_begin + stat_offset)); 2756 } 2757 2758 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2759 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2760 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2761 stats_begin = &adapter->rx_ring[i].rx_stats; 2762 2763 xstats[count].id = count; 2764 xstats[count].value = *((uint64_t *) 2765 ((char *)stats_begin + stat_offset)); 2766 } 2767 } 2768 2769 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2770 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2771 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2772 stats_begin = &adapter->tx_ring[i].rx_stats; 2773 2774 xstats[count].id = count; 2775 xstats[count].value = *((uint64_t *) 2776 ((char *)stats_begin + stat_offset)); 2777 } 2778 } 2779 2780 return count; 2781 } 2782 2783 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2784 const uint64_t *ids, 2785 uint64_t *values, 2786 unsigned int n) 2787 { 2788 struct ena_adapter *adapter = dev->data->dev_private; 2789 uint64_t id; 2790 uint64_t rx_entries, tx_entries; 2791 unsigned int i; 2792 int qid; 2793 int valid = 0; 2794 bool was_eni_copied = false; 2795 2796 for (i = 0; i < n; ++i) { 2797 id = ids[i]; 2798 /* Check if id belongs to global statistics */ 2799 if (id < ENA_STATS_ARRAY_GLOBAL) { 2800 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2801 ++valid; 2802 continue; 2803 } 2804 2805 /* Check if id belongs to ENI statistics */ 2806 id -= ENA_STATS_ARRAY_GLOBAL; 2807 if (id < ENA_STATS_ARRAY_ENI) { 2808 /* Avoid reading ENI stats multiple times in a single 2809 * function call, as it requires communication with the 2810 * admin queue. 2811 */ 2812 if (!was_eni_copied) { 2813 was_eni_copied = true; 2814 ena_copy_eni_stats(adapter); 2815 } 2816 values[i] = *((uint64_t *)&adapter->eni_stats + id); 2817 ++valid; 2818 continue; 2819 } 2820 2821 /* Check if id belongs to rx queue statistics */ 2822 id -= ENA_STATS_ARRAY_ENI; 2823 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2824 if (id < rx_entries) { 2825 qid = id % dev->data->nb_rx_queues; 2826 id /= dev->data->nb_rx_queues; 2827 values[i] = *((uint64_t *) 2828 &adapter->rx_ring[qid].rx_stats + id); 2829 ++valid; 2830 continue; 2831 } 2832 /* Check if id belongs to rx queue statistics */ 2833 id -= rx_entries; 2834 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2835 if (id < tx_entries) { 2836 qid = id % dev->data->nb_tx_queues; 2837 id /= dev->data->nb_tx_queues; 2838 values[i] = *((uint64_t *) 2839 &adapter->tx_ring[qid].tx_stats + id); 2840 ++valid; 2841 continue; 2842 } 2843 } 2844 2845 return valid; 2846 } 2847 2848 static int ena_process_bool_devarg(const char *key, 2849 const char *value, 2850 void *opaque) 2851 { 2852 struct ena_adapter *adapter = opaque; 2853 bool bool_value; 2854 2855 /* Parse the value. */ 2856 if (strcmp(value, "1") == 0) { 2857 bool_value = true; 2858 } else if (strcmp(value, "0") == 0) { 2859 bool_value = false; 2860 } else { 2861 PMD_INIT_LOG(ERR, 2862 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2863 value, key); 2864 return -EINVAL; 2865 } 2866 2867 /* Now, assign it to the proper adapter field. */ 2868 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) 2869 adapter->use_large_llq_hdr = bool_value; 2870 2871 return 0; 2872 } 2873 2874 static int ena_parse_devargs(struct ena_adapter *adapter, 2875 struct rte_devargs *devargs) 2876 { 2877 static const char * const allowed_args[] = { 2878 ENA_DEVARG_LARGE_LLQ_HDR, 2879 NULL, 2880 }; 2881 struct rte_kvargs *kvlist; 2882 int rc; 2883 2884 if (devargs == NULL) 2885 return 0; 2886 2887 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2888 if (kvlist == NULL) { 2889 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2890 devargs->args); 2891 return -EINVAL; 2892 } 2893 2894 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2895 ena_process_bool_devarg, adapter); 2896 2897 rte_kvargs_free(kvlist); 2898 2899 return rc; 2900 } 2901 2902 /********************************************************************* 2903 * PMD configuration 2904 *********************************************************************/ 2905 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2906 struct rte_pci_device *pci_dev) 2907 { 2908 return rte_eth_dev_pci_generic_probe(pci_dev, 2909 sizeof(struct ena_adapter), eth_ena_dev_init); 2910 } 2911 2912 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2913 { 2914 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2915 } 2916 2917 static struct rte_pci_driver rte_ena_pmd = { 2918 .id_table = pci_id_ena_map, 2919 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2920 RTE_PCI_DRV_WC_ACTIVATE, 2921 .probe = eth_ena_pci_probe, 2922 .remove = eth_ena_pci_remove, 2923 }; 2924 2925 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2926 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2927 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2928 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2929 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); 2930 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE); 2931 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2932 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, NOTICE); 2933 #endif 2934 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2935 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, NOTICE); 2936 #endif 2937 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2938 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx_free, tx_free, NOTICE); 2939 #endif 2940 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2941 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, NOTICE); 2942 #endif 2943 2944 /****************************************************************************** 2945 ******************************** AENQ Handlers ******************************* 2946 *****************************************************************************/ 2947 static void ena_update_on_link_change(void *adapter_data, 2948 struct ena_admin_aenq_entry *aenq_e) 2949 { 2950 struct rte_eth_dev *eth_dev; 2951 struct ena_adapter *adapter; 2952 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2953 uint32_t status; 2954 2955 adapter = adapter_data; 2956 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2957 eth_dev = adapter->rte_dev; 2958 2959 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2960 adapter->link_status = status; 2961 2962 ena_link_update(eth_dev, 0); 2963 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2964 } 2965 2966 static void ena_notification(void *data, 2967 struct ena_admin_aenq_entry *aenq_e) 2968 { 2969 struct ena_adapter *adapter = data; 2970 struct ena_admin_ena_hw_hints *hints; 2971 2972 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2973 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2974 aenq_e->aenq_common_desc.group, 2975 ENA_ADMIN_NOTIFICATION); 2976 2977 switch (aenq_e->aenq_common_desc.syndrome) { 2978 case ENA_ADMIN_UPDATE_HINTS: 2979 hints = (struct ena_admin_ena_hw_hints *) 2980 (&aenq_e->inline_data_w4); 2981 ena_update_hints(adapter, hints); 2982 break; 2983 default: 2984 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2985 aenq_e->aenq_common_desc.syndrome); 2986 } 2987 } 2988 2989 static void ena_keep_alive(void *adapter_data, 2990 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2991 { 2992 struct ena_adapter *adapter = adapter_data; 2993 struct ena_admin_aenq_keep_alive_desc *desc; 2994 uint64_t rx_drops; 2995 uint64_t tx_drops; 2996 2997 adapter->timestamp_wd = rte_get_timer_cycles(); 2998 2999 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3000 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3001 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; 3002 3003 adapter->drv_stats->rx_drops = rx_drops; 3004 adapter->dev_stats.tx_drops = tx_drops; 3005 } 3006 3007 /** 3008 * This handler will called for unknown event group or unimplemented handlers 3009 **/ 3010 static void unimplemented_aenq_handler(__rte_unused void *data, 3011 __rte_unused struct ena_admin_aenq_entry *aenq_e) 3012 { 3013 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 3014 "unimplemented handler\n"); 3015 } 3016 3017 static struct ena_aenq_handlers aenq_handlers = { 3018 .handlers = { 3019 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3020 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3021 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 3022 }, 3023 .unimplemented_handler = unimplemented_aenq_handler 3024 }; 3025