1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_ether.h> 35 #include <rte_ethdev_driver.h> 36 #include <rte_ethdev_pci.h> 37 #include <rte_tcp.h> 38 #include <rte_atomic.h> 39 #include <rte_dev.h> 40 #include <rte_errno.h> 41 #include <rte_version.h> 42 #include <rte_eal_memconfig.h> 43 #include <rte_net.h> 44 45 #include "ena_ethdev.h" 46 #include "ena_logs.h" 47 #include "ena_platform.h" 48 #include "ena_com.h" 49 #include "ena_eth_com.h" 50 51 #include <ena_common_defs.h> 52 #include <ena_regs_defs.h> 53 #include <ena_admin_defs.h> 54 #include <ena_eth_io_defs.h> 55 56 #define DRV_MODULE_VER_MAJOR 1 57 #define DRV_MODULE_VER_MINOR 0 58 #define DRV_MODULE_VER_SUBMINOR 0 59 60 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 62 /*reverse version of ENA_IO_RXQ_IDX*/ 63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 64 65 /* While processing submitted and completed descriptors (rx and tx path 66 * respectively) in a loop it is desired to: 67 * - perform batch submissions while populating sumbissmion queue 68 * - avoid blocking transmission of other packets during cleanup phase 69 * Hence the utilization ratio of 1/8 of a queue size. 70 */ 71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 72 73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 75 76 #define GET_L4_HDR_LEN(mbuf) \ 77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \ 78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 79 80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 82 #define ENA_HASH_KEY_SIZE 40 83 #define ENA_ETH_SS_STATS 0xFF 84 #define ETH_GSTRING_LEN 32 85 86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 87 88 enum ethtool_stringset { 89 ETH_SS_TEST = 0, 90 ETH_SS_STATS, 91 }; 92 93 struct ena_stats { 94 char name[ETH_GSTRING_LEN]; 95 int stat_offset; 96 }; 97 98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \ 99 .name = #stat, \ 100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \ 101 } 102 103 #define ENA_STAT_ENTRY(stat, stat_type) { \ 104 .name = #stat, \ 105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 106 } 107 108 #define ENA_STAT_RX_ENTRY(stat) \ 109 ENA_STAT_ENTRY(stat, rx) 110 111 #define ENA_STAT_TX_ENTRY(stat) \ 112 ENA_STAT_ENTRY(stat, tx) 113 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 115 ENA_STAT_ENTRY(stat, dev) 116 117 static const struct ena_stats ena_stats_global_strings[] = { 118 ENA_STAT_GLOBAL_ENTRY(tx_timeout), 119 ENA_STAT_GLOBAL_ENTRY(io_suspend), 120 ENA_STAT_GLOBAL_ENTRY(io_resume), 121 ENA_STAT_GLOBAL_ENTRY(wd_expired), 122 ENA_STAT_GLOBAL_ENTRY(interface_up), 123 ENA_STAT_GLOBAL_ENTRY(interface_down), 124 ENA_STAT_GLOBAL_ENTRY(admin_q_pause), 125 }; 126 127 static const struct ena_stats ena_stats_tx_strings[] = { 128 ENA_STAT_TX_ENTRY(cnt), 129 ENA_STAT_TX_ENTRY(bytes), 130 ENA_STAT_TX_ENTRY(queue_stop), 131 ENA_STAT_TX_ENTRY(queue_wakeup), 132 ENA_STAT_TX_ENTRY(dma_mapping_err), 133 ENA_STAT_TX_ENTRY(linearize), 134 ENA_STAT_TX_ENTRY(linearize_failed), 135 ENA_STAT_TX_ENTRY(tx_poll), 136 ENA_STAT_TX_ENTRY(doorbells), 137 ENA_STAT_TX_ENTRY(prepare_ctx_err), 138 ENA_STAT_TX_ENTRY(missing_tx_comp), 139 ENA_STAT_TX_ENTRY(bad_req_id), 140 }; 141 142 static const struct ena_stats ena_stats_rx_strings[] = { 143 ENA_STAT_RX_ENTRY(cnt), 144 ENA_STAT_RX_ENTRY(bytes), 145 ENA_STAT_RX_ENTRY(refil_partial), 146 ENA_STAT_RX_ENTRY(bad_csum), 147 ENA_STAT_RX_ENTRY(page_alloc_fail), 148 ENA_STAT_RX_ENTRY(skb_alloc_fail), 149 ENA_STAT_RX_ENTRY(dma_mapping_err), 150 ENA_STAT_RX_ENTRY(bad_desc_num), 151 ENA_STAT_RX_ENTRY(small_copy_len_pkt), 152 }; 153 154 static const struct ena_stats ena_stats_ena_com_strings[] = { 155 ENA_STAT_ENA_COM_ENTRY(aborted_cmd), 156 ENA_STAT_ENA_COM_ENTRY(submitted_cmd), 157 ENA_STAT_ENA_COM_ENTRY(completed_cmd), 158 ENA_STAT_ENA_COM_ENTRY(out_of_space), 159 ENA_STAT_ENA_COM_ENTRY(no_completion), 160 }; 161 162 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 163 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 164 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings) 166 167 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 168 DEV_TX_OFFLOAD_UDP_CKSUM |\ 169 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 170 DEV_TX_OFFLOAD_TCP_TSO) 171 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 172 PKT_TX_IP_CKSUM |\ 173 PKT_TX_TCP_SEG) 174 175 /** Vendor ID used by Amazon devices */ 176 #define PCI_VENDOR_ID_AMAZON 0x1D0F 177 /** Amazon devices */ 178 #define PCI_DEVICE_ID_ENA_VF 0xEC20 179 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 180 181 #define ENA_TX_OFFLOAD_MASK (\ 182 PKT_TX_L4_MASK | \ 183 PKT_TX_IP_CKSUM | \ 184 PKT_TX_TCP_SEG) 185 186 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 187 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 188 189 int ena_logtype_init; 190 int ena_logtype_driver; 191 192 static const struct rte_pci_id pci_id_ena_map[] = { 193 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 194 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 195 { .device_id = 0 }, 196 }; 197 198 static int ena_device_init(struct ena_com_dev *ena_dev, 199 struct ena_com_dev_get_features_ctx *get_feat_ctx); 200 static int ena_dev_configure(struct rte_eth_dev *dev); 201 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 202 uint16_t nb_pkts); 203 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 204 uint16_t nb_pkts); 205 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 206 uint16_t nb_desc, unsigned int socket_id, 207 const struct rte_eth_txconf *tx_conf); 208 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 209 uint16_t nb_desc, unsigned int socket_id, 210 const struct rte_eth_rxconf *rx_conf, 211 struct rte_mempool *mp); 212 static uint16_t eth_ena_recv_pkts(void *rx_queue, 213 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 214 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 215 static void ena_init_rings(struct ena_adapter *adapter); 216 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 217 static int ena_start(struct rte_eth_dev *dev); 218 static void ena_close(struct rte_eth_dev *dev); 219 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 220 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 221 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 222 static void ena_rx_queue_release(void *queue); 223 static void ena_tx_queue_release(void *queue); 224 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 225 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 226 static int ena_link_update(struct rte_eth_dev *dev, 227 int wait_to_complete); 228 static int ena_queue_restart(struct ena_ring *ring); 229 static int ena_queue_restart_all(struct rte_eth_dev *dev, 230 enum ena_ring_type ring_type); 231 static void ena_stats_restart(struct rte_eth_dev *dev); 232 static void ena_infos_get(struct rte_eth_dev *dev, 233 struct rte_eth_dev_info *dev_info); 234 static int ena_rss_reta_update(struct rte_eth_dev *dev, 235 struct rte_eth_rss_reta_entry64 *reta_conf, 236 uint16_t reta_size); 237 static int ena_rss_reta_query(struct rte_eth_dev *dev, 238 struct rte_eth_rss_reta_entry64 *reta_conf, 239 uint16_t reta_size); 240 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset); 241 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter, 242 uint64_t offloads); 243 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter, 244 uint64_t offloads); 245 246 static const struct eth_dev_ops ena_dev_ops = { 247 .dev_configure = ena_dev_configure, 248 .dev_infos_get = ena_infos_get, 249 .rx_queue_setup = ena_rx_queue_setup, 250 .tx_queue_setup = ena_tx_queue_setup, 251 .dev_start = ena_start, 252 .link_update = ena_link_update, 253 .stats_get = ena_stats_get, 254 .mtu_set = ena_mtu_set, 255 .rx_queue_release = ena_rx_queue_release, 256 .tx_queue_release = ena_tx_queue_release, 257 .dev_close = ena_close, 258 .reta_update = ena_rss_reta_update, 259 .reta_query = ena_rss_reta_query, 260 }; 261 262 #define NUMA_NO_NODE SOCKET_ID_ANY 263 264 static inline int ena_cpu_to_node(int cpu) 265 { 266 struct rte_config *config = rte_eal_get_configuration(); 267 268 if (likely(cpu < RTE_MAX_MEMZONE)) 269 return config->mem_config->memzone[cpu].socket_id; 270 271 return NUMA_NO_NODE; 272 } 273 274 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 275 struct ena_com_rx_ctx *ena_rx_ctx) 276 { 277 uint64_t ol_flags = 0; 278 uint32_t packet_type = 0; 279 280 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 281 packet_type |= RTE_PTYPE_L4_TCP; 282 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 283 packet_type |= RTE_PTYPE_L4_UDP; 284 285 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 286 packet_type |= RTE_PTYPE_L3_IPV4; 287 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 288 packet_type |= RTE_PTYPE_L3_IPV6; 289 290 if (unlikely(ena_rx_ctx->l4_csum_err)) 291 ol_flags |= PKT_RX_L4_CKSUM_BAD; 292 if (unlikely(ena_rx_ctx->l3_csum_err)) 293 ol_flags |= PKT_RX_IP_CKSUM_BAD; 294 295 mbuf->ol_flags = ol_flags; 296 mbuf->packet_type = packet_type; 297 } 298 299 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 300 struct ena_com_tx_ctx *ena_tx_ctx, 301 uint64_t queue_offloads) 302 { 303 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 304 305 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 306 (queue_offloads & QUEUE_OFFLOADS)) { 307 /* check if TSO is required */ 308 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 309 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 310 ena_tx_ctx->tso_enable = true; 311 312 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 313 } 314 315 /* check if L3 checksum is needed */ 316 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 317 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 318 ena_tx_ctx->l3_csum_enable = true; 319 320 if (mbuf->ol_flags & PKT_TX_IPV6) { 321 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 322 } else { 323 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 324 325 /* set don't fragment (DF) flag */ 326 if (mbuf->packet_type & 327 (RTE_PTYPE_L4_NONFRAG 328 | RTE_PTYPE_INNER_L4_NONFRAG)) 329 ena_tx_ctx->df = true; 330 } 331 332 /* check if L4 checksum is needed */ 333 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) && 334 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 335 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 336 ena_tx_ctx->l4_csum_enable = true; 337 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 339 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 340 ena_tx_ctx->l4_csum_enable = true; 341 } else { 342 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 343 ena_tx_ctx->l4_csum_enable = false; 344 } 345 346 ena_meta->mss = mbuf->tso_segsz; 347 ena_meta->l3_hdr_len = mbuf->l3_len; 348 ena_meta->l3_hdr_offset = mbuf->l2_len; 349 /* this param needed only for TSO */ 350 ena_meta->l3_outer_hdr_len = 0; 351 ena_meta->l3_outer_hdr_offset = 0; 352 353 ena_tx_ctx->meta_valid = true; 354 } else { 355 ena_tx_ctx->meta_valid = false; 356 } 357 } 358 359 static void ena_config_host_info(struct ena_com_dev *ena_dev) 360 { 361 struct ena_admin_host_info *host_info; 362 int rc; 363 364 /* Allocate only the host info */ 365 rc = ena_com_allocate_host_info(ena_dev); 366 if (rc) { 367 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 368 return; 369 } 370 371 host_info = ena_dev->host_attr.host_info; 372 373 host_info->os_type = ENA_ADMIN_OS_DPDK; 374 host_info->kernel_ver = RTE_VERSION; 375 snprintf((char *)host_info->kernel_ver_str, 376 sizeof(host_info->kernel_ver_str), 377 "%s", rte_version()); 378 host_info->os_dist = RTE_VERSION; 379 snprintf((char *)host_info->os_dist_str, 380 sizeof(host_info->os_dist_str), 381 "%s", rte_version()); 382 host_info->driver_version = 383 (DRV_MODULE_VER_MAJOR) | 384 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 385 (DRV_MODULE_VER_SUBMINOR << 386 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 387 388 rc = ena_com_set_host_attributes(ena_dev); 389 if (rc) { 390 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 391 if (rc != -EPERM) 392 goto err; 393 } 394 395 return; 396 397 err: 398 ena_com_delete_host_info(ena_dev); 399 } 400 401 static int 402 ena_get_sset_count(struct rte_eth_dev *dev, int sset) 403 { 404 if (sset != ETH_SS_STATS) 405 return -EOPNOTSUPP; 406 407 /* Workaround for clang: 408 * touch internal structures to prevent 409 * compiler error 410 */ 411 ENA_TOUCH(ena_stats_global_strings); 412 ENA_TOUCH(ena_stats_tx_strings); 413 ENA_TOUCH(ena_stats_rx_strings); 414 ENA_TOUCH(ena_stats_ena_com_strings); 415 416 return dev->data->nb_tx_queues * 417 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) + 418 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM; 419 } 420 421 static void ena_config_debug_area(struct ena_adapter *adapter) 422 { 423 u32 debug_area_size; 424 int rc, ss_count; 425 426 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS); 427 if (ss_count <= 0) { 428 RTE_LOG(ERR, PMD, "SS count is negative\n"); 429 return; 430 } 431 432 /* allocate 32 bytes for each string and 64bit for the value */ 433 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 434 435 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 436 if (rc) { 437 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 438 return; 439 } 440 441 rc = ena_com_set_host_attributes(&adapter->ena_dev); 442 if (rc) { 443 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 444 if (rc != -EPERM) 445 goto err; 446 } 447 448 return; 449 err: 450 ena_com_delete_debug_area(&adapter->ena_dev); 451 } 452 453 static void ena_close(struct rte_eth_dev *dev) 454 { 455 struct ena_adapter *adapter = 456 (struct ena_adapter *)(dev->data->dev_private); 457 458 adapter->state = ENA_ADAPTER_STATE_STOPPED; 459 460 ena_rx_queue_release_all(dev); 461 ena_tx_queue_release_all(dev); 462 } 463 464 static int ena_rss_reta_update(struct rte_eth_dev *dev, 465 struct rte_eth_rss_reta_entry64 *reta_conf, 466 uint16_t reta_size) 467 { 468 struct ena_adapter *adapter = 469 (struct ena_adapter *)(dev->data->dev_private); 470 struct ena_com_dev *ena_dev = &adapter->ena_dev; 471 int ret, i; 472 u16 entry_value; 473 int conf_idx; 474 int idx; 475 476 if ((reta_size == 0) || (reta_conf == NULL)) 477 return -EINVAL; 478 479 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 480 RTE_LOG(WARNING, PMD, 481 "indirection table %d is bigger than supported (%d)\n", 482 reta_size, ENA_RX_RSS_TABLE_SIZE); 483 ret = -EINVAL; 484 goto err; 485 } 486 487 for (i = 0 ; i < reta_size ; i++) { 488 /* each reta_conf is for 64 entries. 489 * to support 128 we use 2 conf of 64 490 */ 491 conf_idx = i / RTE_RETA_GROUP_SIZE; 492 idx = i % RTE_RETA_GROUP_SIZE; 493 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 494 entry_value = 495 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 496 ret = ena_com_indirect_table_fill_entry(ena_dev, 497 i, 498 entry_value); 499 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) { 500 RTE_LOG(ERR, PMD, 501 "Cannot fill indirect table\n"); 502 ret = -ENOTSUP; 503 goto err; 504 } 505 } 506 } 507 508 ret = ena_com_indirect_table_set(ena_dev); 509 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) { 510 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 511 ret = -ENOTSUP; 512 goto err; 513 } 514 515 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 516 __func__, reta_size, adapter->rte_dev->data->port_id); 517 err: 518 return ret; 519 } 520 521 /* Query redirection table. */ 522 static int ena_rss_reta_query(struct rte_eth_dev *dev, 523 struct rte_eth_rss_reta_entry64 *reta_conf, 524 uint16_t reta_size) 525 { 526 struct ena_adapter *adapter = 527 (struct ena_adapter *)(dev->data->dev_private); 528 struct ena_com_dev *ena_dev = &adapter->ena_dev; 529 int ret; 530 int i; 531 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 532 int reta_conf_idx; 533 int reta_idx; 534 535 if (reta_size == 0 || reta_conf == NULL || 536 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 537 return -EINVAL; 538 539 ret = ena_com_indirect_table_get(ena_dev, indirect_table); 540 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) { 541 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 542 ret = -ENOTSUP; 543 goto err; 544 } 545 546 for (i = 0 ; i < reta_size ; i++) { 547 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 548 reta_idx = i % RTE_RETA_GROUP_SIZE; 549 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 550 reta_conf[reta_conf_idx].reta[reta_idx] = 551 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 552 } 553 err: 554 return ret; 555 } 556 557 static int ena_rss_init_default(struct ena_adapter *adapter) 558 { 559 struct ena_com_dev *ena_dev = &adapter->ena_dev; 560 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 561 int rc, i; 562 u32 val; 563 564 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 565 if (unlikely(rc)) { 566 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 567 goto err_rss_init; 568 } 569 570 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 571 val = i % nb_rx_queues; 572 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 573 ENA_IO_RXQ_IDX(val)); 574 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) { 575 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 576 goto err_fill_indir; 577 } 578 } 579 580 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 581 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 582 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) { 583 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 584 goto err_fill_indir; 585 } 586 587 rc = ena_com_set_default_hash_ctrl(ena_dev); 588 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) { 589 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 590 goto err_fill_indir; 591 } 592 593 rc = ena_com_indirect_table_set(ena_dev); 594 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) { 595 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 596 goto err_fill_indir; 597 } 598 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 599 adapter->rte_dev->data->port_id); 600 601 return 0; 602 603 err_fill_indir: 604 ena_com_rss_destroy(ena_dev); 605 err_rss_init: 606 607 return rc; 608 } 609 610 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 611 { 612 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 613 int nb_queues = dev->data->nb_rx_queues; 614 int i; 615 616 for (i = 0; i < nb_queues; i++) 617 ena_rx_queue_release(queues[i]); 618 } 619 620 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 621 { 622 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 623 int nb_queues = dev->data->nb_tx_queues; 624 int i; 625 626 for (i = 0; i < nb_queues; i++) 627 ena_tx_queue_release(queues[i]); 628 } 629 630 static void ena_rx_queue_release(void *queue) 631 { 632 struct ena_ring *ring = (struct ena_ring *)queue; 633 struct ena_adapter *adapter = ring->adapter; 634 int ena_qid; 635 636 ena_assert_msg(ring->configured, 637 "API violation - releasing not configured queue"); 638 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING, 639 "API violation"); 640 641 /* Destroy HW queue */ 642 ena_qid = ENA_IO_RXQ_IDX(ring->id); 643 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid); 644 645 /* Free all bufs */ 646 ena_rx_queue_release_bufs(ring); 647 648 /* Free ring resources */ 649 if (ring->rx_buffer_info) 650 rte_free(ring->rx_buffer_info); 651 ring->rx_buffer_info = NULL; 652 653 ring->configured = 0; 654 655 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 656 ring->port_id, ring->id); 657 } 658 659 static void ena_tx_queue_release(void *queue) 660 { 661 struct ena_ring *ring = (struct ena_ring *)queue; 662 struct ena_adapter *adapter = ring->adapter; 663 int ena_qid; 664 665 ena_assert_msg(ring->configured, 666 "API violation. Releasing not configured queue"); 667 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING, 668 "API violation"); 669 670 /* Destroy HW queue */ 671 ena_qid = ENA_IO_TXQ_IDX(ring->id); 672 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid); 673 674 /* Free all bufs */ 675 ena_tx_queue_release_bufs(ring); 676 677 /* Free ring resources */ 678 if (ring->tx_buffer_info) 679 rte_free(ring->tx_buffer_info); 680 681 if (ring->empty_tx_reqs) 682 rte_free(ring->empty_tx_reqs); 683 684 ring->empty_tx_reqs = NULL; 685 ring->tx_buffer_info = NULL; 686 687 ring->configured = 0; 688 689 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 690 ring->port_id, ring->id); 691 } 692 693 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 694 { 695 unsigned int ring_mask = ring->ring_size - 1; 696 697 while (ring->next_to_clean != ring->next_to_use) { 698 struct rte_mbuf *m = 699 ring->rx_buffer_info[ring->next_to_clean & ring_mask]; 700 701 if (m) 702 rte_mbuf_raw_free(m); 703 704 ring->next_to_clean++; 705 } 706 } 707 708 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 709 { 710 unsigned int i; 711 712 for (i = 0; i < ring->ring_size; ++i) { 713 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 714 715 if (tx_buf->mbuf) 716 rte_pktmbuf_free(tx_buf->mbuf); 717 718 ring->next_to_clean++; 719 } 720 } 721 722 static int ena_link_update(struct rte_eth_dev *dev, 723 __rte_unused int wait_to_complete) 724 { 725 struct rte_eth_link *link = &dev->data->dev_link; 726 727 link->link_status = 1; 728 link->link_speed = ETH_SPEED_NUM_10G; 729 link->link_duplex = ETH_LINK_FULL_DUPLEX; 730 731 return 0; 732 } 733 734 static int ena_queue_restart_all(struct rte_eth_dev *dev, 735 enum ena_ring_type ring_type) 736 { 737 struct ena_adapter *adapter = 738 (struct ena_adapter *)(dev->data->dev_private); 739 struct ena_ring *queues = NULL; 740 int i = 0; 741 int rc = 0; 742 743 queues = (ring_type == ENA_RING_TYPE_RX) ? 744 adapter->rx_ring : adapter->tx_ring; 745 746 for (i = 0; i < adapter->num_queues; i++) { 747 if (queues[i].configured) { 748 if (ring_type == ENA_RING_TYPE_RX) { 749 ena_assert_msg( 750 dev->data->rx_queues[i] == &queues[i], 751 "Inconsistent state of rx queues\n"); 752 } else { 753 ena_assert_msg( 754 dev->data->tx_queues[i] == &queues[i], 755 "Inconsistent state of tx queues\n"); 756 } 757 758 rc = ena_queue_restart(&queues[i]); 759 760 if (rc) { 761 PMD_INIT_LOG(ERR, 762 "failed to restart queue %d type(%d)", 763 i, ring_type); 764 return -1; 765 } 766 } 767 } 768 769 return 0; 770 } 771 772 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 773 { 774 uint32_t max_frame_len = adapter->max_mtu; 775 776 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 777 DEV_RX_OFFLOAD_JUMBO_FRAME) 778 max_frame_len = 779 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 780 781 return max_frame_len; 782 } 783 784 static int ena_check_valid_conf(struct ena_adapter *adapter) 785 { 786 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 787 788 if (max_frame_len > adapter->max_mtu) { 789 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len); 790 return -1; 791 } 792 793 return 0; 794 } 795 796 static int 797 ena_calc_queue_size(struct ena_com_dev *ena_dev, 798 struct ena_com_dev_get_features_ctx *get_feat_ctx) 799 { 800 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 801 802 queue_size = RTE_MIN(queue_size, 803 get_feat_ctx->max_queues.max_cq_depth); 804 queue_size = RTE_MIN(queue_size, 805 get_feat_ctx->max_queues.max_sq_depth); 806 807 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 808 queue_size = RTE_MIN(queue_size, 809 get_feat_ctx->max_queues.max_llq_depth); 810 811 /* Round down to power of 2 */ 812 if (!rte_is_power_of_2(queue_size)) 813 queue_size = rte_align32pow2(queue_size >> 1); 814 815 if (queue_size == 0) { 816 PMD_INIT_LOG(ERR, "Invalid queue size"); 817 return -EFAULT; 818 } 819 820 return queue_size; 821 } 822 823 static void ena_stats_restart(struct rte_eth_dev *dev) 824 { 825 struct ena_adapter *adapter = 826 (struct ena_adapter *)(dev->data->dev_private); 827 828 rte_atomic64_init(&adapter->drv_stats->ierrors); 829 rte_atomic64_init(&adapter->drv_stats->oerrors); 830 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 831 } 832 833 static int ena_stats_get(struct rte_eth_dev *dev, 834 struct rte_eth_stats *stats) 835 { 836 struct ena_admin_basic_stats ena_stats; 837 struct ena_adapter *adapter = 838 (struct ena_adapter *)(dev->data->dev_private); 839 struct ena_com_dev *ena_dev = &adapter->ena_dev; 840 int rc; 841 842 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 843 return -ENOTSUP; 844 845 memset(&ena_stats, 0, sizeof(ena_stats)); 846 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 847 if (unlikely(rc)) { 848 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA"); 849 return rc; 850 } 851 852 /* Set of basic statistics from ENA */ 853 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 854 ena_stats.rx_pkts_low); 855 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 856 ena_stats.tx_pkts_low); 857 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 858 ena_stats.rx_bytes_low); 859 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 860 ena_stats.tx_bytes_low); 861 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high, 862 ena_stats.rx_drops_low); 863 864 /* Driver related stats */ 865 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 866 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 867 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 868 return 0; 869 } 870 871 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 872 { 873 struct ena_adapter *adapter; 874 struct ena_com_dev *ena_dev; 875 int rc = 0; 876 877 ena_assert_msg(dev->data != NULL, "Uninitialized device"); 878 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device"); 879 adapter = (struct ena_adapter *)(dev->data->dev_private); 880 881 ena_dev = &adapter->ena_dev; 882 ena_assert_msg(ena_dev != NULL, "Uninitialized device"); 883 884 if (mtu > ena_get_mtu_conf(adapter)) { 885 RTE_LOG(ERR, PMD, 886 "Given MTU (%d) exceeds maximum MTU supported (%d)\n", 887 mtu, ena_get_mtu_conf(adapter)); 888 rc = -EINVAL; 889 goto err; 890 } 891 892 rc = ena_com_set_dev_mtu(ena_dev, mtu); 893 if (rc) 894 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 895 else 896 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 897 898 err: 899 return rc; 900 } 901 902 static int ena_start(struct rte_eth_dev *dev) 903 { 904 struct ena_adapter *adapter = 905 (struct ena_adapter *)(dev->data->dev_private); 906 int rc = 0; 907 908 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG || 909 adapter->state == ENA_ADAPTER_STATE_STOPPED)) { 910 PMD_INIT_LOG(ERR, "API violation"); 911 return -1; 912 } 913 914 rc = ena_check_valid_conf(adapter); 915 if (rc) 916 return rc; 917 918 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX); 919 if (rc) 920 return rc; 921 922 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX); 923 if (rc) 924 return rc; 925 926 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 927 ETH_MQ_RX_RSS_FLAG) { 928 rc = ena_rss_init_default(adapter); 929 if (rc) 930 return rc; 931 } 932 933 ena_stats_restart(dev); 934 935 adapter->state = ENA_ADAPTER_STATE_RUNNING; 936 937 return 0; 938 } 939 940 static int ena_queue_restart(struct ena_ring *ring) 941 { 942 int rc, bufs_num; 943 944 ena_assert_msg(ring->configured == 1, 945 "Trying to restart unconfigured queue\n"); 946 947 ring->next_to_clean = 0; 948 ring->next_to_use = 0; 949 950 if (ring->type == ENA_RING_TYPE_TX) 951 return 0; 952 953 bufs_num = ring->ring_size - 1; 954 rc = ena_populate_rx_queue(ring, bufs_num); 955 if (rc != bufs_num) { 956 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 957 return (-1); 958 } 959 960 return 0; 961 } 962 963 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 964 uint16_t queue_idx, 965 uint16_t nb_desc, 966 __rte_unused unsigned int socket_id, 967 const struct rte_eth_txconf *tx_conf) 968 { 969 struct ena_com_create_io_ctx ctx = 970 /* policy set to _HOST just to satisfy icc compiler */ 971 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 972 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 }; 973 struct ena_ring *txq = NULL; 974 struct ena_adapter *adapter = 975 (struct ena_adapter *)(dev->data->dev_private); 976 unsigned int i; 977 int ena_qid; 978 int rc; 979 struct ena_com_dev *ena_dev = &adapter->ena_dev; 980 981 txq = &adapter->tx_ring[queue_idx]; 982 983 if (txq->configured) { 984 RTE_LOG(CRIT, PMD, 985 "API violation. Queue %d is already configured\n", 986 queue_idx); 987 return -1; 988 } 989 990 if (!rte_is_power_of_2(nb_desc)) { 991 RTE_LOG(ERR, PMD, 992 "Unsupported size of RX queue: %d is not a power of 2.", 993 nb_desc); 994 return -EINVAL; 995 } 996 997 if (nb_desc > adapter->tx_ring_size) { 998 RTE_LOG(ERR, PMD, 999 "Unsupported size of TX queue (max size: %d)\n", 1000 adapter->tx_ring_size); 1001 return -EINVAL; 1002 } 1003 1004 if (tx_conf->txq_flags == ETH_TXQ_FLAGS_IGNORE && 1005 !ena_are_tx_queue_offloads_allowed(adapter, tx_conf->offloads)) { 1006 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n"); 1007 return -EINVAL; 1008 } 1009 1010 ena_qid = ENA_IO_TXQ_IDX(queue_idx); 1011 1012 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1013 ctx.qid = ena_qid; 1014 ctx.msix_vector = -1; /* admin interrupts not used */ 1015 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1016 ctx.queue_size = adapter->tx_ring_size; 1017 ctx.numa_node = ena_cpu_to_node(queue_idx); 1018 1019 rc = ena_com_create_io_queue(ena_dev, &ctx); 1020 if (rc) { 1021 RTE_LOG(ERR, PMD, 1022 "failed to create io TX queue #%d (qid:%d) rc: %d\n", 1023 queue_idx, ena_qid, rc); 1024 } 1025 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid]; 1026 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid]; 1027 1028 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1029 &txq->ena_com_io_sq, 1030 &txq->ena_com_io_cq); 1031 if (rc) { 1032 RTE_LOG(ERR, PMD, 1033 "Failed to get TX queue handlers. TX queue num %d rc: %d\n", 1034 queue_idx, rc); 1035 ena_com_destroy_io_queue(ena_dev, ena_qid); 1036 goto err; 1037 } 1038 1039 txq->port_id = dev->data->port_id; 1040 txq->next_to_clean = 0; 1041 txq->next_to_use = 0; 1042 txq->ring_size = nb_desc; 1043 1044 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1045 sizeof(struct ena_tx_buffer) * 1046 txq->ring_size, 1047 RTE_CACHE_LINE_SIZE); 1048 if (!txq->tx_buffer_info) { 1049 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1050 return -ENOMEM; 1051 } 1052 1053 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1054 sizeof(u16) * txq->ring_size, 1055 RTE_CACHE_LINE_SIZE); 1056 if (!txq->empty_tx_reqs) { 1057 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1058 rte_free(txq->tx_buffer_info); 1059 return -ENOMEM; 1060 } 1061 for (i = 0; i < txq->ring_size; i++) 1062 txq->empty_tx_reqs[i] = i; 1063 1064 txq->offloads = tx_conf->offloads; 1065 1066 /* Store pointer to this queue in upper layer */ 1067 txq->configured = 1; 1068 dev->data->tx_queues[queue_idx] = txq; 1069 err: 1070 return rc; 1071 } 1072 1073 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1074 uint16_t queue_idx, 1075 uint16_t nb_desc, 1076 __rte_unused unsigned int socket_id, 1077 const struct rte_eth_rxconf *rx_conf, 1078 struct rte_mempool *mp) 1079 { 1080 struct ena_com_create_io_ctx ctx = 1081 /* policy set to _HOST just to satisfy icc compiler */ 1082 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1083 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 }; 1084 struct ena_adapter *adapter = 1085 (struct ena_adapter *)(dev->data->dev_private); 1086 struct ena_ring *rxq = NULL; 1087 uint16_t ena_qid = 0; 1088 int rc = 0; 1089 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1090 1091 rxq = &adapter->rx_ring[queue_idx]; 1092 if (rxq->configured) { 1093 RTE_LOG(CRIT, PMD, 1094 "API violation. Queue %d is already configured\n", 1095 queue_idx); 1096 return -1; 1097 } 1098 1099 if (!rte_is_power_of_2(nb_desc)) { 1100 RTE_LOG(ERR, PMD, 1101 "Unsupported size of TX queue: %d is not a power of 2.", 1102 nb_desc); 1103 return -EINVAL; 1104 } 1105 1106 if (nb_desc > adapter->rx_ring_size) { 1107 RTE_LOG(ERR, PMD, 1108 "Unsupported size of RX queue (max size: %d)\n", 1109 adapter->rx_ring_size); 1110 return -EINVAL; 1111 } 1112 1113 if (!ena_are_rx_queue_offloads_allowed(adapter, rx_conf->offloads)) { 1114 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n"); 1115 return -EINVAL; 1116 } 1117 1118 ena_qid = ENA_IO_RXQ_IDX(queue_idx); 1119 1120 ctx.qid = ena_qid; 1121 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1122 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1123 ctx.msix_vector = -1; /* admin interrupts not used */ 1124 ctx.queue_size = adapter->rx_ring_size; 1125 ctx.numa_node = ena_cpu_to_node(queue_idx); 1126 1127 rc = ena_com_create_io_queue(ena_dev, &ctx); 1128 if (rc) 1129 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n", 1130 queue_idx, rc); 1131 1132 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid]; 1133 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid]; 1134 1135 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1136 &rxq->ena_com_io_sq, 1137 &rxq->ena_com_io_cq); 1138 if (rc) { 1139 RTE_LOG(ERR, PMD, 1140 "Failed to get RX queue handlers. RX queue num %d rc: %d\n", 1141 queue_idx, rc); 1142 ena_com_destroy_io_queue(ena_dev, ena_qid); 1143 } 1144 1145 rxq->port_id = dev->data->port_id; 1146 rxq->next_to_clean = 0; 1147 rxq->next_to_use = 0; 1148 rxq->ring_size = nb_desc; 1149 rxq->mb_pool = mp; 1150 1151 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1152 sizeof(struct rte_mbuf *) * nb_desc, 1153 RTE_CACHE_LINE_SIZE); 1154 if (!rxq->rx_buffer_info) { 1155 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1156 return -ENOMEM; 1157 } 1158 1159 /* Store pointer to this queue in upper layer */ 1160 rxq->configured = 1; 1161 dev->data->rx_queues[queue_idx] = rxq; 1162 1163 return rc; 1164 } 1165 1166 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1167 { 1168 unsigned int i; 1169 int rc; 1170 uint16_t ring_size = rxq->ring_size; 1171 uint16_t ring_mask = ring_size - 1; 1172 uint16_t next_to_use = rxq->next_to_use; 1173 uint16_t in_use; 1174 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0]; 1175 1176 if (unlikely(!count)) 1177 return 0; 1178 1179 in_use = rxq->next_to_use - rxq->next_to_clean; 1180 ena_assert_msg(((in_use + count) < ring_size), "bad ring state"); 1181 1182 count = RTE_MIN(count, 1183 (uint16_t)(ring_size - (next_to_use & ring_mask))); 1184 1185 /* get resources for incoming packets */ 1186 rc = rte_mempool_get_bulk(rxq->mb_pool, 1187 (void **)(&mbufs[next_to_use & ring_mask]), 1188 count); 1189 if (unlikely(rc < 0)) { 1190 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1191 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1192 return 0; 1193 } 1194 1195 for (i = 0; i < count; i++) { 1196 uint16_t next_to_use_masked = next_to_use & ring_mask; 1197 struct rte_mbuf *mbuf = mbufs[next_to_use_masked]; 1198 struct ena_com_buf ebuf; 1199 1200 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]); 1201 /* prepare physical address for DMA transaction */ 1202 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1203 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1204 /* pass resource to device */ 1205 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1206 &ebuf, next_to_use_masked); 1207 if (unlikely(rc)) { 1208 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf), 1209 count - i); 1210 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1211 break; 1212 } 1213 next_to_use++; 1214 } 1215 1216 /* When we submitted free recources to device... */ 1217 if (i > 0) { 1218 /* ...let HW know that it can fill buffers with data */ 1219 rte_wmb(); 1220 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1221 1222 rxq->next_to_use = next_to_use; 1223 } 1224 1225 return i; 1226 } 1227 1228 static int ena_device_init(struct ena_com_dev *ena_dev, 1229 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1230 { 1231 int rc; 1232 bool readless_supported; 1233 1234 /* Initialize mmio registers */ 1235 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1236 if (rc) { 1237 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1238 return rc; 1239 } 1240 1241 /* The PCIe configuration space revision id indicate if mmio reg 1242 * read is disabled. 1243 */ 1244 readless_supported = 1245 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1246 & ENA_MMIO_DISABLE_REG_READ); 1247 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1248 1249 /* reset device */ 1250 rc = ena_com_dev_reset(ena_dev); 1251 if (rc) { 1252 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1253 goto err_mmio_read_less; 1254 } 1255 1256 /* check FW version */ 1257 rc = ena_com_validate_version(ena_dev); 1258 if (rc) { 1259 RTE_LOG(ERR, PMD, "device version is too low\n"); 1260 goto err_mmio_read_less; 1261 } 1262 1263 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1264 1265 /* ENA device administration layer init */ 1266 rc = ena_com_admin_init(ena_dev, NULL, true); 1267 if (rc) { 1268 RTE_LOG(ERR, PMD, 1269 "cannot initialize ena admin queue with device\n"); 1270 goto err_mmio_read_less; 1271 } 1272 1273 /* To enable the msix interrupts the driver needs to know the number 1274 * of queues. So the driver uses polling mode to retrieve this 1275 * information. 1276 */ 1277 ena_com_set_admin_polling_mode(ena_dev, true); 1278 1279 ena_config_host_info(ena_dev); 1280 1281 /* Get Device Attributes and features */ 1282 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1283 if (rc) { 1284 RTE_LOG(ERR, PMD, 1285 "cannot get attribute for ena device rc= %d\n", rc); 1286 goto err_admin_init; 1287 } 1288 1289 return 0; 1290 1291 err_admin_init: 1292 ena_com_admin_destroy(ena_dev); 1293 1294 err_mmio_read_less: 1295 ena_com_mmio_reg_read_request_destroy(ena_dev); 1296 1297 return rc; 1298 } 1299 1300 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1301 { 1302 struct rte_pci_device *pci_dev; 1303 struct ena_adapter *adapter = 1304 (struct ena_adapter *)(eth_dev->data->dev_private); 1305 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1306 struct ena_com_dev_get_features_ctx get_feat_ctx; 1307 int queue_size, rc; 1308 1309 static int adapters_found; 1310 1311 memset(adapter, 0, sizeof(struct ena_adapter)); 1312 ena_dev = &adapter->ena_dev; 1313 1314 eth_dev->dev_ops = &ena_dev_ops; 1315 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1316 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1317 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1318 adapter->rte_eth_dev_data = eth_dev->data; 1319 adapter->rte_dev = eth_dev; 1320 1321 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1322 return 0; 1323 1324 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1325 adapter->pdev = pci_dev; 1326 1327 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1328 pci_dev->addr.domain, 1329 pci_dev->addr.bus, 1330 pci_dev->addr.devid, 1331 pci_dev->addr.function); 1332 1333 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1334 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1335 1336 /* Present ENA_MEM_BAR indicates available LLQ mode. 1337 * Use corresponding policy 1338 */ 1339 if (adapter->dev_mem_base) 1340 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 1341 else if (adapter->regs) 1342 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1343 else 1344 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1345 ENA_REGS_BAR); 1346 1347 ena_dev->reg_bar = adapter->regs; 1348 ena_dev->dmadev = adapter->pdev; 1349 1350 adapter->id_number = adapters_found; 1351 1352 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1353 adapter->id_number); 1354 1355 /* device specific initialization routine */ 1356 rc = ena_device_init(ena_dev, &get_feat_ctx); 1357 if (rc) { 1358 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1359 return -1; 1360 } 1361 1362 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1363 if (get_feat_ctx.max_queues.max_llq_num == 0) { 1364 PMD_INIT_LOG(ERR, 1365 "Trying to use LLQ but llq_num is 0.\n" 1366 "Fall back into regular queues."); 1367 ena_dev->tx_mem_queue_type = 1368 ENA_ADMIN_PLACEMENT_POLICY_HOST; 1369 adapter->num_queues = 1370 get_feat_ctx.max_queues.max_sq_num; 1371 } else { 1372 adapter->num_queues = 1373 get_feat_ctx.max_queues.max_llq_num; 1374 } 1375 } else { 1376 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num; 1377 } 1378 1379 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx); 1380 if ((queue_size <= 0) || (adapter->num_queues <= 0)) 1381 return -EFAULT; 1382 1383 adapter->tx_ring_size = queue_size; 1384 adapter->rx_ring_size = queue_size; 1385 1386 /* prepare ring structures */ 1387 ena_init_rings(adapter); 1388 1389 ena_config_debug_area(adapter); 1390 1391 /* Set max MTU for this device */ 1392 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1393 1394 /* set device support for TSO */ 1395 adapter->tso4_supported = get_feat_ctx.offload.tx & 1396 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1397 1398 /* Copy MAC address and point DPDK to it */ 1399 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr; 1400 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr, 1401 (struct ether_addr *)adapter->mac_addr); 1402 1403 adapter->drv_stats = rte_zmalloc("adapter stats", 1404 sizeof(*adapter->drv_stats), 1405 RTE_CACHE_LINE_SIZE); 1406 if (!adapter->drv_stats) { 1407 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1408 return -ENOMEM; 1409 } 1410 1411 adapters_found++; 1412 adapter->state = ENA_ADAPTER_STATE_INIT; 1413 1414 return 0; 1415 } 1416 1417 static int ena_dev_configure(struct rte_eth_dev *dev) 1418 { 1419 struct ena_adapter *adapter = 1420 (struct ena_adapter *)(dev->data->dev_private); 1421 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads; 1422 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1423 1424 if ((tx_offloads & adapter->tx_supported_offloads) != tx_offloads) { 1425 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported " 1426 "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n", 1427 tx_offloads, adapter->tx_supported_offloads); 1428 return -ENOTSUP; 1429 } 1430 1431 if ((rx_offloads & adapter->rx_supported_offloads) != rx_offloads) { 1432 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported " 1433 "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n", 1434 rx_offloads, adapter->rx_supported_offloads); 1435 return -ENOTSUP; 1436 } 1437 1438 if (!(adapter->state == ENA_ADAPTER_STATE_INIT || 1439 adapter->state == ENA_ADAPTER_STATE_STOPPED)) { 1440 PMD_INIT_LOG(ERR, "Illegal adapter state: %d", 1441 adapter->state); 1442 return -1; 1443 } 1444 1445 switch (adapter->state) { 1446 case ENA_ADAPTER_STATE_INIT: 1447 case ENA_ADAPTER_STATE_STOPPED: 1448 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1449 break; 1450 case ENA_ADAPTER_STATE_CONFIG: 1451 RTE_LOG(WARNING, PMD, 1452 "Ivalid driver state while trying to configure device\n"); 1453 break; 1454 default: 1455 break; 1456 } 1457 1458 adapter->tx_selected_offloads = tx_offloads; 1459 adapter->rx_selected_offloads = rx_offloads; 1460 return 0; 1461 } 1462 1463 static void ena_init_rings(struct ena_adapter *adapter) 1464 { 1465 int i; 1466 1467 for (i = 0; i < adapter->num_queues; i++) { 1468 struct ena_ring *ring = &adapter->tx_ring[i]; 1469 1470 ring->configured = 0; 1471 ring->type = ENA_RING_TYPE_TX; 1472 ring->adapter = adapter; 1473 ring->id = i; 1474 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1475 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1476 } 1477 1478 for (i = 0; i < adapter->num_queues; i++) { 1479 struct ena_ring *ring = &adapter->rx_ring[i]; 1480 1481 ring->configured = 0; 1482 ring->type = ENA_RING_TYPE_RX; 1483 ring->adapter = adapter; 1484 ring->id = i; 1485 } 1486 } 1487 1488 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter, 1489 uint64_t offloads) 1490 { 1491 uint64_t port_offloads = adapter->tx_selected_offloads; 1492 1493 /* Check if port supports all requested offloads. 1494 * True if all offloads selected for queue are set for port. 1495 */ 1496 if ((offloads & port_offloads) != offloads) 1497 return false; 1498 return true; 1499 } 1500 1501 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter, 1502 uint64_t offloads) 1503 { 1504 uint64_t port_offloads = adapter->rx_selected_offloads; 1505 1506 /* Check if port supports all requested offloads. 1507 * True if all offloads selected for queue are set for port. 1508 */ 1509 if ((offloads & port_offloads) != offloads) 1510 return false; 1511 return true; 1512 } 1513 1514 static void ena_infos_get(struct rte_eth_dev *dev, 1515 struct rte_eth_dev_info *dev_info) 1516 { 1517 struct ena_adapter *adapter; 1518 struct ena_com_dev *ena_dev; 1519 struct ena_com_dev_get_features_ctx feat; 1520 uint64_t rx_feat = 0, tx_feat = 0; 1521 int rc = 0; 1522 1523 ena_assert_msg(dev->data != NULL, "Uninitialized device"); 1524 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device"); 1525 adapter = (struct ena_adapter *)(dev->data->dev_private); 1526 1527 ena_dev = &adapter->ena_dev; 1528 ena_assert_msg(ena_dev != NULL, "Uninitialized device"); 1529 1530 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1531 1532 dev_info->speed_capa = 1533 ETH_LINK_SPEED_1G | 1534 ETH_LINK_SPEED_2_5G | 1535 ETH_LINK_SPEED_5G | 1536 ETH_LINK_SPEED_10G | 1537 ETH_LINK_SPEED_25G | 1538 ETH_LINK_SPEED_40G | 1539 ETH_LINK_SPEED_50G | 1540 ETH_LINK_SPEED_100G; 1541 1542 /* Get supported features from HW */ 1543 rc = ena_com_get_dev_attr_feat(ena_dev, &feat); 1544 if (unlikely(rc)) { 1545 RTE_LOG(ERR, PMD, 1546 "Cannot get attribute for ena device rc= %d\n", rc); 1547 return; 1548 } 1549 1550 /* Set Tx & Rx features available for device */ 1551 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 1552 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1553 1554 if (feat.offload.tx & 1555 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 1556 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1557 DEV_TX_OFFLOAD_UDP_CKSUM | 1558 DEV_TX_OFFLOAD_TCP_CKSUM; 1559 1560 if (feat.offload.rx_supported & 1561 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 1562 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1563 DEV_RX_OFFLOAD_UDP_CKSUM | 1564 DEV_RX_OFFLOAD_TCP_CKSUM; 1565 1566 /* Inform framework about available features */ 1567 dev_info->rx_offload_capa = rx_feat; 1568 dev_info->rx_queue_offload_capa = rx_feat; 1569 dev_info->tx_offload_capa = tx_feat; 1570 dev_info->tx_queue_offload_capa = tx_feat; 1571 1572 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1573 dev_info->max_rx_pktlen = adapter->max_mtu; 1574 dev_info->max_mac_addrs = 1; 1575 1576 dev_info->max_rx_queues = adapter->num_queues; 1577 dev_info->max_tx_queues = adapter->num_queues; 1578 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1579 1580 adapter->tx_supported_offloads = tx_feat; 1581 adapter->rx_supported_offloads = rx_feat; 1582 } 1583 1584 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1585 uint16_t nb_pkts) 1586 { 1587 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 1588 unsigned int ring_size = rx_ring->ring_size; 1589 unsigned int ring_mask = ring_size - 1; 1590 uint16_t next_to_clean = rx_ring->next_to_clean; 1591 uint16_t desc_in_use = 0; 1592 unsigned int recv_idx = 0; 1593 struct rte_mbuf *mbuf = NULL; 1594 struct rte_mbuf *mbuf_head = NULL; 1595 struct rte_mbuf *mbuf_prev = NULL; 1596 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 1597 unsigned int completed; 1598 1599 struct ena_com_rx_ctx ena_rx_ctx; 1600 int rc = 0; 1601 1602 /* Check adapter state */ 1603 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 1604 RTE_LOG(ALERT, PMD, 1605 "Trying to receive pkts while device is NOT running\n"); 1606 return 0; 1607 } 1608 1609 desc_in_use = rx_ring->next_to_use - next_to_clean; 1610 if (unlikely(nb_pkts > desc_in_use)) 1611 nb_pkts = desc_in_use; 1612 1613 for (completed = 0; completed < nb_pkts; completed++) { 1614 int segments = 0; 1615 1616 ena_rx_ctx.max_bufs = rx_ring->ring_size; 1617 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1618 ena_rx_ctx.descs = 0; 1619 /* receive packet context */ 1620 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 1621 rx_ring->ena_com_io_sq, 1622 &ena_rx_ctx); 1623 if (unlikely(rc)) { 1624 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 1625 return 0; 1626 } 1627 1628 if (unlikely(ena_rx_ctx.descs == 0)) 1629 break; 1630 1631 while (segments < ena_rx_ctx.descs) { 1632 mbuf = rx_buff_info[next_to_clean & ring_mask]; 1633 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 1634 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 1635 mbuf->refcnt = 1; 1636 mbuf->next = NULL; 1637 if (segments == 0) { 1638 mbuf->nb_segs = ena_rx_ctx.descs; 1639 mbuf->port = rx_ring->port_id; 1640 mbuf->pkt_len = 0; 1641 mbuf_head = mbuf; 1642 } else { 1643 /* for multi-segment pkts create mbuf chain */ 1644 mbuf_prev->next = mbuf; 1645 } 1646 mbuf_head->pkt_len += mbuf->data_len; 1647 1648 mbuf_prev = mbuf; 1649 segments++; 1650 next_to_clean++; 1651 } 1652 1653 /* fill mbuf attributes if any */ 1654 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 1655 mbuf_head->hash.rss = (uint32_t)rx_ring->id; 1656 1657 /* pass to DPDK application head mbuf */ 1658 rx_pkts[recv_idx] = mbuf_head; 1659 recv_idx++; 1660 } 1661 1662 rx_ring->next_to_clean = next_to_clean; 1663 1664 desc_in_use = desc_in_use - completed + 1; 1665 /* Burst refill to save doorbells, memory barriers, const interval */ 1666 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) 1667 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 1668 1669 return recv_idx; 1670 } 1671 1672 static uint16_t 1673 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 1674 uint16_t nb_pkts) 1675 { 1676 int32_t ret; 1677 uint32_t i; 1678 struct rte_mbuf *m; 1679 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 1680 struct ipv4_hdr *ip_hdr; 1681 uint64_t ol_flags; 1682 uint16_t frag_field; 1683 1684 for (i = 0; i != nb_pkts; i++) { 1685 m = tx_pkts[i]; 1686 ol_flags = m->ol_flags; 1687 1688 if (!(ol_flags & PKT_TX_IPV4)) 1689 continue; 1690 1691 /* If there was not L2 header length specified, assume it is 1692 * length of the ethernet header. 1693 */ 1694 if (unlikely(m->l2_len == 0)) 1695 m->l2_len = sizeof(struct ether_hdr); 1696 1697 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, 1698 m->l2_len); 1699 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 1700 1701 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) { 1702 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 1703 1704 /* If IPv4 header has DF flag enabled and TSO support is 1705 * disabled, partial chcecksum should not be calculated. 1706 */ 1707 if (!tx_ring->adapter->tso4_supported) 1708 continue; 1709 } 1710 1711 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 1712 (ol_flags & PKT_TX_L4_MASK) == 1713 PKT_TX_SCTP_CKSUM) { 1714 rte_errno = -ENOTSUP; 1715 return i; 1716 } 1717 1718 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 1719 ret = rte_validate_tx_offload(m); 1720 if (ret != 0) { 1721 rte_errno = ret; 1722 return i; 1723 } 1724 #endif 1725 1726 /* In case we are supposed to TSO and have DF not set (DF=0) 1727 * hardware must be provided with partial checksum, otherwise 1728 * it will take care of necessary calculations. 1729 */ 1730 1731 ret = rte_net_intel_cksum_flags_prepare(m, 1732 ol_flags & ~PKT_TX_TCP_SEG); 1733 if (ret != 0) { 1734 rte_errno = ret; 1735 return i; 1736 } 1737 } 1738 1739 return i; 1740 } 1741 1742 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 1743 uint16_t nb_pkts) 1744 { 1745 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 1746 uint16_t next_to_use = tx_ring->next_to_use; 1747 uint16_t next_to_clean = tx_ring->next_to_clean; 1748 struct rte_mbuf *mbuf; 1749 unsigned int ring_size = tx_ring->ring_size; 1750 unsigned int ring_mask = ring_size - 1; 1751 struct ena_com_tx_ctx ena_tx_ctx; 1752 struct ena_tx_buffer *tx_info; 1753 struct ena_com_buf *ebuf; 1754 uint16_t rc, req_id, total_tx_descs = 0; 1755 uint16_t sent_idx = 0, empty_tx_reqs; 1756 int nb_hw_desc; 1757 1758 /* Check adapter state */ 1759 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 1760 RTE_LOG(ALERT, PMD, 1761 "Trying to xmit pkts while device is NOT running\n"); 1762 return 0; 1763 } 1764 1765 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 1766 if (nb_pkts > empty_tx_reqs) 1767 nb_pkts = empty_tx_reqs; 1768 1769 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 1770 mbuf = tx_pkts[sent_idx]; 1771 1772 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 1773 tx_info = &tx_ring->tx_buffer_info[req_id]; 1774 tx_info->mbuf = mbuf; 1775 tx_info->num_of_bufs = 0; 1776 ebuf = tx_info->bufs; 1777 1778 /* Prepare TX context */ 1779 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 1780 memset(&ena_tx_ctx.ena_meta, 0x0, 1781 sizeof(struct ena_com_tx_meta)); 1782 ena_tx_ctx.ena_bufs = ebuf; 1783 ena_tx_ctx.req_id = req_id; 1784 if (tx_ring->tx_mem_queue_type == 1785 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1786 /* prepare the push buffer with 1787 * virtual address of the data 1788 */ 1789 ena_tx_ctx.header_len = 1790 RTE_MIN(mbuf->data_len, 1791 tx_ring->tx_max_header_size); 1792 ena_tx_ctx.push_header = 1793 (void *)((char *)mbuf->buf_addr + 1794 mbuf->data_off); 1795 } /* there's no else as we take advantage of memset zeroing */ 1796 1797 /* Set TX offloads flags, if applicable */ 1798 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 1799 1800 if (unlikely(mbuf->ol_flags & 1801 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD))) 1802 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 1803 1804 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 1805 1806 /* Process first segment taking into 1807 * consideration pushed header 1808 */ 1809 if (mbuf->data_len > ena_tx_ctx.header_len) { 1810 ebuf->paddr = mbuf->buf_iova + 1811 mbuf->data_off + 1812 ena_tx_ctx.header_len; 1813 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len; 1814 ebuf++; 1815 tx_info->num_of_bufs++; 1816 } 1817 1818 while ((mbuf = mbuf->next) != NULL) { 1819 ebuf->paddr = mbuf->buf_iova + mbuf->data_off; 1820 ebuf->len = mbuf->data_len; 1821 ebuf++; 1822 tx_info->num_of_bufs++; 1823 } 1824 1825 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 1826 1827 /* Write data to device */ 1828 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 1829 &ena_tx_ctx, &nb_hw_desc); 1830 if (unlikely(rc)) 1831 break; 1832 1833 tx_info->tx_descs = nb_hw_desc; 1834 1835 next_to_use++; 1836 } 1837 1838 /* If there are ready packets to be xmitted... */ 1839 if (sent_idx > 0) { 1840 /* ...let HW do its best :-) */ 1841 rte_wmb(); 1842 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 1843 1844 tx_ring->next_to_use = next_to_use; 1845 } 1846 1847 /* Clear complete packets */ 1848 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 1849 /* Get Tx info & store how many descs were processed */ 1850 tx_info = &tx_ring->tx_buffer_info[req_id]; 1851 total_tx_descs += tx_info->tx_descs; 1852 1853 /* Free whole mbuf chain */ 1854 mbuf = tx_info->mbuf; 1855 rte_pktmbuf_free(mbuf); 1856 tx_info->mbuf = NULL; 1857 1858 /* Put back descriptor to the ring for reuse */ 1859 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 1860 next_to_clean++; 1861 1862 /* If too many descs to clean, leave it for another run */ 1863 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 1864 break; 1865 } 1866 1867 if (total_tx_descs > 0) { 1868 /* acknowledge completion of sent packets */ 1869 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 1870 tx_ring->next_to_clean = next_to_clean; 1871 } 1872 1873 return sent_idx; 1874 } 1875 1876 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1877 struct rte_pci_device *pci_dev) 1878 { 1879 return rte_eth_dev_pci_generic_probe(pci_dev, 1880 sizeof(struct ena_adapter), eth_ena_dev_init); 1881 } 1882 1883 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 1884 { 1885 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1886 } 1887 1888 static struct rte_pci_driver rte_ena_pmd = { 1889 .id_table = pci_id_ena_map, 1890 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1891 .probe = eth_ena_pci_probe, 1892 .remove = eth_ena_pci_remove, 1893 }; 1894 1895 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 1896 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 1897 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 1898 1899 RTE_INIT(ena_init_log); 1900 static void 1901 ena_init_log(void) 1902 { 1903 ena_logtype_init = rte_log_register("pmd.ena.init"); 1904 if (ena_logtype_init >= 0) 1905 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 1906 ena_logtype_driver = rte_log_register("pmd.ena.driver"); 1907 if (ena_logtype_driver >= 0) 1908 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 1909 } 1910