1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_string_fns.h> 35 #include <rte_ether.h> 36 #include <rte_ethdev_driver.h> 37 #include <rte_ethdev_pci.h> 38 #include <rte_tcp.h> 39 #include <rte_atomic.h> 40 #include <rte_dev.h> 41 #include <rte_errno.h> 42 #include <rte_version.h> 43 #include <rte_eal_memconfig.h> 44 #include <rte_net.h> 45 46 #include "ena_ethdev.h" 47 #include "ena_logs.h" 48 #include "ena_platform.h" 49 #include "ena_com.h" 50 #include "ena_eth_com.h" 51 52 #include <ena_common_defs.h> 53 #include <ena_regs_defs.h> 54 #include <ena_admin_defs.h> 55 #include <ena_eth_io_defs.h> 56 57 #define DRV_MODULE_VER_MAJOR 2 58 #define DRV_MODULE_VER_MINOR 0 59 #define DRV_MODULE_VER_SUBMINOR 0 60 61 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 62 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 63 /*reverse version of ENA_IO_RXQ_IDX*/ 64 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 65 66 /* While processing submitted and completed descriptors (rx and tx path 67 * respectively) in a loop it is desired to: 68 * - perform batch submissions while populating sumbissmion queue 69 * - avoid blocking transmission of other packets during cleanup phase 70 * Hence the utilization ratio of 1/8 of a queue size. 71 */ 72 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 73 74 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 75 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 76 77 #define GET_L4_HDR_LEN(mbuf) \ 78 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \ 79 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 80 81 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 82 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 83 #define ENA_HASH_KEY_SIZE 40 84 #define ETH_GSTRING_LEN 32 85 86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 87 88 #define ENA_MIN_RING_DESC 128 89 90 enum ethtool_stringset { 91 ETH_SS_TEST = 0, 92 ETH_SS_STATS, 93 }; 94 95 struct ena_stats { 96 char name[ETH_GSTRING_LEN]; 97 int stat_offset; 98 }; 99 100 #define ENA_STAT_ENTRY(stat, stat_type) { \ 101 .name = #stat, \ 102 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 103 } 104 105 #define ENA_STAT_RX_ENTRY(stat) \ 106 ENA_STAT_ENTRY(stat, rx) 107 108 #define ENA_STAT_TX_ENTRY(stat) \ 109 ENA_STAT_ENTRY(stat, tx) 110 111 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 112 ENA_STAT_ENTRY(stat, dev) 113 114 #define ENA_MAX_RING_SIZE_RX 8192 115 #define ENA_MAX_RING_SIZE_TX 1024 116 117 /* 118 * Each rte_memzone should have unique name. 119 * To satisfy it, count number of allocation and add it to name. 120 */ 121 uint32_t ena_alloc_cnt; 122 123 static const struct ena_stats ena_stats_global_strings[] = { 124 ENA_STAT_GLOBAL_ENTRY(wd_expired), 125 ENA_STAT_GLOBAL_ENTRY(dev_start), 126 ENA_STAT_GLOBAL_ENTRY(dev_stop), 127 }; 128 129 static const struct ena_stats ena_stats_tx_strings[] = { 130 ENA_STAT_TX_ENTRY(cnt), 131 ENA_STAT_TX_ENTRY(bytes), 132 ENA_STAT_TX_ENTRY(prepare_ctx_err), 133 ENA_STAT_TX_ENTRY(linearize), 134 ENA_STAT_TX_ENTRY(linearize_failed), 135 ENA_STAT_TX_ENTRY(tx_poll), 136 ENA_STAT_TX_ENTRY(doorbells), 137 ENA_STAT_TX_ENTRY(bad_req_id), 138 ENA_STAT_TX_ENTRY(available_desc), 139 }; 140 141 static const struct ena_stats ena_stats_rx_strings[] = { 142 ENA_STAT_RX_ENTRY(cnt), 143 ENA_STAT_RX_ENTRY(bytes), 144 ENA_STAT_RX_ENTRY(refill_partial), 145 ENA_STAT_RX_ENTRY(bad_csum), 146 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 147 ENA_STAT_RX_ENTRY(bad_desc_num), 148 ENA_STAT_RX_ENTRY(bad_req_id), 149 }; 150 151 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 152 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 153 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 154 155 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 156 DEV_TX_OFFLOAD_UDP_CKSUM |\ 157 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 158 DEV_TX_OFFLOAD_TCP_TSO) 159 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 160 PKT_TX_IP_CKSUM |\ 161 PKT_TX_TCP_SEG) 162 163 /** Vendor ID used by Amazon devices */ 164 #define PCI_VENDOR_ID_AMAZON 0x1D0F 165 /** Amazon devices */ 166 #define PCI_DEVICE_ID_ENA_VF 0xEC20 167 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 168 169 #define ENA_TX_OFFLOAD_MASK (\ 170 PKT_TX_L4_MASK | \ 171 PKT_TX_IPV6 | \ 172 PKT_TX_IPV4 | \ 173 PKT_TX_IP_CKSUM | \ 174 PKT_TX_TCP_SEG) 175 176 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 177 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 178 179 int ena_logtype_init; 180 int ena_logtype_driver; 181 182 static const struct rte_pci_id pci_id_ena_map[] = { 183 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 184 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 185 { .device_id = 0 }, 186 }; 187 188 static struct ena_aenq_handlers aenq_handlers; 189 190 static int ena_device_init(struct ena_com_dev *ena_dev, 191 struct ena_com_dev_get_features_ctx *get_feat_ctx, 192 bool *wd_state); 193 static int ena_dev_configure(struct rte_eth_dev *dev); 194 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 195 uint16_t nb_pkts); 196 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 197 uint16_t nb_pkts); 198 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 199 uint16_t nb_desc, unsigned int socket_id, 200 const struct rte_eth_txconf *tx_conf); 201 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 202 uint16_t nb_desc, unsigned int socket_id, 203 const struct rte_eth_rxconf *rx_conf, 204 struct rte_mempool *mp); 205 static uint16_t eth_ena_recv_pkts(void *rx_queue, 206 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 207 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 208 static void ena_init_rings(struct ena_adapter *adapter); 209 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 210 static int ena_start(struct rte_eth_dev *dev); 211 static void ena_stop(struct rte_eth_dev *dev); 212 static void ena_close(struct rte_eth_dev *dev); 213 static int ena_dev_reset(struct rte_eth_dev *dev); 214 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 215 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 216 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 217 static void ena_rx_queue_release(void *queue); 218 static void ena_tx_queue_release(void *queue); 219 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 220 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 221 static int ena_link_update(struct rte_eth_dev *dev, 222 int wait_to_complete); 223 static int ena_create_io_queue(struct ena_ring *ring); 224 static void ena_queue_stop(struct ena_ring *ring); 225 static void ena_queue_stop_all(struct rte_eth_dev *dev, 226 enum ena_ring_type ring_type); 227 static int ena_queue_start(struct ena_ring *ring); 228 static int ena_queue_start_all(struct rte_eth_dev *dev, 229 enum ena_ring_type ring_type); 230 static void ena_stats_restart(struct rte_eth_dev *dev); 231 static void ena_infos_get(struct rte_eth_dev *dev, 232 struct rte_eth_dev_info *dev_info); 233 static int ena_rss_reta_update(struct rte_eth_dev *dev, 234 struct rte_eth_rss_reta_entry64 *reta_conf, 235 uint16_t reta_size); 236 static int ena_rss_reta_query(struct rte_eth_dev *dev, 237 struct rte_eth_rss_reta_entry64 *reta_conf, 238 uint16_t reta_size); 239 static void ena_interrupt_handler_rte(void *cb_arg); 240 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 241 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 242 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 243 static int ena_xstats_get_names(struct rte_eth_dev *dev, 244 struct rte_eth_xstat_name *xstats_names, 245 unsigned int n); 246 static int ena_xstats_get(struct rte_eth_dev *dev, 247 struct rte_eth_xstat *stats, 248 unsigned int n); 249 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 250 const uint64_t *ids, 251 uint64_t *values, 252 unsigned int n); 253 254 static const struct eth_dev_ops ena_dev_ops = { 255 .dev_configure = ena_dev_configure, 256 .dev_infos_get = ena_infos_get, 257 .rx_queue_setup = ena_rx_queue_setup, 258 .tx_queue_setup = ena_tx_queue_setup, 259 .dev_start = ena_start, 260 .dev_stop = ena_stop, 261 .link_update = ena_link_update, 262 .stats_get = ena_stats_get, 263 .xstats_get_names = ena_xstats_get_names, 264 .xstats_get = ena_xstats_get, 265 .xstats_get_by_id = ena_xstats_get_by_id, 266 .mtu_set = ena_mtu_set, 267 .rx_queue_release = ena_rx_queue_release, 268 .tx_queue_release = ena_tx_queue_release, 269 .dev_close = ena_close, 270 .dev_reset = ena_dev_reset, 271 .reta_update = ena_rss_reta_update, 272 .reta_query = ena_rss_reta_query, 273 }; 274 275 #define NUMA_NO_NODE SOCKET_ID_ANY 276 277 static inline int ena_cpu_to_node(int cpu) 278 { 279 struct rte_config *config = rte_eal_get_configuration(); 280 struct rte_fbarray *arr = &config->mem_config->memzones; 281 const struct rte_memzone *mz; 282 283 if (unlikely(cpu >= RTE_MAX_MEMZONE)) 284 return NUMA_NO_NODE; 285 286 mz = rte_fbarray_get(arr, cpu); 287 288 return mz->socket_id; 289 } 290 291 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 292 struct ena_com_rx_ctx *ena_rx_ctx) 293 { 294 uint64_t ol_flags = 0; 295 uint32_t packet_type = 0; 296 297 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 298 packet_type |= RTE_PTYPE_L4_TCP; 299 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 300 packet_type |= RTE_PTYPE_L4_UDP; 301 302 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 303 packet_type |= RTE_PTYPE_L3_IPV4; 304 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 305 packet_type |= RTE_PTYPE_L3_IPV6; 306 307 if (unlikely(ena_rx_ctx->l4_csum_err)) 308 ol_flags |= PKT_RX_L4_CKSUM_BAD; 309 if (unlikely(ena_rx_ctx->l3_csum_err)) 310 ol_flags |= PKT_RX_IP_CKSUM_BAD; 311 312 mbuf->ol_flags = ol_flags; 313 mbuf->packet_type = packet_type; 314 } 315 316 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 317 struct ena_com_tx_ctx *ena_tx_ctx, 318 uint64_t queue_offloads) 319 { 320 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 321 322 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 323 (queue_offloads & QUEUE_OFFLOADS)) { 324 /* check if TSO is required */ 325 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 326 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 327 ena_tx_ctx->tso_enable = true; 328 329 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 330 } 331 332 /* check if L3 checksum is needed */ 333 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 334 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 335 ena_tx_ctx->l3_csum_enable = true; 336 337 if (mbuf->ol_flags & PKT_TX_IPV6) { 338 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 339 } else { 340 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 341 342 /* set don't fragment (DF) flag */ 343 if (mbuf->packet_type & 344 (RTE_PTYPE_L4_NONFRAG 345 | RTE_PTYPE_INNER_L4_NONFRAG)) 346 ena_tx_ctx->df = true; 347 } 348 349 /* check if L4 checksum is needed */ 350 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) && 351 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 352 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 353 ena_tx_ctx->l4_csum_enable = true; 354 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) && 355 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 357 ena_tx_ctx->l4_csum_enable = true; 358 } else { 359 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 360 ena_tx_ctx->l4_csum_enable = false; 361 } 362 363 ena_meta->mss = mbuf->tso_segsz; 364 ena_meta->l3_hdr_len = mbuf->l3_len; 365 ena_meta->l3_hdr_offset = mbuf->l2_len; 366 367 ena_tx_ctx->meta_valid = true; 368 } else { 369 ena_tx_ctx->meta_valid = false; 370 } 371 } 372 373 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 374 { 375 if (likely(req_id < rx_ring->ring_size)) 376 return 0; 377 378 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id); 379 380 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 381 rx_ring->adapter->trigger_reset = true; 382 ++rx_ring->rx_stats.bad_req_id; 383 384 return -EFAULT; 385 } 386 387 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 388 { 389 struct ena_tx_buffer *tx_info = NULL; 390 391 if (likely(req_id < tx_ring->ring_size)) { 392 tx_info = &tx_ring->tx_buffer_info[req_id]; 393 if (likely(tx_info->mbuf)) 394 return 0; 395 } 396 397 if (tx_info) 398 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n"); 399 else 400 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id); 401 402 /* Trigger device reset */ 403 ++tx_ring->tx_stats.bad_req_id; 404 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 405 tx_ring->adapter->trigger_reset = true; 406 return -EFAULT; 407 } 408 409 static void ena_config_host_info(struct ena_com_dev *ena_dev) 410 { 411 struct ena_admin_host_info *host_info; 412 int rc; 413 414 /* Allocate only the host info */ 415 rc = ena_com_allocate_host_info(ena_dev); 416 if (rc) { 417 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 418 return; 419 } 420 421 host_info = ena_dev->host_attr.host_info; 422 423 host_info->os_type = ENA_ADMIN_OS_DPDK; 424 host_info->kernel_ver = RTE_VERSION; 425 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 426 sizeof(host_info->kernel_ver_str)); 427 host_info->os_dist = RTE_VERSION; 428 strlcpy((char *)host_info->os_dist_str, rte_version(), 429 sizeof(host_info->os_dist_str)); 430 host_info->driver_version = 431 (DRV_MODULE_VER_MAJOR) | 432 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 433 (DRV_MODULE_VER_SUBMINOR << 434 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 435 host_info->num_cpus = rte_lcore_count(); 436 437 rc = ena_com_set_host_attributes(ena_dev); 438 if (rc) { 439 if (rc == -ENA_COM_UNSUPPORTED) 440 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 441 else 442 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 443 444 goto err; 445 } 446 447 return; 448 449 err: 450 ena_com_delete_host_info(ena_dev); 451 } 452 453 /* This function calculates the number of xstats based on the current config */ 454 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 455 { 456 return ENA_STATS_ARRAY_GLOBAL + 457 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 458 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 459 } 460 461 static void ena_config_debug_area(struct ena_adapter *adapter) 462 { 463 u32 debug_area_size; 464 int rc, ss_count; 465 466 ss_count = ena_xstats_calc_num(adapter->rte_dev); 467 468 /* allocate 32 bytes for each string and 64bit for the value */ 469 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 470 471 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 472 if (rc) { 473 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 474 return; 475 } 476 477 rc = ena_com_set_host_attributes(&adapter->ena_dev); 478 if (rc) { 479 if (rc == -ENA_COM_UNSUPPORTED) 480 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 481 else 482 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 483 484 goto err; 485 } 486 487 return; 488 err: 489 ena_com_delete_debug_area(&adapter->ena_dev); 490 } 491 492 static void ena_close(struct rte_eth_dev *dev) 493 { 494 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 495 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 496 struct ena_adapter *adapter = 497 (struct ena_adapter *)(dev->data->dev_private); 498 499 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 500 ena_stop(dev); 501 adapter->state = ENA_ADAPTER_STATE_CLOSED; 502 503 ena_rx_queue_release_all(dev); 504 ena_tx_queue_release_all(dev); 505 506 rte_free(adapter->drv_stats); 507 adapter->drv_stats = NULL; 508 509 rte_intr_disable(intr_handle); 510 rte_intr_callback_unregister(intr_handle, 511 ena_interrupt_handler_rte, 512 adapter); 513 514 /* 515 * MAC is not allocated dynamically. Setting NULL should prevent from 516 * release of the resource in the rte_eth_dev_release_port(). 517 */ 518 dev->data->mac_addrs = NULL; 519 } 520 521 static int 522 ena_dev_reset(struct rte_eth_dev *dev) 523 { 524 int rc = 0; 525 526 ena_destroy_device(dev); 527 rc = eth_ena_dev_init(dev); 528 if (rc) 529 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 530 531 return rc; 532 } 533 534 static int ena_rss_reta_update(struct rte_eth_dev *dev, 535 struct rte_eth_rss_reta_entry64 *reta_conf, 536 uint16_t reta_size) 537 { 538 struct ena_adapter *adapter = 539 (struct ena_adapter *)(dev->data->dev_private); 540 struct ena_com_dev *ena_dev = &adapter->ena_dev; 541 int rc, i; 542 u16 entry_value; 543 int conf_idx; 544 int idx; 545 546 if ((reta_size == 0) || (reta_conf == NULL)) 547 return -EINVAL; 548 549 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 550 RTE_LOG(WARNING, PMD, 551 "indirection table %d is bigger than supported (%d)\n", 552 reta_size, ENA_RX_RSS_TABLE_SIZE); 553 return -EINVAL; 554 } 555 556 for (i = 0 ; i < reta_size ; i++) { 557 /* each reta_conf is for 64 entries. 558 * to support 128 we use 2 conf of 64 559 */ 560 conf_idx = i / RTE_RETA_GROUP_SIZE; 561 idx = i % RTE_RETA_GROUP_SIZE; 562 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 563 entry_value = 564 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 565 566 rc = ena_com_indirect_table_fill_entry(ena_dev, 567 i, 568 entry_value); 569 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 570 RTE_LOG(ERR, PMD, 571 "Cannot fill indirect table\n"); 572 return rc; 573 } 574 } 575 } 576 577 rc = ena_com_indirect_table_set(ena_dev); 578 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 579 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 580 return rc; 581 } 582 583 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 584 __func__, reta_size, adapter->rte_dev->data->port_id); 585 586 return 0; 587 } 588 589 /* Query redirection table. */ 590 static int ena_rss_reta_query(struct rte_eth_dev *dev, 591 struct rte_eth_rss_reta_entry64 *reta_conf, 592 uint16_t reta_size) 593 { 594 struct ena_adapter *adapter = 595 (struct ena_adapter *)(dev->data->dev_private); 596 struct ena_com_dev *ena_dev = &adapter->ena_dev; 597 int rc; 598 int i; 599 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 600 int reta_conf_idx; 601 int reta_idx; 602 603 if (reta_size == 0 || reta_conf == NULL || 604 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 605 return -EINVAL; 606 607 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 608 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 609 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 610 return -ENOTSUP; 611 } 612 613 for (i = 0 ; i < reta_size ; i++) { 614 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 615 reta_idx = i % RTE_RETA_GROUP_SIZE; 616 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 617 reta_conf[reta_conf_idx].reta[reta_idx] = 618 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 619 } 620 621 return 0; 622 } 623 624 static int ena_rss_init_default(struct ena_adapter *adapter) 625 { 626 struct ena_com_dev *ena_dev = &adapter->ena_dev; 627 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 628 int rc, i; 629 u32 val; 630 631 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 632 if (unlikely(rc)) { 633 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 634 goto err_rss_init; 635 } 636 637 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 638 val = i % nb_rx_queues; 639 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 640 ENA_IO_RXQ_IDX(val)); 641 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 642 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 643 goto err_fill_indir; 644 } 645 } 646 647 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 648 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 649 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 650 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 651 goto err_fill_indir; 652 } 653 654 rc = ena_com_set_default_hash_ctrl(ena_dev); 655 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 656 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 657 goto err_fill_indir; 658 } 659 660 rc = ena_com_indirect_table_set(ena_dev); 661 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 662 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 663 goto err_fill_indir; 664 } 665 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 666 adapter->rte_dev->data->port_id); 667 668 return 0; 669 670 err_fill_indir: 671 ena_com_rss_destroy(ena_dev); 672 err_rss_init: 673 674 return rc; 675 } 676 677 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 678 { 679 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 680 int nb_queues = dev->data->nb_rx_queues; 681 int i; 682 683 for (i = 0; i < nb_queues; i++) 684 ena_rx_queue_release(queues[i]); 685 } 686 687 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 688 { 689 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 690 int nb_queues = dev->data->nb_tx_queues; 691 int i; 692 693 for (i = 0; i < nb_queues; i++) 694 ena_tx_queue_release(queues[i]); 695 } 696 697 static void ena_rx_queue_release(void *queue) 698 { 699 struct ena_ring *ring = (struct ena_ring *)queue; 700 701 /* Free ring resources */ 702 if (ring->rx_buffer_info) 703 rte_free(ring->rx_buffer_info); 704 ring->rx_buffer_info = NULL; 705 706 if (ring->rx_refill_buffer) 707 rte_free(ring->rx_refill_buffer); 708 ring->rx_refill_buffer = NULL; 709 710 if (ring->empty_rx_reqs) 711 rte_free(ring->empty_rx_reqs); 712 ring->empty_rx_reqs = NULL; 713 714 ring->configured = 0; 715 716 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 717 ring->port_id, ring->id); 718 } 719 720 static void ena_tx_queue_release(void *queue) 721 { 722 struct ena_ring *ring = (struct ena_ring *)queue; 723 724 /* Free ring resources */ 725 if (ring->push_buf_intermediate_buf) 726 rte_free(ring->push_buf_intermediate_buf); 727 728 if (ring->tx_buffer_info) 729 rte_free(ring->tx_buffer_info); 730 731 if (ring->empty_tx_reqs) 732 rte_free(ring->empty_tx_reqs); 733 734 ring->empty_tx_reqs = NULL; 735 ring->tx_buffer_info = NULL; 736 ring->push_buf_intermediate_buf = NULL; 737 738 ring->configured = 0; 739 740 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 741 ring->port_id, ring->id); 742 } 743 744 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 745 { 746 unsigned int i; 747 748 for (i = 0; i < ring->ring_size; ++i) 749 if (ring->rx_buffer_info[i]) { 750 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 751 ring->rx_buffer_info[i] = NULL; 752 } 753 } 754 755 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 756 { 757 unsigned int i; 758 759 for (i = 0; i < ring->ring_size; ++i) { 760 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 761 762 if (tx_buf->mbuf) 763 rte_pktmbuf_free(tx_buf->mbuf); 764 } 765 } 766 767 static int ena_link_update(struct rte_eth_dev *dev, 768 __rte_unused int wait_to_complete) 769 { 770 struct rte_eth_link *link = &dev->data->dev_link; 771 struct ena_adapter *adapter; 772 773 adapter = (struct ena_adapter *)(dev->data->dev_private); 774 775 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 776 link->link_speed = ETH_SPEED_NUM_NONE; 777 link->link_duplex = ETH_LINK_FULL_DUPLEX; 778 779 return 0; 780 } 781 782 static int ena_queue_start_all(struct rte_eth_dev *dev, 783 enum ena_ring_type ring_type) 784 { 785 struct ena_adapter *adapter = 786 (struct ena_adapter *)(dev->data->dev_private); 787 struct ena_ring *queues = NULL; 788 int nb_queues; 789 int i = 0; 790 int rc = 0; 791 792 if (ring_type == ENA_RING_TYPE_RX) { 793 queues = adapter->rx_ring; 794 nb_queues = dev->data->nb_rx_queues; 795 } else { 796 queues = adapter->tx_ring; 797 nb_queues = dev->data->nb_tx_queues; 798 } 799 for (i = 0; i < nb_queues; i++) { 800 if (queues[i].configured) { 801 if (ring_type == ENA_RING_TYPE_RX) { 802 ena_assert_msg( 803 dev->data->rx_queues[i] == &queues[i], 804 "Inconsistent state of rx queues\n"); 805 } else { 806 ena_assert_msg( 807 dev->data->tx_queues[i] == &queues[i], 808 "Inconsistent state of tx queues\n"); 809 } 810 811 rc = ena_queue_start(&queues[i]); 812 813 if (rc) { 814 PMD_INIT_LOG(ERR, 815 "failed to start queue %d type(%d)", 816 i, ring_type); 817 goto err; 818 } 819 } 820 } 821 822 return 0; 823 824 err: 825 while (i--) 826 if (queues[i].configured) 827 ena_queue_stop(&queues[i]); 828 829 return rc; 830 } 831 832 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 833 { 834 uint32_t max_frame_len = adapter->max_mtu; 835 836 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 837 DEV_RX_OFFLOAD_JUMBO_FRAME) 838 max_frame_len = 839 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 840 841 return max_frame_len; 842 } 843 844 static int ena_check_valid_conf(struct ena_adapter *adapter) 845 { 846 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 847 848 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 849 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 850 "max mtu: %d, min mtu: %d", 851 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 852 return ENA_COM_UNSUPPORTED; 853 } 854 855 return 0; 856 } 857 858 static int 859 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) 860 { 861 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 862 struct ena_com_dev *ena_dev = ctx->ena_dev; 863 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; 864 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; 865 866 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 867 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 868 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 869 rx_queue_size = RTE_MIN(rx_queue_size, 870 max_queue_ext->max_rx_cq_depth); 871 rx_queue_size = RTE_MIN(rx_queue_size, 872 max_queue_ext->max_rx_sq_depth); 873 tx_queue_size = RTE_MIN(tx_queue_size, 874 max_queue_ext->max_tx_cq_depth); 875 876 if (ena_dev->tx_mem_queue_type == 877 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 878 tx_queue_size = RTE_MIN(tx_queue_size, 879 llq->max_llq_depth); 880 } else { 881 tx_queue_size = RTE_MIN(tx_queue_size, 882 max_queue_ext->max_tx_sq_depth); 883 } 884 885 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 886 max_queue_ext->max_per_packet_rx_descs); 887 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 888 max_queue_ext->max_per_packet_tx_descs); 889 } else { 890 struct ena_admin_queue_feature_desc *max_queues = 891 &ctx->get_feat_ctx->max_queues; 892 rx_queue_size = RTE_MIN(rx_queue_size, 893 max_queues->max_cq_depth); 894 rx_queue_size = RTE_MIN(rx_queue_size, 895 max_queues->max_sq_depth); 896 tx_queue_size = RTE_MIN(tx_queue_size, 897 max_queues->max_cq_depth); 898 899 if (ena_dev->tx_mem_queue_type == 900 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 901 tx_queue_size = RTE_MIN(tx_queue_size, 902 llq->max_llq_depth); 903 } else { 904 tx_queue_size = RTE_MIN(tx_queue_size, 905 max_queues->max_sq_depth); 906 } 907 908 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 909 max_queues->max_packet_tx_descs); 910 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 911 max_queues->max_packet_rx_descs); 912 } 913 914 /* Round down to the nearest power of 2 */ 915 rx_queue_size = rte_align32prevpow2(rx_queue_size); 916 tx_queue_size = rte_align32prevpow2(tx_queue_size); 917 918 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { 919 PMD_INIT_LOG(ERR, "Invalid queue size"); 920 return -EFAULT; 921 } 922 923 ctx->rx_queue_size = rx_queue_size; 924 ctx->tx_queue_size = tx_queue_size; 925 926 return 0; 927 } 928 929 static void ena_stats_restart(struct rte_eth_dev *dev) 930 { 931 struct ena_adapter *adapter = 932 (struct ena_adapter *)(dev->data->dev_private); 933 934 rte_atomic64_init(&adapter->drv_stats->ierrors); 935 rte_atomic64_init(&adapter->drv_stats->oerrors); 936 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 937 rte_atomic64_init(&adapter->drv_stats->rx_drops); 938 } 939 940 static int ena_stats_get(struct rte_eth_dev *dev, 941 struct rte_eth_stats *stats) 942 { 943 struct ena_admin_basic_stats ena_stats; 944 struct ena_adapter *adapter = 945 (struct ena_adapter *)(dev->data->dev_private); 946 struct ena_com_dev *ena_dev = &adapter->ena_dev; 947 int rc; 948 int i; 949 int max_rings_stats; 950 951 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 952 return -ENOTSUP; 953 954 memset(&ena_stats, 0, sizeof(ena_stats)); 955 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 956 if (unlikely(rc)) { 957 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n"); 958 return rc; 959 } 960 961 /* Set of basic statistics from ENA */ 962 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 963 ena_stats.rx_pkts_low); 964 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 965 ena_stats.tx_pkts_low); 966 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 967 ena_stats.rx_bytes_low); 968 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 969 ena_stats.tx_bytes_low); 970 971 /* Driver related stats */ 972 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 973 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 974 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 975 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 976 977 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 978 RTE_ETHDEV_QUEUE_STAT_CNTRS); 979 for (i = 0; i < max_rings_stats; ++i) { 980 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 981 982 stats->q_ibytes[i] = rx_stats->bytes; 983 stats->q_ipackets[i] = rx_stats->cnt; 984 stats->q_errors[i] = rx_stats->bad_desc_num + 985 rx_stats->bad_req_id; 986 } 987 988 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 989 RTE_ETHDEV_QUEUE_STAT_CNTRS); 990 for (i = 0; i < max_rings_stats; ++i) { 991 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 992 993 stats->q_obytes[i] = tx_stats->bytes; 994 stats->q_opackets[i] = tx_stats->cnt; 995 } 996 997 return 0; 998 } 999 1000 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1001 { 1002 struct ena_adapter *adapter; 1003 struct ena_com_dev *ena_dev; 1004 int rc = 0; 1005 1006 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1007 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1008 adapter = (struct ena_adapter *)(dev->data->dev_private); 1009 1010 ena_dev = &adapter->ena_dev; 1011 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1012 1013 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1014 RTE_LOG(ERR, PMD, 1015 "Invalid MTU setting. new_mtu: %d " 1016 "max mtu: %d min mtu: %d\n", 1017 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1018 return -EINVAL; 1019 } 1020 1021 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1022 if (rc) 1023 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 1024 else 1025 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 1026 1027 return rc; 1028 } 1029 1030 static int ena_start(struct rte_eth_dev *dev) 1031 { 1032 struct ena_adapter *adapter = 1033 (struct ena_adapter *)(dev->data->dev_private); 1034 uint64_t ticks; 1035 int rc = 0; 1036 1037 rc = ena_check_valid_conf(adapter); 1038 if (rc) 1039 return rc; 1040 1041 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1042 if (rc) 1043 return rc; 1044 1045 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1046 if (rc) 1047 goto err_start_tx; 1048 1049 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1050 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1051 rc = ena_rss_init_default(adapter); 1052 if (rc) 1053 goto err_rss_init; 1054 } 1055 1056 ena_stats_restart(dev); 1057 1058 adapter->timestamp_wd = rte_get_timer_cycles(); 1059 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1060 1061 ticks = rte_get_timer_hz(); 1062 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1063 ena_timer_wd_callback, adapter); 1064 1065 ++adapter->dev_stats.dev_start; 1066 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1067 1068 return 0; 1069 1070 err_rss_init: 1071 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1072 err_start_tx: 1073 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1074 return rc; 1075 } 1076 1077 static void ena_stop(struct rte_eth_dev *dev) 1078 { 1079 struct ena_adapter *adapter = 1080 (struct ena_adapter *)(dev->data->dev_private); 1081 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1082 int rc; 1083 1084 rte_timer_stop_sync(&adapter->timer_wd); 1085 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1086 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1087 1088 if (adapter->trigger_reset) { 1089 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1090 if (rc) 1091 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc); 1092 } 1093 1094 ++adapter->dev_stats.dev_stop; 1095 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1096 } 1097 1098 static int ena_create_io_queue(struct ena_ring *ring) 1099 { 1100 struct ena_adapter *adapter; 1101 struct ena_com_dev *ena_dev; 1102 struct ena_com_create_io_ctx ctx = 1103 /* policy set to _HOST just to satisfy icc compiler */ 1104 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1105 0, 0, 0, 0, 0 }; 1106 uint16_t ena_qid; 1107 unsigned int i; 1108 int rc; 1109 1110 adapter = ring->adapter; 1111 ena_dev = &adapter->ena_dev; 1112 1113 if (ring->type == ENA_RING_TYPE_TX) { 1114 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1115 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1116 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1117 ctx.queue_size = adapter->tx_ring_size; 1118 for (i = 0; i < ring->ring_size; i++) 1119 ring->empty_tx_reqs[i] = i; 1120 } else { 1121 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1122 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1123 ctx.queue_size = adapter->rx_ring_size; 1124 for (i = 0; i < ring->ring_size; i++) 1125 ring->empty_rx_reqs[i] = i; 1126 } 1127 ctx.qid = ena_qid; 1128 ctx.msix_vector = -1; /* interrupts not used */ 1129 ctx.numa_node = ena_cpu_to_node(ring->id); 1130 1131 rc = ena_com_create_io_queue(ena_dev, &ctx); 1132 if (rc) { 1133 RTE_LOG(ERR, PMD, 1134 "failed to create io queue #%d (qid:%d) rc: %d\n", 1135 ring->id, ena_qid, rc); 1136 return rc; 1137 } 1138 1139 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1140 &ring->ena_com_io_sq, 1141 &ring->ena_com_io_cq); 1142 if (rc) { 1143 RTE_LOG(ERR, PMD, 1144 "Failed to get io queue handlers. queue num %d rc: %d\n", 1145 ring->id, rc); 1146 ena_com_destroy_io_queue(ena_dev, ena_qid); 1147 return rc; 1148 } 1149 1150 if (ring->type == ENA_RING_TYPE_TX) 1151 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1152 1153 return 0; 1154 } 1155 1156 static void ena_queue_stop(struct ena_ring *ring) 1157 { 1158 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1159 1160 if (ring->type == ENA_RING_TYPE_RX) { 1161 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1162 ena_rx_queue_release_bufs(ring); 1163 } else { 1164 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1165 ena_tx_queue_release_bufs(ring); 1166 } 1167 } 1168 1169 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1170 enum ena_ring_type ring_type) 1171 { 1172 struct ena_adapter *adapter = 1173 (struct ena_adapter *)(dev->data->dev_private); 1174 struct ena_ring *queues = NULL; 1175 uint16_t nb_queues, i; 1176 1177 if (ring_type == ENA_RING_TYPE_RX) { 1178 queues = adapter->rx_ring; 1179 nb_queues = dev->data->nb_rx_queues; 1180 } else { 1181 queues = adapter->tx_ring; 1182 nb_queues = dev->data->nb_tx_queues; 1183 } 1184 1185 for (i = 0; i < nb_queues; ++i) 1186 if (queues[i].configured) 1187 ena_queue_stop(&queues[i]); 1188 } 1189 1190 static int ena_queue_start(struct ena_ring *ring) 1191 { 1192 int rc, bufs_num; 1193 1194 ena_assert_msg(ring->configured == 1, 1195 "Trying to start unconfigured queue\n"); 1196 1197 rc = ena_create_io_queue(ring); 1198 if (rc) { 1199 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1200 return rc; 1201 } 1202 1203 ring->next_to_clean = 0; 1204 ring->next_to_use = 0; 1205 1206 if (ring->type == ENA_RING_TYPE_TX) { 1207 ring->tx_stats.available_desc = 1208 ena_com_free_desc(ring->ena_com_io_sq); 1209 return 0; 1210 } 1211 1212 bufs_num = ring->ring_size - 1; 1213 rc = ena_populate_rx_queue(ring, bufs_num); 1214 if (rc != bufs_num) { 1215 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1216 ENA_IO_RXQ_IDX(ring->id)); 1217 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1218 return ENA_COM_FAULT; 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1225 uint16_t queue_idx, 1226 uint16_t nb_desc, 1227 __rte_unused unsigned int socket_id, 1228 const struct rte_eth_txconf *tx_conf) 1229 { 1230 struct ena_ring *txq = NULL; 1231 struct ena_adapter *adapter = 1232 (struct ena_adapter *)(dev->data->dev_private); 1233 unsigned int i; 1234 1235 txq = &adapter->tx_ring[queue_idx]; 1236 1237 if (txq->configured) { 1238 RTE_LOG(CRIT, PMD, 1239 "API violation. Queue %d is already configured\n", 1240 queue_idx); 1241 return ENA_COM_FAULT; 1242 } 1243 1244 if (!rte_is_power_of_2(nb_desc)) { 1245 RTE_LOG(ERR, PMD, 1246 "Unsupported size of TX queue: %d is not a power of 2.\n", 1247 nb_desc); 1248 return -EINVAL; 1249 } 1250 1251 if (nb_desc > adapter->tx_ring_size) { 1252 RTE_LOG(ERR, PMD, 1253 "Unsupported size of TX queue (max size: %d)\n", 1254 adapter->tx_ring_size); 1255 return -EINVAL; 1256 } 1257 1258 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1259 nb_desc = adapter->tx_ring_size; 1260 1261 txq->port_id = dev->data->port_id; 1262 txq->next_to_clean = 0; 1263 txq->next_to_use = 0; 1264 txq->ring_size = nb_desc; 1265 1266 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1267 sizeof(struct ena_tx_buffer) * 1268 txq->ring_size, 1269 RTE_CACHE_LINE_SIZE); 1270 if (!txq->tx_buffer_info) { 1271 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1272 return -ENOMEM; 1273 } 1274 1275 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1276 sizeof(u16) * txq->ring_size, 1277 RTE_CACHE_LINE_SIZE); 1278 if (!txq->empty_tx_reqs) { 1279 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1280 rte_free(txq->tx_buffer_info); 1281 return -ENOMEM; 1282 } 1283 1284 txq->push_buf_intermediate_buf = 1285 rte_zmalloc("txq->push_buf_intermediate_buf", 1286 txq->tx_max_header_size, 1287 RTE_CACHE_LINE_SIZE); 1288 if (!txq->push_buf_intermediate_buf) { 1289 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n"); 1290 rte_free(txq->tx_buffer_info); 1291 rte_free(txq->empty_tx_reqs); 1292 return -ENOMEM; 1293 } 1294 1295 for (i = 0; i < txq->ring_size; i++) 1296 txq->empty_tx_reqs[i] = i; 1297 1298 if (tx_conf != NULL) { 1299 txq->offloads = 1300 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1301 } 1302 /* Store pointer to this queue in upper layer */ 1303 txq->configured = 1; 1304 dev->data->tx_queues[queue_idx] = txq; 1305 1306 return 0; 1307 } 1308 1309 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1310 uint16_t queue_idx, 1311 uint16_t nb_desc, 1312 __rte_unused unsigned int socket_id, 1313 __rte_unused const struct rte_eth_rxconf *rx_conf, 1314 struct rte_mempool *mp) 1315 { 1316 struct ena_adapter *adapter = 1317 (struct ena_adapter *)(dev->data->dev_private); 1318 struct ena_ring *rxq = NULL; 1319 int i; 1320 1321 rxq = &adapter->rx_ring[queue_idx]; 1322 if (rxq->configured) { 1323 RTE_LOG(CRIT, PMD, 1324 "API violation. Queue %d is already configured\n", 1325 queue_idx); 1326 return ENA_COM_FAULT; 1327 } 1328 1329 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1330 nb_desc = adapter->rx_ring_size; 1331 1332 if (!rte_is_power_of_2(nb_desc)) { 1333 RTE_LOG(ERR, PMD, 1334 "Unsupported size of RX queue: %d is not a power of 2.\n", 1335 nb_desc); 1336 return -EINVAL; 1337 } 1338 1339 if (nb_desc > adapter->rx_ring_size) { 1340 RTE_LOG(ERR, PMD, 1341 "Unsupported size of RX queue (max size: %d)\n", 1342 adapter->rx_ring_size); 1343 return -EINVAL; 1344 } 1345 1346 rxq->port_id = dev->data->port_id; 1347 rxq->next_to_clean = 0; 1348 rxq->next_to_use = 0; 1349 rxq->ring_size = nb_desc; 1350 rxq->mb_pool = mp; 1351 1352 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1353 sizeof(struct rte_mbuf *) * nb_desc, 1354 RTE_CACHE_LINE_SIZE); 1355 if (!rxq->rx_buffer_info) { 1356 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1357 return -ENOMEM; 1358 } 1359 1360 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1361 sizeof(struct rte_mbuf *) * nb_desc, 1362 RTE_CACHE_LINE_SIZE); 1363 1364 if (!rxq->rx_refill_buffer) { 1365 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n"); 1366 rte_free(rxq->rx_buffer_info); 1367 rxq->rx_buffer_info = NULL; 1368 return -ENOMEM; 1369 } 1370 1371 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1372 sizeof(uint16_t) * nb_desc, 1373 RTE_CACHE_LINE_SIZE); 1374 if (!rxq->empty_rx_reqs) { 1375 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n"); 1376 rte_free(rxq->rx_buffer_info); 1377 rxq->rx_buffer_info = NULL; 1378 rte_free(rxq->rx_refill_buffer); 1379 rxq->rx_refill_buffer = NULL; 1380 return -ENOMEM; 1381 } 1382 1383 for (i = 0; i < nb_desc; i++) 1384 rxq->empty_rx_reqs[i] = i; 1385 1386 /* Store pointer to this queue in upper layer */ 1387 rxq->configured = 1; 1388 dev->data->rx_queues[queue_idx] = rxq; 1389 1390 return 0; 1391 } 1392 1393 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1394 { 1395 unsigned int i; 1396 int rc; 1397 uint16_t ring_size = rxq->ring_size; 1398 uint16_t ring_mask = ring_size - 1; 1399 uint16_t next_to_use = rxq->next_to_use; 1400 uint16_t in_use, req_id; 1401 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1402 1403 if (unlikely(!count)) 1404 return 0; 1405 1406 in_use = rxq->next_to_use - rxq->next_to_clean; 1407 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1408 1409 /* get resources for incoming packets */ 1410 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1411 if (unlikely(rc < 0)) { 1412 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1413 ++rxq->rx_stats.mbuf_alloc_fail; 1414 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1415 return 0; 1416 } 1417 1418 for (i = 0; i < count; i++) { 1419 uint16_t next_to_use_masked = next_to_use & ring_mask; 1420 struct rte_mbuf *mbuf = mbufs[i]; 1421 struct ena_com_buf ebuf; 1422 1423 if (likely((i + 4) < count)) 1424 rte_prefetch0(mbufs[i + 4]); 1425 1426 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1427 rc = validate_rx_req_id(rxq, req_id); 1428 if (unlikely(rc < 0)) 1429 break; 1430 rxq->rx_buffer_info[req_id] = mbuf; 1431 1432 /* prepare physical address for DMA transaction */ 1433 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1434 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1435 /* pass resource to device */ 1436 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1437 &ebuf, req_id); 1438 if (unlikely(rc)) { 1439 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1440 rxq->rx_buffer_info[req_id] = NULL; 1441 break; 1442 } 1443 next_to_use++; 1444 } 1445 1446 if (unlikely(i < count)) { 1447 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d " 1448 "buffers (from %d)\n", rxq->id, i, count); 1449 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1450 count - i); 1451 ++rxq->rx_stats.refill_partial; 1452 } 1453 1454 /* When we submitted free recources to device... */ 1455 if (likely(i > 0)) { 1456 /* ...let HW know that it can fill buffers with data 1457 * 1458 * Add memory barrier to make sure the desc were written before 1459 * issue a doorbell 1460 */ 1461 rte_wmb(); 1462 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1463 1464 rxq->next_to_use = next_to_use; 1465 } 1466 1467 return i; 1468 } 1469 1470 static int ena_device_init(struct ena_com_dev *ena_dev, 1471 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1472 bool *wd_state) 1473 { 1474 uint32_t aenq_groups; 1475 int rc; 1476 bool readless_supported; 1477 1478 /* Initialize mmio registers */ 1479 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1480 if (rc) { 1481 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1482 return rc; 1483 } 1484 1485 /* The PCIe configuration space revision id indicate if mmio reg 1486 * read is disabled. 1487 */ 1488 readless_supported = 1489 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1490 & ENA_MMIO_DISABLE_REG_READ); 1491 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1492 1493 /* reset device */ 1494 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1495 if (rc) { 1496 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1497 goto err_mmio_read_less; 1498 } 1499 1500 /* check FW version */ 1501 rc = ena_com_validate_version(ena_dev); 1502 if (rc) { 1503 RTE_LOG(ERR, PMD, "device version is too low\n"); 1504 goto err_mmio_read_less; 1505 } 1506 1507 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1508 1509 /* ENA device administration layer init */ 1510 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1511 if (rc) { 1512 RTE_LOG(ERR, PMD, 1513 "cannot initialize ena admin queue with device\n"); 1514 goto err_mmio_read_less; 1515 } 1516 1517 /* To enable the msix interrupts the driver needs to know the number 1518 * of queues. So the driver uses polling mode to retrieve this 1519 * information. 1520 */ 1521 ena_com_set_admin_polling_mode(ena_dev, true); 1522 1523 ena_config_host_info(ena_dev); 1524 1525 /* Get Device Attributes and features */ 1526 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1527 if (rc) { 1528 RTE_LOG(ERR, PMD, 1529 "cannot get attribute for ena device rc= %d\n", rc); 1530 goto err_admin_init; 1531 } 1532 1533 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1534 BIT(ENA_ADMIN_NOTIFICATION) | 1535 BIT(ENA_ADMIN_KEEP_ALIVE) | 1536 BIT(ENA_ADMIN_FATAL_ERROR) | 1537 BIT(ENA_ADMIN_WARNING); 1538 1539 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1540 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1541 if (rc) { 1542 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc); 1543 goto err_admin_init; 1544 } 1545 1546 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1547 1548 return 0; 1549 1550 err_admin_init: 1551 ena_com_admin_destroy(ena_dev); 1552 1553 err_mmio_read_less: 1554 ena_com_mmio_reg_read_request_destroy(ena_dev); 1555 1556 return rc; 1557 } 1558 1559 static void ena_interrupt_handler_rte(void *cb_arg) 1560 { 1561 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg; 1562 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1563 1564 ena_com_admin_q_comp_intr_handler(ena_dev); 1565 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1566 ena_com_aenq_intr_handler(ena_dev, adapter); 1567 } 1568 1569 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1570 { 1571 if (!adapter->wd_state) 1572 return; 1573 1574 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1575 return; 1576 1577 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1578 adapter->keep_alive_timeout)) { 1579 RTE_LOG(ERR, PMD, "Keep alive timeout\n"); 1580 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1581 adapter->trigger_reset = true; 1582 ++adapter->dev_stats.wd_expired; 1583 } 1584 } 1585 1586 /* Check if admin queue is enabled */ 1587 static void check_for_admin_com_state(struct ena_adapter *adapter) 1588 { 1589 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1590 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n"); 1591 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1592 adapter->trigger_reset = true; 1593 } 1594 } 1595 1596 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1597 void *arg) 1598 { 1599 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1600 struct rte_eth_dev *dev = adapter->rte_dev; 1601 1602 check_for_missing_keep_alive(adapter); 1603 check_for_admin_com_state(adapter); 1604 1605 if (unlikely(adapter->trigger_reset)) { 1606 RTE_LOG(ERR, PMD, "Trigger reset is on\n"); 1607 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1608 NULL); 1609 } 1610 } 1611 1612 static inline void 1613 set_default_llq_configurations(struct ena_llq_configurations *llq_config) 1614 { 1615 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1616 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1617 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1618 llq_config->llq_num_decs_before_header = 1619 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1620 llq_config->llq_ring_entry_size_value = 128; 1621 } 1622 1623 static int 1624 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1625 struct ena_com_dev *ena_dev, 1626 struct ena_admin_feature_llq_desc *llq, 1627 struct ena_llq_configurations *llq_default_configurations) 1628 { 1629 int rc; 1630 u32 llq_feature_mask; 1631 1632 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1633 if (!(ena_dev->supported_features & llq_feature_mask)) { 1634 RTE_LOG(INFO, PMD, 1635 "LLQ is not supported. Fallback to host mode policy.\n"); 1636 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1637 return 0; 1638 } 1639 1640 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1641 if (unlikely(rc)) { 1642 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1643 "Fallback to host mode policy."); 1644 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1645 return 0; 1646 } 1647 1648 /* Nothing to config, exit */ 1649 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1650 return 0; 1651 1652 if (!adapter->dev_mem_base) { 1653 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. " 1654 "Fallback to host mode policy.\n."); 1655 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1656 return 0; 1657 } 1658 1659 ena_dev->mem_bar = adapter->dev_mem_base; 1660 1661 return 0; 1662 } 1663 1664 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, 1665 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1666 { 1667 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; 1668 1669 /* Regular queues capabilities */ 1670 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1671 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1672 &get_feat_ctx->max_queue_ext.max_queue_ext; 1673 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1674 max_queue_ext->max_rx_cq_num); 1675 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1676 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1677 } else { 1678 struct ena_admin_queue_feature_desc *max_queues = 1679 &get_feat_ctx->max_queues; 1680 io_tx_sq_num = max_queues->max_sq_num; 1681 io_tx_cq_num = max_queues->max_cq_num; 1682 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1683 } 1684 1685 /* In case of LLQ use the llq number in the get feature cmd */ 1686 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1687 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1688 1689 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1690 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); 1691 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); 1692 1693 if (unlikely(io_queue_num == 0)) { 1694 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n"); 1695 return -EFAULT; 1696 } 1697 1698 return io_queue_num; 1699 } 1700 1701 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1702 { 1703 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1704 struct rte_pci_device *pci_dev; 1705 struct rte_intr_handle *intr_handle; 1706 struct ena_adapter *adapter = 1707 (struct ena_adapter *)(eth_dev->data->dev_private); 1708 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1709 struct ena_com_dev_get_features_ctx get_feat_ctx; 1710 struct ena_llq_configurations llq_config; 1711 const char *queue_type_str; 1712 int rc; 1713 1714 static int adapters_found; 1715 bool wd_state; 1716 1717 eth_dev->dev_ops = &ena_dev_ops; 1718 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1719 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1720 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1721 1722 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1723 return 0; 1724 1725 memset(adapter, 0, sizeof(struct ena_adapter)); 1726 ena_dev = &adapter->ena_dev; 1727 1728 adapter->rte_eth_dev_data = eth_dev->data; 1729 adapter->rte_dev = eth_dev; 1730 1731 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1732 adapter->pdev = pci_dev; 1733 1734 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1735 pci_dev->addr.domain, 1736 pci_dev->addr.bus, 1737 pci_dev->addr.devid, 1738 pci_dev->addr.function); 1739 1740 intr_handle = &pci_dev->intr_handle; 1741 1742 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1743 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1744 1745 if (!adapter->regs) { 1746 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1747 ENA_REGS_BAR); 1748 return -ENXIO; 1749 } 1750 1751 ena_dev->reg_bar = adapter->regs; 1752 ena_dev->dmadev = adapter->pdev; 1753 1754 adapter->id_number = adapters_found; 1755 1756 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1757 adapter->id_number); 1758 1759 /* device specific initialization routine */ 1760 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1761 if (rc) { 1762 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1763 goto err; 1764 } 1765 adapter->wd_state = wd_state; 1766 1767 set_default_llq_configurations(&llq_config); 1768 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1769 &get_feat_ctx.llq, &llq_config); 1770 if (unlikely(rc)) { 1771 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1772 return rc; 1773 } 1774 1775 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1776 queue_type_str = "Regular"; 1777 else 1778 queue_type_str = "Low latency"; 1779 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str); 1780 1781 calc_queue_ctx.ena_dev = ena_dev; 1782 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1783 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1784 &get_feat_ctx); 1785 1786 rc = ena_calc_queue_size(&calc_queue_ctx); 1787 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { 1788 rc = -EFAULT; 1789 goto err_device_destroy; 1790 } 1791 1792 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; 1793 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; 1794 1795 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1796 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1797 1798 /* prepare ring structures */ 1799 ena_init_rings(adapter); 1800 1801 ena_config_debug_area(adapter); 1802 1803 /* Set max MTU for this device */ 1804 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1805 1806 /* set device support for offloads */ 1807 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1808 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1809 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1810 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1811 adapter->offloads.rx_csum_supported = 1812 (get_feat_ctx.offload.rx_supported & 1813 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1814 1815 /* Copy MAC address and point DPDK to it */ 1816 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr; 1817 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr, 1818 (struct ether_addr *)adapter->mac_addr); 1819 1820 /* 1821 * Pass the information to the rte_eth_dev_close() that it should also 1822 * release the private port resources. 1823 */ 1824 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1825 1826 adapter->drv_stats = rte_zmalloc("adapter stats", 1827 sizeof(*adapter->drv_stats), 1828 RTE_CACHE_LINE_SIZE); 1829 if (!adapter->drv_stats) { 1830 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1831 rc = -ENOMEM; 1832 goto err_delete_debug_area; 1833 } 1834 1835 rte_intr_callback_register(intr_handle, 1836 ena_interrupt_handler_rte, 1837 adapter); 1838 rte_intr_enable(intr_handle); 1839 ena_com_set_admin_polling_mode(ena_dev, false); 1840 ena_com_admin_aenq_enable(ena_dev); 1841 1842 if (adapters_found == 0) 1843 rte_timer_subsystem_init(); 1844 rte_timer_init(&adapter->timer_wd); 1845 1846 adapters_found++; 1847 adapter->state = ENA_ADAPTER_STATE_INIT; 1848 1849 return 0; 1850 1851 err_delete_debug_area: 1852 ena_com_delete_debug_area(ena_dev); 1853 1854 err_device_destroy: 1855 ena_com_delete_host_info(ena_dev); 1856 ena_com_admin_destroy(ena_dev); 1857 1858 err: 1859 return rc; 1860 } 1861 1862 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1863 { 1864 struct ena_adapter *adapter = 1865 (struct ena_adapter *)(eth_dev->data->dev_private); 1866 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1867 1868 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1869 return; 1870 1871 ena_com_set_admin_running_state(ena_dev, false); 1872 1873 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1874 ena_close(eth_dev); 1875 1876 ena_com_delete_debug_area(ena_dev); 1877 ena_com_delete_host_info(ena_dev); 1878 1879 ena_com_abort_admin_commands(ena_dev); 1880 ena_com_wait_for_abort_completion(ena_dev); 1881 ena_com_admin_destroy(ena_dev); 1882 ena_com_mmio_reg_read_request_destroy(ena_dev); 1883 1884 adapter->state = ENA_ADAPTER_STATE_FREE; 1885 } 1886 1887 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1888 { 1889 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1890 return 0; 1891 1892 ena_destroy_device(eth_dev); 1893 1894 eth_dev->dev_ops = NULL; 1895 eth_dev->rx_pkt_burst = NULL; 1896 eth_dev->tx_pkt_burst = NULL; 1897 eth_dev->tx_pkt_prepare = NULL; 1898 1899 return 0; 1900 } 1901 1902 static int ena_dev_configure(struct rte_eth_dev *dev) 1903 { 1904 struct ena_adapter *adapter = 1905 (struct ena_adapter *)(dev->data->dev_private); 1906 1907 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1908 1909 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1910 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1911 return 0; 1912 } 1913 1914 static void ena_init_rings(struct ena_adapter *adapter) 1915 { 1916 int i; 1917 1918 for (i = 0; i < adapter->num_queues; i++) { 1919 struct ena_ring *ring = &adapter->tx_ring[i]; 1920 1921 ring->configured = 0; 1922 ring->type = ENA_RING_TYPE_TX; 1923 ring->adapter = adapter; 1924 ring->id = i; 1925 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1926 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1927 ring->sgl_size = adapter->max_tx_sgl_size; 1928 } 1929 1930 for (i = 0; i < adapter->num_queues; i++) { 1931 struct ena_ring *ring = &adapter->rx_ring[i]; 1932 1933 ring->configured = 0; 1934 ring->type = ENA_RING_TYPE_RX; 1935 ring->adapter = adapter; 1936 ring->id = i; 1937 ring->sgl_size = adapter->max_rx_sgl_size; 1938 } 1939 } 1940 1941 static void ena_infos_get(struct rte_eth_dev *dev, 1942 struct rte_eth_dev_info *dev_info) 1943 { 1944 struct ena_adapter *adapter; 1945 struct ena_com_dev *ena_dev; 1946 uint64_t rx_feat = 0, tx_feat = 0; 1947 1948 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1949 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1950 adapter = (struct ena_adapter *)(dev->data->dev_private); 1951 1952 ena_dev = &adapter->ena_dev; 1953 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1954 1955 dev_info->speed_capa = 1956 ETH_LINK_SPEED_1G | 1957 ETH_LINK_SPEED_2_5G | 1958 ETH_LINK_SPEED_5G | 1959 ETH_LINK_SPEED_10G | 1960 ETH_LINK_SPEED_25G | 1961 ETH_LINK_SPEED_40G | 1962 ETH_LINK_SPEED_50G | 1963 ETH_LINK_SPEED_100G; 1964 1965 /* Set Tx & Rx features available for device */ 1966 if (adapter->offloads.tso4_supported) 1967 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1968 1969 if (adapter->offloads.tx_csum_supported) 1970 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1971 DEV_TX_OFFLOAD_UDP_CKSUM | 1972 DEV_TX_OFFLOAD_TCP_CKSUM; 1973 1974 if (adapter->offloads.rx_csum_supported) 1975 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1976 DEV_RX_OFFLOAD_UDP_CKSUM | 1977 DEV_RX_OFFLOAD_TCP_CKSUM; 1978 1979 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1980 1981 /* Inform framework about available features */ 1982 dev_info->rx_offload_capa = rx_feat; 1983 dev_info->rx_queue_offload_capa = rx_feat; 1984 dev_info->tx_offload_capa = tx_feat; 1985 dev_info->tx_queue_offload_capa = tx_feat; 1986 1987 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1988 ETH_RSS_UDP; 1989 1990 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1991 dev_info->max_rx_pktlen = adapter->max_mtu; 1992 dev_info->max_mac_addrs = 1; 1993 1994 dev_info->max_rx_queues = adapter->num_queues; 1995 dev_info->max_tx_queues = adapter->num_queues; 1996 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1997 1998 adapter->tx_supported_offloads = tx_feat; 1999 adapter->rx_supported_offloads = rx_feat; 2000 2001 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; 2002 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2003 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2004 adapter->max_rx_sgl_size); 2005 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2006 adapter->max_rx_sgl_size); 2007 2008 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; 2009 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2010 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2011 adapter->max_tx_sgl_size); 2012 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2013 adapter->max_tx_sgl_size); 2014 } 2015 2016 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2017 uint16_t nb_pkts) 2018 { 2019 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2020 unsigned int ring_size = rx_ring->ring_size; 2021 unsigned int ring_mask = ring_size - 1; 2022 uint16_t next_to_clean = rx_ring->next_to_clean; 2023 uint16_t desc_in_use = 0; 2024 uint16_t req_id; 2025 unsigned int recv_idx = 0; 2026 struct rte_mbuf *mbuf = NULL; 2027 struct rte_mbuf *mbuf_head = NULL; 2028 struct rte_mbuf *mbuf_prev = NULL; 2029 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2030 unsigned int completed; 2031 2032 struct ena_com_rx_ctx ena_rx_ctx; 2033 int rc = 0; 2034 2035 /* Check adapter state */ 2036 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2037 RTE_LOG(ALERT, PMD, 2038 "Trying to receive pkts while device is NOT running\n"); 2039 return 0; 2040 } 2041 2042 desc_in_use = rx_ring->next_to_use - next_to_clean; 2043 if (unlikely(nb_pkts > desc_in_use)) 2044 nb_pkts = desc_in_use; 2045 2046 for (completed = 0; completed < nb_pkts; completed++) { 2047 int segments = 0; 2048 2049 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2050 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2051 ena_rx_ctx.descs = 0; 2052 /* receive packet context */ 2053 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2054 rx_ring->ena_com_io_sq, 2055 &ena_rx_ctx); 2056 if (unlikely(rc)) { 2057 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 2058 rx_ring->adapter->reset_reason = 2059 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2060 rx_ring->adapter->trigger_reset = true; 2061 ++rx_ring->rx_stats.bad_desc_num; 2062 return 0; 2063 } 2064 2065 if (unlikely(ena_rx_ctx.descs == 0)) 2066 break; 2067 2068 while (segments < ena_rx_ctx.descs) { 2069 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2070 rc = validate_rx_req_id(rx_ring, req_id); 2071 if (unlikely(rc)) { 2072 if (segments != 0) 2073 rte_mbuf_raw_free(mbuf_head); 2074 break; 2075 } 2076 2077 mbuf = rx_buff_info[req_id]; 2078 rx_buff_info[req_id] = NULL; 2079 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2080 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2081 mbuf->refcnt = 1; 2082 mbuf->next = NULL; 2083 if (unlikely(segments == 0)) { 2084 mbuf->nb_segs = ena_rx_ctx.descs; 2085 mbuf->port = rx_ring->port_id; 2086 mbuf->pkt_len = 0; 2087 mbuf_head = mbuf; 2088 } else { 2089 /* for multi-segment pkts create mbuf chain */ 2090 mbuf_prev->next = mbuf; 2091 } 2092 mbuf_head->pkt_len += mbuf->data_len; 2093 2094 mbuf_prev = mbuf; 2095 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2096 req_id; 2097 segments++; 2098 next_to_clean++; 2099 } 2100 if (unlikely(rc)) 2101 break; 2102 2103 /* fill mbuf attributes if any */ 2104 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2105 2106 if (unlikely(mbuf_head->ol_flags & 2107 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) 2108 ++rx_ring->rx_stats.bad_csum; 2109 2110 mbuf_head->hash.rss = ena_rx_ctx.hash; 2111 2112 /* pass to DPDK application head mbuf */ 2113 rx_pkts[recv_idx] = mbuf_head; 2114 recv_idx++; 2115 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2116 } 2117 2118 rx_ring->rx_stats.cnt += recv_idx; 2119 rx_ring->next_to_clean = next_to_clean; 2120 2121 desc_in_use = desc_in_use - completed + 1; 2122 /* Burst refill to save doorbells, memory barriers, const interval */ 2123 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2124 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2125 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2126 } 2127 2128 return recv_idx; 2129 } 2130 2131 static uint16_t 2132 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2133 uint16_t nb_pkts) 2134 { 2135 int32_t ret; 2136 uint32_t i; 2137 struct rte_mbuf *m; 2138 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2139 struct ipv4_hdr *ip_hdr; 2140 uint64_t ol_flags; 2141 uint16_t frag_field; 2142 2143 for (i = 0; i != nb_pkts; i++) { 2144 m = tx_pkts[i]; 2145 ol_flags = m->ol_flags; 2146 2147 if (!(ol_flags & PKT_TX_IPV4)) 2148 continue; 2149 2150 /* If there was not L2 header length specified, assume it is 2151 * length of the ethernet header. 2152 */ 2153 if (unlikely(m->l2_len == 0)) 2154 m->l2_len = sizeof(struct ether_hdr); 2155 2156 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, 2157 m->l2_len); 2158 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2159 2160 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) { 2161 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2162 2163 /* If IPv4 header has DF flag enabled and TSO support is 2164 * disabled, partial chcecksum should not be calculated. 2165 */ 2166 if (!tx_ring->adapter->offloads.tso4_supported) 2167 continue; 2168 } 2169 2170 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2171 (ol_flags & PKT_TX_L4_MASK) == 2172 PKT_TX_SCTP_CKSUM) { 2173 rte_errno = ENOTSUP; 2174 return i; 2175 } 2176 2177 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2178 ret = rte_validate_tx_offload(m); 2179 if (ret != 0) { 2180 rte_errno = -ret; 2181 return i; 2182 } 2183 #endif 2184 2185 /* In case we are supposed to TSO and have DF not set (DF=0) 2186 * hardware must be provided with partial checksum, otherwise 2187 * it will take care of necessary calculations. 2188 */ 2189 2190 ret = rte_net_intel_cksum_flags_prepare(m, 2191 ol_flags & ~PKT_TX_TCP_SEG); 2192 if (ret != 0) { 2193 rte_errno = -ret; 2194 return i; 2195 } 2196 } 2197 2198 return i; 2199 } 2200 2201 static void ena_update_hints(struct ena_adapter *adapter, 2202 struct ena_admin_ena_hw_hints *hints) 2203 { 2204 if (hints->admin_completion_tx_timeout) 2205 adapter->ena_dev.admin_queue.completion_timeout = 2206 hints->admin_completion_tx_timeout * 1000; 2207 2208 if (hints->mmio_read_timeout) 2209 /* convert to usec */ 2210 adapter->ena_dev.mmio_read.reg_read_to = 2211 hints->mmio_read_timeout * 1000; 2212 2213 if (hints->driver_watchdog_timeout) { 2214 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2215 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2216 else 2217 // Convert msecs to ticks 2218 adapter->keep_alive_timeout = 2219 (hints->driver_watchdog_timeout * 2220 rte_get_timer_hz()) / 1000; 2221 } 2222 } 2223 2224 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2225 struct rte_mbuf *mbuf) 2226 { 2227 struct ena_com_dev *ena_dev; 2228 int num_segments, header_len, rc; 2229 2230 ena_dev = &tx_ring->adapter->ena_dev; 2231 num_segments = mbuf->nb_segs; 2232 header_len = mbuf->data_len; 2233 2234 if (likely(num_segments < tx_ring->sgl_size)) 2235 return 0; 2236 2237 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2238 (num_segments == tx_ring->sgl_size) && 2239 (header_len < tx_ring->tx_max_header_size)) 2240 return 0; 2241 2242 ++tx_ring->tx_stats.linearize; 2243 rc = rte_pktmbuf_linearize(mbuf); 2244 if (unlikely(rc)) { 2245 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n"); 2246 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2247 ++tx_ring->tx_stats.linearize_failed; 2248 return rc; 2249 } 2250 2251 return rc; 2252 } 2253 2254 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2255 uint16_t nb_pkts) 2256 { 2257 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2258 uint16_t next_to_use = tx_ring->next_to_use; 2259 uint16_t next_to_clean = tx_ring->next_to_clean; 2260 struct rte_mbuf *mbuf; 2261 uint16_t seg_len; 2262 unsigned int ring_size = tx_ring->ring_size; 2263 unsigned int ring_mask = ring_size - 1; 2264 struct ena_com_tx_ctx ena_tx_ctx; 2265 struct ena_tx_buffer *tx_info; 2266 struct ena_com_buf *ebuf; 2267 uint16_t rc, req_id, total_tx_descs = 0; 2268 uint16_t sent_idx = 0, empty_tx_reqs; 2269 uint16_t push_len = 0; 2270 uint16_t delta = 0; 2271 int nb_hw_desc; 2272 uint32_t total_length; 2273 2274 /* Check adapter state */ 2275 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2276 RTE_LOG(ALERT, PMD, 2277 "Trying to xmit pkts while device is NOT running\n"); 2278 return 0; 2279 } 2280 2281 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2282 if (nb_pkts > empty_tx_reqs) 2283 nb_pkts = empty_tx_reqs; 2284 2285 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2286 mbuf = tx_pkts[sent_idx]; 2287 total_length = 0; 2288 2289 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2290 if (unlikely(rc)) 2291 break; 2292 2293 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2294 tx_info = &tx_ring->tx_buffer_info[req_id]; 2295 tx_info->mbuf = mbuf; 2296 tx_info->num_of_bufs = 0; 2297 ebuf = tx_info->bufs; 2298 2299 /* Prepare TX context */ 2300 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2301 memset(&ena_tx_ctx.ena_meta, 0x0, 2302 sizeof(struct ena_com_tx_meta)); 2303 ena_tx_ctx.ena_bufs = ebuf; 2304 ena_tx_ctx.req_id = req_id; 2305 2306 delta = 0; 2307 seg_len = mbuf->data_len; 2308 2309 if (tx_ring->tx_mem_queue_type == 2310 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2311 push_len = RTE_MIN(mbuf->pkt_len, 2312 tx_ring->tx_max_header_size); 2313 ena_tx_ctx.header_len = push_len; 2314 2315 if (likely(push_len <= seg_len)) { 2316 /* If the push header is in the single segment, 2317 * then just point it to the 1st mbuf data. 2318 */ 2319 ena_tx_ctx.push_header = 2320 rte_pktmbuf_mtod(mbuf, uint8_t *); 2321 } else { 2322 /* If the push header lays in the several 2323 * segments, copy it to the intermediate buffer. 2324 */ 2325 rte_pktmbuf_read(mbuf, 0, push_len, 2326 tx_ring->push_buf_intermediate_buf); 2327 ena_tx_ctx.push_header = 2328 tx_ring->push_buf_intermediate_buf; 2329 delta = push_len - seg_len; 2330 } 2331 } /* there's no else as we take advantage of memset zeroing */ 2332 2333 /* Set TX offloads flags, if applicable */ 2334 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2335 2336 if (unlikely(mbuf->ol_flags & 2337 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD))) 2338 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2339 2340 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2341 2342 /* Process first segment taking into 2343 * consideration pushed header 2344 */ 2345 if (seg_len > push_len) { 2346 ebuf->paddr = mbuf->buf_iova + 2347 mbuf->data_off + 2348 push_len; 2349 ebuf->len = seg_len - push_len; 2350 ebuf++; 2351 tx_info->num_of_bufs++; 2352 } 2353 total_length += mbuf->data_len; 2354 2355 while ((mbuf = mbuf->next) != NULL) { 2356 seg_len = mbuf->data_len; 2357 2358 /* Skip mbufs if whole data is pushed as a header */ 2359 if (unlikely(delta > seg_len)) { 2360 delta -= seg_len; 2361 continue; 2362 } 2363 2364 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2365 ebuf->len = seg_len - delta; 2366 total_length += ebuf->len; 2367 ebuf++; 2368 tx_info->num_of_bufs++; 2369 2370 delta = 0; 2371 } 2372 2373 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2374 2375 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2376 &ena_tx_ctx)) { 2377 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d" 2378 " achieved, writing doorbell to send burst\n", 2379 tx_ring->id); 2380 rte_wmb(); 2381 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2382 } 2383 2384 /* prepare the packet's descriptors to dma engine */ 2385 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2386 &ena_tx_ctx, &nb_hw_desc); 2387 if (unlikely(rc)) { 2388 ++tx_ring->tx_stats.prepare_ctx_err; 2389 break; 2390 } 2391 tx_info->tx_descs = nb_hw_desc; 2392 2393 next_to_use++; 2394 tx_ring->tx_stats.cnt += tx_info->num_of_bufs; 2395 tx_ring->tx_stats.bytes += total_length; 2396 } 2397 tx_ring->tx_stats.available_desc = 2398 ena_com_free_desc(tx_ring->ena_com_io_sq); 2399 2400 /* If there are ready packets to be xmitted... */ 2401 if (sent_idx > 0) { 2402 /* ...let HW do its best :-) */ 2403 rte_wmb(); 2404 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2405 tx_ring->tx_stats.doorbells++; 2406 tx_ring->next_to_use = next_to_use; 2407 } 2408 2409 /* Clear complete packets */ 2410 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2411 rc = validate_tx_req_id(tx_ring, req_id); 2412 if (rc) 2413 break; 2414 2415 /* Get Tx info & store how many descs were processed */ 2416 tx_info = &tx_ring->tx_buffer_info[req_id]; 2417 total_tx_descs += tx_info->tx_descs; 2418 2419 /* Free whole mbuf chain */ 2420 mbuf = tx_info->mbuf; 2421 rte_pktmbuf_free(mbuf); 2422 tx_info->mbuf = NULL; 2423 2424 /* Put back descriptor to the ring for reuse */ 2425 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2426 next_to_clean++; 2427 2428 /* If too many descs to clean, leave it for another run */ 2429 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2430 break; 2431 } 2432 tx_ring->tx_stats.available_desc = 2433 ena_com_free_desc(tx_ring->ena_com_io_sq); 2434 2435 if (total_tx_descs > 0) { 2436 /* acknowledge completion of sent packets */ 2437 tx_ring->next_to_clean = next_to_clean; 2438 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2439 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2440 } 2441 2442 tx_ring->tx_stats.tx_poll++; 2443 2444 return sent_idx; 2445 } 2446 2447 /** 2448 * DPDK callback to retrieve names of extended device statistics 2449 * 2450 * @param dev 2451 * Pointer to Ethernet device structure. 2452 * @param[out] xstats_names 2453 * Buffer to insert names into. 2454 * @param n 2455 * Number of names. 2456 * 2457 * @return 2458 * Number of xstats names. 2459 */ 2460 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2461 struct rte_eth_xstat_name *xstats_names, 2462 unsigned int n) 2463 { 2464 unsigned int xstats_count = ena_xstats_calc_num(dev); 2465 unsigned int stat, i, count = 0; 2466 2467 if (n < xstats_count || !xstats_names) 2468 return xstats_count; 2469 2470 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2471 strcpy(xstats_names[count].name, 2472 ena_stats_global_strings[stat].name); 2473 2474 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2475 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2476 snprintf(xstats_names[count].name, 2477 sizeof(xstats_names[count].name), 2478 "rx_q%d_%s", i, 2479 ena_stats_rx_strings[stat].name); 2480 2481 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2482 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2483 snprintf(xstats_names[count].name, 2484 sizeof(xstats_names[count].name), 2485 "tx_q%d_%s", i, 2486 ena_stats_tx_strings[stat].name); 2487 2488 return xstats_count; 2489 } 2490 2491 /** 2492 * DPDK callback to get extended device statistics. 2493 * 2494 * @param dev 2495 * Pointer to Ethernet device structure. 2496 * @param[out] stats 2497 * Stats table output buffer. 2498 * @param n 2499 * The size of the stats table. 2500 * 2501 * @return 2502 * Number of xstats on success, negative on failure. 2503 */ 2504 static int ena_xstats_get(struct rte_eth_dev *dev, 2505 struct rte_eth_xstat *xstats, 2506 unsigned int n) 2507 { 2508 struct ena_adapter *adapter = 2509 (struct ena_adapter *)(dev->data->dev_private); 2510 unsigned int xstats_count = ena_xstats_calc_num(dev); 2511 unsigned int stat, i, count = 0; 2512 int stat_offset; 2513 void *stats_begin; 2514 2515 if (n < xstats_count) 2516 return xstats_count; 2517 2518 if (!xstats) 2519 return 0; 2520 2521 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2522 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2523 stats_begin = &adapter->dev_stats; 2524 2525 xstats[count].id = count; 2526 xstats[count].value = *((uint64_t *) 2527 ((char *)stats_begin + stat_offset)); 2528 } 2529 2530 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2531 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2532 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2533 stats_begin = &adapter->rx_ring[i].rx_stats; 2534 2535 xstats[count].id = count; 2536 xstats[count].value = *((uint64_t *) 2537 ((char *)stats_begin + stat_offset)); 2538 } 2539 } 2540 2541 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2542 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2543 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2544 stats_begin = &adapter->tx_ring[i].rx_stats; 2545 2546 xstats[count].id = count; 2547 xstats[count].value = *((uint64_t *) 2548 ((char *)stats_begin + stat_offset)); 2549 } 2550 } 2551 2552 return count; 2553 } 2554 2555 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2556 const uint64_t *ids, 2557 uint64_t *values, 2558 unsigned int n) 2559 { 2560 struct ena_adapter *adapter = 2561 (struct ena_adapter *)(dev->data->dev_private); 2562 uint64_t id; 2563 uint64_t rx_entries, tx_entries; 2564 unsigned int i; 2565 int qid; 2566 int valid = 0; 2567 for (i = 0; i < n; ++i) { 2568 id = ids[i]; 2569 /* Check if id belongs to global statistics */ 2570 if (id < ENA_STATS_ARRAY_GLOBAL) { 2571 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2572 ++valid; 2573 continue; 2574 } 2575 2576 /* Check if id belongs to rx queue statistics */ 2577 id -= ENA_STATS_ARRAY_GLOBAL; 2578 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2579 if (id < rx_entries) { 2580 qid = id % dev->data->nb_rx_queues; 2581 id /= dev->data->nb_rx_queues; 2582 values[i] = *((uint64_t *) 2583 &adapter->rx_ring[qid].rx_stats + id); 2584 ++valid; 2585 continue; 2586 } 2587 /* Check if id belongs to rx queue statistics */ 2588 id -= rx_entries; 2589 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2590 if (id < tx_entries) { 2591 qid = id % dev->data->nb_tx_queues; 2592 id /= dev->data->nb_tx_queues; 2593 values[i] = *((uint64_t *) 2594 &adapter->tx_ring[qid].tx_stats + id); 2595 ++valid; 2596 continue; 2597 } 2598 } 2599 2600 return valid; 2601 } 2602 2603 /********************************************************************* 2604 * PMD configuration 2605 *********************************************************************/ 2606 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2607 struct rte_pci_device *pci_dev) 2608 { 2609 return rte_eth_dev_pci_generic_probe(pci_dev, 2610 sizeof(struct ena_adapter), eth_ena_dev_init); 2611 } 2612 2613 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2614 { 2615 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2616 } 2617 2618 static struct rte_pci_driver rte_ena_pmd = { 2619 .id_table = pci_id_ena_map, 2620 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2621 RTE_PCI_DRV_WC_ACTIVATE, 2622 .probe = eth_ena_pci_probe, 2623 .remove = eth_ena_pci_remove, 2624 }; 2625 2626 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2627 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2628 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2629 2630 RTE_INIT(ena_init_log) 2631 { 2632 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2633 if (ena_logtype_init >= 0) 2634 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2635 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2636 if (ena_logtype_driver >= 0) 2637 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2638 } 2639 2640 /****************************************************************************** 2641 ******************************** AENQ Handlers ******************************* 2642 *****************************************************************************/ 2643 static void ena_update_on_link_change(void *adapter_data, 2644 struct ena_admin_aenq_entry *aenq_e) 2645 { 2646 struct rte_eth_dev *eth_dev; 2647 struct ena_adapter *adapter; 2648 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2649 uint32_t status; 2650 2651 adapter = (struct ena_adapter *)adapter_data; 2652 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2653 eth_dev = adapter->rte_dev; 2654 2655 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2656 adapter->link_status = status; 2657 2658 ena_link_update(eth_dev, 0); 2659 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2660 } 2661 2662 static void ena_notification(void *data, 2663 struct ena_admin_aenq_entry *aenq_e) 2664 { 2665 struct ena_adapter *adapter = (struct ena_adapter *)data; 2666 struct ena_admin_ena_hw_hints *hints; 2667 2668 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2669 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n", 2670 aenq_e->aenq_common_desc.group, 2671 ENA_ADMIN_NOTIFICATION); 2672 2673 switch (aenq_e->aenq_common_desc.syndrom) { 2674 case ENA_ADMIN_UPDATE_HINTS: 2675 hints = (struct ena_admin_ena_hw_hints *) 2676 (&aenq_e->inline_data_w4); 2677 ena_update_hints(adapter, hints); 2678 break; 2679 default: 2680 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n", 2681 aenq_e->aenq_common_desc.syndrom); 2682 } 2683 } 2684 2685 static void ena_keep_alive(void *adapter_data, 2686 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2687 { 2688 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 2689 struct ena_admin_aenq_keep_alive_desc *desc; 2690 uint64_t rx_drops; 2691 2692 adapter->timestamp_wd = rte_get_timer_cycles(); 2693 2694 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2695 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2696 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2697 } 2698 2699 /** 2700 * This handler will called for unknown event group or unimplemented handlers 2701 **/ 2702 static void unimplemented_aenq_handler(__rte_unused void *data, 2703 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2704 { 2705 RTE_LOG(ERR, PMD, "Unknown event was received or event with " 2706 "unimplemented handler\n"); 2707 } 2708 2709 static struct ena_aenq_handlers aenq_handlers = { 2710 .handlers = { 2711 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2712 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2713 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2714 }, 2715 .unimplemented_handler = unimplemented_aenq_handler 2716 }; 2717