1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 #include <rte_kvargs.h> 17 18 #include "ena_ethdev.h" 19 #include "ena_logs.h" 20 #include "ena_platform.h" 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #include <ena_common_defs.h> 25 #include <ena_regs_defs.h> 26 #include <ena_admin_defs.h> 27 #include <ena_eth_io_defs.h> 28 29 #define DRV_MODULE_VER_MAJOR 2 30 #define DRV_MODULE_VER_MINOR 0 31 #define DRV_MODULE_VER_SUBMINOR 3 32 33 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 35 /*reverse version of ENA_IO_RXQ_IDX*/ 36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 37 38 /* While processing submitted and completed descriptors (rx and tx path 39 * respectively) in a loop it is desired to: 40 * - perform batch submissions while populating sumbissmion queue 41 * - avoid blocking transmission of other packets during cleanup phase 42 * Hence the utilization ratio of 1/8 of a queue size. 43 */ 44 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 45 46 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 47 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 48 49 #define GET_L4_HDR_LEN(mbuf) \ 50 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 51 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 52 53 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 54 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 55 #define ENA_HASH_KEY_SIZE 40 56 #define ETH_GSTRING_LEN 32 57 58 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 59 60 #define ENA_MIN_RING_DESC 128 61 62 enum ethtool_stringset { 63 ETH_SS_TEST = 0, 64 ETH_SS_STATS, 65 }; 66 67 struct ena_stats { 68 char name[ETH_GSTRING_LEN]; 69 int stat_offset; 70 }; 71 72 #define ENA_STAT_ENTRY(stat, stat_type) { \ 73 .name = #stat, \ 74 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 75 } 76 77 #define ENA_STAT_RX_ENTRY(stat) \ 78 ENA_STAT_ENTRY(stat, rx) 79 80 #define ENA_STAT_TX_ENTRY(stat) \ 81 ENA_STAT_ENTRY(stat, tx) 82 83 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 84 ENA_STAT_ENTRY(stat, dev) 85 86 /* Device arguments */ 87 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" 88 89 /* 90 * Each rte_memzone should have unique name. 91 * To satisfy it, count number of allocation and add it to name. 92 */ 93 rte_atomic32_t ena_alloc_cnt; 94 95 static const struct ena_stats ena_stats_global_strings[] = { 96 ENA_STAT_GLOBAL_ENTRY(wd_expired), 97 ENA_STAT_GLOBAL_ENTRY(dev_start), 98 ENA_STAT_GLOBAL_ENTRY(dev_stop), 99 }; 100 101 static const struct ena_stats ena_stats_tx_strings[] = { 102 ENA_STAT_TX_ENTRY(cnt), 103 ENA_STAT_TX_ENTRY(bytes), 104 ENA_STAT_TX_ENTRY(prepare_ctx_err), 105 ENA_STAT_TX_ENTRY(linearize), 106 ENA_STAT_TX_ENTRY(linearize_failed), 107 ENA_STAT_TX_ENTRY(tx_poll), 108 ENA_STAT_TX_ENTRY(doorbells), 109 ENA_STAT_TX_ENTRY(bad_req_id), 110 ENA_STAT_TX_ENTRY(available_desc), 111 }; 112 113 static const struct ena_stats ena_stats_rx_strings[] = { 114 ENA_STAT_RX_ENTRY(cnt), 115 ENA_STAT_RX_ENTRY(bytes), 116 ENA_STAT_RX_ENTRY(refill_partial), 117 ENA_STAT_RX_ENTRY(bad_csum), 118 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 119 ENA_STAT_RX_ENTRY(bad_desc_num), 120 ENA_STAT_RX_ENTRY(bad_req_id), 121 }; 122 123 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 124 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 125 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 126 127 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 128 DEV_TX_OFFLOAD_UDP_CKSUM |\ 129 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 130 DEV_TX_OFFLOAD_TCP_TSO) 131 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 132 PKT_TX_IP_CKSUM |\ 133 PKT_TX_TCP_SEG) 134 135 /** Vendor ID used by Amazon devices */ 136 #define PCI_VENDOR_ID_AMAZON 0x1D0F 137 /** Amazon devices */ 138 #define PCI_DEVICE_ID_ENA_VF 0xEC20 139 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 140 141 #define ENA_TX_OFFLOAD_MASK (\ 142 PKT_TX_L4_MASK | \ 143 PKT_TX_IPV6 | \ 144 PKT_TX_IPV4 | \ 145 PKT_TX_IP_CKSUM | \ 146 PKT_TX_TCP_SEG) 147 148 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 149 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 150 151 int ena_logtype_init; 152 int ena_logtype_driver; 153 154 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 155 int ena_logtype_rx; 156 #endif 157 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 158 int ena_logtype_tx; 159 #endif 160 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 161 int ena_logtype_tx_free; 162 #endif 163 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 164 int ena_logtype_com; 165 #endif 166 167 static const struct rte_pci_id pci_id_ena_map[] = { 168 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 169 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 170 { .device_id = 0 }, 171 }; 172 173 static struct ena_aenq_handlers aenq_handlers; 174 175 static int ena_device_init(struct ena_com_dev *ena_dev, 176 struct ena_com_dev_get_features_ctx *get_feat_ctx, 177 bool *wd_state); 178 static int ena_dev_configure(struct rte_eth_dev *dev); 179 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 180 uint16_t nb_pkts); 181 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 182 uint16_t nb_pkts); 183 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 184 uint16_t nb_desc, unsigned int socket_id, 185 const struct rte_eth_txconf *tx_conf); 186 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 187 uint16_t nb_desc, unsigned int socket_id, 188 const struct rte_eth_rxconf *rx_conf, 189 struct rte_mempool *mp); 190 static uint16_t eth_ena_recv_pkts(void *rx_queue, 191 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 192 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 193 static void ena_init_rings(struct ena_adapter *adapter); 194 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 195 static int ena_start(struct rte_eth_dev *dev); 196 static void ena_stop(struct rte_eth_dev *dev); 197 static void ena_close(struct rte_eth_dev *dev); 198 static int ena_dev_reset(struct rte_eth_dev *dev); 199 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 200 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 201 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 202 static void ena_rx_queue_release(void *queue); 203 static void ena_tx_queue_release(void *queue); 204 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 205 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 206 static int ena_link_update(struct rte_eth_dev *dev, 207 int wait_to_complete); 208 static int ena_create_io_queue(struct ena_ring *ring); 209 static void ena_queue_stop(struct ena_ring *ring); 210 static void ena_queue_stop_all(struct rte_eth_dev *dev, 211 enum ena_ring_type ring_type); 212 static int ena_queue_start(struct ena_ring *ring); 213 static int ena_queue_start_all(struct rte_eth_dev *dev, 214 enum ena_ring_type ring_type); 215 static void ena_stats_restart(struct rte_eth_dev *dev); 216 static int ena_infos_get(struct rte_eth_dev *dev, 217 struct rte_eth_dev_info *dev_info); 218 static int ena_rss_reta_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_reta_entry64 *reta_conf, 220 uint16_t reta_size); 221 static int ena_rss_reta_query(struct rte_eth_dev *dev, 222 struct rte_eth_rss_reta_entry64 *reta_conf, 223 uint16_t reta_size); 224 static void ena_interrupt_handler_rte(void *cb_arg); 225 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 226 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 227 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 228 static int ena_xstats_get_names(struct rte_eth_dev *dev, 229 struct rte_eth_xstat_name *xstats_names, 230 unsigned int n); 231 static int ena_xstats_get(struct rte_eth_dev *dev, 232 struct rte_eth_xstat *stats, 233 unsigned int n); 234 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 235 const uint64_t *ids, 236 uint64_t *values, 237 unsigned int n); 238 static int ena_process_bool_devarg(const char *key, 239 const char *value, 240 void *opaque); 241 static int ena_parse_devargs(struct ena_adapter *adapter, 242 struct rte_devargs *devargs); 243 244 static const struct eth_dev_ops ena_dev_ops = { 245 .dev_configure = ena_dev_configure, 246 .dev_infos_get = ena_infos_get, 247 .rx_queue_setup = ena_rx_queue_setup, 248 .tx_queue_setup = ena_tx_queue_setup, 249 .dev_start = ena_start, 250 .dev_stop = ena_stop, 251 .link_update = ena_link_update, 252 .stats_get = ena_stats_get, 253 .xstats_get_names = ena_xstats_get_names, 254 .xstats_get = ena_xstats_get, 255 .xstats_get_by_id = ena_xstats_get_by_id, 256 .mtu_set = ena_mtu_set, 257 .rx_queue_release = ena_rx_queue_release, 258 .tx_queue_release = ena_tx_queue_release, 259 .dev_close = ena_close, 260 .dev_reset = ena_dev_reset, 261 .reta_update = ena_rss_reta_update, 262 .reta_query = ena_rss_reta_query, 263 }; 264 265 void ena_rss_key_fill(void *key, size_t size) 266 { 267 static bool key_generated; 268 static uint8_t default_key[ENA_HASH_KEY_SIZE]; 269 size_t i; 270 271 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); 272 273 if (!key_generated) { 274 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) 275 default_key[i] = rte_rand() & 0xff; 276 key_generated = true; 277 } 278 279 rte_memcpy(key, default_key, size); 280 } 281 282 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 283 struct ena_com_rx_ctx *ena_rx_ctx) 284 { 285 uint64_t ol_flags = 0; 286 uint32_t packet_type = 0; 287 288 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 289 packet_type |= RTE_PTYPE_L4_TCP; 290 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 291 packet_type |= RTE_PTYPE_L4_UDP; 292 293 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 294 packet_type |= RTE_PTYPE_L3_IPV4; 295 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 296 packet_type |= RTE_PTYPE_L3_IPV6; 297 298 if (!ena_rx_ctx->l4_csum_checked) 299 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 300 else 301 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 302 ol_flags |= PKT_RX_L4_CKSUM_BAD; 303 else 304 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 305 306 if (unlikely(ena_rx_ctx->l3_csum_err)) 307 ol_flags |= PKT_RX_IP_CKSUM_BAD; 308 309 mbuf->ol_flags = ol_flags; 310 mbuf->packet_type = packet_type; 311 } 312 313 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 314 struct ena_com_tx_ctx *ena_tx_ctx, 315 uint64_t queue_offloads) 316 { 317 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 318 319 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 320 (queue_offloads & QUEUE_OFFLOADS)) { 321 /* check if TSO is required */ 322 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 323 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 324 ena_tx_ctx->tso_enable = true; 325 326 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 327 } 328 329 /* check if L3 checksum is needed */ 330 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 331 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 332 ena_tx_ctx->l3_csum_enable = true; 333 334 if (mbuf->ol_flags & PKT_TX_IPV6) { 335 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 336 } else { 337 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 338 339 /* set don't fragment (DF) flag */ 340 if (mbuf->packet_type & 341 (RTE_PTYPE_L4_NONFRAG 342 | RTE_PTYPE_INNER_L4_NONFRAG)) 343 ena_tx_ctx->df = true; 344 } 345 346 /* check if L4 checksum is needed */ 347 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 348 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 349 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 350 ena_tx_ctx->l4_csum_enable = true; 351 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 352 PKT_TX_UDP_CKSUM) && 353 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 354 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 355 ena_tx_ctx->l4_csum_enable = true; 356 } else { 357 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 358 ena_tx_ctx->l4_csum_enable = false; 359 } 360 361 ena_meta->mss = mbuf->tso_segsz; 362 ena_meta->l3_hdr_len = mbuf->l3_len; 363 ena_meta->l3_hdr_offset = mbuf->l2_len; 364 365 ena_tx_ctx->meta_valid = true; 366 } else { 367 ena_tx_ctx->meta_valid = false; 368 } 369 } 370 371 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 372 { 373 if (likely(req_id < rx_ring->ring_size)) 374 return 0; 375 376 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 377 378 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 379 rx_ring->adapter->trigger_reset = true; 380 ++rx_ring->rx_stats.bad_req_id; 381 382 return -EFAULT; 383 } 384 385 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 386 { 387 struct ena_tx_buffer *tx_info = NULL; 388 389 if (likely(req_id < tx_ring->ring_size)) { 390 tx_info = &tx_ring->tx_buffer_info[req_id]; 391 if (likely(tx_info->mbuf)) 392 return 0; 393 } 394 395 if (tx_info) 396 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 397 else 398 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 399 400 /* Trigger device reset */ 401 ++tx_ring->tx_stats.bad_req_id; 402 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 403 tx_ring->adapter->trigger_reset = true; 404 return -EFAULT; 405 } 406 407 static void ena_config_host_info(struct ena_com_dev *ena_dev) 408 { 409 struct ena_admin_host_info *host_info; 410 int rc; 411 412 /* Allocate only the host info */ 413 rc = ena_com_allocate_host_info(ena_dev); 414 if (rc) { 415 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 416 return; 417 } 418 419 host_info = ena_dev->host_attr.host_info; 420 421 host_info->os_type = ENA_ADMIN_OS_DPDK; 422 host_info->kernel_ver = RTE_VERSION; 423 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 424 sizeof(host_info->kernel_ver_str)); 425 host_info->os_dist = RTE_VERSION; 426 strlcpy((char *)host_info->os_dist_str, rte_version(), 427 sizeof(host_info->os_dist_str)); 428 host_info->driver_version = 429 (DRV_MODULE_VER_MAJOR) | 430 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 431 (DRV_MODULE_VER_SUBMINOR << 432 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 433 host_info->num_cpus = rte_lcore_count(); 434 435 host_info->driver_supported_features = 436 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 437 438 rc = ena_com_set_host_attributes(ena_dev); 439 if (rc) { 440 if (rc == -ENA_COM_UNSUPPORTED) 441 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 442 else 443 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 444 445 goto err; 446 } 447 448 return; 449 450 err: 451 ena_com_delete_host_info(ena_dev); 452 } 453 454 /* This function calculates the number of xstats based on the current config */ 455 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 456 { 457 return ENA_STATS_ARRAY_GLOBAL + 458 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 459 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 460 } 461 462 static void ena_config_debug_area(struct ena_adapter *adapter) 463 { 464 u32 debug_area_size; 465 int rc, ss_count; 466 467 ss_count = ena_xstats_calc_num(adapter->rte_dev); 468 469 /* allocate 32 bytes for each string and 64bit for the value */ 470 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 471 472 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 473 if (rc) { 474 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 475 return; 476 } 477 478 rc = ena_com_set_host_attributes(&adapter->ena_dev); 479 if (rc) { 480 if (rc == -ENA_COM_UNSUPPORTED) 481 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 482 else 483 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 484 485 goto err; 486 } 487 488 return; 489 err: 490 ena_com_delete_debug_area(&adapter->ena_dev); 491 } 492 493 static void ena_close(struct rte_eth_dev *dev) 494 { 495 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 496 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 497 struct ena_adapter *adapter = dev->data->dev_private; 498 499 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 500 ena_stop(dev); 501 adapter->state = ENA_ADAPTER_STATE_CLOSED; 502 503 ena_rx_queue_release_all(dev); 504 ena_tx_queue_release_all(dev); 505 506 rte_free(adapter->drv_stats); 507 adapter->drv_stats = NULL; 508 509 rte_intr_disable(intr_handle); 510 rte_intr_callback_unregister(intr_handle, 511 ena_interrupt_handler_rte, 512 adapter); 513 514 /* 515 * MAC is not allocated dynamically. Setting NULL should prevent from 516 * release of the resource in the rte_eth_dev_release_port(). 517 */ 518 dev->data->mac_addrs = NULL; 519 } 520 521 static int 522 ena_dev_reset(struct rte_eth_dev *dev) 523 { 524 int rc = 0; 525 526 ena_destroy_device(dev); 527 rc = eth_ena_dev_init(dev); 528 if (rc) 529 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 530 531 return rc; 532 } 533 534 static int ena_rss_reta_update(struct rte_eth_dev *dev, 535 struct rte_eth_rss_reta_entry64 *reta_conf, 536 uint16_t reta_size) 537 { 538 struct ena_adapter *adapter = dev->data->dev_private; 539 struct ena_com_dev *ena_dev = &adapter->ena_dev; 540 int rc, i; 541 u16 entry_value; 542 int conf_idx; 543 int idx; 544 545 if ((reta_size == 0) || (reta_conf == NULL)) 546 return -EINVAL; 547 548 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 549 PMD_DRV_LOG(WARNING, 550 "indirection table %d is bigger than supported (%d)\n", 551 reta_size, ENA_RX_RSS_TABLE_SIZE); 552 return -EINVAL; 553 } 554 555 for (i = 0 ; i < reta_size ; i++) { 556 /* each reta_conf is for 64 entries. 557 * to support 128 we use 2 conf of 64 558 */ 559 conf_idx = i / RTE_RETA_GROUP_SIZE; 560 idx = i % RTE_RETA_GROUP_SIZE; 561 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 562 entry_value = 563 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 564 565 rc = ena_com_indirect_table_fill_entry(ena_dev, 566 i, 567 entry_value); 568 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 569 PMD_DRV_LOG(ERR, 570 "Cannot fill indirect table\n"); 571 return rc; 572 } 573 } 574 } 575 576 rc = ena_com_indirect_table_set(ena_dev); 577 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 578 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 579 return rc; 580 } 581 582 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 583 __func__, reta_size, adapter->rte_dev->data->port_id); 584 585 return 0; 586 } 587 588 /* Query redirection table. */ 589 static int ena_rss_reta_query(struct rte_eth_dev *dev, 590 struct rte_eth_rss_reta_entry64 *reta_conf, 591 uint16_t reta_size) 592 { 593 struct ena_adapter *adapter = dev->data->dev_private; 594 struct ena_com_dev *ena_dev = &adapter->ena_dev; 595 int rc; 596 int i; 597 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 598 int reta_conf_idx; 599 int reta_idx; 600 601 if (reta_size == 0 || reta_conf == NULL || 602 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 603 return -EINVAL; 604 605 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 606 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 607 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 608 return -ENOTSUP; 609 } 610 611 for (i = 0 ; i < reta_size ; i++) { 612 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 613 reta_idx = i % RTE_RETA_GROUP_SIZE; 614 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 615 reta_conf[reta_conf_idx].reta[reta_idx] = 616 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 617 } 618 619 return 0; 620 } 621 622 static int ena_rss_init_default(struct ena_adapter *adapter) 623 { 624 struct ena_com_dev *ena_dev = &adapter->ena_dev; 625 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 626 int rc, i; 627 u32 val; 628 629 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 630 if (unlikely(rc)) { 631 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 632 goto err_rss_init; 633 } 634 635 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 636 val = i % nb_rx_queues; 637 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 638 ENA_IO_RXQ_IDX(val)); 639 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 640 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 641 goto err_fill_indir; 642 } 643 } 644 645 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 646 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 647 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 648 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 649 goto err_fill_indir; 650 } 651 652 rc = ena_com_set_default_hash_ctrl(ena_dev); 653 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 654 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 655 goto err_fill_indir; 656 } 657 658 rc = ena_com_indirect_table_set(ena_dev); 659 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 660 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 661 goto err_fill_indir; 662 } 663 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 664 adapter->rte_dev->data->port_id); 665 666 return 0; 667 668 err_fill_indir: 669 ena_com_rss_destroy(ena_dev); 670 err_rss_init: 671 672 return rc; 673 } 674 675 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 676 { 677 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 678 int nb_queues = dev->data->nb_rx_queues; 679 int i; 680 681 for (i = 0; i < nb_queues; i++) 682 ena_rx_queue_release(queues[i]); 683 } 684 685 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 686 { 687 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 688 int nb_queues = dev->data->nb_tx_queues; 689 int i; 690 691 for (i = 0; i < nb_queues; i++) 692 ena_tx_queue_release(queues[i]); 693 } 694 695 static void ena_rx_queue_release(void *queue) 696 { 697 struct ena_ring *ring = (struct ena_ring *)queue; 698 699 /* Free ring resources */ 700 if (ring->rx_buffer_info) 701 rte_free(ring->rx_buffer_info); 702 ring->rx_buffer_info = NULL; 703 704 if (ring->rx_refill_buffer) 705 rte_free(ring->rx_refill_buffer); 706 ring->rx_refill_buffer = NULL; 707 708 if (ring->empty_rx_reqs) 709 rte_free(ring->empty_rx_reqs); 710 ring->empty_rx_reqs = NULL; 711 712 ring->configured = 0; 713 714 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 715 ring->port_id, ring->id); 716 } 717 718 static void ena_tx_queue_release(void *queue) 719 { 720 struct ena_ring *ring = (struct ena_ring *)queue; 721 722 /* Free ring resources */ 723 if (ring->push_buf_intermediate_buf) 724 rte_free(ring->push_buf_intermediate_buf); 725 726 if (ring->tx_buffer_info) 727 rte_free(ring->tx_buffer_info); 728 729 if (ring->empty_tx_reqs) 730 rte_free(ring->empty_tx_reqs); 731 732 ring->empty_tx_reqs = NULL; 733 ring->tx_buffer_info = NULL; 734 ring->push_buf_intermediate_buf = NULL; 735 736 ring->configured = 0; 737 738 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 739 ring->port_id, ring->id); 740 } 741 742 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 743 { 744 unsigned int i; 745 746 for (i = 0; i < ring->ring_size; ++i) 747 if (ring->rx_buffer_info[i]) { 748 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 749 ring->rx_buffer_info[i] = NULL; 750 } 751 } 752 753 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 754 { 755 unsigned int i; 756 757 for (i = 0; i < ring->ring_size; ++i) { 758 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 759 760 if (tx_buf->mbuf) 761 rte_pktmbuf_free(tx_buf->mbuf); 762 } 763 } 764 765 static int ena_link_update(struct rte_eth_dev *dev, 766 __rte_unused int wait_to_complete) 767 { 768 struct rte_eth_link *link = &dev->data->dev_link; 769 struct ena_adapter *adapter = dev->data->dev_private; 770 771 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 772 link->link_speed = ETH_SPEED_NUM_NONE; 773 link->link_duplex = ETH_LINK_FULL_DUPLEX; 774 775 return 0; 776 } 777 778 static int ena_queue_start_all(struct rte_eth_dev *dev, 779 enum ena_ring_type ring_type) 780 { 781 struct ena_adapter *adapter = dev->data->dev_private; 782 struct ena_ring *queues = NULL; 783 int nb_queues; 784 int i = 0; 785 int rc = 0; 786 787 if (ring_type == ENA_RING_TYPE_RX) { 788 queues = adapter->rx_ring; 789 nb_queues = dev->data->nb_rx_queues; 790 } else { 791 queues = adapter->tx_ring; 792 nb_queues = dev->data->nb_tx_queues; 793 } 794 for (i = 0; i < nb_queues; i++) { 795 if (queues[i].configured) { 796 if (ring_type == ENA_RING_TYPE_RX) { 797 ena_assert_msg( 798 dev->data->rx_queues[i] == &queues[i], 799 "Inconsistent state of rx queues\n"); 800 } else { 801 ena_assert_msg( 802 dev->data->tx_queues[i] == &queues[i], 803 "Inconsistent state of tx queues\n"); 804 } 805 806 rc = ena_queue_start(&queues[i]); 807 808 if (rc) { 809 PMD_INIT_LOG(ERR, 810 "failed to start queue %d type(%d)", 811 i, ring_type); 812 goto err; 813 } 814 } 815 } 816 817 return 0; 818 819 err: 820 while (i--) 821 if (queues[i].configured) 822 ena_queue_stop(&queues[i]); 823 824 return rc; 825 } 826 827 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 828 { 829 uint32_t max_frame_len = adapter->max_mtu; 830 831 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 832 DEV_RX_OFFLOAD_JUMBO_FRAME) 833 max_frame_len = 834 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 835 836 return max_frame_len; 837 } 838 839 static int ena_check_valid_conf(struct ena_adapter *adapter) 840 { 841 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 842 843 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 844 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 845 "max mtu: %d, min mtu: %d", 846 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 847 return ENA_COM_UNSUPPORTED; 848 } 849 850 return 0; 851 } 852 853 static int 854 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, 855 bool use_large_llq_hdr) 856 { 857 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 858 struct ena_com_dev *ena_dev = ctx->ena_dev; 859 uint32_t max_tx_queue_size; 860 uint32_t max_rx_queue_size; 861 862 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 863 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 864 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 865 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth, 866 max_queue_ext->max_rx_sq_depth); 867 max_tx_queue_size = max_queue_ext->max_tx_cq_depth; 868 869 if (ena_dev->tx_mem_queue_type == 870 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 871 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 872 llq->max_llq_depth); 873 } else { 874 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 875 max_queue_ext->max_tx_sq_depth); 876 } 877 878 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 879 max_queue_ext->max_per_packet_rx_descs); 880 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 881 max_queue_ext->max_per_packet_tx_descs); 882 } else { 883 struct ena_admin_queue_feature_desc *max_queues = 884 &ctx->get_feat_ctx->max_queues; 885 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth, 886 max_queues->max_sq_depth); 887 max_tx_queue_size = max_queues->max_cq_depth; 888 889 if (ena_dev->tx_mem_queue_type == 890 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 891 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 892 llq->max_llq_depth); 893 } else { 894 max_tx_queue_size = RTE_MIN(max_tx_queue_size, 895 max_queues->max_sq_depth); 896 } 897 898 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 899 max_queues->max_packet_rx_descs); 900 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 901 max_queues->max_packet_tx_descs); 902 } 903 904 /* Round down to the nearest power of 2 */ 905 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); 906 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); 907 908 if (use_large_llq_hdr) { 909 if ((llq->entry_size_ctrl_supported & 910 ENA_ADMIN_LIST_ENTRY_SIZE_256B) && 911 (ena_dev->tx_mem_queue_type == 912 ENA_ADMIN_PLACEMENT_POLICY_DEV)) { 913 max_tx_queue_size /= 2; 914 PMD_INIT_LOG(INFO, 915 "Forcing large headers and decreasing maximum TX queue size to %d\n", 916 max_tx_queue_size); 917 } else { 918 PMD_INIT_LOG(ERR, 919 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); 920 } 921 } 922 923 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) { 924 PMD_INIT_LOG(ERR, "Invalid queue size"); 925 return -EFAULT; 926 } 927 928 ctx->max_tx_queue_size = max_tx_queue_size; 929 ctx->max_rx_queue_size = max_rx_queue_size; 930 931 return 0; 932 } 933 934 static void ena_stats_restart(struct rte_eth_dev *dev) 935 { 936 struct ena_adapter *adapter = dev->data->dev_private; 937 938 rte_atomic64_init(&adapter->drv_stats->ierrors); 939 rte_atomic64_init(&adapter->drv_stats->oerrors); 940 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 941 rte_atomic64_init(&adapter->drv_stats->rx_drops); 942 } 943 944 static int ena_stats_get(struct rte_eth_dev *dev, 945 struct rte_eth_stats *stats) 946 { 947 struct ena_admin_basic_stats ena_stats; 948 struct ena_adapter *adapter = dev->data->dev_private; 949 struct ena_com_dev *ena_dev = &adapter->ena_dev; 950 int rc; 951 int i; 952 int max_rings_stats; 953 954 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 955 return -ENOTSUP; 956 957 memset(&ena_stats, 0, sizeof(ena_stats)); 958 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 959 if (unlikely(rc)) { 960 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 961 return rc; 962 } 963 964 /* Set of basic statistics from ENA */ 965 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 966 ena_stats.rx_pkts_low); 967 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 968 ena_stats.tx_pkts_low); 969 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 970 ena_stats.rx_bytes_low); 971 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 972 ena_stats.tx_bytes_low); 973 974 /* Driver related stats */ 975 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 976 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 977 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 978 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 979 980 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 981 RTE_ETHDEV_QUEUE_STAT_CNTRS); 982 for (i = 0; i < max_rings_stats; ++i) { 983 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 984 985 stats->q_ibytes[i] = rx_stats->bytes; 986 stats->q_ipackets[i] = rx_stats->cnt; 987 stats->q_errors[i] = rx_stats->bad_desc_num + 988 rx_stats->bad_req_id; 989 } 990 991 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 992 RTE_ETHDEV_QUEUE_STAT_CNTRS); 993 for (i = 0; i < max_rings_stats; ++i) { 994 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 995 996 stats->q_obytes[i] = tx_stats->bytes; 997 stats->q_opackets[i] = tx_stats->cnt; 998 } 999 1000 return 0; 1001 } 1002 1003 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1004 { 1005 struct ena_adapter *adapter; 1006 struct ena_com_dev *ena_dev; 1007 int rc = 0; 1008 1009 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1010 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1011 adapter = dev->data->dev_private; 1012 1013 ena_dev = &adapter->ena_dev; 1014 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1015 1016 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 1017 PMD_DRV_LOG(ERR, 1018 "Invalid MTU setting. new_mtu: %d " 1019 "max mtu: %d min mtu: %d\n", 1020 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 1021 return -EINVAL; 1022 } 1023 1024 rc = ena_com_set_dev_mtu(ena_dev, mtu); 1025 if (rc) 1026 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 1027 else 1028 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 1029 1030 return rc; 1031 } 1032 1033 static int ena_start(struct rte_eth_dev *dev) 1034 { 1035 struct ena_adapter *adapter = dev->data->dev_private; 1036 uint64_t ticks; 1037 int rc = 0; 1038 1039 rc = ena_check_valid_conf(adapter); 1040 if (rc) 1041 return rc; 1042 1043 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1044 if (rc) 1045 return rc; 1046 1047 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1048 if (rc) 1049 goto err_start_tx; 1050 1051 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1052 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1053 rc = ena_rss_init_default(adapter); 1054 if (rc) 1055 goto err_rss_init; 1056 } 1057 1058 ena_stats_restart(dev); 1059 1060 adapter->timestamp_wd = rte_get_timer_cycles(); 1061 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1062 1063 ticks = rte_get_timer_hz(); 1064 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1065 ena_timer_wd_callback, adapter); 1066 1067 ++adapter->dev_stats.dev_start; 1068 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1069 1070 return 0; 1071 1072 err_rss_init: 1073 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1074 err_start_tx: 1075 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1076 return rc; 1077 } 1078 1079 static void ena_stop(struct rte_eth_dev *dev) 1080 { 1081 struct ena_adapter *adapter = dev->data->dev_private; 1082 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1083 int rc; 1084 1085 rte_timer_stop_sync(&adapter->timer_wd); 1086 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1087 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1088 1089 if (adapter->trigger_reset) { 1090 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1091 if (rc) 1092 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1093 } 1094 1095 ++adapter->dev_stats.dev_stop; 1096 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1097 } 1098 1099 static int ena_create_io_queue(struct ena_ring *ring) 1100 { 1101 struct ena_adapter *adapter; 1102 struct ena_com_dev *ena_dev; 1103 struct ena_com_create_io_ctx ctx = 1104 /* policy set to _HOST just to satisfy icc compiler */ 1105 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1106 0, 0, 0, 0, 0 }; 1107 uint16_t ena_qid; 1108 unsigned int i; 1109 int rc; 1110 1111 adapter = ring->adapter; 1112 ena_dev = &adapter->ena_dev; 1113 1114 if (ring->type == ENA_RING_TYPE_TX) { 1115 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1116 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1117 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1118 for (i = 0; i < ring->ring_size; i++) 1119 ring->empty_tx_reqs[i] = i; 1120 } else { 1121 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1122 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1123 for (i = 0; i < ring->ring_size; i++) 1124 ring->empty_rx_reqs[i] = i; 1125 } 1126 ctx.queue_size = ring->ring_size; 1127 ctx.qid = ena_qid; 1128 ctx.msix_vector = -1; /* interrupts not used */ 1129 ctx.numa_node = ring->numa_socket_id; 1130 1131 rc = ena_com_create_io_queue(ena_dev, &ctx); 1132 if (rc) { 1133 PMD_DRV_LOG(ERR, 1134 "failed to create io queue #%d (qid:%d) rc: %d\n", 1135 ring->id, ena_qid, rc); 1136 return rc; 1137 } 1138 1139 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1140 &ring->ena_com_io_sq, 1141 &ring->ena_com_io_cq); 1142 if (rc) { 1143 PMD_DRV_LOG(ERR, 1144 "Failed to get io queue handlers. queue num %d rc: %d\n", 1145 ring->id, rc); 1146 ena_com_destroy_io_queue(ena_dev, ena_qid); 1147 return rc; 1148 } 1149 1150 if (ring->type == ENA_RING_TYPE_TX) 1151 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1152 1153 return 0; 1154 } 1155 1156 static void ena_queue_stop(struct ena_ring *ring) 1157 { 1158 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1159 1160 if (ring->type == ENA_RING_TYPE_RX) { 1161 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1162 ena_rx_queue_release_bufs(ring); 1163 } else { 1164 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1165 ena_tx_queue_release_bufs(ring); 1166 } 1167 } 1168 1169 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1170 enum ena_ring_type ring_type) 1171 { 1172 struct ena_adapter *adapter = dev->data->dev_private; 1173 struct ena_ring *queues = NULL; 1174 uint16_t nb_queues, i; 1175 1176 if (ring_type == ENA_RING_TYPE_RX) { 1177 queues = adapter->rx_ring; 1178 nb_queues = dev->data->nb_rx_queues; 1179 } else { 1180 queues = adapter->tx_ring; 1181 nb_queues = dev->data->nb_tx_queues; 1182 } 1183 1184 for (i = 0; i < nb_queues; ++i) 1185 if (queues[i].configured) 1186 ena_queue_stop(&queues[i]); 1187 } 1188 1189 static int ena_queue_start(struct ena_ring *ring) 1190 { 1191 int rc, bufs_num; 1192 1193 ena_assert_msg(ring->configured == 1, 1194 "Trying to start unconfigured queue\n"); 1195 1196 rc = ena_create_io_queue(ring); 1197 if (rc) { 1198 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1199 return rc; 1200 } 1201 1202 ring->next_to_clean = 0; 1203 ring->next_to_use = 0; 1204 1205 if (ring->type == ENA_RING_TYPE_TX) { 1206 ring->tx_stats.available_desc = 1207 ena_com_free_q_entries(ring->ena_com_io_sq); 1208 return 0; 1209 } 1210 1211 bufs_num = ring->ring_size - 1; 1212 rc = ena_populate_rx_queue(ring, bufs_num); 1213 if (rc != bufs_num) { 1214 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1215 ENA_IO_RXQ_IDX(ring->id)); 1216 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1217 return ENA_COM_FAULT; 1218 } 1219 1220 return 0; 1221 } 1222 1223 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1224 uint16_t queue_idx, 1225 uint16_t nb_desc, 1226 unsigned int socket_id, 1227 const struct rte_eth_txconf *tx_conf) 1228 { 1229 struct ena_ring *txq = NULL; 1230 struct ena_adapter *adapter = dev->data->dev_private; 1231 unsigned int i; 1232 1233 txq = &adapter->tx_ring[queue_idx]; 1234 1235 if (txq->configured) { 1236 PMD_DRV_LOG(CRIT, 1237 "API violation. Queue %d is already configured\n", 1238 queue_idx); 1239 return ENA_COM_FAULT; 1240 } 1241 1242 if (!rte_is_power_of_2(nb_desc)) { 1243 PMD_DRV_LOG(ERR, 1244 "Unsupported size of TX queue: %d is not a power of 2.\n", 1245 nb_desc); 1246 return -EINVAL; 1247 } 1248 1249 if (nb_desc > adapter->max_tx_ring_size) { 1250 PMD_DRV_LOG(ERR, 1251 "Unsupported size of TX queue (max size: %d)\n", 1252 adapter->max_tx_ring_size); 1253 return -EINVAL; 1254 } 1255 1256 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1257 nb_desc = adapter->max_tx_ring_size; 1258 1259 txq->port_id = dev->data->port_id; 1260 txq->next_to_clean = 0; 1261 txq->next_to_use = 0; 1262 txq->ring_size = nb_desc; 1263 txq->numa_socket_id = socket_id; 1264 1265 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1266 sizeof(struct ena_tx_buffer) * 1267 txq->ring_size, 1268 RTE_CACHE_LINE_SIZE); 1269 if (!txq->tx_buffer_info) { 1270 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1271 return -ENOMEM; 1272 } 1273 1274 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1275 sizeof(u16) * txq->ring_size, 1276 RTE_CACHE_LINE_SIZE); 1277 if (!txq->empty_tx_reqs) { 1278 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1279 rte_free(txq->tx_buffer_info); 1280 return -ENOMEM; 1281 } 1282 1283 txq->push_buf_intermediate_buf = 1284 rte_zmalloc("txq->push_buf_intermediate_buf", 1285 txq->tx_max_header_size, 1286 RTE_CACHE_LINE_SIZE); 1287 if (!txq->push_buf_intermediate_buf) { 1288 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1289 rte_free(txq->tx_buffer_info); 1290 rte_free(txq->empty_tx_reqs); 1291 return -ENOMEM; 1292 } 1293 1294 for (i = 0; i < txq->ring_size; i++) 1295 txq->empty_tx_reqs[i] = i; 1296 1297 if (tx_conf != NULL) { 1298 txq->offloads = 1299 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1300 } 1301 /* Store pointer to this queue in upper layer */ 1302 txq->configured = 1; 1303 dev->data->tx_queues[queue_idx] = txq; 1304 1305 return 0; 1306 } 1307 1308 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1309 uint16_t queue_idx, 1310 uint16_t nb_desc, 1311 unsigned int socket_id, 1312 __rte_unused const struct rte_eth_rxconf *rx_conf, 1313 struct rte_mempool *mp) 1314 { 1315 struct ena_adapter *adapter = dev->data->dev_private; 1316 struct ena_ring *rxq = NULL; 1317 size_t buffer_size; 1318 int i; 1319 1320 rxq = &adapter->rx_ring[queue_idx]; 1321 if (rxq->configured) { 1322 PMD_DRV_LOG(CRIT, 1323 "API violation. Queue %d is already configured\n", 1324 queue_idx); 1325 return ENA_COM_FAULT; 1326 } 1327 1328 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1329 nb_desc = adapter->max_rx_ring_size; 1330 1331 if (!rte_is_power_of_2(nb_desc)) { 1332 PMD_DRV_LOG(ERR, 1333 "Unsupported size of RX queue: %d is not a power of 2.\n", 1334 nb_desc); 1335 return -EINVAL; 1336 } 1337 1338 if (nb_desc > adapter->max_rx_ring_size) { 1339 PMD_DRV_LOG(ERR, 1340 "Unsupported size of RX queue (max size: %d)\n", 1341 adapter->max_rx_ring_size); 1342 return -EINVAL; 1343 } 1344 1345 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1346 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1347 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1348 PMD_DRV_LOG(ERR, 1349 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1350 buffer_size, ENA_RX_BUF_MIN_SIZE); 1351 return -EINVAL; 1352 } 1353 1354 rxq->port_id = dev->data->port_id; 1355 rxq->next_to_clean = 0; 1356 rxq->next_to_use = 0; 1357 rxq->ring_size = nb_desc; 1358 rxq->numa_socket_id = socket_id; 1359 rxq->mb_pool = mp; 1360 1361 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1362 sizeof(struct rte_mbuf *) * nb_desc, 1363 RTE_CACHE_LINE_SIZE); 1364 if (!rxq->rx_buffer_info) { 1365 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1366 return -ENOMEM; 1367 } 1368 1369 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1370 sizeof(struct rte_mbuf *) * nb_desc, 1371 RTE_CACHE_LINE_SIZE); 1372 1373 if (!rxq->rx_refill_buffer) { 1374 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1375 rte_free(rxq->rx_buffer_info); 1376 rxq->rx_buffer_info = NULL; 1377 return -ENOMEM; 1378 } 1379 1380 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1381 sizeof(uint16_t) * nb_desc, 1382 RTE_CACHE_LINE_SIZE); 1383 if (!rxq->empty_rx_reqs) { 1384 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1385 rte_free(rxq->rx_buffer_info); 1386 rxq->rx_buffer_info = NULL; 1387 rte_free(rxq->rx_refill_buffer); 1388 rxq->rx_refill_buffer = NULL; 1389 return -ENOMEM; 1390 } 1391 1392 for (i = 0; i < nb_desc; i++) 1393 rxq->empty_rx_reqs[i] = i; 1394 1395 /* Store pointer to this queue in upper layer */ 1396 rxq->configured = 1; 1397 dev->data->rx_queues[queue_idx] = rxq; 1398 1399 return 0; 1400 } 1401 1402 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1403 { 1404 unsigned int i; 1405 int rc; 1406 uint16_t ring_size = rxq->ring_size; 1407 uint16_t ring_mask = ring_size - 1; 1408 uint16_t next_to_use = rxq->next_to_use; 1409 uint16_t in_use, req_id; 1410 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1411 1412 if (unlikely(!count)) 1413 return 0; 1414 1415 in_use = rxq->next_to_use - rxq->next_to_clean; 1416 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1417 1418 /* get resources for incoming packets */ 1419 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1420 if (unlikely(rc < 0)) { 1421 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1422 ++rxq->rx_stats.mbuf_alloc_fail; 1423 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1424 return 0; 1425 } 1426 1427 for (i = 0; i < count; i++) { 1428 uint16_t next_to_use_masked = next_to_use & ring_mask; 1429 struct rte_mbuf *mbuf = mbufs[i]; 1430 struct ena_com_buf ebuf; 1431 1432 if (likely((i + 4) < count)) 1433 rte_prefetch0(mbufs[i + 4]); 1434 1435 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1436 rc = validate_rx_req_id(rxq, req_id); 1437 if (unlikely(rc < 0)) 1438 break; 1439 rxq->rx_buffer_info[req_id] = mbuf; 1440 1441 /* prepare physical address for DMA transaction */ 1442 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1443 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1444 /* pass resource to device */ 1445 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1446 &ebuf, req_id); 1447 if (unlikely(rc)) { 1448 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1449 rxq->rx_buffer_info[req_id] = NULL; 1450 break; 1451 } 1452 next_to_use++; 1453 } 1454 1455 if (unlikely(i < count)) { 1456 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1457 "buffers (from %d)\n", rxq->id, i, count); 1458 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1459 count - i); 1460 ++rxq->rx_stats.refill_partial; 1461 } 1462 1463 /* When we submitted free recources to device... */ 1464 if (likely(i > 0)) { 1465 /* ...let HW know that it can fill buffers with data. */ 1466 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1467 1468 rxq->next_to_use = next_to_use; 1469 } 1470 1471 return i; 1472 } 1473 1474 static int ena_device_init(struct ena_com_dev *ena_dev, 1475 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1476 bool *wd_state) 1477 { 1478 uint32_t aenq_groups; 1479 int rc; 1480 bool readless_supported; 1481 1482 /* Initialize mmio registers */ 1483 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1484 if (rc) { 1485 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1486 return rc; 1487 } 1488 1489 /* The PCIe configuration space revision id indicate if mmio reg 1490 * read is disabled. 1491 */ 1492 readless_supported = 1493 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1494 & ENA_MMIO_DISABLE_REG_READ); 1495 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1496 1497 /* reset device */ 1498 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1499 if (rc) { 1500 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1501 goto err_mmio_read_less; 1502 } 1503 1504 /* check FW version */ 1505 rc = ena_com_validate_version(ena_dev); 1506 if (rc) { 1507 PMD_DRV_LOG(ERR, "device version is too low\n"); 1508 goto err_mmio_read_less; 1509 } 1510 1511 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1512 1513 /* ENA device administration layer init */ 1514 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1515 if (rc) { 1516 PMD_DRV_LOG(ERR, 1517 "cannot initialize ena admin queue with device\n"); 1518 goto err_mmio_read_less; 1519 } 1520 1521 /* To enable the msix interrupts the driver needs to know the number 1522 * of queues. So the driver uses polling mode to retrieve this 1523 * information. 1524 */ 1525 ena_com_set_admin_polling_mode(ena_dev, true); 1526 1527 ena_config_host_info(ena_dev); 1528 1529 /* Get Device Attributes and features */ 1530 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1531 if (rc) { 1532 PMD_DRV_LOG(ERR, 1533 "cannot get attribute for ena device rc= %d\n", rc); 1534 goto err_admin_init; 1535 } 1536 1537 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1538 BIT(ENA_ADMIN_NOTIFICATION) | 1539 BIT(ENA_ADMIN_KEEP_ALIVE) | 1540 BIT(ENA_ADMIN_FATAL_ERROR) | 1541 BIT(ENA_ADMIN_WARNING); 1542 1543 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1544 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1545 if (rc) { 1546 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1547 goto err_admin_init; 1548 } 1549 1550 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1551 1552 return 0; 1553 1554 err_admin_init: 1555 ena_com_admin_destroy(ena_dev); 1556 1557 err_mmio_read_less: 1558 ena_com_mmio_reg_read_request_destroy(ena_dev); 1559 1560 return rc; 1561 } 1562 1563 static void ena_interrupt_handler_rte(void *cb_arg) 1564 { 1565 struct ena_adapter *adapter = cb_arg; 1566 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1567 1568 ena_com_admin_q_comp_intr_handler(ena_dev); 1569 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1570 ena_com_aenq_intr_handler(ena_dev, adapter); 1571 } 1572 1573 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1574 { 1575 if (!adapter->wd_state) 1576 return; 1577 1578 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1579 return; 1580 1581 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1582 adapter->keep_alive_timeout)) { 1583 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1584 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1585 adapter->trigger_reset = true; 1586 ++adapter->dev_stats.wd_expired; 1587 } 1588 } 1589 1590 /* Check if admin queue is enabled */ 1591 static void check_for_admin_com_state(struct ena_adapter *adapter) 1592 { 1593 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1594 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1595 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1596 adapter->trigger_reset = true; 1597 } 1598 } 1599 1600 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1601 void *arg) 1602 { 1603 struct ena_adapter *adapter = arg; 1604 struct rte_eth_dev *dev = adapter->rte_dev; 1605 1606 check_for_missing_keep_alive(adapter); 1607 check_for_admin_com_state(adapter); 1608 1609 if (unlikely(adapter->trigger_reset)) { 1610 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1611 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1612 NULL); 1613 } 1614 } 1615 1616 static inline void 1617 set_default_llq_configurations(struct ena_llq_configurations *llq_config, 1618 struct ena_admin_feature_llq_desc *llq, 1619 bool use_large_llq_hdr) 1620 { 1621 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1622 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1623 llq_config->llq_num_decs_before_header = 1624 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1625 1626 if (use_large_llq_hdr && 1627 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) { 1628 llq_config->llq_ring_entry_size = 1629 ENA_ADMIN_LIST_ENTRY_SIZE_256B; 1630 llq_config->llq_ring_entry_size_value = 256; 1631 } else { 1632 llq_config->llq_ring_entry_size = 1633 ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1634 llq_config->llq_ring_entry_size_value = 128; 1635 } 1636 } 1637 1638 static int 1639 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1640 struct ena_com_dev *ena_dev, 1641 struct ena_admin_feature_llq_desc *llq, 1642 struct ena_llq_configurations *llq_default_configurations) 1643 { 1644 int rc; 1645 u32 llq_feature_mask; 1646 1647 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1648 if (!(ena_dev->supported_features & llq_feature_mask)) { 1649 PMD_DRV_LOG(INFO, 1650 "LLQ is not supported. Fallback to host mode policy.\n"); 1651 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1652 return 0; 1653 } 1654 1655 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1656 if (unlikely(rc)) { 1657 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1658 "Fallback to host mode policy."); 1659 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1660 return 0; 1661 } 1662 1663 /* Nothing to config, exit */ 1664 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1665 return 0; 1666 1667 if (!adapter->dev_mem_base) { 1668 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1669 "Fallback to host mode policy.\n."); 1670 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1671 return 0; 1672 } 1673 1674 ena_dev->mem_bar = adapter->dev_mem_base; 1675 1676 return 0; 1677 } 1678 1679 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, 1680 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1681 { 1682 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues; 1683 1684 /* Regular queues capabilities */ 1685 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1686 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1687 &get_feat_ctx->max_queue_ext.max_queue_ext; 1688 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1689 max_queue_ext->max_rx_cq_num); 1690 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1691 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1692 } else { 1693 struct ena_admin_queue_feature_desc *max_queues = 1694 &get_feat_ctx->max_queues; 1695 io_tx_sq_num = max_queues->max_sq_num; 1696 io_tx_cq_num = max_queues->max_cq_num; 1697 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1698 } 1699 1700 /* In case of LLQ use the llq number in the get feature cmd */ 1701 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1702 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1703 1704 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1705 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num); 1706 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num); 1707 1708 if (unlikely(max_num_io_queues == 0)) { 1709 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1710 return -EFAULT; 1711 } 1712 1713 return max_num_io_queues; 1714 } 1715 1716 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1717 { 1718 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1719 struct rte_pci_device *pci_dev; 1720 struct rte_intr_handle *intr_handle; 1721 struct ena_adapter *adapter = eth_dev->data->dev_private; 1722 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1723 struct ena_com_dev_get_features_ctx get_feat_ctx; 1724 struct ena_llq_configurations llq_config; 1725 const char *queue_type_str; 1726 uint32_t max_num_io_queues; 1727 int rc; 1728 1729 static int adapters_found; 1730 bool wd_state; 1731 1732 eth_dev->dev_ops = &ena_dev_ops; 1733 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1734 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1735 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1736 1737 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1738 return 0; 1739 1740 memset(adapter, 0, sizeof(struct ena_adapter)); 1741 ena_dev = &adapter->ena_dev; 1742 1743 adapter->rte_eth_dev_data = eth_dev->data; 1744 adapter->rte_dev = eth_dev; 1745 1746 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1747 adapter->pdev = pci_dev; 1748 1749 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1750 pci_dev->addr.domain, 1751 pci_dev->addr.bus, 1752 pci_dev->addr.devid, 1753 pci_dev->addr.function); 1754 1755 intr_handle = &pci_dev->intr_handle; 1756 1757 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1758 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1759 1760 if (!adapter->regs) { 1761 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1762 ENA_REGS_BAR); 1763 return -ENXIO; 1764 } 1765 1766 ena_dev->reg_bar = adapter->regs; 1767 ena_dev->dmadev = adapter->pdev; 1768 1769 adapter->id_number = adapters_found; 1770 1771 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1772 adapter->id_number); 1773 1774 rc = ena_parse_devargs(adapter, pci_dev->device.devargs); 1775 if (rc != 0) { 1776 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); 1777 goto err; 1778 } 1779 1780 /* device specific initialization routine */ 1781 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1782 if (rc) { 1783 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1784 goto err; 1785 } 1786 adapter->wd_state = wd_state; 1787 1788 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, 1789 adapter->use_large_llq_hdr); 1790 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1791 &get_feat_ctx.llq, &llq_config); 1792 if (unlikely(rc)) { 1793 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1794 return rc; 1795 } 1796 1797 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1798 queue_type_str = "Regular"; 1799 else 1800 queue_type_str = "Low latency"; 1801 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1802 1803 calc_queue_ctx.ena_dev = ena_dev; 1804 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1805 1806 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); 1807 rc = ena_calc_io_queue_size(&calc_queue_ctx, 1808 adapter->use_large_llq_hdr); 1809 if (unlikely((rc != 0) || (max_num_io_queues == 0))) { 1810 rc = -EFAULT; 1811 goto err_device_destroy; 1812 } 1813 1814 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size; 1815 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size; 1816 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1817 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1818 adapter->max_num_io_queues = max_num_io_queues; 1819 1820 /* prepare ring structures */ 1821 ena_init_rings(adapter); 1822 1823 ena_config_debug_area(adapter); 1824 1825 /* Set max MTU for this device */ 1826 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1827 1828 /* set device support for offloads */ 1829 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1830 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1831 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1832 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1833 adapter->offloads.rx_csum_supported = 1834 (get_feat_ctx.offload.rx_supported & 1835 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1836 1837 /* Copy MAC address and point DPDK to it */ 1838 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1839 rte_ether_addr_copy((struct rte_ether_addr *) 1840 get_feat_ctx.dev_attr.mac_addr, 1841 (struct rte_ether_addr *)adapter->mac_addr); 1842 1843 /* 1844 * Pass the information to the rte_eth_dev_close() that it should also 1845 * release the private port resources. 1846 */ 1847 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1848 1849 adapter->drv_stats = rte_zmalloc("adapter stats", 1850 sizeof(*adapter->drv_stats), 1851 RTE_CACHE_LINE_SIZE); 1852 if (!adapter->drv_stats) { 1853 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1854 rc = -ENOMEM; 1855 goto err_delete_debug_area; 1856 } 1857 1858 rte_intr_callback_register(intr_handle, 1859 ena_interrupt_handler_rte, 1860 adapter); 1861 rte_intr_enable(intr_handle); 1862 ena_com_set_admin_polling_mode(ena_dev, false); 1863 ena_com_admin_aenq_enable(ena_dev); 1864 1865 if (adapters_found == 0) 1866 rte_timer_subsystem_init(); 1867 rte_timer_init(&adapter->timer_wd); 1868 1869 adapters_found++; 1870 adapter->state = ENA_ADAPTER_STATE_INIT; 1871 1872 return 0; 1873 1874 err_delete_debug_area: 1875 ena_com_delete_debug_area(ena_dev); 1876 1877 err_device_destroy: 1878 ena_com_delete_host_info(ena_dev); 1879 ena_com_admin_destroy(ena_dev); 1880 1881 err: 1882 return rc; 1883 } 1884 1885 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1886 { 1887 struct ena_adapter *adapter = eth_dev->data->dev_private; 1888 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1889 1890 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1891 return; 1892 1893 ena_com_set_admin_running_state(ena_dev, false); 1894 1895 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1896 ena_close(eth_dev); 1897 1898 ena_com_delete_debug_area(ena_dev); 1899 ena_com_delete_host_info(ena_dev); 1900 1901 ena_com_abort_admin_commands(ena_dev); 1902 ena_com_wait_for_abort_completion(ena_dev); 1903 ena_com_admin_destroy(ena_dev); 1904 ena_com_mmio_reg_read_request_destroy(ena_dev); 1905 1906 adapter->state = ENA_ADAPTER_STATE_FREE; 1907 } 1908 1909 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1910 { 1911 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1912 return 0; 1913 1914 ena_destroy_device(eth_dev); 1915 1916 eth_dev->dev_ops = NULL; 1917 eth_dev->rx_pkt_burst = NULL; 1918 eth_dev->tx_pkt_burst = NULL; 1919 eth_dev->tx_pkt_prepare = NULL; 1920 1921 return 0; 1922 } 1923 1924 static int ena_dev_configure(struct rte_eth_dev *dev) 1925 { 1926 struct ena_adapter *adapter = dev->data->dev_private; 1927 1928 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1929 1930 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1931 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1932 return 0; 1933 } 1934 1935 static void ena_init_rings(struct ena_adapter *adapter) 1936 { 1937 size_t i; 1938 1939 for (i = 0; i < adapter->max_num_io_queues; i++) { 1940 struct ena_ring *ring = &adapter->tx_ring[i]; 1941 1942 ring->configured = 0; 1943 ring->type = ENA_RING_TYPE_TX; 1944 ring->adapter = adapter; 1945 ring->id = i; 1946 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1947 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1948 ring->sgl_size = adapter->max_tx_sgl_size; 1949 } 1950 1951 for (i = 0; i < adapter->max_num_io_queues; i++) { 1952 struct ena_ring *ring = &adapter->rx_ring[i]; 1953 1954 ring->configured = 0; 1955 ring->type = ENA_RING_TYPE_RX; 1956 ring->adapter = adapter; 1957 ring->id = i; 1958 ring->sgl_size = adapter->max_rx_sgl_size; 1959 } 1960 } 1961 1962 static int ena_infos_get(struct rte_eth_dev *dev, 1963 struct rte_eth_dev_info *dev_info) 1964 { 1965 struct ena_adapter *adapter; 1966 struct ena_com_dev *ena_dev; 1967 uint64_t rx_feat = 0, tx_feat = 0; 1968 1969 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1970 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1971 adapter = dev->data->dev_private; 1972 1973 ena_dev = &adapter->ena_dev; 1974 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1975 1976 dev_info->speed_capa = 1977 ETH_LINK_SPEED_1G | 1978 ETH_LINK_SPEED_2_5G | 1979 ETH_LINK_SPEED_5G | 1980 ETH_LINK_SPEED_10G | 1981 ETH_LINK_SPEED_25G | 1982 ETH_LINK_SPEED_40G | 1983 ETH_LINK_SPEED_50G | 1984 ETH_LINK_SPEED_100G; 1985 1986 /* Set Tx & Rx features available for device */ 1987 if (adapter->offloads.tso4_supported) 1988 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1989 1990 if (adapter->offloads.tx_csum_supported) 1991 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1992 DEV_TX_OFFLOAD_UDP_CKSUM | 1993 DEV_TX_OFFLOAD_TCP_CKSUM; 1994 1995 if (adapter->offloads.rx_csum_supported) 1996 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1997 DEV_RX_OFFLOAD_UDP_CKSUM | 1998 DEV_RX_OFFLOAD_TCP_CKSUM; 1999 2000 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2001 2002 /* Inform framework about available features */ 2003 dev_info->rx_offload_capa = rx_feat; 2004 dev_info->rx_queue_offload_capa = rx_feat; 2005 dev_info->tx_offload_capa = tx_feat; 2006 dev_info->tx_queue_offload_capa = tx_feat; 2007 2008 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 2009 ETH_RSS_UDP; 2010 2011 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 2012 dev_info->max_rx_pktlen = adapter->max_mtu; 2013 dev_info->max_mac_addrs = 1; 2014 2015 dev_info->max_rx_queues = adapter->max_num_io_queues; 2016 dev_info->max_tx_queues = adapter->max_num_io_queues; 2017 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 2018 2019 adapter->tx_supported_offloads = tx_feat; 2020 adapter->rx_supported_offloads = rx_feat; 2021 2022 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size; 2023 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2024 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2025 adapter->max_rx_sgl_size); 2026 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2027 adapter->max_rx_sgl_size); 2028 2029 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size; 2030 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 2031 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2032 adapter->max_tx_sgl_size); 2033 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 2034 adapter->max_tx_sgl_size); 2035 2036 return 0; 2037 } 2038 2039 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 2040 uint16_t nb_pkts) 2041 { 2042 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 2043 unsigned int ring_size = rx_ring->ring_size; 2044 unsigned int ring_mask = ring_size - 1; 2045 uint16_t next_to_clean = rx_ring->next_to_clean; 2046 uint16_t desc_in_use = 0; 2047 uint16_t req_id; 2048 unsigned int recv_idx = 0; 2049 struct rte_mbuf *mbuf = NULL; 2050 struct rte_mbuf *mbuf_head = NULL; 2051 struct rte_mbuf *mbuf_prev = NULL; 2052 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2053 unsigned int completed; 2054 2055 struct ena_com_rx_ctx ena_rx_ctx; 2056 int rc = 0; 2057 2058 /* Check adapter state */ 2059 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2060 PMD_DRV_LOG(ALERT, 2061 "Trying to receive pkts while device is NOT running\n"); 2062 return 0; 2063 } 2064 2065 desc_in_use = rx_ring->next_to_use - next_to_clean; 2066 if (unlikely(nb_pkts > desc_in_use)) 2067 nb_pkts = desc_in_use; 2068 2069 for (completed = 0; completed < nb_pkts; completed++) { 2070 int segments = 0; 2071 2072 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2073 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2074 ena_rx_ctx.descs = 0; 2075 ena_rx_ctx.pkt_offset = 0; 2076 /* receive packet context */ 2077 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2078 rx_ring->ena_com_io_sq, 2079 &ena_rx_ctx); 2080 if (unlikely(rc)) { 2081 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2082 rx_ring->adapter->reset_reason = 2083 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2084 rx_ring->adapter->trigger_reset = true; 2085 ++rx_ring->rx_stats.bad_desc_num; 2086 return 0; 2087 } 2088 2089 if (unlikely(ena_rx_ctx.descs == 0)) 2090 break; 2091 2092 while (segments < ena_rx_ctx.descs) { 2093 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2094 rc = validate_rx_req_id(rx_ring, req_id); 2095 if (unlikely(rc)) { 2096 if (segments != 0) 2097 rte_mbuf_raw_free(mbuf_head); 2098 break; 2099 } 2100 2101 mbuf = rx_buff_info[req_id]; 2102 rx_buff_info[req_id] = NULL; 2103 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2104 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2105 mbuf->refcnt = 1; 2106 mbuf->next = NULL; 2107 if (unlikely(segments == 0)) { 2108 mbuf->nb_segs = ena_rx_ctx.descs; 2109 mbuf->port = rx_ring->port_id; 2110 mbuf->pkt_len = 0; 2111 mbuf->data_off += ena_rx_ctx.pkt_offset; 2112 mbuf_head = mbuf; 2113 } else { 2114 /* for multi-segment pkts create mbuf chain */ 2115 mbuf_prev->next = mbuf; 2116 } 2117 mbuf_head->pkt_len += mbuf->data_len; 2118 2119 mbuf_prev = mbuf; 2120 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2121 req_id; 2122 segments++; 2123 next_to_clean++; 2124 } 2125 if (unlikely(rc)) 2126 break; 2127 2128 /* fill mbuf attributes if any */ 2129 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2130 2131 if (unlikely(mbuf_head->ol_flags & 2132 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2133 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2134 ++rx_ring->rx_stats.bad_csum; 2135 } 2136 2137 mbuf_head->hash.rss = ena_rx_ctx.hash; 2138 2139 /* pass to DPDK application head mbuf */ 2140 rx_pkts[recv_idx] = mbuf_head; 2141 recv_idx++; 2142 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2143 } 2144 2145 rx_ring->rx_stats.cnt += recv_idx; 2146 rx_ring->next_to_clean = next_to_clean; 2147 2148 desc_in_use = desc_in_use - completed + 1; 2149 /* Burst refill to save doorbells, memory barriers, const interval */ 2150 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2151 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2152 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2153 } 2154 2155 return recv_idx; 2156 } 2157 2158 static uint16_t 2159 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2160 uint16_t nb_pkts) 2161 { 2162 int32_t ret; 2163 uint32_t i; 2164 struct rte_mbuf *m; 2165 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2166 struct rte_ipv4_hdr *ip_hdr; 2167 uint64_t ol_flags; 2168 uint16_t frag_field; 2169 2170 for (i = 0; i != nb_pkts; i++) { 2171 m = tx_pkts[i]; 2172 ol_flags = m->ol_flags; 2173 2174 if (!(ol_flags & PKT_TX_IPV4)) 2175 continue; 2176 2177 /* If there was not L2 header length specified, assume it is 2178 * length of the ethernet header. 2179 */ 2180 if (unlikely(m->l2_len == 0)) 2181 m->l2_len = sizeof(struct rte_ether_hdr); 2182 2183 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2184 m->l2_len); 2185 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2186 2187 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2188 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2189 2190 /* If IPv4 header has DF flag enabled and TSO support is 2191 * disabled, partial chcecksum should not be calculated. 2192 */ 2193 if (!tx_ring->adapter->offloads.tso4_supported) 2194 continue; 2195 } 2196 2197 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2198 (ol_flags & PKT_TX_L4_MASK) == 2199 PKT_TX_SCTP_CKSUM) { 2200 rte_errno = ENOTSUP; 2201 return i; 2202 } 2203 2204 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2205 ret = rte_validate_tx_offload(m); 2206 if (ret != 0) { 2207 rte_errno = -ret; 2208 return i; 2209 } 2210 #endif 2211 2212 /* In case we are supposed to TSO and have DF not set (DF=0) 2213 * hardware must be provided with partial checksum, otherwise 2214 * it will take care of necessary calculations. 2215 */ 2216 2217 ret = rte_net_intel_cksum_flags_prepare(m, 2218 ol_flags & ~PKT_TX_TCP_SEG); 2219 if (ret != 0) { 2220 rte_errno = -ret; 2221 return i; 2222 } 2223 } 2224 2225 return i; 2226 } 2227 2228 static void ena_update_hints(struct ena_adapter *adapter, 2229 struct ena_admin_ena_hw_hints *hints) 2230 { 2231 if (hints->admin_completion_tx_timeout) 2232 adapter->ena_dev.admin_queue.completion_timeout = 2233 hints->admin_completion_tx_timeout * 1000; 2234 2235 if (hints->mmio_read_timeout) 2236 /* convert to usec */ 2237 adapter->ena_dev.mmio_read.reg_read_to = 2238 hints->mmio_read_timeout * 1000; 2239 2240 if (hints->driver_watchdog_timeout) { 2241 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2242 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2243 else 2244 // Convert msecs to ticks 2245 adapter->keep_alive_timeout = 2246 (hints->driver_watchdog_timeout * 2247 rte_get_timer_hz()) / 1000; 2248 } 2249 } 2250 2251 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2252 struct rte_mbuf *mbuf) 2253 { 2254 struct ena_com_dev *ena_dev; 2255 int num_segments, header_len, rc; 2256 2257 ena_dev = &tx_ring->adapter->ena_dev; 2258 num_segments = mbuf->nb_segs; 2259 header_len = mbuf->data_len; 2260 2261 if (likely(num_segments < tx_ring->sgl_size)) 2262 return 0; 2263 2264 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2265 (num_segments == tx_ring->sgl_size) && 2266 (header_len < tx_ring->tx_max_header_size)) 2267 return 0; 2268 2269 ++tx_ring->tx_stats.linearize; 2270 rc = rte_pktmbuf_linearize(mbuf); 2271 if (unlikely(rc)) { 2272 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2273 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2274 ++tx_ring->tx_stats.linearize_failed; 2275 return rc; 2276 } 2277 2278 return rc; 2279 } 2280 2281 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2282 uint16_t nb_pkts) 2283 { 2284 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2285 uint16_t next_to_use = tx_ring->next_to_use; 2286 uint16_t next_to_clean = tx_ring->next_to_clean; 2287 struct rte_mbuf *mbuf; 2288 uint16_t seg_len; 2289 unsigned int ring_size = tx_ring->ring_size; 2290 unsigned int ring_mask = ring_size - 1; 2291 struct ena_com_tx_ctx ena_tx_ctx; 2292 struct ena_tx_buffer *tx_info; 2293 struct ena_com_buf *ebuf; 2294 uint16_t rc, req_id, total_tx_descs = 0; 2295 uint16_t sent_idx = 0, empty_tx_reqs; 2296 uint16_t push_len = 0; 2297 uint16_t delta = 0; 2298 int nb_hw_desc; 2299 uint32_t total_length; 2300 2301 /* Check adapter state */ 2302 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2303 PMD_DRV_LOG(ALERT, 2304 "Trying to xmit pkts while device is NOT running\n"); 2305 return 0; 2306 } 2307 2308 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2309 if (nb_pkts > empty_tx_reqs) 2310 nb_pkts = empty_tx_reqs; 2311 2312 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2313 mbuf = tx_pkts[sent_idx]; 2314 total_length = 0; 2315 2316 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2317 if (unlikely(rc)) 2318 break; 2319 2320 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2321 tx_info = &tx_ring->tx_buffer_info[req_id]; 2322 tx_info->mbuf = mbuf; 2323 tx_info->num_of_bufs = 0; 2324 ebuf = tx_info->bufs; 2325 2326 /* Prepare TX context */ 2327 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2328 memset(&ena_tx_ctx.ena_meta, 0x0, 2329 sizeof(struct ena_com_tx_meta)); 2330 ena_tx_ctx.ena_bufs = ebuf; 2331 ena_tx_ctx.req_id = req_id; 2332 2333 delta = 0; 2334 seg_len = mbuf->data_len; 2335 2336 if (tx_ring->tx_mem_queue_type == 2337 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2338 push_len = RTE_MIN(mbuf->pkt_len, 2339 tx_ring->tx_max_header_size); 2340 ena_tx_ctx.header_len = push_len; 2341 2342 if (likely(push_len <= seg_len)) { 2343 /* If the push header is in the single segment, 2344 * then just point it to the 1st mbuf data. 2345 */ 2346 ena_tx_ctx.push_header = 2347 rte_pktmbuf_mtod(mbuf, uint8_t *); 2348 } else { 2349 /* If the push header lays in the several 2350 * segments, copy it to the intermediate buffer. 2351 */ 2352 rte_pktmbuf_read(mbuf, 0, push_len, 2353 tx_ring->push_buf_intermediate_buf); 2354 ena_tx_ctx.push_header = 2355 tx_ring->push_buf_intermediate_buf; 2356 delta = push_len - seg_len; 2357 } 2358 } /* there's no else as we take advantage of memset zeroing */ 2359 2360 /* Set TX offloads flags, if applicable */ 2361 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2362 2363 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2364 2365 /* Process first segment taking into 2366 * consideration pushed header 2367 */ 2368 if (seg_len > push_len) { 2369 ebuf->paddr = mbuf->buf_iova + 2370 mbuf->data_off + 2371 push_len; 2372 ebuf->len = seg_len - push_len; 2373 ebuf++; 2374 tx_info->num_of_bufs++; 2375 } 2376 total_length += mbuf->data_len; 2377 2378 while ((mbuf = mbuf->next) != NULL) { 2379 seg_len = mbuf->data_len; 2380 2381 /* Skip mbufs if whole data is pushed as a header */ 2382 if (unlikely(delta > seg_len)) { 2383 delta -= seg_len; 2384 continue; 2385 } 2386 2387 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2388 ebuf->len = seg_len - delta; 2389 total_length += ebuf->len; 2390 ebuf++; 2391 tx_info->num_of_bufs++; 2392 2393 delta = 0; 2394 } 2395 2396 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2397 2398 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2399 &ena_tx_ctx)) { 2400 PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d" 2401 " achieved, writing doorbell to send burst\n", 2402 tx_ring->id); 2403 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2404 } 2405 2406 /* prepare the packet's descriptors to dma engine */ 2407 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2408 &ena_tx_ctx, &nb_hw_desc); 2409 if (unlikely(rc)) { 2410 ++tx_ring->tx_stats.prepare_ctx_err; 2411 break; 2412 } 2413 tx_info->tx_descs = nb_hw_desc; 2414 2415 next_to_use++; 2416 tx_ring->tx_stats.cnt++; 2417 tx_ring->tx_stats.bytes += total_length; 2418 } 2419 tx_ring->tx_stats.available_desc = 2420 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2421 2422 /* If there are ready packets to be xmitted... */ 2423 if (sent_idx > 0) { 2424 /* ...let HW do its best :-) */ 2425 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2426 tx_ring->tx_stats.doorbells++; 2427 tx_ring->next_to_use = next_to_use; 2428 } 2429 2430 /* Clear complete packets */ 2431 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2432 rc = validate_tx_req_id(tx_ring, req_id); 2433 if (rc) 2434 break; 2435 2436 /* Get Tx info & store how many descs were processed */ 2437 tx_info = &tx_ring->tx_buffer_info[req_id]; 2438 total_tx_descs += tx_info->tx_descs; 2439 2440 /* Free whole mbuf chain */ 2441 mbuf = tx_info->mbuf; 2442 rte_pktmbuf_free(mbuf); 2443 tx_info->mbuf = NULL; 2444 2445 /* Put back descriptor to the ring for reuse */ 2446 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2447 next_to_clean++; 2448 2449 /* If too many descs to clean, leave it for another run */ 2450 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2451 break; 2452 } 2453 tx_ring->tx_stats.available_desc = 2454 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2455 2456 if (total_tx_descs > 0) { 2457 /* acknowledge completion of sent packets */ 2458 tx_ring->next_to_clean = next_to_clean; 2459 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2460 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2461 } 2462 2463 tx_ring->tx_stats.tx_poll++; 2464 2465 return sent_idx; 2466 } 2467 2468 /** 2469 * DPDK callback to retrieve names of extended device statistics 2470 * 2471 * @param dev 2472 * Pointer to Ethernet device structure. 2473 * @param[out] xstats_names 2474 * Buffer to insert names into. 2475 * @param n 2476 * Number of names. 2477 * 2478 * @return 2479 * Number of xstats names. 2480 */ 2481 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2482 struct rte_eth_xstat_name *xstats_names, 2483 unsigned int n) 2484 { 2485 unsigned int xstats_count = ena_xstats_calc_num(dev); 2486 unsigned int stat, i, count = 0; 2487 2488 if (n < xstats_count || !xstats_names) 2489 return xstats_count; 2490 2491 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2492 strcpy(xstats_names[count].name, 2493 ena_stats_global_strings[stat].name); 2494 2495 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2496 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2497 snprintf(xstats_names[count].name, 2498 sizeof(xstats_names[count].name), 2499 "rx_q%d_%s", i, 2500 ena_stats_rx_strings[stat].name); 2501 2502 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2503 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2504 snprintf(xstats_names[count].name, 2505 sizeof(xstats_names[count].name), 2506 "tx_q%d_%s", i, 2507 ena_stats_tx_strings[stat].name); 2508 2509 return xstats_count; 2510 } 2511 2512 /** 2513 * DPDK callback to get extended device statistics. 2514 * 2515 * @param dev 2516 * Pointer to Ethernet device structure. 2517 * @param[out] stats 2518 * Stats table output buffer. 2519 * @param n 2520 * The size of the stats table. 2521 * 2522 * @return 2523 * Number of xstats on success, negative on failure. 2524 */ 2525 static int ena_xstats_get(struct rte_eth_dev *dev, 2526 struct rte_eth_xstat *xstats, 2527 unsigned int n) 2528 { 2529 struct ena_adapter *adapter = dev->data->dev_private; 2530 unsigned int xstats_count = ena_xstats_calc_num(dev); 2531 unsigned int stat, i, count = 0; 2532 int stat_offset; 2533 void *stats_begin; 2534 2535 if (n < xstats_count) 2536 return xstats_count; 2537 2538 if (!xstats) 2539 return 0; 2540 2541 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2542 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2543 stats_begin = &adapter->dev_stats; 2544 2545 xstats[count].id = count; 2546 xstats[count].value = *((uint64_t *) 2547 ((char *)stats_begin + stat_offset)); 2548 } 2549 2550 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2551 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2552 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2553 stats_begin = &adapter->rx_ring[i].rx_stats; 2554 2555 xstats[count].id = count; 2556 xstats[count].value = *((uint64_t *) 2557 ((char *)stats_begin + stat_offset)); 2558 } 2559 } 2560 2561 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2562 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2563 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2564 stats_begin = &adapter->tx_ring[i].rx_stats; 2565 2566 xstats[count].id = count; 2567 xstats[count].value = *((uint64_t *) 2568 ((char *)stats_begin + stat_offset)); 2569 } 2570 } 2571 2572 return count; 2573 } 2574 2575 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2576 const uint64_t *ids, 2577 uint64_t *values, 2578 unsigned int n) 2579 { 2580 struct ena_adapter *adapter = dev->data->dev_private; 2581 uint64_t id; 2582 uint64_t rx_entries, tx_entries; 2583 unsigned int i; 2584 int qid; 2585 int valid = 0; 2586 for (i = 0; i < n; ++i) { 2587 id = ids[i]; 2588 /* Check if id belongs to global statistics */ 2589 if (id < ENA_STATS_ARRAY_GLOBAL) { 2590 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2591 ++valid; 2592 continue; 2593 } 2594 2595 /* Check if id belongs to rx queue statistics */ 2596 id -= ENA_STATS_ARRAY_GLOBAL; 2597 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2598 if (id < rx_entries) { 2599 qid = id % dev->data->nb_rx_queues; 2600 id /= dev->data->nb_rx_queues; 2601 values[i] = *((uint64_t *) 2602 &adapter->rx_ring[qid].rx_stats + id); 2603 ++valid; 2604 continue; 2605 } 2606 /* Check if id belongs to rx queue statistics */ 2607 id -= rx_entries; 2608 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2609 if (id < tx_entries) { 2610 qid = id % dev->data->nb_tx_queues; 2611 id /= dev->data->nb_tx_queues; 2612 values[i] = *((uint64_t *) 2613 &adapter->tx_ring[qid].tx_stats + id); 2614 ++valid; 2615 continue; 2616 } 2617 } 2618 2619 return valid; 2620 } 2621 2622 static int ena_process_bool_devarg(const char *key, 2623 const char *value, 2624 void *opaque) 2625 { 2626 struct ena_adapter *adapter = opaque; 2627 bool bool_value; 2628 2629 /* Parse the value. */ 2630 if (strcmp(value, "1") == 0) { 2631 bool_value = true; 2632 } else if (strcmp(value, "0") == 0) { 2633 bool_value = false; 2634 } else { 2635 PMD_INIT_LOG(ERR, 2636 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n", 2637 value, key); 2638 return -EINVAL; 2639 } 2640 2641 /* Now, assign it to the proper adapter field. */ 2642 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) 2643 adapter->use_large_llq_hdr = bool_value; 2644 2645 return 0; 2646 } 2647 2648 static int ena_parse_devargs(struct ena_adapter *adapter, 2649 struct rte_devargs *devargs) 2650 { 2651 static const char * const allowed_args[] = { 2652 ENA_DEVARG_LARGE_LLQ_HDR, 2653 }; 2654 struct rte_kvargs *kvlist; 2655 int rc; 2656 2657 if (devargs == NULL) 2658 return 0; 2659 2660 kvlist = rte_kvargs_parse(devargs->args, allowed_args); 2661 if (kvlist == NULL) { 2662 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n", 2663 devargs->args); 2664 return -EINVAL; 2665 } 2666 2667 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR, 2668 ena_process_bool_devarg, adapter); 2669 2670 rte_kvargs_free(kvlist); 2671 2672 return rc; 2673 } 2674 2675 /********************************************************************* 2676 * PMD configuration 2677 *********************************************************************/ 2678 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2679 struct rte_pci_device *pci_dev) 2680 { 2681 return rte_eth_dev_pci_generic_probe(pci_dev, 2682 sizeof(struct ena_adapter), eth_ena_dev_init); 2683 } 2684 2685 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2686 { 2687 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2688 } 2689 2690 static struct rte_pci_driver rte_ena_pmd = { 2691 .id_table = pci_id_ena_map, 2692 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2693 RTE_PCI_DRV_WC_ACTIVATE, 2694 .probe = eth_ena_pci_probe, 2695 .remove = eth_ena_pci_remove, 2696 }; 2697 2698 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2699 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2700 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2701 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>"); 2702 2703 RTE_INIT(ena_init_log) 2704 { 2705 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2706 if (ena_logtype_init >= 0) 2707 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2708 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2709 if (ena_logtype_driver >= 0) 2710 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2711 2712 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2713 ena_logtype_rx = rte_log_register("pmd.net.ena.rx"); 2714 if (ena_logtype_rx >= 0) 2715 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE); 2716 #endif 2717 2718 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2719 ena_logtype_tx = rte_log_register("pmd.net.ena.tx"); 2720 if (ena_logtype_tx >= 0) 2721 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE); 2722 #endif 2723 2724 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2725 ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free"); 2726 if (ena_logtype_tx_free >= 0) 2727 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE); 2728 #endif 2729 2730 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2731 ena_logtype_com = rte_log_register("pmd.net.ena.com"); 2732 if (ena_logtype_com >= 0) 2733 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE); 2734 #endif 2735 } 2736 2737 /****************************************************************************** 2738 ******************************** AENQ Handlers ******************************* 2739 *****************************************************************************/ 2740 static void ena_update_on_link_change(void *adapter_data, 2741 struct ena_admin_aenq_entry *aenq_e) 2742 { 2743 struct rte_eth_dev *eth_dev; 2744 struct ena_adapter *adapter; 2745 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2746 uint32_t status; 2747 2748 adapter = adapter_data; 2749 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2750 eth_dev = adapter->rte_dev; 2751 2752 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2753 adapter->link_status = status; 2754 2755 ena_link_update(eth_dev, 0); 2756 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2757 } 2758 2759 static void ena_notification(void *data, 2760 struct ena_admin_aenq_entry *aenq_e) 2761 { 2762 struct ena_adapter *adapter = data; 2763 struct ena_admin_ena_hw_hints *hints; 2764 2765 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2766 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2767 aenq_e->aenq_common_desc.group, 2768 ENA_ADMIN_NOTIFICATION); 2769 2770 switch (aenq_e->aenq_common_desc.syndrom) { 2771 case ENA_ADMIN_UPDATE_HINTS: 2772 hints = (struct ena_admin_ena_hw_hints *) 2773 (&aenq_e->inline_data_w4); 2774 ena_update_hints(adapter, hints); 2775 break; 2776 default: 2777 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2778 aenq_e->aenq_common_desc.syndrom); 2779 } 2780 } 2781 2782 static void ena_keep_alive(void *adapter_data, 2783 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2784 { 2785 struct ena_adapter *adapter = adapter_data; 2786 struct ena_admin_aenq_keep_alive_desc *desc; 2787 uint64_t rx_drops; 2788 2789 adapter->timestamp_wd = rte_get_timer_cycles(); 2790 2791 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2792 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2793 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2794 } 2795 2796 /** 2797 * This handler will called for unknown event group or unimplemented handlers 2798 **/ 2799 static void unimplemented_aenq_handler(__rte_unused void *data, 2800 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2801 { 2802 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 2803 "unimplemented handler\n"); 2804 } 2805 2806 static struct ena_aenq_handlers aenq_handlers = { 2807 .handlers = { 2808 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2809 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2810 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2811 }, 2812 .unimplemented_handler = unimplemented_aenq_handler 2813 }; 2814