1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include <rte_string_fns.h> 7 #include <rte_ether.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_ethdev_pci.h> 10 #include <rte_tcp.h> 11 #include <rte_atomic.h> 12 #include <rte_dev.h> 13 #include <rte_errno.h> 14 #include <rte_version.h> 15 #include <rte_net.h> 16 17 #include "ena_ethdev.h" 18 #include "ena_logs.h" 19 #include "ena_platform.h" 20 #include "ena_com.h" 21 #include "ena_eth_com.h" 22 23 #include <ena_common_defs.h> 24 #include <ena_regs_defs.h> 25 #include <ena_admin_defs.h> 26 #include <ena_eth_io_defs.h> 27 28 #define DRV_MODULE_VER_MAJOR 2 29 #define DRV_MODULE_VER_MINOR 0 30 #define DRV_MODULE_VER_SUBMINOR 3 31 32 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 33 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 34 /*reverse version of ENA_IO_RXQ_IDX*/ 35 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 36 37 /* While processing submitted and completed descriptors (rx and tx path 38 * respectively) in a loop it is desired to: 39 * - perform batch submissions while populating sumbissmion queue 40 * - avoid blocking transmission of other packets during cleanup phase 41 * Hence the utilization ratio of 1/8 of a queue size. 42 */ 43 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 44 45 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 46 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 47 48 #define GET_L4_HDR_LEN(mbuf) \ 49 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 50 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 51 52 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 53 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 54 #define ENA_HASH_KEY_SIZE 40 55 #define ETH_GSTRING_LEN 32 56 57 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 58 59 #define ENA_MIN_RING_DESC 128 60 61 enum ethtool_stringset { 62 ETH_SS_TEST = 0, 63 ETH_SS_STATS, 64 }; 65 66 struct ena_stats { 67 char name[ETH_GSTRING_LEN]; 68 int stat_offset; 69 }; 70 71 #define ENA_STAT_ENTRY(stat, stat_type) { \ 72 .name = #stat, \ 73 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 74 } 75 76 #define ENA_STAT_RX_ENTRY(stat) \ 77 ENA_STAT_ENTRY(stat, rx) 78 79 #define ENA_STAT_TX_ENTRY(stat) \ 80 ENA_STAT_ENTRY(stat, tx) 81 82 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 83 ENA_STAT_ENTRY(stat, dev) 84 85 #define ENA_MAX_RING_SIZE_RX 8192 86 #define ENA_MAX_RING_SIZE_TX 1024 87 88 /* 89 * Each rte_memzone should have unique name. 90 * To satisfy it, count number of allocation and add it to name. 91 */ 92 uint32_t ena_alloc_cnt; 93 94 static const struct ena_stats ena_stats_global_strings[] = { 95 ENA_STAT_GLOBAL_ENTRY(wd_expired), 96 ENA_STAT_GLOBAL_ENTRY(dev_start), 97 ENA_STAT_GLOBAL_ENTRY(dev_stop), 98 }; 99 100 static const struct ena_stats ena_stats_tx_strings[] = { 101 ENA_STAT_TX_ENTRY(cnt), 102 ENA_STAT_TX_ENTRY(bytes), 103 ENA_STAT_TX_ENTRY(prepare_ctx_err), 104 ENA_STAT_TX_ENTRY(linearize), 105 ENA_STAT_TX_ENTRY(linearize_failed), 106 ENA_STAT_TX_ENTRY(tx_poll), 107 ENA_STAT_TX_ENTRY(doorbells), 108 ENA_STAT_TX_ENTRY(bad_req_id), 109 ENA_STAT_TX_ENTRY(available_desc), 110 }; 111 112 static const struct ena_stats ena_stats_rx_strings[] = { 113 ENA_STAT_RX_ENTRY(cnt), 114 ENA_STAT_RX_ENTRY(bytes), 115 ENA_STAT_RX_ENTRY(refill_partial), 116 ENA_STAT_RX_ENTRY(bad_csum), 117 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 118 ENA_STAT_RX_ENTRY(bad_desc_num), 119 ENA_STAT_RX_ENTRY(bad_req_id), 120 }; 121 122 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 123 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 124 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 125 126 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 127 DEV_TX_OFFLOAD_UDP_CKSUM |\ 128 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 129 DEV_TX_OFFLOAD_TCP_TSO) 130 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 131 PKT_TX_IP_CKSUM |\ 132 PKT_TX_TCP_SEG) 133 134 /** Vendor ID used by Amazon devices */ 135 #define PCI_VENDOR_ID_AMAZON 0x1D0F 136 /** Amazon devices */ 137 #define PCI_DEVICE_ID_ENA_VF 0xEC20 138 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 139 140 #define ENA_TX_OFFLOAD_MASK (\ 141 PKT_TX_L4_MASK | \ 142 PKT_TX_IPV6 | \ 143 PKT_TX_IPV4 | \ 144 PKT_TX_IP_CKSUM | \ 145 PKT_TX_TCP_SEG) 146 147 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 148 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 149 150 int ena_logtype_init; 151 int ena_logtype_driver; 152 153 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 154 int ena_logtype_rx; 155 #endif 156 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 157 int ena_logtype_tx; 158 #endif 159 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 160 int ena_logtype_tx_free; 161 #endif 162 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 163 int ena_logtype_com; 164 #endif 165 166 static const struct rte_pci_id pci_id_ena_map[] = { 167 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 168 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 169 { .device_id = 0 }, 170 }; 171 172 static struct ena_aenq_handlers aenq_handlers; 173 174 static int ena_device_init(struct ena_com_dev *ena_dev, 175 struct ena_com_dev_get_features_ctx *get_feat_ctx, 176 bool *wd_state); 177 static int ena_dev_configure(struct rte_eth_dev *dev); 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 179 uint16_t nb_pkts); 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 181 uint16_t nb_pkts); 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 183 uint16_t nb_desc, unsigned int socket_id, 184 const struct rte_eth_txconf *tx_conf); 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 186 uint16_t nb_desc, unsigned int socket_id, 187 const struct rte_eth_rxconf *rx_conf, 188 struct rte_mempool *mp); 189 static uint16_t eth_ena_recv_pkts(void *rx_queue, 190 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 192 static void ena_init_rings(struct ena_adapter *adapter); 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 194 static int ena_start(struct rte_eth_dev *dev); 195 static void ena_stop(struct rte_eth_dev *dev); 196 static void ena_close(struct rte_eth_dev *dev); 197 static int ena_dev_reset(struct rte_eth_dev *dev); 198 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 199 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 200 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 201 static void ena_rx_queue_release(void *queue); 202 static void ena_tx_queue_release(void *queue); 203 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 204 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 205 static int ena_link_update(struct rte_eth_dev *dev, 206 int wait_to_complete); 207 static int ena_create_io_queue(struct ena_ring *ring); 208 static void ena_queue_stop(struct ena_ring *ring); 209 static void ena_queue_stop_all(struct rte_eth_dev *dev, 210 enum ena_ring_type ring_type); 211 static int ena_queue_start(struct ena_ring *ring); 212 static int ena_queue_start_all(struct rte_eth_dev *dev, 213 enum ena_ring_type ring_type); 214 static void ena_stats_restart(struct rte_eth_dev *dev); 215 static int ena_infos_get(struct rte_eth_dev *dev, 216 struct rte_eth_dev_info *dev_info); 217 static int ena_rss_reta_update(struct rte_eth_dev *dev, 218 struct rte_eth_rss_reta_entry64 *reta_conf, 219 uint16_t reta_size); 220 static int ena_rss_reta_query(struct rte_eth_dev *dev, 221 struct rte_eth_rss_reta_entry64 *reta_conf, 222 uint16_t reta_size); 223 static void ena_interrupt_handler_rte(void *cb_arg); 224 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 225 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 226 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 227 static int ena_xstats_get_names(struct rte_eth_dev *dev, 228 struct rte_eth_xstat_name *xstats_names, 229 unsigned int n); 230 static int ena_xstats_get(struct rte_eth_dev *dev, 231 struct rte_eth_xstat *stats, 232 unsigned int n); 233 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 234 const uint64_t *ids, 235 uint64_t *values, 236 unsigned int n); 237 238 static const struct eth_dev_ops ena_dev_ops = { 239 .dev_configure = ena_dev_configure, 240 .dev_infos_get = ena_infos_get, 241 .rx_queue_setup = ena_rx_queue_setup, 242 .tx_queue_setup = ena_tx_queue_setup, 243 .dev_start = ena_start, 244 .dev_stop = ena_stop, 245 .link_update = ena_link_update, 246 .stats_get = ena_stats_get, 247 .xstats_get_names = ena_xstats_get_names, 248 .xstats_get = ena_xstats_get, 249 .xstats_get_by_id = ena_xstats_get_by_id, 250 .mtu_set = ena_mtu_set, 251 .rx_queue_release = ena_rx_queue_release, 252 .tx_queue_release = ena_tx_queue_release, 253 .dev_close = ena_close, 254 .dev_reset = ena_dev_reset, 255 .reta_update = ena_rss_reta_update, 256 .reta_query = ena_rss_reta_query, 257 }; 258 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 260 struct ena_com_rx_ctx *ena_rx_ctx) 261 { 262 uint64_t ol_flags = 0; 263 uint32_t packet_type = 0; 264 265 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 266 packet_type |= RTE_PTYPE_L4_TCP; 267 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 268 packet_type |= RTE_PTYPE_L4_UDP; 269 270 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 271 packet_type |= RTE_PTYPE_L3_IPV4; 272 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 273 packet_type |= RTE_PTYPE_L3_IPV6; 274 275 if (!ena_rx_ctx->l4_csum_checked) 276 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 277 else 278 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag) 279 ol_flags |= PKT_RX_L4_CKSUM_BAD; 280 else 281 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 282 283 if (unlikely(ena_rx_ctx->l3_csum_err)) 284 ol_flags |= PKT_RX_IP_CKSUM_BAD; 285 286 mbuf->ol_flags = ol_flags; 287 mbuf->packet_type = packet_type; 288 } 289 290 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 291 struct ena_com_tx_ctx *ena_tx_ctx, 292 uint64_t queue_offloads) 293 { 294 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 295 296 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 297 (queue_offloads & QUEUE_OFFLOADS)) { 298 /* check if TSO is required */ 299 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 300 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 301 ena_tx_ctx->tso_enable = true; 302 303 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 304 } 305 306 /* check if L3 checksum is needed */ 307 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 308 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 309 ena_tx_ctx->l3_csum_enable = true; 310 311 if (mbuf->ol_flags & PKT_TX_IPV6) { 312 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 313 } else { 314 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 315 316 /* set don't fragment (DF) flag */ 317 if (mbuf->packet_type & 318 (RTE_PTYPE_L4_NONFRAG 319 | RTE_PTYPE_INNER_L4_NONFRAG)) 320 ena_tx_ctx->df = true; 321 } 322 323 /* check if L4 checksum is needed */ 324 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 325 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 326 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 327 ena_tx_ctx->l4_csum_enable = true; 328 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 329 PKT_TX_UDP_CKSUM) && 330 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 331 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 332 ena_tx_ctx->l4_csum_enable = true; 333 } else { 334 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 335 ena_tx_ctx->l4_csum_enable = false; 336 } 337 338 ena_meta->mss = mbuf->tso_segsz; 339 ena_meta->l3_hdr_len = mbuf->l3_len; 340 ena_meta->l3_hdr_offset = mbuf->l2_len; 341 342 ena_tx_ctx->meta_valid = true; 343 } else { 344 ena_tx_ctx->meta_valid = false; 345 } 346 } 347 348 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 349 { 350 if (likely(req_id < rx_ring->ring_size)) 351 return 0; 352 353 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id); 354 355 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 356 rx_ring->adapter->trigger_reset = true; 357 ++rx_ring->rx_stats.bad_req_id; 358 359 return -EFAULT; 360 } 361 362 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 363 { 364 struct ena_tx_buffer *tx_info = NULL; 365 366 if (likely(req_id < tx_ring->ring_size)) { 367 tx_info = &tx_ring->tx_buffer_info[req_id]; 368 if (likely(tx_info->mbuf)) 369 return 0; 370 } 371 372 if (tx_info) 373 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n"); 374 else 375 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id); 376 377 /* Trigger device reset */ 378 ++tx_ring->tx_stats.bad_req_id; 379 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 380 tx_ring->adapter->trigger_reset = true; 381 return -EFAULT; 382 } 383 384 static void ena_config_host_info(struct ena_com_dev *ena_dev) 385 { 386 struct ena_admin_host_info *host_info; 387 int rc; 388 389 /* Allocate only the host info */ 390 rc = ena_com_allocate_host_info(ena_dev); 391 if (rc) { 392 PMD_DRV_LOG(ERR, "Cannot allocate host info\n"); 393 return; 394 } 395 396 host_info = ena_dev->host_attr.host_info; 397 398 host_info->os_type = ENA_ADMIN_OS_DPDK; 399 host_info->kernel_ver = RTE_VERSION; 400 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 401 sizeof(host_info->kernel_ver_str)); 402 host_info->os_dist = RTE_VERSION; 403 strlcpy((char *)host_info->os_dist_str, rte_version(), 404 sizeof(host_info->os_dist_str)); 405 host_info->driver_version = 406 (DRV_MODULE_VER_MAJOR) | 407 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 408 (DRV_MODULE_VER_SUBMINOR << 409 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 410 host_info->num_cpus = rte_lcore_count(); 411 412 host_info->driver_supported_features = 413 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 414 415 rc = ena_com_set_host_attributes(ena_dev); 416 if (rc) { 417 if (rc == -ENA_COM_UNSUPPORTED) 418 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 419 else 420 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 421 422 goto err; 423 } 424 425 return; 426 427 err: 428 ena_com_delete_host_info(ena_dev); 429 } 430 431 /* This function calculates the number of xstats based on the current config */ 432 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 433 { 434 return ENA_STATS_ARRAY_GLOBAL + 435 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 436 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 437 } 438 439 static void ena_config_debug_area(struct ena_adapter *adapter) 440 { 441 u32 debug_area_size; 442 int rc, ss_count; 443 444 ss_count = ena_xstats_calc_num(adapter->rte_dev); 445 446 /* allocate 32 bytes for each string and 64bit for the value */ 447 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 448 449 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 450 if (rc) { 451 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n"); 452 return; 453 } 454 455 rc = ena_com_set_host_attributes(&adapter->ena_dev); 456 if (rc) { 457 if (rc == -ENA_COM_UNSUPPORTED) 458 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n"); 459 else 460 PMD_DRV_LOG(ERR, "Cannot set host attributes\n"); 461 462 goto err; 463 } 464 465 return; 466 err: 467 ena_com_delete_debug_area(&adapter->ena_dev); 468 } 469 470 static void ena_close(struct rte_eth_dev *dev) 471 { 472 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 473 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 474 struct ena_adapter *adapter = dev->data->dev_private; 475 476 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 477 ena_stop(dev); 478 adapter->state = ENA_ADAPTER_STATE_CLOSED; 479 480 ena_rx_queue_release_all(dev); 481 ena_tx_queue_release_all(dev); 482 483 rte_free(adapter->drv_stats); 484 adapter->drv_stats = NULL; 485 486 rte_intr_disable(intr_handle); 487 rte_intr_callback_unregister(intr_handle, 488 ena_interrupt_handler_rte, 489 adapter); 490 491 /* 492 * MAC is not allocated dynamically. Setting NULL should prevent from 493 * release of the resource in the rte_eth_dev_release_port(). 494 */ 495 dev->data->mac_addrs = NULL; 496 } 497 498 static int 499 ena_dev_reset(struct rte_eth_dev *dev) 500 { 501 int rc = 0; 502 503 ena_destroy_device(dev); 504 rc = eth_ena_dev_init(dev); 505 if (rc) 506 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 507 508 return rc; 509 } 510 511 static int ena_rss_reta_update(struct rte_eth_dev *dev, 512 struct rte_eth_rss_reta_entry64 *reta_conf, 513 uint16_t reta_size) 514 { 515 struct ena_adapter *adapter = dev->data->dev_private; 516 struct ena_com_dev *ena_dev = &adapter->ena_dev; 517 int rc, i; 518 u16 entry_value; 519 int conf_idx; 520 int idx; 521 522 if ((reta_size == 0) || (reta_conf == NULL)) 523 return -EINVAL; 524 525 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 526 PMD_DRV_LOG(WARNING, 527 "indirection table %d is bigger than supported (%d)\n", 528 reta_size, ENA_RX_RSS_TABLE_SIZE); 529 return -EINVAL; 530 } 531 532 for (i = 0 ; i < reta_size ; i++) { 533 /* each reta_conf is for 64 entries. 534 * to support 128 we use 2 conf of 64 535 */ 536 conf_idx = i / RTE_RETA_GROUP_SIZE; 537 idx = i % RTE_RETA_GROUP_SIZE; 538 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 539 entry_value = 540 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 541 542 rc = ena_com_indirect_table_fill_entry(ena_dev, 543 i, 544 entry_value); 545 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 546 PMD_DRV_LOG(ERR, 547 "Cannot fill indirect table\n"); 548 return rc; 549 } 550 } 551 } 552 553 rc = ena_com_indirect_table_set(ena_dev); 554 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 555 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 556 return rc; 557 } 558 559 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", 560 __func__, reta_size, adapter->rte_dev->data->port_id); 561 562 return 0; 563 } 564 565 /* Query redirection table. */ 566 static int ena_rss_reta_query(struct rte_eth_dev *dev, 567 struct rte_eth_rss_reta_entry64 *reta_conf, 568 uint16_t reta_size) 569 { 570 struct ena_adapter *adapter = dev->data->dev_private; 571 struct ena_com_dev *ena_dev = &adapter->ena_dev; 572 int rc; 573 int i; 574 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 575 int reta_conf_idx; 576 int reta_idx; 577 578 if (reta_size == 0 || reta_conf == NULL || 579 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 580 return -EINVAL; 581 582 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 584 PMD_DRV_LOG(ERR, "cannot get indirect table\n"); 585 return -ENOTSUP; 586 } 587 588 for (i = 0 ; i < reta_size ; i++) { 589 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 590 reta_idx = i % RTE_RETA_GROUP_SIZE; 591 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 592 reta_conf[reta_conf_idx].reta[reta_idx] = 593 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 594 } 595 596 return 0; 597 } 598 599 static int ena_rss_init_default(struct ena_adapter *adapter) 600 { 601 struct ena_com_dev *ena_dev = &adapter->ena_dev; 602 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 603 int rc, i; 604 u32 val; 605 606 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 607 if (unlikely(rc)) { 608 PMD_DRV_LOG(ERR, "Cannot init indirect table\n"); 609 goto err_rss_init; 610 } 611 612 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 613 val = i % nb_rx_queues; 614 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 615 ENA_IO_RXQ_IDX(val)); 616 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 617 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n"); 618 goto err_fill_indir; 619 } 620 } 621 622 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 623 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 624 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 625 PMD_DRV_LOG(INFO, "Cannot fill hash function\n"); 626 goto err_fill_indir; 627 } 628 629 rc = ena_com_set_default_hash_ctrl(ena_dev); 630 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 631 PMD_DRV_LOG(INFO, "Cannot fill hash control\n"); 632 goto err_fill_indir; 633 } 634 635 rc = ena_com_indirect_table_set(ena_dev); 636 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 637 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); 638 goto err_fill_indir; 639 } 640 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", 641 adapter->rte_dev->data->port_id); 642 643 return 0; 644 645 err_fill_indir: 646 ena_com_rss_destroy(ena_dev); 647 err_rss_init: 648 649 return rc; 650 } 651 652 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 653 { 654 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 655 int nb_queues = dev->data->nb_rx_queues; 656 int i; 657 658 for (i = 0; i < nb_queues; i++) 659 ena_rx_queue_release(queues[i]); 660 } 661 662 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 663 { 664 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 665 int nb_queues = dev->data->nb_tx_queues; 666 int i; 667 668 for (i = 0; i < nb_queues; i++) 669 ena_tx_queue_release(queues[i]); 670 } 671 672 static void ena_rx_queue_release(void *queue) 673 { 674 struct ena_ring *ring = (struct ena_ring *)queue; 675 676 /* Free ring resources */ 677 if (ring->rx_buffer_info) 678 rte_free(ring->rx_buffer_info); 679 ring->rx_buffer_info = NULL; 680 681 if (ring->rx_refill_buffer) 682 rte_free(ring->rx_refill_buffer); 683 ring->rx_refill_buffer = NULL; 684 685 if (ring->empty_rx_reqs) 686 rte_free(ring->empty_rx_reqs); 687 ring->empty_rx_reqs = NULL; 688 689 ring->configured = 0; 690 691 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n", 692 ring->port_id, ring->id); 693 } 694 695 static void ena_tx_queue_release(void *queue) 696 { 697 struct ena_ring *ring = (struct ena_ring *)queue; 698 699 /* Free ring resources */ 700 if (ring->push_buf_intermediate_buf) 701 rte_free(ring->push_buf_intermediate_buf); 702 703 if (ring->tx_buffer_info) 704 rte_free(ring->tx_buffer_info); 705 706 if (ring->empty_tx_reqs) 707 rte_free(ring->empty_tx_reqs); 708 709 ring->empty_tx_reqs = NULL; 710 ring->tx_buffer_info = NULL; 711 ring->push_buf_intermediate_buf = NULL; 712 713 ring->configured = 0; 714 715 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n", 716 ring->port_id, ring->id); 717 } 718 719 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 720 { 721 unsigned int i; 722 723 for (i = 0; i < ring->ring_size; ++i) 724 if (ring->rx_buffer_info[i]) { 725 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 726 ring->rx_buffer_info[i] = NULL; 727 } 728 } 729 730 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 731 { 732 unsigned int i; 733 734 for (i = 0; i < ring->ring_size; ++i) { 735 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 736 737 if (tx_buf->mbuf) 738 rte_pktmbuf_free(tx_buf->mbuf); 739 } 740 } 741 742 static int ena_link_update(struct rte_eth_dev *dev, 743 __rte_unused int wait_to_complete) 744 { 745 struct rte_eth_link *link = &dev->data->dev_link; 746 struct ena_adapter *adapter = dev->data->dev_private; 747 748 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 749 link->link_speed = ETH_SPEED_NUM_NONE; 750 link->link_duplex = ETH_LINK_FULL_DUPLEX; 751 752 return 0; 753 } 754 755 static int ena_queue_start_all(struct rte_eth_dev *dev, 756 enum ena_ring_type ring_type) 757 { 758 struct ena_adapter *adapter = dev->data->dev_private; 759 struct ena_ring *queues = NULL; 760 int nb_queues; 761 int i = 0; 762 int rc = 0; 763 764 if (ring_type == ENA_RING_TYPE_RX) { 765 queues = adapter->rx_ring; 766 nb_queues = dev->data->nb_rx_queues; 767 } else { 768 queues = adapter->tx_ring; 769 nb_queues = dev->data->nb_tx_queues; 770 } 771 for (i = 0; i < nb_queues; i++) { 772 if (queues[i].configured) { 773 if (ring_type == ENA_RING_TYPE_RX) { 774 ena_assert_msg( 775 dev->data->rx_queues[i] == &queues[i], 776 "Inconsistent state of rx queues\n"); 777 } else { 778 ena_assert_msg( 779 dev->data->tx_queues[i] == &queues[i], 780 "Inconsistent state of tx queues\n"); 781 } 782 783 rc = ena_queue_start(&queues[i]); 784 785 if (rc) { 786 PMD_INIT_LOG(ERR, 787 "failed to start queue %d type(%d)", 788 i, ring_type); 789 goto err; 790 } 791 } 792 } 793 794 return 0; 795 796 err: 797 while (i--) 798 if (queues[i].configured) 799 ena_queue_stop(&queues[i]); 800 801 return rc; 802 } 803 804 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 805 { 806 uint32_t max_frame_len = adapter->max_mtu; 807 808 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 809 DEV_RX_OFFLOAD_JUMBO_FRAME) 810 max_frame_len = 811 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 812 813 return max_frame_len; 814 } 815 816 static int ena_check_valid_conf(struct ena_adapter *adapter) 817 { 818 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 819 820 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 821 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 822 "max mtu: %d, min mtu: %d", 823 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 824 return ENA_COM_UNSUPPORTED; 825 } 826 827 return 0; 828 } 829 830 static int 831 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) 832 { 833 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 834 struct ena_com_dev *ena_dev = ctx->ena_dev; 835 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; 836 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; 837 838 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 839 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 840 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 841 rx_queue_size = RTE_MIN(rx_queue_size, 842 max_queue_ext->max_rx_cq_depth); 843 rx_queue_size = RTE_MIN(rx_queue_size, 844 max_queue_ext->max_rx_sq_depth); 845 tx_queue_size = RTE_MIN(tx_queue_size, 846 max_queue_ext->max_tx_cq_depth); 847 848 if (ena_dev->tx_mem_queue_type == 849 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 850 tx_queue_size = RTE_MIN(tx_queue_size, 851 llq->max_llq_depth); 852 } else { 853 tx_queue_size = RTE_MIN(tx_queue_size, 854 max_queue_ext->max_tx_sq_depth); 855 } 856 857 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 858 max_queue_ext->max_per_packet_rx_descs); 859 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 860 max_queue_ext->max_per_packet_tx_descs); 861 } else { 862 struct ena_admin_queue_feature_desc *max_queues = 863 &ctx->get_feat_ctx->max_queues; 864 rx_queue_size = RTE_MIN(rx_queue_size, 865 max_queues->max_cq_depth); 866 rx_queue_size = RTE_MIN(rx_queue_size, 867 max_queues->max_sq_depth); 868 tx_queue_size = RTE_MIN(tx_queue_size, 869 max_queues->max_cq_depth); 870 871 if (ena_dev->tx_mem_queue_type == 872 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 873 tx_queue_size = RTE_MIN(tx_queue_size, 874 llq->max_llq_depth); 875 } else { 876 tx_queue_size = RTE_MIN(tx_queue_size, 877 max_queues->max_sq_depth); 878 } 879 880 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 881 max_queues->max_packet_tx_descs); 882 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 883 max_queues->max_packet_rx_descs); 884 } 885 886 /* Round down to the nearest power of 2 */ 887 rx_queue_size = rte_align32prevpow2(rx_queue_size); 888 tx_queue_size = rte_align32prevpow2(tx_queue_size); 889 890 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { 891 PMD_INIT_LOG(ERR, "Invalid queue size"); 892 return -EFAULT; 893 } 894 895 ctx->rx_queue_size = rx_queue_size; 896 ctx->tx_queue_size = tx_queue_size; 897 898 return 0; 899 } 900 901 static void ena_stats_restart(struct rte_eth_dev *dev) 902 { 903 struct ena_adapter *adapter = dev->data->dev_private; 904 905 rte_atomic64_init(&adapter->drv_stats->ierrors); 906 rte_atomic64_init(&adapter->drv_stats->oerrors); 907 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 908 rte_atomic64_init(&adapter->drv_stats->rx_drops); 909 } 910 911 static int ena_stats_get(struct rte_eth_dev *dev, 912 struct rte_eth_stats *stats) 913 { 914 struct ena_admin_basic_stats ena_stats; 915 struct ena_adapter *adapter = dev->data->dev_private; 916 struct ena_com_dev *ena_dev = &adapter->ena_dev; 917 int rc; 918 int i; 919 int max_rings_stats; 920 921 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 922 return -ENOTSUP; 923 924 memset(&ena_stats, 0, sizeof(ena_stats)); 925 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 926 if (unlikely(rc)) { 927 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n"); 928 return rc; 929 } 930 931 /* Set of basic statistics from ENA */ 932 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 933 ena_stats.rx_pkts_low); 934 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 935 ena_stats.tx_pkts_low); 936 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 937 ena_stats.rx_bytes_low); 938 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 939 ena_stats.tx_bytes_low); 940 941 /* Driver related stats */ 942 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 943 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 944 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 945 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 946 947 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 948 RTE_ETHDEV_QUEUE_STAT_CNTRS); 949 for (i = 0; i < max_rings_stats; ++i) { 950 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 951 952 stats->q_ibytes[i] = rx_stats->bytes; 953 stats->q_ipackets[i] = rx_stats->cnt; 954 stats->q_errors[i] = rx_stats->bad_desc_num + 955 rx_stats->bad_req_id; 956 } 957 958 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 959 RTE_ETHDEV_QUEUE_STAT_CNTRS); 960 for (i = 0; i < max_rings_stats; ++i) { 961 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 962 963 stats->q_obytes[i] = tx_stats->bytes; 964 stats->q_opackets[i] = tx_stats->cnt; 965 } 966 967 return 0; 968 } 969 970 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 971 { 972 struct ena_adapter *adapter; 973 struct ena_com_dev *ena_dev; 974 int rc = 0; 975 976 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 977 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 978 adapter = dev->data->dev_private; 979 980 ena_dev = &adapter->ena_dev; 981 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 982 983 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 984 PMD_DRV_LOG(ERR, 985 "Invalid MTU setting. new_mtu: %d " 986 "max mtu: %d min mtu: %d\n", 987 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 988 return -EINVAL; 989 } 990 991 rc = ena_com_set_dev_mtu(ena_dev, mtu); 992 if (rc) 993 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu); 994 else 995 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu); 996 997 return rc; 998 } 999 1000 static int ena_start(struct rte_eth_dev *dev) 1001 { 1002 struct ena_adapter *adapter = dev->data->dev_private; 1003 uint64_t ticks; 1004 int rc = 0; 1005 1006 rc = ena_check_valid_conf(adapter); 1007 if (rc) 1008 return rc; 1009 1010 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1011 if (rc) 1012 return rc; 1013 1014 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1015 if (rc) 1016 goto err_start_tx; 1017 1018 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1019 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1020 rc = ena_rss_init_default(adapter); 1021 if (rc) 1022 goto err_rss_init; 1023 } 1024 1025 ena_stats_restart(dev); 1026 1027 adapter->timestamp_wd = rte_get_timer_cycles(); 1028 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1029 1030 ticks = rte_get_timer_hz(); 1031 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1032 ena_timer_wd_callback, adapter); 1033 1034 ++adapter->dev_stats.dev_start; 1035 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1036 1037 return 0; 1038 1039 err_rss_init: 1040 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1041 err_start_tx: 1042 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1043 return rc; 1044 } 1045 1046 static void ena_stop(struct rte_eth_dev *dev) 1047 { 1048 struct ena_adapter *adapter = dev->data->dev_private; 1049 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1050 int rc; 1051 1052 rte_timer_stop_sync(&adapter->timer_wd); 1053 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1054 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1055 1056 if (adapter->trigger_reset) { 1057 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1058 if (rc) 1059 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc); 1060 } 1061 1062 ++adapter->dev_stats.dev_stop; 1063 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1064 } 1065 1066 static int ena_create_io_queue(struct ena_ring *ring) 1067 { 1068 struct ena_adapter *adapter; 1069 struct ena_com_dev *ena_dev; 1070 struct ena_com_create_io_ctx ctx = 1071 /* policy set to _HOST just to satisfy icc compiler */ 1072 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1073 0, 0, 0, 0, 0 }; 1074 uint16_t ena_qid; 1075 unsigned int i; 1076 int rc; 1077 1078 adapter = ring->adapter; 1079 ena_dev = &adapter->ena_dev; 1080 1081 if (ring->type == ENA_RING_TYPE_TX) { 1082 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1083 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1084 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1085 ctx.queue_size = adapter->tx_ring_size; 1086 for (i = 0; i < ring->ring_size; i++) 1087 ring->empty_tx_reqs[i] = i; 1088 } else { 1089 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1090 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1091 ctx.queue_size = adapter->rx_ring_size; 1092 for (i = 0; i < ring->ring_size; i++) 1093 ring->empty_rx_reqs[i] = i; 1094 } 1095 ctx.qid = ena_qid; 1096 ctx.msix_vector = -1; /* interrupts not used */ 1097 ctx.numa_node = ring->numa_socket_id; 1098 1099 rc = ena_com_create_io_queue(ena_dev, &ctx); 1100 if (rc) { 1101 PMD_DRV_LOG(ERR, 1102 "failed to create io queue #%d (qid:%d) rc: %d\n", 1103 ring->id, ena_qid, rc); 1104 return rc; 1105 } 1106 1107 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1108 &ring->ena_com_io_sq, 1109 &ring->ena_com_io_cq); 1110 if (rc) { 1111 PMD_DRV_LOG(ERR, 1112 "Failed to get io queue handlers. queue num %d rc: %d\n", 1113 ring->id, rc); 1114 ena_com_destroy_io_queue(ena_dev, ena_qid); 1115 return rc; 1116 } 1117 1118 if (ring->type == ENA_RING_TYPE_TX) 1119 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1120 1121 return 0; 1122 } 1123 1124 static void ena_queue_stop(struct ena_ring *ring) 1125 { 1126 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1127 1128 if (ring->type == ENA_RING_TYPE_RX) { 1129 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1130 ena_rx_queue_release_bufs(ring); 1131 } else { 1132 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1133 ena_tx_queue_release_bufs(ring); 1134 } 1135 } 1136 1137 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1138 enum ena_ring_type ring_type) 1139 { 1140 struct ena_adapter *adapter = dev->data->dev_private; 1141 struct ena_ring *queues = NULL; 1142 uint16_t nb_queues, i; 1143 1144 if (ring_type == ENA_RING_TYPE_RX) { 1145 queues = adapter->rx_ring; 1146 nb_queues = dev->data->nb_rx_queues; 1147 } else { 1148 queues = adapter->tx_ring; 1149 nb_queues = dev->data->nb_tx_queues; 1150 } 1151 1152 for (i = 0; i < nb_queues; ++i) 1153 if (queues[i].configured) 1154 ena_queue_stop(&queues[i]); 1155 } 1156 1157 static int ena_queue_start(struct ena_ring *ring) 1158 { 1159 int rc, bufs_num; 1160 1161 ena_assert_msg(ring->configured == 1, 1162 "Trying to start unconfigured queue\n"); 1163 1164 rc = ena_create_io_queue(ring); 1165 if (rc) { 1166 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1167 return rc; 1168 } 1169 1170 ring->next_to_clean = 0; 1171 ring->next_to_use = 0; 1172 1173 if (ring->type == ENA_RING_TYPE_TX) { 1174 ring->tx_stats.available_desc = 1175 ena_com_free_q_entries(ring->ena_com_io_sq); 1176 return 0; 1177 } 1178 1179 bufs_num = ring->ring_size - 1; 1180 rc = ena_populate_rx_queue(ring, bufs_num); 1181 if (rc != bufs_num) { 1182 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1183 ENA_IO_RXQ_IDX(ring->id)); 1184 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1185 return ENA_COM_FAULT; 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1192 uint16_t queue_idx, 1193 uint16_t nb_desc, 1194 unsigned int socket_id, 1195 const struct rte_eth_txconf *tx_conf) 1196 { 1197 struct ena_ring *txq = NULL; 1198 struct ena_adapter *adapter = dev->data->dev_private; 1199 unsigned int i; 1200 1201 txq = &adapter->tx_ring[queue_idx]; 1202 1203 if (txq->configured) { 1204 PMD_DRV_LOG(CRIT, 1205 "API violation. Queue %d is already configured\n", 1206 queue_idx); 1207 return ENA_COM_FAULT; 1208 } 1209 1210 if (!rte_is_power_of_2(nb_desc)) { 1211 PMD_DRV_LOG(ERR, 1212 "Unsupported size of TX queue: %d is not a power of 2.\n", 1213 nb_desc); 1214 return -EINVAL; 1215 } 1216 1217 if (nb_desc > adapter->tx_ring_size) { 1218 PMD_DRV_LOG(ERR, 1219 "Unsupported size of TX queue (max size: %d)\n", 1220 adapter->tx_ring_size); 1221 return -EINVAL; 1222 } 1223 1224 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1225 nb_desc = adapter->tx_ring_size; 1226 1227 txq->port_id = dev->data->port_id; 1228 txq->next_to_clean = 0; 1229 txq->next_to_use = 0; 1230 txq->ring_size = nb_desc; 1231 txq->numa_socket_id = socket_id; 1232 1233 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1234 sizeof(struct ena_tx_buffer) * 1235 txq->ring_size, 1236 RTE_CACHE_LINE_SIZE); 1237 if (!txq->tx_buffer_info) { 1238 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n"); 1239 return -ENOMEM; 1240 } 1241 1242 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1243 sizeof(u16) * txq->ring_size, 1244 RTE_CACHE_LINE_SIZE); 1245 if (!txq->empty_tx_reqs) { 1246 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n"); 1247 rte_free(txq->tx_buffer_info); 1248 return -ENOMEM; 1249 } 1250 1251 txq->push_buf_intermediate_buf = 1252 rte_zmalloc("txq->push_buf_intermediate_buf", 1253 txq->tx_max_header_size, 1254 RTE_CACHE_LINE_SIZE); 1255 if (!txq->push_buf_intermediate_buf) { 1256 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n"); 1257 rte_free(txq->tx_buffer_info); 1258 rte_free(txq->empty_tx_reqs); 1259 return -ENOMEM; 1260 } 1261 1262 for (i = 0; i < txq->ring_size; i++) 1263 txq->empty_tx_reqs[i] = i; 1264 1265 if (tx_conf != NULL) { 1266 txq->offloads = 1267 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1268 } 1269 /* Store pointer to this queue in upper layer */ 1270 txq->configured = 1; 1271 dev->data->tx_queues[queue_idx] = txq; 1272 1273 return 0; 1274 } 1275 1276 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1277 uint16_t queue_idx, 1278 uint16_t nb_desc, 1279 unsigned int socket_id, 1280 __rte_unused const struct rte_eth_rxconf *rx_conf, 1281 struct rte_mempool *mp) 1282 { 1283 struct ena_adapter *adapter = dev->data->dev_private; 1284 struct ena_ring *rxq = NULL; 1285 size_t buffer_size; 1286 int i; 1287 1288 rxq = &adapter->rx_ring[queue_idx]; 1289 if (rxq->configured) { 1290 PMD_DRV_LOG(CRIT, 1291 "API violation. Queue %d is already configured\n", 1292 queue_idx); 1293 return ENA_COM_FAULT; 1294 } 1295 1296 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1297 nb_desc = adapter->rx_ring_size; 1298 1299 if (!rte_is_power_of_2(nb_desc)) { 1300 PMD_DRV_LOG(ERR, 1301 "Unsupported size of RX queue: %d is not a power of 2.\n", 1302 nb_desc); 1303 return -EINVAL; 1304 } 1305 1306 if (nb_desc > adapter->rx_ring_size) { 1307 PMD_DRV_LOG(ERR, 1308 "Unsupported size of RX queue (max size: %d)\n", 1309 adapter->rx_ring_size); 1310 return -EINVAL; 1311 } 1312 1313 /* ENA isn't supporting buffers smaller than 1400 bytes */ 1314 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1315 if (buffer_size < ENA_RX_BUF_MIN_SIZE) { 1316 PMD_DRV_LOG(ERR, 1317 "Unsupported size of RX buffer: %zu (min size: %d)\n", 1318 buffer_size, ENA_RX_BUF_MIN_SIZE); 1319 return -EINVAL; 1320 } 1321 1322 rxq->port_id = dev->data->port_id; 1323 rxq->next_to_clean = 0; 1324 rxq->next_to_use = 0; 1325 rxq->ring_size = nb_desc; 1326 rxq->numa_socket_id = socket_id; 1327 rxq->mb_pool = mp; 1328 1329 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1330 sizeof(struct rte_mbuf *) * nb_desc, 1331 RTE_CACHE_LINE_SIZE); 1332 if (!rxq->rx_buffer_info) { 1333 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n"); 1334 return -ENOMEM; 1335 } 1336 1337 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1338 sizeof(struct rte_mbuf *) * nb_desc, 1339 RTE_CACHE_LINE_SIZE); 1340 1341 if (!rxq->rx_refill_buffer) { 1342 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n"); 1343 rte_free(rxq->rx_buffer_info); 1344 rxq->rx_buffer_info = NULL; 1345 return -ENOMEM; 1346 } 1347 1348 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1349 sizeof(uint16_t) * nb_desc, 1350 RTE_CACHE_LINE_SIZE); 1351 if (!rxq->empty_rx_reqs) { 1352 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n"); 1353 rte_free(rxq->rx_buffer_info); 1354 rxq->rx_buffer_info = NULL; 1355 rte_free(rxq->rx_refill_buffer); 1356 rxq->rx_refill_buffer = NULL; 1357 return -ENOMEM; 1358 } 1359 1360 for (i = 0; i < nb_desc; i++) 1361 rxq->empty_rx_reqs[i] = i; 1362 1363 /* Store pointer to this queue in upper layer */ 1364 rxq->configured = 1; 1365 dev->data->rx_queues[queue_idx] = rxq; 1366 1367 return 0; 1368 } 1369 1370 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1371 { 1372 unsigned int i; 1373 int rc; 1374 uint16_t ring_size = rxq->ring_size; 1375 uint16_t ring_mask = ring_size - 1; 1376 uint16_t next_to_use = rxq->next_to_use; 1377 uint16_t in_use, req_id; 1378 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1379 1380 if (unlikely(!count)) 1381 return 0; 1382 1383 in_use = rxq->next_to_use - rxq->next_to_clean; 1384 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1385 1386 /* get resources for incoming packets */ 1387 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1388 if (unlikely(rc < 0)) { 1389 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1390 ++rxq->rx_stats.mbuf_alloc_fail; 1391 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1392 return 0; 1393 } 1394 1395 for (i = 0; i < count; i++) { 1396 uint16_t next_to_use_masked = next_to_use & ring_mask; 1397 struct rte_mbuf *mbuf = mbufs[i]; 1398 struct ena_com_buf ebuf; 1399 1400 if (likely((i + 4) < count)) 1401 rte_prefetch0(mbufs[i + 4]); 1402 1403 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1404 rc = validate_rx_req_id(rxq, req_id); 1405 if (unlikely(rc < 0)) 1406 break; 1407 rxq->rx_buffer_info[req_id] = mbuf; 1408 1409 /* prepare physical address for DMA transaction */ 1410 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1411 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1412 /* pass resource to device */ 1413 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1414 &ebuf, req_id); 1415 if (unlikely(rc)) { 1416 PMD_DRV_LOG(WARNING, "failed adding rx desc\n"); 1417 rxq->rx_buffer_info[req_id] = NULL; 1418 break; 1419 } 1420 next_to_use++; 1421 } 1422 1423 if (unlikely(i < count)) { 1424 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d " 1425 "buffers (from %d)\n", rxq->id, i, count); 1426 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1427 count - i); 1428 ++rxq->rx_stats.refill_partial; 1429 } 1430 1431 /* When we submitted free recources to device... */ 1432 if (likely(i > 0)) { 1433 /* ...let HW know that it can fill buffers with data 1434 * 1435 * Add memory barrier to make sure the desc were written before 1436 * issue a doorbell 1437 */ 1438 rte_wmb(); 1439 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1440 1441 rxq->next_to_use = next_to_use; 1442 } 1443 1444 return i; 1445 } 1446 1447 static int ena_device_init(struct ena_com_dev *ena_dev, 1448 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1449 bool *wd_state) 1450 { 1451 uint32_t aenq_groups; 1452 int rc; 1453 bool readless_supported; 1454 1455 /* Initialize mmio registers */ 1456 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1457 if (rc) { 1458 PMD_DRV_LOG(ERR, "failed to init mmio read less\n"); 1459 return rc; 1460 } 1461 1462 /* The PCIe configuration space revision id indicate if mmio reg 1463 * read is disabled. 1464 */ 1465 readless_supported = 1466 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1467 & ENA_MMIO_DISABLE_REG_READ); 1468 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1469 1470 /* reset device */ 1471 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1472 if (rc) { 1473 PMD_DRV_LOG(ERR, "cannot reset device\n"); 1474 goto err_mmio_read_less; 1475 } 1476 1477 /* check FW version */ 1478 rc = ena_com_validate_version(ena_dev); 1479 if (rc) { 1480 PMD_DRV_LOG(ERR, "device version is too low\n"); 1481 goto err_mmio_read_less; 1482 } 1483 1484 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1485 1486 /* ENA device administration layer init */ 1487 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1488 if (rc) { 1489 PMD_DRV_LOG(ERR, 1490 "cannot initialize ena admin queue with device\n"); 1491 goto err_mmio_read_less; 1492 } 1493 1494 /* To enable the msix interrupts the driver needs to know the number 1495 * of queues. So the driver uses polling mode to retrieve this 1496 * information. 1497 */ 1498 ena_com_set_admin_polling_mode(ena_dev, true); 1499 1500 ena_config_host_info(ena_dev); 1501 1502 /* Get Device Attributes and features */ 1503 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1504 if (rc) { 1505 PMD_DRV_LOG(ERR, 1506 "cannot get attribute for ena device rc= %d\n", rc); 1507 goto err_admin_init; 1508 } 1509 1510 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1511 BIT(ENA_ADMIN_NOTIFICATION) | 1512 BIT(ENA_ADMIN_KEEP_ALIVE) | 1513 BIT(ENA_ADMIN_FATAL_ERROR) | 1514 BIT(ENA_ADMIN_WARNING); 1515 1516 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1517 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1518 if (rc) { 1519 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc); 1520 goto err_admin_init; 1521 } 1522 1523 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1524 1525 return 0; 1526 1527 err_admin_init: 1528 ena_com_admin_destroy(ena_dev); 1529 1530 err_mmio_read_less: 1531 ena_com_mmio_reg_read_request_destroy(ena_dev); 1532 1533 return rc; 1534 } 1535 1536 static void ena_interrupt_handler_rte(void *cb_arg) 1537 { 1538 struct ena_adapter *adapter = cb_arg; 1539 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1540 1541 ena_com_admin_q_comp_intr_handler(ena_dev); 1542 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1543 ena_com_aenq_intr_handler(ena_dev, adapter); 1544 } 1545 1546 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1547 { 1548 if (!adapter->wd_state) 1549 return; 1550 1551 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1552 return; 1553 1554 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1555 adapter->keep_alive_timeout)) { 1556 PMD_DRV_LOG(ERR, "Keep alive timeout\n"); 1557 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1558 adapter->trigger_reset = true; 1559 ++adapter->dev_stats.wd_expired; 1560 } 1561 } 1562 1563 /* Check if admin queue is enabled */ 1564 static void check_for_admin_com_state(struct ena_adapter *adapter) 1565 { 1566 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1567 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n"); 1568 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1569 adapter->trigger_reset = true; 1570 } 1571 } 1572 1573 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1574 void *arg) 1575 { 1576 struct ena_adapter *adapter = arg; 1577 struct rte_eth_dev *dev = adapter->rte_dev; 1578 1579 check_for_missing_keep_alive(adapter); 1580 check_for_admin_com_state(adapter); 1581 1582 if (unlikely(adapter->trigger_reset)) { 1583 PMD_DRV_LOG(ERR, "Trigger reset is on\n"); 1584 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1585 NULL); 1586 } 1587 } 1588 1589 static inline void 1590 set_default_llq_configurations(struct ena_llq_configurations *llq_config) 1591 { 1592 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1593 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1594 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1595 llq_config->llq_num_decs_before_header = 1596 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1597 llq_config->llq_ring_entry_size_value = 128; 1598 } 1599 1600 static int 1601 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1602 struct ena_com_dev *ena_dev, 1603 struct ena_admin_feature_llq_desc *llq, 1604 struct ena_llq_configurations *llq_default_configurations) 1605 { 1606 int rc; 1607 u32 llq_feature_mask; 1608 1609 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1610 if (!(ena_dev->supported_features & llq_feature_mask)) { 1611 PMD_DRV_LOG(INFO, 1612 "LLQ is not supported. Fallback to host mode policy.\n"); 1613 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1614 return 0; 1615 } 1616 1617 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1618 if (unlikely(rc)) { 1619 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1620 "Fallback to host mode policy."); 1621 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1622 return 0; 1623 } 1624 1625 /* Nothing to config, exit */ 1626 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1627 return 0; 1628 1629 if (!adapter->dev_mem_base) { 1630 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. " 1631 "Fallback to host mode policy.\n."); 1632 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1633 return 0; 1634 } 1635 1636 ena_dev->mem_bar = adapter->dev_mem_base; 1637 1638 return 0; 1639 } 1640 1641 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, 1642 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1643 { 1644 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; 1645 1646 /* Regular queues capabilities */ 1647 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1648 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1649 &get_feat_ctx->max_queue_ext.max_queue_ext; 1650 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1651 max_queue_ext->max_rx_cq_num); 1652 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1653 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1654 } else { 1655 struct ena_admin_queue_feature_desc *max_queues = 1656 &get_feat_ctx->max_queues; 1657 io_tx_sq_num = max_queues->max_sq_num; 1658 io_tx_cq_num = max_queues->max_cq_num; 1659 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1660 } 1661 1662 /* In case of LLQ use the llq number in the get feature cmd */ 1663 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1664 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1665 1666 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1667 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); 1668 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); 1669 1670 if (unlikely(io_queue_num == 0)) { 1671 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n"); 1672 return -EFAULT; 1673 } 1674 1675 return io_queue_num; 1676 } 1677 1678 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1679 { 1680 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1681 struct rte_pci_device *pci_dev; 1682 struct rte_intr_handle *intr_handle; 1683 struct ena_adapter *adapter = eth_dev->data->dev_private; 1684 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1685 struct ena_com_dev_get_features_ctx get_feat_ctx; 1686 struct ena_llq_configurations llq_config; 1687 const char *queue_type_str; 1688 int rc; 1689 1690 static int adapters_found; 1691 bool wd_state; 1692 1693 eth_dev->dev_ops = &ena_dev_ops; 1694 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1695 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1696 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1697 1698 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1699 return 0; 1700 1701 memset(adapter, 0, sizeof(struct ena_adapter)); 1702 ena_dev = &adapter->ena_dev; 1703 1704 adapter->rte_eth_dev_data = eth_dev->data; 1705 adapter->rte_dev = eth_dev; 1706 1707 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1708 adapter->pdev = pci_dev; 1709 1710 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1711 pci_dev->addr.domain, 1712 pci_dev->addr.bus, 1713 pci_dev->addr.devid, 1714 pci_dev->addr.function); 1715 1716 intr_handle = &pci_dev->intr_handle; 1717 1718 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1719 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1720 1721 if (!adapter->regs) { 1722 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1723 ENA_REGS_BAR); 1724 return -ENXIO; 1725 } 1726 1727 ena_dev->reg_bar = adapter->regs; 1728 ena_dev->dmadev = adapter->pdev; 1729 1730 adapter->id_number = adapters_found; 1731 1732 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1733 adapter->id_number); 1734 1735 /* device specific initialization routine */ 1736 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1737 if (rc) { 1738 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1739 goto err; 1740 } 1741 adapter->wd_state = wd_state; 1742 1743 set_default_llq_configurations(&llq_config); 1744 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1745 &get_feat_ctx.llq, &llq_config); 1746 if (unlikely(rc)) { 1747 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1748 return rc; 1749 } 1750 1751 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1752 queue_type_str = "Regular"; 1753 else 1754 queue_type_str = "Low latency"; 1755 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); 1756 1757 calc_queue_ctx.ena_dev = ena_dev; 1758 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1759 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1760 &get_feat_ctx); 1761 1762 rc = ena_calc_queue_size(&calc_queue_ctx); 1763 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { 1764 rc = -EFAULT; 1765 goto err_device_destroy; 1766 } 1767 1768 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; 1769 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; 1770 1771 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1772 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1773 1774 /* prepare ring structures */ 1775 ena_init_rings(adapter); 1776 1777 ena_config_debug_area(adapter); 1778 1779 /* Set max MTU for this device */ 1780 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1781 1782 /* set device support for offloads */ 1783 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1784 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1785 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1786 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1787 adapter->offloads.rx_csum_supported = 1788 (get_feat_ctx.offload.rx_supported & 1789 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1790 1791 /* Copy MAC address and point DPDK to it */ 1792 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1793 rte_ether_addr_copy((struct rte_ether_addr *) 1794 get_feat_ctx.dev_attr.mac_addr, 1795 (struct rte_ether_addr *)adapter->mac_addr); 1796 1797 /* 1798 * Pass the information to the rte_eth_dev_close() that it should also 1799 * release the private port resources. 1800 */ 1801 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1802 1803 adapter->drv_stats = rte_zmalloc("adapter stats", 1804 sizeof(*adapter->drv_stats), 1805 RTE_CACHE_LINE_SIZE); 1806 if (!adapter->drv_stats) { 1807 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n"); 1808 rc = -ENOMEM; 1809 goto err_delete_debug_area; 1810 } 1811 1812 rte_intr_callback_register(intr_handle, 1813 ena_interrupt_handler_rte, 1814 adapter); 1815 rte_intr_enable(intr_handle); 1816 ena_com_set_admin_polling_mode(ena_dev, false); 1817 ena_com_admin_aenq_enable(ena_dev); 1818 1819 if (adapters_found == 0) 1820 rte_timer_subsystem_init(); 1821 rte_timer_init(&adapter->timer_wd); 1822 1823 adapters_found++; 1824 adapter->state = ENA_ADAPTER_STATE_INIT; 1825 1826 return 0; 1827 1828 err_delete_debug_area: 1829 ena_com_delete_debug_area(ena_dev); 1830 1831 err_device_destroy: 1832 ena_com_delete_host_info(ena_dev); 1833 ena_com_admin_destroy(ena_dev); 1834 1835 err: 1836 return rc; 1837 } 1838 1839 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1840 { 1841 struct ena_adapter *adapter = eth_dev->data->dev_private; 1842 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1843 1844 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1845 return; 1846 1847 ena_com_set_admin_running_state(ena_dev, false); 1848 1849 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1850 ena_close(eth_dev); 1851 1852 ena_com_delete_debug_area(ena_dev); 1853 ena_com_delete_host_info(ena_dev); 1854 1855 ena_com_abort_admin_commands(ena_dev); 1856 ena_com_wait_for_abort_completion(ena_dev); 1857 ena_com_admin_destroy(ena_dev); 1858 ena_com_mmio_reg_read_request_destroy(ena_dev); 1859 1860 adapter->state = ENA_ADAPTER_STATE_FREE; 1861 } 1862 1863 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1864 { 1865 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1866 return 0; 1867 1868 ena_destroy_device(eth_dev); 1869 1870 eth_dev->dev_ops = NULL; 1871 eth_dev->rx_pkt_burst = NULL; 1872 eth_dev->tx_pkt_burst = NULL; 1873 eth_dev->tx_pkt_prepare = NULL; 1874 1875 return 0; 1876 } 1877 1878 static int ena_dev_configure(struct rte_eth_dev *dev) 1879 { 1880 struct ena_adapter *adapter = dev->data->dev_private; 1881 1882 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1883 1884 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1885 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1886 return 0; 1887 } 1888 1889 static void ena_init_rings(struct ena_adapter *adapter) 1890 { 1891 int i; 1892 1893 for (i = 0; i < adapter->num_queues; i++) { 1894 struct ena_ring *ring = &adapter->tx_ring[i]; 1895 1896 ring->configured = 0; 1897 ring->type = ENA_RING_TYPE_TX; 1898 ring->adapter = adapter; 1899 ring->id = i; 1900 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1901 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1902 ring->sgl_size = adapter->max_tx_sgl_size; 1903 } 1904 1905 for (i = 0; i < adapter->num_queues; i++) { 1906 struct ena_ring *ring = &adapter->rx_ring[i]; 1907 1908 ring->configured = 0; 1909 ring->type = ENA_RING_TYPE_RX; 1910 ring->adapter = adapter; 1911 ring->id = i; 1912 ring->sgl_size = adapter->max_rx_sgl_size; 1913 } 1914 } 1915 1916 static int ena_infos_get(struct rte_eth_dev *dev, 1917 struct rte_eth_dev_info *dev_info) 1918 { 1919 struct ena_adapter *adapter; 1920 struct ena_com_dev *ena_dev; 1921 uint64_t rx_feat = 0, tx_feat = 0; 1922 1923 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1924 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1925 adapter = dev->data->dev_private; 1926 1927 ena_dev = &adapter->ena_dev; 1928 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1929 1930 dev_info->speed_capa = 1931 ETH_LINK_SPEED_1G | 1932 ETH_LINK_SPEED_2_5G | 1933 ETH_LINK_SPEED_5G | 1934 ETH_LINK_SPEED_10G | 1935 ETH_LINK_SPEED_25G | 1936 ETH_LINK_SPEED_40G | 1937 ETH_LINK_SPEED_50G | 1938 ETH_LINK_SPEED_100G; 1939 1940 /* Set Tx & Rx features available for device */ 1941 if (adapter->offloads.tso4_supported) 1942 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1943 1944 if (adapter->offloads.tx_csum_supported) 1945 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1946 DEV_TX_OFFLOAD_UDP_CKSUM | 1947 DEV_TX_OFFLOAD_TCP_CKSUM; 1948 1949 if (adapter->offloads.rx_csum_supported) 1950 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1951 DEV_RX_OFFLOAD_UDP_CKSUM | 1952 DEV_RX_OFFLOAD_TCP_CKSUM; 1953 1954 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1955 1956 /* Inform framework about available features */ 1957 dev_info->rx_offload_capa = rx_feat; 1958 dev_info->rx_queue_offload_capa = rx_feat; 1959 dev_info->tx_offload_capa = tx_feat; 1960 dev_info->tx_queue_offload_capa = tx_feat; 1961 1962 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1963 ETH_RSS_UDP; 1964 1965 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1966 dev_info->max_rx_pktlen = adapter->max_mtu; 1967 dev_info->max_mac_addrs = 1; 1968 1969 dev_info->max_rx_queues = adapter->num_queues; 1970 dev_info->max_tx_queues = adapter->num_queues; 1971 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1972 1973 adapter->tx_supported_offloads = tx_feat; 1974 adapter->rx_supported_offloads = rx_feat; 1975 1976 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; 1977 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1978 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1979 adapter->max_rx_sgl_size); 1980 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1981 adapter->max_rx_sgl_size); 1982 1983 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; 1984 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1985 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1986 adapter->max_tx_sgl_size); 1987 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1988 adapter->max_tx_sgl_size); 1989 1990 return 0; 1991 } 1992 1993 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1994 uint16_t nb_pkts) 1995 { 1996 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 1997 unsigned int ring_size = rx_ring->ring_size; 1998 unsigned int ring_mask = ring_size - 1; 1999 uint16_t next_to_clean = rx_ring->next_to_clean; 2000 uint16_t desc_in_use = 0; 2001 uint16_t req_id; 2002 unsigned int recv_idx = 0; 2003 struct rte_mbuf *mbuf = NULL; 2004 struct rte_mbuf *mbuf_head = NULL; 2005 struct rte_mbuf *mbuf_prev = NULL; 2006 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2007 unsigned int completed; 2008 2009 struct ena_com_rx_ctx ena_rx_ctx; 2010 int rc = 0; 2011 2012 /* Check adapter state */ 2013 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2014 PMD_DRV_LOG(ALERT, 2015 "Trying to receive pkts while device is NOT running\n"); 2016 return 0; 2017 } 2018 2019 desc_in_use = rx_ring->next_to_use - next_to_clean; 2020 if (unlikely(nb_pkts > desc_in_use)) 2021 nb_pkts = desc_in_use; 2022 2023 for (completed = 0; completed < nb_pkts; completed++) { 2024 int segments = 0; 2025 2026 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2027 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2028 ena_rx_ctx.descs = 0; 2029 ena_rx_ctx.pkt_offset = 0; 2030 /* receive packet context */ 2031 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2032 rx_ring->ena_com_io_sq, 2033 &ena_rx_ctx); 2034 if (unlikely(rc)) { 2035 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc); 2036 rx_ring->adapter->reset_reason = 2037 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2038 rx_ring->adapter->trigger_reset = true; 2039 ++rx_ring->rx_stats.bad_desc_num; 2040 return 0; 2041 } 2042 2043 if (unlikely(ena_rx_ctx.descs == 0)) 2044 break; 2045 2046 while (segments < ena_rx_ctx.descs) { 2047 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2048 rc = validate_rx_req_id(rx_ring, req_id); 2049 if (unlikely(rc)) { 2050 if (segments != 0) 2051 rte_mbuf_raw_free(mbuf_head); 2052 break; 2053 } 2054 2055 mbuf = rx_buff_info[req_id]; 2056 rx_buff_info[req_id] = NULL; 2057 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2058 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2059 mbuf->refcnt = 1; 2060 mbuf->next = NULL; 2061 if (unlikely(segments == 0)) { 2062 mbuf->nb_segs = ena_rx_ctx.descs; 2063 mbuf->port = rx_ring->port_id; 2064 mbuf->pkt_len = 0; 2065 mbuf->data_off += ena_rx_ctx.pkt_offset; 2066 mbuf_head = mbuf; 2067 } else { 2068 /* for multi-segment pkts create mbuf chain */ 2069 mbuf_prev->next = mbuf; 2070 } 2071 mbuf_head->pkt_len += mbuf->data_len; 2072 2073 mbuf_prev = mbuf; 2074 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2075 req_id; 2076 segments++; 2077 next_to_clean++; 2078 } 2079 if (unlikely(rc)) 2080 break; 2081 2082 /* fill mbuf attributes if any */ 2083 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2084 2085 if (unlikely(mbuf_head->ol_flags & 2086 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2087 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2088 ++rx_ring->rx_stats.bad_csum; 2089 } 2090 2091 mbuf_head->hash.rss = ena_rx_ctx.hash; 2092 2093 /* pass to DPDK application head mbuf */ 2094 rx_pkts[recv_idx] = mbuf_head; 2095 recv_idx++; 2096 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2097 } 2098 2099 rx_ring->rx_stats.cnt += recv_idx; 2100 rx_ring->next_to_clean = next_to_clean; 2101 2102 desc_in_use = desc_in_use - completed + 1; 2103 /* Burst refill to save doorbells, memory barriers, const interval */ 2104 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2105 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2106 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2107 } 2108 2109 return recv_idx; 2110 } 2111 2112 static uint16_t 2113 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2114 uint16_t nb_pkts) 2115 { 2116 int32_t ret; 2117 uint32_t i; 2118 struct rte_mbuf *m; 2119 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2120 struct rte_ipv4_hdr *ip_hdr; 2121 uint64_t ol_flags; 2122 uint16_t frag_field; 2123 2124 for (i = 0; i != nb_pkts; i++) { 2125 m = tx_pkts[i]; 2126 ol_flags = m->ol_flags; 2127 2128 if (!(ol_flags & PKT_TX_IPV4)) 2129 continue; 2130 2131 /* If there was not L2 header length specified, assume it is 2132 * length of the ethernet header. 2133 */ 2134 if (unlikely(m->l2_len == 0)) 2135 m->l2_len = sizeof(struct rte_ether_hdr); 2136 2137 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2138 m->l2_len); 2139 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2140 2141 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2142 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2143 2144 /* If IPv4 header has DF flag enabled and TSO support is 2145 * disabled, partial chcecksum should not be calculated. 2146 */ 2147 if (!tx_ring->adapter->offloads.tso4_supported) 2148 continue; 2149 } 2150 2151 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2152 (ol_flags & PKT_TX_L4_MASK) == 2153 PKT_TX_SCTP_CKSUM) { 2154 rte_errno = ENOTSUP; 2155 return i; 2156 } 2157 2158 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2159 ret = rte_validate_tx_offload(m); 2160 if (ret != 0) { 2161 rte_errno = -ret; 2162 return i; 2163 } 2164 #endif 2165 2166 /* In case we are supposed to TSO and have DF not set (DF=0) 2167 * hardware must be provided with partial checksum, otherwise 2168 * it will take care of necessary calculations. 2169 */ 2170 2171 ret = rte_net_intel_cksum_flags_prepare(m, 2172 ol_flags & ~PKT_TX_TCP_SEG); 2173 if (ret != 0) { 2174 rte_errno = -ret; 2175 return i; 2176 } 2177 } 2178 2179 return i; 2180 } 2181 2182 static void ena_update_hints(struct ena_adapter *adapter, 2183 struct ena_admin_ena_hw_hints *hints) 2184 { 2185 if (hints->admin_completion_tx_timeout) 2186 adapter->ena_dev.admin_queue.completion_timeout = 2187 hints->admin_completion_tx_timeout * 1000; 2188 2189 if (hints->mmio_read_timeout) 2190 /* convert to usec */ 2191 adapter->ena_dev.mmio_read.reg_read_to = 2192 hints->mmio_read_timeout * 1000; 2193 2194 if (hints->driver_watchdog_timeout) { 2195 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2196 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2197 else 2198 // Convert msecs to ticks 2199 adapter->keep_alive_timeout = 2200 (hints->driver_watchdog_timeout * 2201 rte_get_timer_hz()) / 1000; 2202 } 2203 } 2204 2205 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2206 struct rte_mbuf *mbuf) 2207 { 2208 struct ena_com_dev *ena_dev; 2209 int num_segments, header_len, rc; 2210 2211 ena_dev = &tx_ring->adapter->ena_dev; 2212 num_segments = mbuf->nb_segs; 2213 header_len = mbuf->data_len; 2214 2215 if (likely(num_segments < tx_ring->sgl_size)) 2216 return 0; 2217 2218 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2219 (num_segments == tx_ring->sgl_size) && 2220 (header_len < tx_ring->tx_max_header_size)) 2221 return 0; 2222 2223 ++tx_ring->tx_stats.linearize; 2224 rc = rte_pktmbuf_linearize(mbuf); 2225 if (unlikely(rc)) { 2226 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n"); 2227 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2228 ++tx_ring->tx_stats.linearize_failed; 2229 return rc; 2230 } 2231 2232 return rc; 2233 } 2234 2235 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2236 uint16_t nb_pkts) 2237 { 2238 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2239 uint16_t next_to_use = tx_ring->next_to_use; 2240 uint16_t next_to_clean = tx_ring->next_to_clean; 2241 struct rte_mbuf *mbuf; 2242 uint16_t seg_len; 2243 unsigned int ring_size = tx_ring->ring_size; 2244 unsigned int ring_mask = ring_size - 1; 2245 struct ena_com_tx_ctx ena_tx_ctx; 2246 struct ena_tx_buffer *tx_info; 2247 struct ena_com_buf *ebuf; 2248 uint16_t rc, req_id, total_tx_descs = 0; 2249 uint16_t sent_idx = 0, empty_tx_reqs; 2250 uint16_t push_len = 0; 2251 uint16_t delta = 0; 2252 int nb_hw_desc; 2253 uint32_t total_length; 2254 2255 /* Check adapter state */ 2256 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2257 PMD_DRV_LOG(ALERT, 2258 "Trying to xmit pkts while device is NOT running\n"); 2259 return 0; 2260 } 2261 2262 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2263 if (nb_pkts > empty_tx_reqs) 2264 nb_pkts = empty_tx_reqs; 2265 2266 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2267 mbuf = tx_pkts[sent_idx]; 2268 total_length = 0; 2269 2270 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2271 if (unlikely(rc)) 2272 break; 2273 2274 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2275 tx_info = &tx_ring->tx_buffer_info[req_id]; 2276 tx_info->mbuf = mbuf; 2277 tx_info->num_of_bufs = 0; 2278 ebuf = tx_info->bufs; 2279 2280 /* Prepare TX context */ 2281 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2282 memset(&ena_tx_ctx.ena_meta, 0x0, 2283 sizeof(struct ena_com_tx_meta)); 2284 ena_tx_ctx.ena_bufs = ebuf; 2285 ena_tx_ctx.req_id = req_id; 2286 2287 delta = 0; 2288 seg_len = mbuf->data_len; 2289 2290 if (tx_ring->tx_mem_queue_type == 2291 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2292 push_len = RTE_MIN(mbuf->pkt_len, 2293 tx_ring->tx_max_header_size); 2294 ena_tx_ctx.header_len = push_len; 2295 2296 if (likely(push_len <= seg_len)) { 2297 /* If the push header is in the single segment, 2298 * then just point it to the 1st mbuf data. 2299 */ 2300 ena_tx_ctx.push_header = 2301 rte_pktmbuf_mtod(mbuf, uint8_t *); 2302 } else { 2303 /* If the push header lays in the several 2304 * segments, copy it to the intermediate buffer. 2305 */ 2306 rte_pktmbuf_read(mbuf, 0, push_len, 2307 tx_ring->push_buf_intermediate_buf); 2308 ena_tx_ctx.push_header = 2309 tx_ring->push_buf_intermediate_buf; 2310 delta = push_len - seg_len; 2311 } 2312 } /* there's no else as we take advantage of memset zeroing */ 2313 2314 /* Set TX offloads flags, if applicable */ 2315 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2316 2317 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2318 2319 /* Process first segment taking into 2320 * consideration pushed header 2321 */ 2322 if (seg_len > push_len) { 2323 ebuf->paddr = mbuf->buf_iova + 2324 mbuf->data_off + 2325 push_len; 2326 ebuf->len = seg_len - push_len; 2327 ebuf++; 2328 tx_info->num_of_bufs++; 2329 } 2330 total_length += mbuf->data_len; 2331 2332 while ((mbuf = mbuf->next) != NULL) { 2333 seg_len = mbuf->data_len; 2334 2335 /* Skip mbufs if whole data is pushed as a header */ 2336 if (unlikely(delta > seg_len)) { 2337 delta -= seg_len; 2338 continue; 2339 } 2340 2341 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2342 ebuf->len = seg_len - delta; 2343 total_length += ebuf->len; 2344 ebuf++; 2345 tx_info->num_of_bufs++; 2346 2347 delta = 0; 2348 } 2349 2350 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2351 2352 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2353 &ena_tx_ctx)) { 2354 PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d" 2355 " achieved, writing doorbell to send burst\n", 2356 tx_ring->id); 2357 rte_wmb(); 2358 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2359 } 2360 2361 /* prepare the packet's descriptors to dma engine */ 2362 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2363 &ena_tx_ctx, &nb_hw_desc); 2364 if (unlikely(rc)) { 2365 ++tx_ring->tx_stats.prepare_ctx_err; 2366 break; 2367 } 2368 tx_info->tx_descs = nb_hw_desc; 2369 2370 next_to_use++; 2371 tx_ring->tx_stats.cnt++; 2372 tx_ring->tx_stats.bytes += total_length; 2373 } 2374 tx_ring->tx_stats.available_desc = 2375 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2376 2377 /* If there are ready packets to be xmitted... */ 2378 if (sent_idx > 0) { 2379 /* ...let HW do its best :-) */ 2380 rte_wmb(); 2381 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2382 tx_ring->tx_stats.doorbells++; 2383 tx_ring->next_to_use = next_to_use; 2384 } 2385 2386 /* Clear complete packets */ 2387 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2388 rc = validate_tx_req_id(tx_ring, req_id); 2389 if (rc) 2390 break; 2391 2392 /* Get Tx info & store how many descs were processed */ 2393 tx_info = &tx_ring->tx_buffer_info[req_id]; 2394 total_tx_descs += tx_info->tx_descs; 2395 2396 /* Free whole mbuf chain */ 2397 mbuf = tx_info->mbuf; 2398 rte_pktmbuf_free(mbuf); 2399 tx_info->mbuf = NULL; 2400 2401 /* Put back descriptor to the ring for reuse */ 2402 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2403 next_to_clean++; 2404 2405 /* If too many descs to clean, leave it for another run */ 2406 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2407 break; 2408 } 2409 tx_ring->tx_stats.available_desc = 2410 ena_com_free_q_entries(tx_ring->ena_com_io_sq); 2411 2412 if (total_tx_descs > 0) { 2413 /* acknowledge completion of sent packets */ 2414 tx_ring->next_to_clean = next_to_clean; 2415 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2416 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2417 } 2418 2419 tx_ring->tx_stats.tx_poll++; 2420 2421 return sent_idx; 2422 } 2423 2424 /** 2425 * DPDK callback to retrieve names of extended device statistics 2426 * 2427 * @param dev 2428 * Pointer to Ethernet device structure. 2429 * @param[out] xstats_names 2430 * Buffer to insert names into. 2431 * @param n 2432 * Number of names. 2433 * 2434 * @return 2435 * Number of xstats names. 2436 */ 2437 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2438 struct rte_eth_xstat_name *xstats_names, 2439 unsigned int n) 2440 { 2441 unsigned int xstats_count = ena_xstats_calc_num(dev); 2442 unsigned int stat, i, count = 0; 2443 2444 if (n < xstats_count || !xstats_names) 2445 return xstats_count; 2446 2447 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2448 strcpy(xstats_names[count].name, 2449 ena_stats_global_strings[stat].name); 2450 2451 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2452 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2453 snprintf(xstats_names[count].name, 2454 sizeof(xstats_names[count].name), 2455 "rx_q%d_%s", i, 2456 ena_stats_rx_strings[stat].name); 2457 2458 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2459 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2460 snprintf(xstats_names[count].name, 2461 sizeof(xstats_names[count].name), 2462 "tx_q%d_%s", i, 2463 ena_stats_tx_strings[stat].name); 2464 2465 return xstats_count; 2466 } 2467 2468 /** 2469 * DPDK callback to get extended device statistics. 2470 * 2471 * @param dev 2472 * Pointer to Ethernet device structure. 2473 * @param[out] stats 2474 * Stats table output buffer. 2475 * @param n 2476 * The size of the stats table. 2477 * 2478 * @return 2479 * Number of xstats on success, negative on failure. 2480 */ 2481 static int ena_xstats_get(struct rte_eth_dev *dev, 2482 struct rte_eth_xstat *xstats, 2483 unsigned int n) 2484 { 2485 struct ena_adapter *adapter = dev->data->dev_private; 2486 unsigned int xstats_count = ena_xstats_calc_num(dev); 2487 unsigned int stat, i, count = 0; 2488 int stat_offset; 2489 void *stats_begin; 2490 2491 if (n < xstats_count) 2492 return xstats_count; 2493 2494 if (!xstats) 2495 return 0; 2496 2497 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2498 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2499 stats_begin = &adapter->dev_stats; 2500 2501 xstats[count].id = count; 2502 xstats[count].value = *((uint64_t *) 2503 ((char *)stats_begin + stat_offset)); 2504 } 2505 2506 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2507 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2508 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2509 stats_begin = &adapter->rx_ring[i].rx_stats; 2510 2511 xstats[count].id = count; 2512 xstats[count].value = *((uint64_t *) 2513 ((char *)stats_begin + stat_offset)); 2514 } 2515 } 2516 2517 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2518 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2519 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2520 stats_begin = &adapter->tx_ring[i].rx_stats; 2521 2522 xstats[count].id = count; 2523 xstats[count].value = *((uint64_t *) 2524 ((char *)stats_begin + stat_offset)); 2525 } 2526 } 2527 2528 return count; 2529 } 2530 2531 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2532 const uint64_t *ids, 2533 uint64_t *values, 2534 unsigned int n) 2535 { 2536 struct ena_adapter *adapter = dev->data->dev_private; 2537 uint64_t id; 2538 uint64_t rx_entries, tx_entries; 2539 unsigned int i; 2540 int qid; 2541 int valid = 0; 2542 for (i = 0; i < n; ++i) { 2543 id = ids[i]; 2544 /* Check if id belongs to global statistics */ 2545 if (id < ENA_STATS_ARRAY_GLOBAL) { 2546 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2547 ++valid; 2548 continue; 2549 } 2550 2551 /* Check if id belongs to rx queue statistics */ 2552 id -= ENA_STATS_ARRAY_GLOBAL; 2553 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2554 if (id < rx_entries) { 2555 qid = id % dev->data->nb_rx_queues; 2556 id /= dev->data->nb_rx_queues; 2557 values[i] = *((uint64_t *) 2558 &adapter->rx_ring[qid].rx_stats + id); 2559 ++valid; 2560 continue; 2561 } 2562 /* Check if id belongs to rx queue statistics */ 2563 id -= rx_entries; 2564 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2565 if (id < tx_entries) { 2566 qid = id % dev->data->nb_tx_queues; 2567 id /= dev->data->nb_tx_queues; 2568 values[i] = *((uint64_t *) 2569 &adapter->tx_ring[qid].tx_stats + id); 2570 ++valid; 2571 continue; 2572 } 2573 } 2574 2575 return valid; 2576 } 2577 2578 /********************************************************************* 2579 * PMD configuration 2580 *********************************************************************/ 2581 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2582 struct rte_pci_device *pci_dev) 2583 { 2584 return rte_eth_dev_pci_generic_probe(pci_dev, 2585 sizeof(struct ena_adapter), eth_ena_dev_init); 2586 } 2587 2588 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2589 { 2590 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2591 } 2592 2593 static struct rte_pci_driver rte_ena_pmd = { 2594 .id_table = pci_id_ena_map, 2595 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2596 RTE_PCI_DRV_WC_ACTIVATE, 2597 .probe = eth_ena_pci_probe, 2598 .remove = eth_ena_pci_remove, 2599 }; 2600 2601 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2602 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2603 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2604 2605 RTE_INIT(ena_init_log) 2606 { 2607 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2608 if (ena_logtype_init >= 0) 2609 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2610 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2611 if (ena_logtype_driver >= 0) 2612 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2613 2614 #ifdef RTE_LIBRTE_ENA_DEBUG_RX 2615 ena_logtype_rx = rte_log_register("pmd.net.ena.rx"); 2616 if (ena_logtype_rx >= 0) 2617 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE); 2618 #endif 2619 2620 #ifdef RTE_LIBRTE_ENA_DEBUG_TX 2621 ena_logtype_tx = rte_log_register("pmd.net.ena.tx"); 2622 if (ena_logtype_tx >= 0) 2623 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE); 2624 #endif 2625 2626 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE 2627 ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free"); 2628 if (ena_logtype_tx_free >= 0) 2629 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE); 2630 #endif 2631 2632 #ifdef RTE_LIBRTE_ENA_COM_DEBUG 2633 ena_logtype_com = rte_log_register("pmd.net.ena.com"); 2634 if (ena_logtype_com >= 0) 2635 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE); 2636 #endif 2637 } 2638 2639 /****************************************************************************** 2640 ******************************** AENQ Handlers ******************************* 2641 *****************************************************************************/ 2642 static void ena_update_on_link_change(void *adapter_data, 2643 struct ena_admin_aenq_entry *aenq_e) 2644 { 2645 struct rte_eth_dev *eth_dev; 2646 struct ena_adapter *adapter; 2647 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2648 uint32_t status; 2649 2650 adapter = adapter_data; 2651 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2652 eth_dev = adapter->rte_dev; 2653 2654 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2655 adapter->link_status = status; 2656 2657 ena_link_update(eth_dev, 0); 2658 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2659 } 2660 2661 static void ena_notification(void *data, 2662 struct ena_admin_aenq_entry *aenq_e) 2663 { 2664 struct ena_adapter *adapter = data; 2665 struct ena_admin_ena_hw_hints *hints; 2666 2667 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2668 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n", 2669 aenq_e->aenq_common_desc.group, 2670 ENA_ADMIN_NOTIFICATION); 2671 2672 switch (aenq_e->aenq_common_desc.syndrom) { 2673 case ENA_ADMIN_UPDATE_HINTS: 2674 hints = (struct ena_admin_ena_hw_hints *) 2675 (&aenq_e->inline_data_w4); 2676 ena_update_hints(adapter, hints); 2677 break; 2678 default: 2679 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", 2680 aenq_e->aenq_common_desc.syndrom); 2681 } 2682 } 2683 2684 static void ena_keep_alive(void *adapter_data, 2685 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2686 { 2687 struct ena_adapter *adapter = adapter_data; 2688 struct ena_admin_aenq_keep_alive_desc *desc; 2689 uint64_t rx_drops; 2690 2691 adapter->timestamp_wd = rte_get_timer_cycles(); 2692 2693 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2694 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2695 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2696 } 2697 2698 /** 2699 * This handler will called for unknown event group or unimplemented handlers 2700 **/ 2701 static void unimplemented_aenq_handler(__rte_unused void *data, 2702 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2703 { 2704 PMD_DRV_LOG(ERR, "Unknown event was received or event with " 2705 "unimplemented handler\n"); 2706 } 2707 2708 static struct ena_aenq_handlers aenq_handlers = { 2709 .handlers = { 2710 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2711 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2712 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2713 }, 2714 .unimplemented_handler = unimplemented_aenq_handler 2715 }; 2716