1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_string_fns.h> 35 #include <rte_ether.h> 36 #include <rte_ethdev_driver.h> 37 #include <rte_ethdev_pci.h> 38 #include <rte_tcp.h> 39 #include <rte_atomic.h> 40 #include <rte_dev.h> 41 #include <rte_errno.h> 42 #include <rte_version.h> 43 #include <rte_net.h> 44 45 #include "ena_ethdev.h" 46 #include "ena_logs.h" 47 #include "ena_platform.h" 48 #include "ena_com.h" 49 #include "ena_eth_com.h" 50 51 #include <ena_common_defs.h> 52 #include <ena_regs_defs.h> 53 #include <ena_admin_defs.h> 54 #include <ena_eth_io_defs.h> 55 56 #define DRV_MODULE_VER_MAJOR 2 57 #define DRV_MODULE_VER_MINOR 0 58 #define DRV_MODULE_VER_SUBMINOR 0 59 60 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 62 /*reverse version of ENA_IO_RXQ_IDX*/ 63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 64 65 /* While processing submitted and completed descriptors (rx and tx path 66 * respectively) in a loop it is desired to: 67 * - perform batch submissions while populating sumbissmion queue 68 * - avoid blocking transmission of other packets during cleanup phase 69 * Hence the utilization ratio of 1/8 of a queue size. 70 */ 71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 72 73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 75 76 #define GET_L4_HDR_LEN(mbuf) \ 77 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 79 80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 82 #define ENA_HASH_KEY_SIZE 40 83 #define ETH_GSTRING_LEN 32 84 85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 86 87 #define ENA_MIN_RING_DESC 128 88 89 enum ethtool_stringset { 90 ETH_SS_TEST = 0, 91 ETH_SS_STATS, 92 }; 93 94 struct ena_stats { 95 char name[ETH_GSTRING_LEN]; 96 int stat_offset; 97 }; 98 99 #define ENA_STAT_ENTRY(stat, stat_type) { \ 100 .name = #stat, \ 101 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 102 } 103 104 #define ENA_STAT_RX_ENTRY(stat) \ 105 ENA_STAT_ENTRY(stat, rx) 106 107 #define ENA_STAT_TX_ENTRY(stat) \ 108 ENA_STAT_ENTRY(stat, tx) 109 110 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 111 ENA_STAT_ENTRY(stat, dev) 112 113 #define ENA_MAX_RING_SIZE_RX 8192 114 #define ENA_MAX_RING_SIZE_TX 1024 115 116 /* 117 * Each rte_memzone should have unique name. 118 * To satisfy it, count number of allocation and add it to name. 119 */ 120 uint32_t ena_alloc_cnt; 121 122 static const struct ena_stats ena_stats_global_strings[] = { 123 ENA_STAT_GLOBAL_ENTRY(wd_expired), 124 ENA_STAT_GLOBAL_ENTRY(dev_start), 125 ENA_STAT_GLOBAL_ENTRY(dev_stop), 126 }; 127 128 static const struct ena_stats ena_stats_tx_strings[] = { 129 ENA_STAT_TX_ENTRY(cnt), 130 ENA_STAT_TX_ENTRY(bytes), 131 ENA_STAT_TX_ENTRY(prepare_ctx_err), 132 ENA_STAT_TX_ENTRY(linearize), 133 ENA_STAT_TX_ENTRY(linearize_failed), 134 ENA_STAT_TX_ENTRY(tx_poll), 135 ENA_STAT_TX_ENTRY(doorbells), 136 ENA_STAT_TX_ENTRY(bad_req_id), 137 ENA_STAT_TX_ENTRY(available_desc), 138 }; 139 140 static const struct ena_stats ena_stats_rx_strings[] = { 141 ENA_STAT_RX_ENTRY(cnt), 142 ENA_STAT_RX_ENTRY(bytes), 143 ENA_STAT_RX_ENTRY(refill_partial), 144 ENA_STAT_RX_ENTRY(bad_csum), 145 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 146 ENA_STAT_RX_ENTRY(bad_desc_num), 147 ENA_STAT_RX_ENTRY(bad_req_id), 148 }; 149 150 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 151 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 152 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 153 154 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 155 DEV_TX_OFFLOAD_UDP_CKSUM |\ 156 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 157 DEV_TX_OFFLOAD_TCP_TSO) 158 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 159 PKT_TX_IP_CKSUM |\ 160 PKT_TX_TCP_SEG) 161 162 /** Vendor ID used by Amazon devices */ 163 #define PCI_VENDOR_ID_AMAZON 0x1D0F 164 /** Amazon devices */ 165 #define PCI_DEVICE_ID_ENA_VF 0xEC20 166 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 167 168 #define ENA_TX_OFFLOAD_MASK (\ 169 PKT_TX_L4_MASK | \ 170 PKT_TX_IPV6 | \ 171 PKT_TX_IPV4 | \ 172 PKT_TX_IP_CKSUM | \ 173 PKT_TX_TCP_SEG) 174 175 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 176 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 177 178 int ena_logtype_init; 179 int ena_logtype_driver; 180 181 static const struct rte_pci_id pci_id_ena_map[] = { 182 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 183 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 184 { .device_id = 0 }, 185 }; 186 187 static struct ena_aenq_handlers aenq_handlers; 188 189 static int ena_device_init(struct ena_com_dev *ena_dev, 190 struct ena_com_dev_get_features_ctx *get_feat_ctx, 191 bool *wd_state); 192 static int ena_dev_configure(struct rte_eth_dev *dev); 193 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 194 uint16_t nb_pkts); 195 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 196 uint16_t nb_pkts); 197 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 198 uint16_t nb_desc, unsigned int socket_id, 199 const struct rte_eth_txconf *tx_conf); 200 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 201 uint16_t nb_desc, unsigned int socket_id, 202 const struct rte_eth_rxconf *rx_conf, 203 struct rte_mempool *mp); 204 static uint16_t eth_ena_recv_pkts(void *rx_queue, 205 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 206 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 207 static void ena_init_rings(struct ena_adapter *adapter); 208 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 209 static int ena_start(struct rte_eth_dev *dev); 210 static void ena_stop(struct rte_eth_dev *dev); 211 static void ena_close(struct rte_eth_dev *dev); 212 static int ena_dev_reset(struct rte_eth_dev *dev); 213 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 214 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 215 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 216 static void ena_rx_queue_release(void *queue); 217 static void ena_tx_queue_release(void *queue); 218 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 219 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 220 static int ena_link_update(struct rte_eth_dev *dev, 221 int wait_to_complete); 222 static int ena_create_io_queue(struct ena_ring *ring); 223 static void ena_queue_stop(struct ena_ring *ring); 224 static void ena_queue_stop_all(struct rte_eth_dev *dev, 225 enum ena_ring_type ring_type); 226 static int ena_queue_start(struct ena_ring *ring); 227 static int ena_queue_start_all(struct rte_eth_dev *dev, 228 enum ena_ring_type ring_type); 229 static void ena_stats_restart(struct rte_eth_dev *dev); 230 static void ena_infos_get(struct rte_eth_dev *dev, 231 struct rte_eth_dev_info *dev_info); 232 static int ena_rss_reta_update(struct rte_eth_dev *dev, 233 struct rte_eth_rss_reta_entry64 *reta_conf, 234 uint16_t reta_size); 235 static int ena_rss_reta_query(struct rte_eth_dev *dev, 236 struct rte_eth_rss_reta_entry64 *reta_conf, 237 uint16_t reta_size); 238 static void ena_interrupt_handler_rte(void *cb_arg); 239 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 240 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 241 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 242 static int ena_xstats_get_names(struct rte_eth_dev *dev, 243 struct rte_eth_xstat_name *xstats_names, 244 unsigned int n); 245 static int ena_xstats_get(struct rte_eth_dev *dev, 246 struct rte_eth_xstat *stats, 247 unsigned int n); 248 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 249 const uint64_t *ids, 250 uint64_t *values, 251 unsigned int n); 252 253 static const struct eth_dev_ops ena_dev_ops = { 254 .dev_configure = ena_dev_configure, 255 .dev_infos_get = ena_infos_get, 256 .rx_queue_setup = ena_rx_queue_setup, 257 .tx_queue_setup = ena_tx_queue_setup, 258 .dev_start = ena_start, 259 .dev_stop = ena_stop, 260 .link_update = ena_link_update, 261 .stats_get = ena_stats_get, 262 .xstats_get_names = ena_xstats_get_names, 263 .xstats_get = ena_xstats_get, 264 .xstats_get_by_id = ena_xstats_get_by_id, 265 .mtu_set = ena_mtu_set, 266 .rx_queue_release = ena_rx_queue_release, 267 .tx_queue_release = ena_tx_queue_release, 268 .dev_close = ena_close, 269 .dev_reset = ena_dev_reset, 270 .reta_update = ena_rss_reta_update, 271 .reta_query = ena_rss_reta_query, 272 }; 273 274 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 275 struct ena_com_rx_ctx *ena_rx_ctx) 276 { 277 uint64_t ol_flags = 0; 278 uint32_t packet_type = 0; 279 280 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 281 packet_type |= RTE_PTYPE_L4_TCP; 282 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 283 packet_type |= RTE_PTYPE_L4_UDP; 284 285 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 286 packet_type |= RTE_PTYPE_L3_IPV4; 287 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 288 packet_type |= RTE_PTYPE_L3_IPV6; 289 290 if (unlikely(ena_rx_ctx->l4_csum_err)) 291 ol_flags |= PKT_RX_L4_CKSUM_BAD; 292 if (unlikely(ena_rx_ctx->l3_csum_err)) 293 ol_flags |= PKT_RX_IP_CKSUM_BAD; 294 295 mbuf->ol_flags = ol_flags; 296 mbuf->packet_type = packet_type; 297 } 298 299 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 300 struct ena_com_tx_ctx *ena_tx_ctx, 301 uint64_t queue_offloads) 302 { 303 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 304 305 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 306 (queue_offloads & QUEUE_OFFLOADS)) { 307 /* check if TSO is required */ 308 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 309 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 310 ena_tx_ctx->tso_enable = true; 311 312 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 313 } 314 315 /* check if L3 checksum is needed */ 316 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 317 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 318 ena_tx_ctx->l3_csum_enable = true; 319 320 if (mbuf->ol_flags & PKT_TX_IPV6) { 321 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 322 } else { 323 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 324 325 /* set don't fragment (DF) flag */ 326 if (mbuf->packet_type & 327 (RTE_PTYPE_L4_NONFRAG 328 | RTE_PTYPE_INNER_L4_NONFRAG)) 329 ena_tx_ctx->df = true; 330 } 331 332 /* check if L4 checksum is needed */ 333 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) && 334 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 335 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 336 ena_tx_ctx->l4_csum_enable = true; 337 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) && 338 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 339 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 340 ena_tx_ctx->l4_csum_enable = true; 341 } else { 342 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 343 ena_tx_ctx->l4_csum_enable = false; 344 } 345 346 ena_meta->mss = mbuf->tso_segsz; 347 ena_meta->l3_hdr_len = mbuf->l3_len; 348 ena_meta->l3_hdr_offset = mbuf->l2_len; 349 350 ena_tx_ctx->meta_valid = true; 351 } else { 352 ena_tx_ctx->meta_valid = false; 353 } 354 } 355 356 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 357 { 358 if (likely(req_id < rx_ring->ring_size)) 359 return 0; 360 361 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id); 362 363 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 364 rx_ring->adapter->trigger_reset = true; 365 ++rx_ring->rx_stats.bad_req_id; 366 367 return -EFAULT; 368 } 369 370 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 371 { 372 struct ena_tx_buffer *tx_info = NULL; 373 374 if (likely(req_id < tx_ring->ring_size)) { 375 tx_info = &tx_ring->tx_buffer_info[req_id]; 376 if (likely(tx_info->mbuf)) 377 return 0; 378 } 379 380 if (tx_info) 381 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n"); 382 else 383 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id); 384 385 /* Trigger device reset */ 386 ++tx_ring->tx_stats.bad_req_id; 387 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 388 tx_ring->adapter->trigger_reset = true; 389 return -EFAULT; 390 } 391 392 static void ena_config_host_info(struct ena_com_dev *ena_dev) 393 { 394 struct ena_admin_host_info *host_info; 395 int rc; 396 397 /* Allocate only the host info */ 398 rc = ena_com_allocate_host_info(ena_dev); 399 if (rc) { 400 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 401 return; 402 } 403 404 host_info = ena_dev->host_attr.host_info; 405 406 host_info->os_type = ENA_ADMIN_OS_DPDK; 407 host_info->kernel_ver = RTE_VERSION; 408 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 409 sizeof(host_info->kernel_ver_str)); 410 host_info->os_dist = RTE_VERSION; 411 strlcpy((char *)host_info->os_dist_str, rte_version(), 412 sizeof(host_info->os_dist_str)); 413 host_info->driver_version = 414 (DRV_MODULE_VER_MAJOR) | 415 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 416 (DRV_MODULE_VER_SUBMINOR << 417 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 418 host_info->num_cpus = rte_lcore_count(); 419 420 rc = ena_com_set_host_attributes(ena_dev); 421 if (rc) { 422 if (rc == -ENA_COM_UNSUPPORTED) 423 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 424 else 425 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 426 427 goto err; 428 } 429 430 return; 431 432 err: 433 ena_com_delete_host_info(ena_dev); 434 } 435 436 /* This function calculates the number of xstats based on the current config */ 437 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 438 { 439 return ENA_STATS_ARRAY_GLOBAL + 440 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 441 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 442 } 443 444 static void ena_config_debug_area(struct ena_adapter *adapter) 445 { 446 u32 debug_area_size; 447 int rc, ss_count; 448 449 ss_count = ena_xstats_calc_num(adapter->rte_dev); 450 451 /* allocate 32 bytes for each string and 64bit for the value */ 452 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 453 454 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 455 if (rc) { 456 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 457 return; 458 } 459 460 rc = ena_com_set_host_attributes(&adapter->ena_dev); 461 if (rc) { 462 if (rc == -ENA_COM_UNSUPPORTED) 463 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 464 else 465 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 466 467 goto err; 468 } 469 470 return; 471 err: 472 ena_com_delete_debug_area(&adapter->ena_dev); 473 } 474 475 static void ena_close(struct rte_eth_dev *dev) 476 { 477 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 478 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 479 struct ena_adapter *adapter = dev->data->dev_private; 480 481 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 482 ena_stop(dev); 483 adapter->state = ENA_ADAPTER_STATE_CLOSED; 484 485 ena_rx_queue_release_all(dev); 486 ena_tx_queue_release_all(dev); 487 488 rte_free(adapter->drv_stats); 489 adapter->drv_stats = NULL; 490 491 rte_intr_disable(intr_handle); 492 rte_intr_callback_unregister(intr_handle, 493 ena_interrupt_handler_rte, 494 adapter); 495 496 /* 497 * MAC is not allocated dynamically. Setting NULL should prevent from 498 * release of the resource in the rte_eth_dev_release_port(). 499 */ 500 dev->data->mac_addrs = NULL; 501 } 502 503 static int 504 ena_dev_reset(struct rte_eth_dev *dev) 505 { 506 int rc = 0; 507 508 ena_destroy_device(dev); 509 rc = eth_ena_dev_init(dev); 510 if (rc) 511 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 512 513 return rc; 514 } 515 516 static int ena_rss_reta_update(struct rte_eth_dev *dev, 517 struct rte_eth_rss_reta_entry64 *reta_conf, 518 uint16_t reta_size) 519 { 520 struct ena_adapter *adapter = dev->data->dev_private; 521 struct ena_com_dev *ena_dev = &adapter->ena_dev; 522 int rc, i; 523 u16 entry_value; 524 int conf_idx; 525 int idx; 526 527 if ((reta_size == 0) || (reta_conf == NULL)) 528 return -EINVAL; 529 530 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 531 RTE_LOG(WARNING, PMD, 532 "indirection table %d is bigger than supported (%d)\n", 533 reta_size, ENA_RX_RSS_TABLE_SIZE); 534 return -EINVAL; 535 } 536 537 for (i = 0 ; i < reta_size ; i++) { 538 /* each reta_conf is for 64 entries. 539 * to support 128 we use 2 conf of 64 540 */ 541 conf_idx = i / RTE_RETA_GROUP_SIZE; 542 idx = i % RTE_RETA_GROUP_SIZE; 543 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 544 entry_value = 545 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 546 547 rc = ena_com_indirect_table_fill_entry(ena_dev, 548 i, 549 entry_value); 550 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 551 RTE_LOG(ERR, PMD, 552 "Cannot fill indirect table\n"); 553 return rc; 554 } 555 } 556 } 557 558 rc = ena_com_indirect_table_set(ena_dev); 559 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 560 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 561 return rc; 562 } 563 564 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 565 __func__, reta_size, adapter->rte_dev->data->port_id); 566 567 return 0; 568 } 569 570 /* Query redirection table. */ 571 static int ena_rss_reta_query(struct rte_eth_dev *dev, 572 struct rte_eth_rss_reta_entry64 *reta_conf, 573 uint16_t reta_size) 574 { 575 struct ena_adapter *adapter = dev->data->dev_private; 576 struct ena_com_dev *ena_dev = &adapter->ena_dev; 577 int rc; 578 int i; 579 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 580 int reta_conf_idx; 581 int reta_idx; 582 583 if (reta_size == 0 || reta_conf == NULL || 584 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 585 return -EINVAL; 586 587 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 588 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 589 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 590 return -ENOTSUP; 591 } 592 593 for (i = 0 ; i < reta_size ; i++) { 594 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 595 reta_idx = i % RTE_RETA_GROUP_SIZE; 596 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 597 reta_conf[reta_conf_idx].reta[reta_idx] = 598 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 599 } 600 601 return 0; 602 } 603 604 static int ena_rss_init_default(struct ena_adapter *adapter) 605 { 606 struct ena_com_dev *ena_dev = &adapter->ena_dev; 607 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 608 int rc, i; 609 u32 val; 610 611 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 612 if (unlikely(rc)) { 613 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 614 goto err_rss_init; 615 } 616 617 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 618 val = i % nb_rx_queues; 619 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 620 ENA_IO_RXQ_IDX(val)); 621 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 622 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 623 goto err_fill_indir; 624 } 625 } 626 627 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 628 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 629 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 630 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 631 goto err_fill_indir; 632 } 633 634 rc = ena_com_set_default_hash_ctrl(ena_dev); 635 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 636 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 637 goto err_fill_indir; 638 } 639 640 rc = ena_com_indirect_table_set(ena_dev); 641 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 642 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 643 goto err_fill_indir; 644 } 645 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 646 adapter->rte_dev->data->port_id); 647 648 return 0; 649 650 err_fill_indir: 651 ena_com_rss_destroy(ena_dev); 652 err_rss_init: 653 654 return rc; 655 } 656 657 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 658 { 659 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 660 int nb_queues = dev->data->nb_rx_queues; 661 int i; 662 663 for (i = 0; i < nb_queues; i++) 664 ena_rx_queue_release(queues[i]); 665 } 666 667 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 668 { 669 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 670 int nb_queues = dev->data->nb_tx_queues; 671 int i; 672 673 for (i = 0; i < nb_queues; i++) 674 ena_tx_queue_release(queues[i]); 675 } 676 677 static void ena_rx_queue_release(void *queue) 678 { 679 struct ena_ring *ring = (struct ena_ring *)queue; 680 681 /* Free ring resources */ 682 if (ring->rx_buffer_info) 683 rte_free(ring->rx_buffer_info); 684 ring->rx_buffer_info = NULL; 685 686 if (ring->rx_refill_buffer) 687 rte_free(ring->rx_refill_buffer); 688 ring->rx_refill_buffer = NULL; 689 690 if (ring->empty_rx_reqs) 691 rte_free(ring->empty_rx_reqs); 692 ring->empty_rx_reqs = NULL; 693 694 ring->configured = 0; 695 696 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 697 ring->port_id, ring->id); 698 } 699 700 static void ena_tx_queue_release(void *queue) 701 { 702 struct ena_ring *ring = (struct ena_ring *)queue; 703 704 /* Free ring resources */ 705 if (ring->push_buf_intermediate_buf) 706 rte_free(ring->push_buf_intermediate_buf); 707 708 if (ring->tx_buffer_info) 709 rte_free(ring->tx_buffer_info); 710 711 if (ring->empty_tx_reqs) 712 rte_free(ring->empty_tx_reqs); 713 714 ring->empty_tx_reqs = NULL; 715 ring->tx_buffer_info = NULL; 716 ring->push_buf_intermediate_buf = NULL; 717 718 ring->configured = 0; 719 720 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 721 ring->port_id, ring->id); 722 } 723 724 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 725 { 726 unsigned int i; 727 728 for (i = 0; i < ring->ring_size; ++i) 729 if (ring->rx_buffer_info[i]) { 730 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 731 ring->rx_buffer_info[i] = NULL; 732 } 733 } 734 735 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 736 { 737 unsigned int i; 738 739 for (i = 0; i < ring->ring_size; ++i) { 740 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 741 742 if (tx_buf->mbuf) 743 rte_pktmbuf_free(tx_buf->mbuf); 744 } 745 } 746 747 static int ena_link_update(struct rte_eth_dev *dev, 748 __rte_unused int wait_to_complete) 749 { 750 struct rte_eth_link *link = &dev->data->dev_link; 751 struct ena_adapter *adapter = dev->data->dev_private; 752 753 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 754 link->link_speed = ETH_SPEED_NUM_NONE; 755 link->link_duplex = ETH_LINK_FULL_DUPLEX; 756 757 return 0; 758 } 759 760 static int ena_queue_start_all(struct rte_eth_dev *dev, 761 enum ena_ring_type ring_type) 762 { 763 struct ena_adapter *adapter = dev->data->dev_private; 764 struct ena_ring *queues = NULL; 765 int nb_queues; 766 int i = 0; 767 int rc = 0; 768 769 if (ring_type == ENA_RING_TYPE_RX) { 770 queues = adapter->rx_ring; 771 nb_queues = dev->data->nb_rx_queues; 772 } else { 773 queues = adapter->tx_ring; 774 nb_queues = dev->data->nb_tx_queues; 775 } 776 for (i = 0; i < nb_queues; i++) { 777 if (queues[i].configured) { 778 if (ring_type == ENA_RING_TYPE_RX) { 779 ena_assert_msg( 780 dev->data->rx_queues[i] == &queues[i], 781 "Inconsistent state of rx queues\n"); 782 } else { 783 ena_assert_msg( 784 dev->data->tx_queues[i] == &queues[i], 785 "Inconsistent state of tx queues\n"); 786 } 787 788 rc = ena_queue_start(&queues[i]); 789 790 if (rc) { 791 PMD_INIT_LOG(ERR, 792 "failed to start queue %d type(%d)", 793 i, ring_type); 794 goto err; 795 } 796 } 797 } 798 799 return 0; 800 801 err: 802 while (i--) 803 if (queues[i].configured) 804 ena_queue_stop(&queues[i]); 805 806 return rc; 807 } 808 809 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 810 { 811 uint32_t max_frame_len = adapter->max_mtu; 812 813 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 814 DEV_RX_OFFLOAD_JUMBO_FRAME) 815 max_frame_len = 816 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 817 818 return max_frame_len; 819 } 820 821 static int ena_check_valid_conf(struct ena_adapter *adapter) 822 { 823 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 824 825 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 826 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 827 "max mtu: %d, min mtu: %d", 828 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 829 return ENA_COM_UNSUPPORTED; 830 } 831 832 return 0; 833 } 834 835 static int 836 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) 837 { 838 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 839 struct ena_com_dev *ena_dev = ctx->ena_dev; 840 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; 841 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; 842 843 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 844 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 845 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 846 rx_queue_size = RTE_MIN(rx_queue_size, 847 max_queue_ext->max_rx_cq_depth); 848 rx_queue_size = RTE_MIN(rx_queue_size, 849 max_queue_ext->max_rx_sq_depth); 850 tx_queue_size = RTE_MIN(tx_queue_size, 851 max_queue_ext->max_tx_cq_depth); 852 853 if (ena_dev->tx_mem_queue_type == 854 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 855 tx_queue_size = RTE_MIN(tx_queue_size, 856 llq->max_llq_depth); 857 } else { 858 tx_queue_size = RTE_MIN(tx_queue_size, 859 max_queue_ext->max_tx_sq_depth); 860 } 861 862 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 863 max_queue_ext->max_per_packet_rx_descs); 864 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 865 max_queue_ext->max_per_packet_tx_descs); 866 } else { 867 struct ena_admin_queue_feature_desc *max_queues = 868 &ctx->get_feat_ctx->max_queues; 869 rx_queue_size = RTE_MIN(rx_queue_size, 870 max_queues->max_cq_depth); 871 rx_queue_size = RTE_MIN(rx_queue_size, 872 max_queues->max_sq_depth); 873 tx_queue_size = RTE_MIN(tx_queue_size, 874 max_queues->max_cq_depth); 875 876 if (ena_dev->tx_mem_queue_type == 877 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 878 tx_queue_size = RTE_MIN(tx_queue_size, 879 llq->max_llq_depth); 880 } else { 881 tx_queue_size = RTE_MIN(tx_queue_size, 882 max_queues->max_sq_depth); 883 } 884 885 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 886 max_queues->max_packet_tx_descs); 887 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 888 max_queues->max_packet_rx_descs); 889 } 890 891 /* Round down to the nearest power of 2 */ 892 rx_queue_size = rte_align32prevpow2(rx_queue_size); 893 tx_queue_size = rte_align32prevpow2(tx_queue_size); 894 895 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { 896 PMD_INIT_LOG(ERR, "Invalid queue size"); 897 return -EFAULT; 898 } 899 900 ctx->rx_queue_size = rx_queue_size; 901 ctx->tx_queue_size = tx_queue_size; 902 903 return 0; 904 } 905 906 static void ena_stats_restart(struct rte_eth_dev *dev) 907 { 908 struct ena_adapter *adapter = dev->data->dev_private; 909 910 rte_atomic64_init(&adapter->drv_stats->ierrors); 911 rte_atomic64_init(&adapter->drv_stats->oerrors); 912 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 913 rte_atomic64_init(&adapter->drv_stats->rx_drops); 914 } 915 916 static int ena_stats_get(struct rte_eth_dev *dev, 917 struct rte_eth_stats *stats) 918 { 919 struct ena_admin_basic_stats ena_stats; 920 struct ena_adapter *adapter = dev->data->dev_private; 921 struct ena_com_dev *ena_dev = &adapter->ena_dev; 922 int rc; 923 int i; 924 int max_rings_stats; 925 926 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 927 return -ENOTSUP; 928 929 memset(&ena_stats, 0, sizeof(ena_stats)); 930 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 931 if (unlikely(rc)) { 932 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n"); 933 return rc; 934 } 935 936 /* Set of basic statistics from ENA */ 937 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 938 ena_stats.rx_pkts_low); 939 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 940 ena_stats.tx_pkts_low); 941 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 942 ena_stats.rx_bytes_low); 943 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 944 ena_stats.tx_bytes_low); 945 946 /* Driver related stats */ 947 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 948 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 949 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 950 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 951 952 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 953 RTE_ETHDEV_QUEUE_STAT_CNTRS); 954 for (i = 0; i < max_rings_stats; ++i) { 955 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 956 957 stats->q_ibytes[i] = rx_stats->bytes; 958 stats->q_ipackets[i] = rx_stats->cnt; 959 stats->q_errors[i] = rx_stats->bad_desc_num + 960 rx_stats->bad_req_id; 961 } 962 963 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 964 RTE_ETHDEV_QUEUE_STAT_CNTRS); 965 for (i = 0; i < max_rings_stats; ++i) { 966 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 967 968 stats->q_obytes[i] = tx_stats->bytes; 969 stats->q_opackets[i] = tx_stats->cnt; 970 } 971 972 return 0; 973 } 974 975 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 976 { 977 struct ena_adapter *adapter; 978 struct ena_com_dev *ena_dev; 979 int rc = 0; 980 981 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 982 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 983 adapter = dev->data->dev_private; 984 985 ena_dev = &adapter->ena_dev; 986 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 987 988 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 989 RTE_LOG(ERR, PMD, 990 "Invalid MTU setting. new_mtu: %d " 991 "max mtu: %d min mtu: %d\n", 992 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 993 return -EINVAL; 994 } 995 996 rc = ena_com_set_dev_mtu(ena_dev, mtu); 997 if (rc) 998 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 999 else 1000 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 1001 1002 return rc; 1003 } 1004 1005 static int ena_start(struct rte_eth_dev *dev) 1006 { 1007 struct ena_adapter *adapter = dev->data->dev_private; 1008 uint64_t ticks; 1009 int rc = 0; 1010 1011 rc = ena_check_valid_conf(adapter); 1012 if (rc) 1013 return rc; 1014 1015 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1016 if (rc) 1017 return rc; 1018 1019 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1020 if (rc) 1021 goto err_start_tx; 1022 1023 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1024 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1025 rc = ena_rss_init_default(adapter); 1026 if (rc) 1027 goto err_rss_init; 1028 } 1029 1030 ena_stats_restart(dev); 1031 1032 adapter->timestamp_wd = rte_get_timer_cycles(); 1033 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1034 1035 ticks = rte_get_timer_hz(); 1036 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1037 ena_timer_wd_callback, adapter); 1038 1039 ++adapter->dev_stats.dev_start; 1040 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1041 1042 return 0; 1043 1044 err_rss_init: 1045 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1046 err_start_tx: 1047 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1048 return rc; 1049 } 1050 1051 static void ena_stop(struct rte_eth_dev *dev) 1052 { 1053 struct ena_adapter *adapter = dev->data->dev_private; 1054 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1055 int rc; 1056 1057 rte_timer_stop_sync(&adapter->timer_wd); 1058 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1059 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1060 1061 if (adapter->trigger_reset) { 1062 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1063 if (rc) 1064 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc); 1065 } 1066 1067 ++adapter->dev_stats.dev_stop; 1068 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1069 } 1070 1071 static int ena_create_io_queue(struct ena_ring *ring) 1072 { 1073 struct ena_adapter *adapter; 1074 struct ena_com_dev *ena_dev; 1075 struct ena_com_create_io_ctx ctx = 1076 /* policy set to _HOST just to satisfy icc compiler */ 1077 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1078 0, 0, 0, 0, 0 }; 1079 uint16_t ena_qid; 1080 unsigned int i; 1081 int rc; 1082 1083 adapter = ring->adapter; 1084 ena_dev = &adapter->ena_dev; 1085 1086 if (ring->type == ENA_RING_TYPE_TX) { 1087 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1088 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1089 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1090 ctx.queue_size = adapter->tx_ring_size; 1091 for (i = 0; i < ring->ring_size; i++) 1092 ring->empty_tx_reqs[i] = i; 1093 } else { 1094 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1095 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1096 ctx.queue_size = adapter->rx_ring_size; 1097 for (i = 0; i < ring->ring_size; i++) 1098 ring->empty_rx_reqs[i] = i; 1099 } 1100 ctx.qid = ena_qid; 1101 ctx.msix_vector = -1; /* interrupts not used */ 1102 ctx.numa_node = ring->numa_socket_id; 1103 1104 rc = ena_com_create_io_queue(ena_dev, &ctx); 1105 if (rc) { 1106 RTE_LOG(ERR, PMD, 1107 "failed to create io queue #%d (qid:%d) rc: %d\n", 1108 ring->id, ena_qid, rc); 1109 return rc; 1110 } 1111 1112 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1113 &ring->ena_com_io_sq, 1114 &ring->ena_com_io_cq); 1115 if (rc) { 1116 RTE_LOG(ERR, PMD, 1117 "Failed to get io queue handlers. queue num %d rc: %d\n", 1118 ring->id, rc); 1119 ena_com_destroy_io_queue(ena_dev, ena_qid); 1120 return rc; 1121 } 1122 1123 if (ring->type == ENA_RING_TYPE_TX) 1124 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1125 1126 return 0; 1127 } 1128 1129 static void ena_queue_stop(struct ena_ring *ring) 1130 { 1131 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1132 1133 if (ring->type == ENA_RING_TYPE_RX) { 1134 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1135 ena_rx_queue_release_bufs(ring); 1136 } else { 1137 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1138 ena_tx_queue_release_bufs(ring); 1139 } 1140 } 1141 1142 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1143 enum ena_ring_type ring_type) 1144 { 1145 struct ena_adapter *adapter = dev->data->dev_private; 1146 struct ena_ring *queues = NULL; 1147 uint16_t nb_queues, i; 1148 1149 if (ring_type == ENA_RING_TYPE_RX) { 1150 queues = adapter->rx_ring; 1151 nb_queues = dev->data->nb_rx_queues; 1152 } else { 1153 queues = adapter->tx_ring; 1154 nb_queues = dev->data->nb_tx_queues; 1155 } 1156 1157 for (i = 0; i < nb_queues; ++i) 1158 if (queues[i].configured) 1159 ena_queue_stop(&queues[i]); 1160 } 1161 1162 static int ena_queue_start(struct ena_ring *ring) 1163 { 1164 int rc, bufs_num; 1165 1166 ena_assert_msg(ring->configured == 1, 1167 "Trying to start unconfigured queue\n"); 1168 1169 rc = ena_create_io_queue(ring); 1170 if (rc) { 1171 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1172 return rc; 1173 } 1174 1175 ring->next_to_clean = 0; 1176 ring->next_to_use = 0; 1177 1178 if (ring->type == ENA_RING_TYPE_TX) { 1179 ring->tx_stats.available_desc = 1180 ena_com_free_desc(ring->ena_com_io_sq); 1181 return 0; 1182 } 1183 1184 bufs_num = ring->ring_size - 1; 1185 rc = ena_populate_rx_queue(ring, bufs_num); 1186 if (rc != bufs_num) { 1187 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1188 ENA_IO_RXQ_IDX(ring->id)); 1189 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1190 return ENA_COM_FAULT; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1197 uint16_t queue_idx, 1198 uint16_t nb_desc, 1199 unsigned int socket_id, 1200 const struct rte_eth_txconf *tx_conf) 1201 { 1202 struct ena_ring *txq = NULL; 1203 struct ena_adapter *adapter = dev->data->dev_private; 1204 unsigned int i; 1205 1206 txq = &adapter->tx_ring[queue_idx]; 1207 1208 if (txq->configured) { 1209 RTE_LOG(CRIT, PMD, 1210 "API violation. Queue %d is already configured\n", 1211 queue_idx); 1212 return ENA_COM_FAULT; 1213 } 1214 1215 if (!rte_is_power_of_2(nb_desc)) { 1216 RTE_LOG(ERR, PMD, 1217 "Unsupported size of TX queue: %d is not a power of 2.\n", 1218 nb_desc); 1219 return -EINVAL; 1220 } 1221 1222 if (nb_desc > adapter->tx_ring_size) { 1223 RTE_LOG(ERR, PMD, 1224 "Unsupported size of TX queue (max size: %d)\n", 1225 adapter->tx_ring_size); 1226 return -EINVAL; 1227 } 1228 1229 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1230 nb_desc = adapter->tx_ring_size; 1231 1232 txq->port_id = dev->data->port_id; 1233 txq->next_to_clean = 0; 1234 txq->next_to_use = 0; 1235 txq->ring_size = nb_desc; 1236 txq->numa_socket_id = socket_id; 1237 1238 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1239 sizeof(struct ena_tx_buffer) * 1240 txq->ring_size, 1241 RTE_CACHE_LINE_SIZE); 1242 if (!txq->tx_buffer_info) { 1243 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1244 return -ENOMEM; 1245 } 1246 1247 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1248 sizeof(u16) * txq->ring_size, 1249 RTE_CACHE_LINE_SIZE); 1250 if (!txq->empty_tx_reqs) { 1251 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1252 rte_free(txq->tx_buffer_info); 1253 return -ENOMEM; 1254 } 1255 1256 txq->push_buf_intermediate_buf = 1257 rte_zmalloc("txq->push_buf_intermediate_buf", 1258 txq->tx_max_header_size, 1259 RTE_CACHE_LINE_SIZE); 1260 if (!txq->push_buf_intermediate_buf) { 1261 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n"); 1262 rte_free(txq->tx_buffer_info); 1263 rte_free(txq->empty_tx_reqs); 1264 return -ENOMEM; 1265 } 1266 1267 for (i = 0; i < txq->ring_size; i++) 1268 txq->empty_tx_reqs[i] = i; 1269 1270 if (tx_conf != NULL) { 1271 txq->offloads = 1272 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1273 } 1274 /* Store pointer to this queue in upper layer */ 1275 txq->configured = 1; 1276 dev->data->tx_queues[queue_idx] = txq; 1277 1278 return 0; 1279 } 1280 1281 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1282 uint16_t queue_idx, 1283 uint16_t nb_desc, 1284 unsigned int socket_id, 1285 __rte_unused const struct rte_eth_rxconf *rx_conf, 1286 struct rte_mempool *mp) 1287 { 1288 struct ena_adapter *adapter = dev->data->dev_private; 1289 struct ena_ring *rxq = NULL; 1290 int i; 1291 1292 rxq = &adapter->rx_ring[queue_idx]; 1293 if (rxq->configured) { 1294 RTE_LOG(CRIT, PMD, 1295 "API violation. Queue %d is already configured\n", 1296 queue_idx); 1297 return ENA_COM_FAULT; 1298 } 1299 1300 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1301 nb_desc = adapter->rx_ring_size; 1302 1303 if (!rte_is_power_of_2(nb_desc)) { 1304 RTE_LOG(ERR, PMD, 1305 "Unsupported size of RX queue: %d is not a power of 2.\n", 1306 nb_desc); 1307 return -EINVAL; 1308 } 1309 1310 if (nb_desc > adapter->rx_ring_size) { 1311 RTE_LOG(ERR, PMD, 1312 "Unsupported size of RX queue (max size: %d)\n", 1313 adapter->rx_ring_size); 1314 return -EINVAL; 1315 } 1316 1317 rxq->port_id = dev->data->port_id; 1318 rxq->next_to_clean = 0; 1319 rxq->next_to_use = 0; 1320 rxq->ring_size = nb_desc; 1321 rxq->numa_socket_id = socket_id; 1322 rxq->mb_pool = mp; 1323 1324 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1325 sizeof(struct rte_mbuf *) * nb_desc, 1326 RTE_CACHE_LINE_SIZE); 1327 if (!rxq->rx_buffer_info) { 1328 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1329 return -ENOMEM; 1330 } 1331 1332 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1333 sizeof(struct rte_mbuf *) * nb_desc, 1334 RTE_CACHE_LINE_SIZE); 1335 1336 if (!rxq->rx_refill_buffer) { 1337 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n"); 1338 rte_free(rxq->rx_buffer_info); 1339 rxq->rx_buffer_info = NULL; 1340 return -ENOMEM; 1341 } 1342 1343 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1344 sizeof(uint16_t) * nb_desc, 1345 RTE_CACHE_LINE_SIZE); 1346 if (!rxq->empty_rx_reqs) { 1347 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n"); 1348 rte_free(rxq->rx_buffer_info); 1349 rxq->rx_buffer_info = NULL; 1350 rte_free(rxq->rx_refill_buffer); 1351 rxq->rx_refill_buffer = NULL; 1352 return -ENOMEM; 1353 } 1354 1355 for (i = 0; i < nb_desc; i++) 1356 rxq->empty_rx_reqs[i] = i; 1357 1358 /* Store pointer to this queue in upper layer */ 1359 rxq->configured = 1; 1360 dev->data->rx_queues[queue_idx] = rxq; 1361 1362 return 0; 1363 } 1364 1365 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1366 { 1367 unsigned int i; 1368 int rc; 1369 uint16_t ring_size = rxq->ring_size; 1370 uint16_t ring_mask = ring_size - 1; 1371 uint16_t next_to_use = rxq->next_to_use; 1372 uint16_t in_use, req_id; 1373 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1374 1375 if (unlikely(!count)) 1376 return 0; 1377 1378 in_use = rxq->next_to_use - rxq->next_to_clean; 1379 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1380 1381 /* get resources for incoming packets */ 1382 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1383 if (unlikely(rc < 0)) { 1384 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1385 ++rxq->rx_stats.mbuf_alloc_fail; 1386 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1387 return 0; 1388 } 1389 1390 for (i = 0; i < count; i++) { 1391 uint16_t next_to_use_masked = next_to_use & ring_mask; 1392 struct rte_mbuf *mbuf = mbufs[i]; 1393 struct ena_com_buf ebuf; 1394 1395 if (likely((i + 4) < count)) 1396 rte_prefetch0(mbufs[i + 4]); 1397 1398 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1399 rc = validate_rx_req_id(rxq, req_id); 1400 if (unlikely(rc < 0)) 1401 break; 1402 rxq->rx_buffer_info[req_id] = mbuf; 1403 1404 /* prepare physical address for DMA transaction */ 1405 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1406 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1407 /* pass resource to device */ 1408 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1409 &ebuf, req_id); 1410 if (unlikely(rc)) { 1411 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1412 rxq->rx_buffer_info[req_id] = NULL; 1413 break; 1414 } 1415 next_to_use++; 1416 } 1417 1418 if (unlikely(i < count)) { 1419 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d " 1420 "buffers (from %d)\n", rxq->id, i, count); 1421 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1422 count - i); 1423 ++rxq->rx_stats.refill_partial; 1424 } 1425 1426 /* When we submitted free recources to device... */ 1427 if (likely(i > 0)) { 1428 /* ...let HW know that it can fill buffers with data 1429 * 1430 * Add memory barrier to make sure the desc were written before 1431 * issue a doorbell 1432 */ 1433 rte_wmb(); 1434 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1435 1436 rxq->next_to_use = next_to_use; 1437 } 1438 1439 return i; 1440 } 1441 1442 static int ena_device_init(struct ena_com_dev *ena_dev, 1443 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1444 bool *wd_state) 1445 { 1446 uint32_t aenq_groups; 1447 int rc; 1448 bool readless_supported; 1449 1450 /* Initialize mmio registers */ 1451 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1452 if (rc) { 1453 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1454 return rc; 1455 } 1456 1457 /* The PCIe configuration space revision id indicate if mmio reg 1458 * read is disabled. 1459 */ 1460 readless_supported = 1461 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1462 & ENA_MMIO_DISABLE_REG_READ); 1463 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1464 1465 /* reset device */ 1466 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1467 if (rc) { 1468 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1469 goto err_mmio_read_less; 1470 } 1471 1472 /* check FW version */ 1473 rc = ena_com_validate_version(ena_dev); 1474 if (rc) { 1475 RTE_LOG(ERR, PMD, "device version is too low\n"); 1476 goto err_mmio_read_less; 1477 } 1478 1479 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1480 1481 /* ENA device administration layer init */ 1482 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1483 if (rc) { 1484 RTE_LOG(ERR, PMD, 1485 "cannot initialize ena admin queue with device\n"); 1486 goto err_mmio_read_less; 1487 } 1488 1489 /* To enable the msix interrupts the driver needs to know the number 1490 * of queues. So the driver uses polling mode to retrieve this 1491 * information. 1492 */ 1493 ena_com_set_admin_polling_mode(ena_dev, true); 1494 1495 ena_config_host_info(ena_dev); 1496 1497 /* Get Device Attributes and features */ 1498 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1499 if (rc) { 1500 RTE_LOG(ERR, PMD, 1501 "cannot get attribute for ena device rc= %d\n", rc); 1502 goto err_admin_init; 1503 } 1504 1505 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1506 BIT(ENA_ADMIN_NOTIFICATION) | 1507 BIT(ENA_ADMIN_KEEP_ALIVE) | 1508 BIT(ENA_ADMIN_FATAL_ERROR) | 1509 BIT(ENA_ADMIN_WARNING); 1510 1511 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1512 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1513 if (rc) { 1514 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc); 1515 goto err_admin_init; 1516 } 1517 1518 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1519 1520 return 0; 1521 1522 err_admin_init: 1523 ena_com_admin_destroy(ena_dev); 1524 1525 err_mmio_read_less: 1526 ena_com_mmio_reg_read_request_destroy(ena_dev); 1527 1528 return rc; 1529 } 1530 1531 static void ena_interrupt_handler_rte(void *cb_arg) 1532 { 1533 struct ena_adapter *adapter = cb_arg; 1534 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1535 1536 ena_com_admin_q_comp_intr_handler(ena_dev); 1537 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1538 ena_com_aenq_intr_handler(ena_dev, adapter); 1539 } 1540 1541 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1542 { 1543 if (!adapter->wd_state) 1544 return; 1545 1546 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1547 return; 1548 1549 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1550 adapter->keep_alive_timeout)) { 1551 RTE_LOG(ERR, PMD, "Keep alive timeout\n"); 1552 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1553 adapter->trigger_reset = true; 1554 ++adapter->dev_stats.wd_expired; 1555 } 1556 } 1557 1558 /* Check if admin queue is enabled */ 1559 static void check_for_admin_com_state(struct ena_adapter *adapter) 1560 { 1561 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1562 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n"); 1563 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1564 adapter->trigger_reset = true; 1565 } 1566 } 1567 1568 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1569 void *arg) 1570 { 1571 struct ena_adapter *adapter = arg; 1572 struct rte_eth_dev *dev = adapter->rte_dev; 1573 1574 check_for_missing_keep_alive(adapter); 1575 check_for_admin_com_state(adapter); 1576 1577 if (unlikely(adapter->trigger_reset)) { 1578 RTE_LOG(ERR, PMD, "Trigger reset is on\n"); 1579 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1580 NULL); 1581 } 1582 } 1583 1584 static inline void 1585 set_default_llq_configurations(struct ena_llq_configurations *llq_config) 1586 { 1587 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1588 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1589 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1590 llq_config->llq_num_decs_before_header = 1591 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1592 llq_config->llq_ring_entry_size_value = 128; 1593 } 1594 1595 static int 1596 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1597 struct ena_com_dev *ena_dev, 1598 struct ena_admin_feature_llq_desc *llq, 1599 struct ena_llq_configurations *llq_default_configurations) 1600 { 1601 int rc; 1602 u32 llq_feature_mask; 1603 1604 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1605 if (!(ena_dev->supported_features & llq_feature_mask)) { 1606 RTE_LOG(INFO, PMD, 1607 "LLQ is not supported. Fallback to host mode policy.\n"); 1608 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1609 return 0; 1610 } 1611 1612 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1613 if (unlikely(rc)) { 1614 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1615 "Fallback to host mode policy."); 1616 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1617 return 0; 1618 } 1619 1620 /* Nothing to config, exit */ 1621 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1622 return 0; 1623 1624 if (!adapter->dev_mem_base) { 1625 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. " 1626 "Fallback to host mode policy.\n."); 1627 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1628 return 0; 1629 } 1630 1631 ena_dev->mem_bar = adapter->dev_mem_base; 1632 1633 return 0; 1634 } 1635 1636 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, 1637 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1638 { 1639 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; 1640 1641 /* Regular queues capabilities */ 1642 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1643 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1644 &get_feat_ctx->max_queue_ext.max_queue_ext; 1645 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1646 max_queue_ext->max_rx_cq_num); 1647 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1648 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1649 } else { 1650 struct ena_admin_queue_feature_desc *max_queues = 1651 &get_feat_ctx->max_queues; 1652 io_tx_sq_num = max_queues->max_sq_num; 1653 io_tx_cq_num = max_queues->max_cq_num; 1654 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1655 } 1656 1657 /* In case of LLQ use the llq number in the get feature cmd */ 1658 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1659 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1660 1661 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1662 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); 1663 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); 1664 1665 if (unlikely(io_queue_num == 0)) { 1666 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n"); 1667 return -EFAULT; 1668 } 1669 1670 return io_queue_num; 1671 } 1672 1673 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1674 { 1675 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1676 struct rte_pci_device *pci_dev; 1677 struct rte_intr_handle *intr_handle; 1678 struct ena_adapter *adapter = eth_dev->data->dev_private; 1679 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1680 struct ena_com_dev_get_features_ctx get_feat_ctx; 1681 struct ena_llq_configurations llq_config; 1682 const char *queue_type_str; 1683 int rc; 1684 1685 static int adapters_found; 1686 bool wd_state; 1687 1688 eth_dev->dev_ops = &ena_dev_ops; 1689 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1690 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1691 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1692 1693 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1694 return 0; 1695 1696 memset(adapter, 0, sizeof(struct ena_adapter)); 1697 ena_dev = &adapter->ena_dev; 1698 1699 adapter->rte_eth_dev_data = eth_dev->data; 1700 adapter->rte_dev = eth_dev; 1701 1702 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1703 adapter->pdev = pci_dev; 1704 1705 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1706 pci_dev->addr.domain, 1707 pci_dev->addr.bus, 1708 pci_dev->addr.devid, 1709 pci_dev->addr.function); 1710 1711 intr_handle = &pci_dev->intr_handle; 1712 1713 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1714 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1715 1716 if (!adapter->regs) { 1717 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1718 ENA_REGS_BAR); 1719 return -ENXIO; 1720 } 1721 1722 ena_dev->reg_bar = adapter->regs; 1723 ena_dev->dmadev = adapter->pdev; 1724 1725 adapter->id_number = adapters_found; 1726 1727 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1728 adapter->id_number); 1729 1730 /* device specific initialization routine */ 1731 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1732 if (rc) { 1733 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1734 goto err; 1735 } 1736 adapter->wd_state = wd_state; 1737 1738 set_default_llq_configurations(&llq_config); 1739 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1740 &get_feat_ctx.llq, &llq_config); 1741 if (unlikely(rc)) { 1742 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1743 return rc; 1744 } 1745 1746 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1747 queue_type_str = "Regular"; 1748 else 1749 queue_type_str = "Low latency"; 1750 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str); 1751 1752 calc_queue_ctx.ena_dev = ena_dev; 1753 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1754 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1755 &get_feat_ctx); 1756 1757 rc = ena_calc_queue_size(&calc_queue_ctx); 1758 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { 1759 rc = -EFAULT; 1760 goto err_device_destroy; 1761 } 1762 1763 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; 1764 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; 1765 1766 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1767 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1768 1769 /* prepare ring structures */ 1770 ena_init_rings(adapter); 1771 1772 ena_config_debug_area(adapter); 1773 1774 /* Set max MTU for this device */ 1775 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1776 1777 /* set device support for offloads */ 1778 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1779 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1780 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1781 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1782 adapter->offloads.rx_csum_supported = 1783 (get_feat_ctx.offload.rx_supported & 1784 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1785 1786 /* Copy MAC address and point DPDK to it */ 1787 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1788 rte_ether_addr_copy((struct rte_ether_addr *) 1789 get_feat_ctx.dev_attr.mac_addr, 1790 (struct rte_ether_addr *)adapter->mac_addr); 1791 1792 /* 1793 * Pass the information to the rte_eth_dev_close() that it should also 1794 * release the private port resources. 1795 */ 1796 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1797 1798 adapter->drv_stats = rte_zmalloc("adapter stats", 1799 sizeof(*adapter->drv_stats), 1800 RTE_CACHE_LINE_SIZE); 1801 if (!adapter->drv_stats) { 1802 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1803 rc = -ENOMEM; 1804 goto err_delete_debug_area; 1805 } 1806 1807 rte_intr_callback_register(intr_handle, 1808 ena_interrupt_handler_rte, 1809 adapter); 1810 rte_intr_enable(intr_handle); 1811 ena_com_set_admin_polling_mode(ena_dev, false); 1812 ena_com_admin_aenq_enable(ena_dev); 1813 1814 if (adapters_found == 0) 1815 rte_timer_subsystem_init(); 1816 rte_timer_init(&adapter->timer_wd); 1817 1818 adapters_found++; 1819 adapter->state = ENA_ADAPTER_STATE_INIT; 1820 1821 return 0; 1822 1823 err_delete_debug_area: 1824 ena_com_delete_debug_area(ena_dev); 1825 1826 err_device_destroy: 1827 ena_com_delete_host_info(ena_dev); 1828 ena_com_admin_destroy(ena_dev); 1829 1830 err: 1831 return rc; 1832 } 1833 1834 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1835 { 1836 struct ena_adapter *adapter = eth_dev->data->dev_private; 1837 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1838 1839 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1840 return; 1841 1842 ena_com_set_admin_running_state(ena_dev, false); 1843 1844 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1845 ena_close(eth_dev); 1846 1847 ena_com_delete_debug_area(ena_dev); 1848 ena_com_delete_host_info(ena_dev); 1849 1850 ena_com_abort_admin_commands(ena_dev); 1851 ena_com_wait_for_abort_completion(ena_dev); 1852 ena_com_admin_destroy(ena_dev); 1853 ena_com_mmio_reg_read_request_destroy(ena_dev); 1854 1855 adapter->state = ENA_ADAPTER_STATE_FREE; 1856 } 1857 1858 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1859 { 1860 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1861 return 0; 1862 1863 ena_destroy_device(eth_dev); 1864 1865 eth_dev->dev_ops = NULL; 1866 eth_dev->rx_pkt_burst = NULL; 1867 eth_dev->tx_pkt_burst = NULL; 1868 eth_dev->tx_pkt_prepare = NULL; 1869 1870 return 0; 1871 } 1872 1873 static int ena_dev_configure(struct rte_eth_dev *dev) 1874 { 1875 struct ena_adapter *adapter = dev->data->dev_private; 1876 1877 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1878 1879 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1880 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1881 return 0; 1882 } 1883 1884 static void ena_init_rings(struct ena_adapter *adapter) 1885 { 1886 int i; 1887 1888 for (i = 0; i < adapter->num_queues; i++) { 1889 struct ena_ring *ring = &adapter->tx_ring[i]; 1890 1891 ring->configured = 0; 1892 ring->type = ENA_RING_TYPE_TX; 1893 ring->adapter = adapter; 1894 ring->id = i; 1895 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1896 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1897 ring->sgl_size = adapter->max_tx_sgl_size; 1898 } 1899 1900 for (i = 0; i < adapter->num_queues; i++) { 1901 struct ena_ring *ring = &adapter->rx_ring[i]; 1902 1903 ring->configured = 0; 1904 ring->type = ENA_RING_TYPE_RX; 1905 ring->adapter = adapter; 1906 ring->id = i; 1907 ring->sgl_size = adapter->max_rx_sgl_size; 1908 } 1909 } 1910 1911 static void ena_infos_get(struct rte_eth_dev *dev, 1912 struct rte_eth_dev_info *dev_info) 1913 { 1914 struct ena_adapter *adapter; 1915 struct ena_com_dev *ena_dev; 1916 uint64_t rx_feat = 0, tx_feat = 0; 1917 1918 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1919 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1920 adapter = dev->data->dev_private; 1921 1922 ena_dev = &adapter->ena_dev; 1923 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1924 1925 dev_info->speed_capa = 1926 ETH_LINK_SPEED_1G | 1927 ETH_LINK_SPEED_2_5G | 1928 ETH_LINK_SPEED_5G | 1929 ETH_LINK_SPEED_10G | 1930 ETH_LINK_SPEED_25G | 1931 ETH_LINK_SPEED_40G | 1932 ETH_LINK_SPEED_50G | 1933 ETH_LINK_SPEED_100G; 1934 1935 /* Set Tx & Rx features available for device */ 1936 if (adapter->offloads.tso4_supported) 1937 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1938 1939 if (adapter->offloads.tx_csum_supported) 1940 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1941 DEV_TX_OFFLOAD_UDP_CKSUM | 1942 DEV_TX_OFFLOAD_TCP_CKSUM; 1943 1944 if (adapter->offloads.rx_csum_supported) 1945 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1946 DEV_RX_OFFLOAD_UDP_CKSUM | 1947 DEV_RX_OFFLOAD_TCP_CKSUM; 1948 1949 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1950 1951 /* Inform framework about available features */ 1952 dev_info->rx_offload_capa = rx_feat; 1953 dev_info->rx_queue_offload_capa = rx_feat; 1954 dev_info->tx_offload_capa = tx_feat; 1955 dev_info->tx_queue_offload_capa = tx_feat; 1956 1957 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1958 ETH_RSS_UDP; 1959 1960 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1961 dev_info->max_rx_pktlen = adapter->max_mtu; 1962 dev_info->max_mac_addrs = 1; 1963 1964 dev_info->max_rx_queues = adapter->num_queues; 1965 dev_info->max_tx_queues = adapter->num_queues; 1966 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1967 1968 adapter->tx_supported_offloads = tx_feat; 1969 adapter->rx_supported_offloads = rx_feat; 1970 1971 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; 1972 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1973 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1974 adapter->max_rx_sgl_size); 1975 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1976 adapter->max_rx_sgl_size); 1977 1978 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; 1979 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1980 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1981 adapter->max_tx_sgl_size); 1982 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1983 adapter->max_tx_sgl_size); 1984 } 1985 1986 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1987 uint16_t nb_pkts) 1988 { 1989 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 1990 unsigned int ring_size = rx_ring->ring_size; 1991 unsigned int ring_mask = ring_size - 1; 1992 uint16_t next_to_clean = rx_ring->next_to_clean; 1993 uint16_t desc_in_use = 0; 1994 uint16_t req_id; 1995 unsigned int recv_idx = 0; 1996 struct rte_mbuf *mbuf = NULL; 1997 struct rte_mbuf *mbuf_head = NULL; 1998 struct rte_mbuf *mbuf_prev = NULL; 1999 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2000 unsigned int completed; 2001 2002 struct ena_com_rx_ctx ena_rx_ctx; 2003 int rc = 0; 2004 2005 /* Check adapter state */ 2006 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2007 RTE_LOG(ALERT, PMD, 2008 "Trying to receive pkts while device is NOT running\n"); 2009 return 0; 2010 } 2011 2012 desc_in_use = rx_ring->next_to_use - next_to_clean; 2013 if (unlikely(nb_pkts > desc_in_use)) 2014 nb_pkts = desc_in_use; 2015 2016 for (completed = 0; completed < nb_pkts; completed++) { 2017 int segments = 0; 2018 2019 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2020 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2021 ena_rx_ctx.descs = 0; 2022 /* receive packet context */ 2023 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2024 rx_ring->ena_com_io_sq, 2025 &ena_rx_ctx); 2026 if (unlikely(rc)) { 2027 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 2028 rx_ring->adapter->reset_reason = 2029 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2030 rx_ring->adapter->trigger_reset = true; 2031 ++rx_ring->rx_stats.bad_desc_num; 2032 return 0; 2033 } 2034 2035 if (unlikely(ena_rx_ctx.descs == 0)) 2036 break; 2037 2038 while (segments < ena_rx_ctx.descs) { 2039 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2040 rc = validate_rx_req_id(rx_ring, req_id); 2041 if (unlikely(rc)) { 2042 if (segments != 0) 2043 rte_mbuf_raw_free(mbuf_head); 2044 break; 2045 } 2046 2047 mbuf = rx_buff_info[req_id]; 2048 rx_buff_info[req_id] = NULL; 2049 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2050 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2051 mbuf->refcnt = 1; 2052 mbuf->next = NULL; 2053 if (unlikely(segments == 0)) { 2054 mbuf->nb_segs = ena_rx_ctx.descs; 2055 mbuf->port = rx_ring->port_id; 2056 mbuf->pkt_len = 0; 2057 mbuf_head = mbuf; 2058 } else { 2059 /* for multi-segment pkts create mbuf chain */ 2060 mbuf_prev->next = mbuf; 2061 } 2062 mbuf_head->pkt_len += mbuf->data_len; 2063 2064 mbuf_prev = mbuf; 2065 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2066 req_id; 2067 segments++; 2068 next_to_clean++; 2069 } 2070 if (unlikely(rc)) 2071 break; 2072 2073 /* fill mbuf attributes if any */ 2074 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2075 2076 if (unlikely(mbuf_head->ol_flags & 2077 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2078 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2079 ++rx_ring->rx_stats.bad_csum; 2080 } 2081 2082 mbuf_head->hash.rss = ena_rx_ctx.hash; 2083 2084 /* pass to DPDK application head mbuf */ 2085 rx_pkts[recv_idx] = mbuf_head; 2086 recv_idx++; 2087 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2088 } 2089 2090 rx_ring->rx_stats.cnt += recv_idx; 2091 rx_ring->next_to_clean = next_to_clean; 2092 2093 desc_in_use = desc_in_use - completed + 1; 2094 /* Burst refill to save doorbells, memory barriers, const interval */ 2095 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2096 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2097 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2098 } 2099 2100 return recv_idx; 2101 } 2102 2103 static uint16_t 2104 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2105 uint16_t nb_pkts) 2106 { 2107 int32_t ret; 2108 uint32_t i; 2109 struct rte_mbuf *m; 2110 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2111 struct rte_ipv4_hdr *ip_hdr; 2112 uint64_t ol_flags; 2113 uint16_t frag_field; 2114 2115 for (i = 0; i != nb_pkts; i++) { 2116 m = tx_pkts[i]; 2117 ol_flags = m->ol_flags; 2118 2119 if (!(ol_flags & PKT_TX_IPV4)) 2120 continue; 2121 2122 /* If there was not L2 header length specified, assume it is 2123 * length of the ethernet header. 2124 */ 2125 if (unlikely(m->l2_len == 0)) 2126 m->l2_len = sizeof(struct rte_ether_hdr); 2127 2128 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2129 m->l2_len); 2130 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2131 2132 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2133 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2134 2135 /* If IPv4 header has DF flag enabled and TSO support is 2136 * disabled, partial chcecksum should not be calculated. 2137 */ 2138 if (!tx_ring->adapter->offloads.tso4_supported) 2139 continue; 2140 } 2141 2142 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2143 (ol_flags & PKT_TX_L4_MASK) == 2144 PKT_TX_SCTP_CKSUM) { 2145 rte_errno = ENOTSUP; 2146 return i; 2147 } 2148 2149 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2150 ret = rte_validate_tx_offload(m); 2151 if (ret != 0) { 2152 rte_errno = -ret; 2153 return i; 2154 } 2155 #endif 2156 2157 /* In case we are supposed to TSO and have DF not set (DF=0) 2158 * hardware must be provided with partial checksum, otherwise 2159 * it will take care of necessary calculations. 2160 */ 2161 2162 ret = rte_net_intel_cksum_flags_prepare(m, 2163 ol_flags & ~PKT_TX_TCP_SEG); 2164 if (ret != 0) { 2165 rte_errno = -ret; 2166 return i; 2167 } 2168 } 2169 2170 return i; 2171 } 2172 2173 static void ena_update_hints(struct ena_adapter *adapter, 2174 struct ena_admin_ena_hw_hints *hints) 2175 { 2176 if (hints->admin_completion_tx_timeout) 2177 adapter->ena_dev.admin_queue.completion_timeout = 2178 hints->admin_completion_tx_timeout * 1000; 2179 2180 if (hints->mmio_read_timeout) 2181 /* convert to usec */ 2182 adapter->ena_dev.mmio_read.reg_read_to = 2183 hints->mmio_read_timeout * 1000; 2184 2185 if (hints->driver_watchdog_timeout) { 2186 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2187 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2188 else 2189 // Convert msecs to ticks 2190 adapter->keep_alive_timeout = 2191 (hints->driver_watchdog_timeout * 2192 rte_get_timer_hz()) / 1000; 2193 } 2194 } 2195 2196 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2197 struct rte_mbuf *mbuf) 2198 { 2199 struct ena_com_dev *ena_dev; 2200 int num_segments, header_len, rc; 2201 2202 ena_dev = &tx_ring->adapter->ena_dev; 2203 num_segments = mbuf->nb_segs; 2204 header_len = mbuf->data_len; 2205 2206 if (likely(num_segments < tx_ring->sgl_size)) 2207 return 0; 2208 2209 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2210 (num_segments == tx_ring->sgl_size) && 2211 (header_len < tx_ring->tx_max_header_size)) 2212 return 0; 2213 2214 ++tx_ring->tx_stats.linearize; 2215 rc = rte_pktmbuf_linearize(mbuf); 2216 if (unlikely(rc)) { 2217 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n"); 2218 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2219 ++tx_ring->tx_stats.linearize_failed; 2220 return rc; 2221 } 2222 2223 return rc; 2224 } 2225 2226 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2227 uint16_t nb_pkts) 2228 { 2229 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2230 uint16_t next_to_use = tx_ring->next_to_use; 2231 uint16_t next_to_clean = tx_ring->next_to_clean; 2232 struct rte_mbuf *mbuf; 2233 uint16_t seg_len; 2234 unsigned int ring_size = tx_ring->ring_size; 2235 unsigned int ring_mask = ring_size - 1; 2236 struct ena_com_tx_ctx ena_tx_ctx; 2237 struct ena_tx_buffer *tx_info; 2238 struct ena_com_buf *ebuf; 2239 uint16_t rc, req_id, total_tx_descs = 0; 2240 uint16_t sent_idx = 0, empty_tx_reqs; 2241 uint16_t push_len = 0; 2242 uint16_t delta = 0; 2243 int nb_hw_desc; 2244 uint32_t total_length; 2245 2246 /* Check adapter state */ 2247 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2248 RTE_LOG(ALERT, PMD, 2249 "Trying to xmit pkts while device is NOT running\n"); 2250 return 0; 2251 } 2252 2253 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2254 if (nb_pkts > empty_tx_reqs) 2255 nb_pkts = empty_tx_reqs; 2256 2257 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2258 mbuf = tx_pkts[sent_idx]; 2259 total_length = 0; 2260 2261 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2262 if (unlikely(rc)) 2263 break; 2264 2265 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2266 tx_info = &tx_ring->tx_buffer_info[req_id]; 2267 tx_info->mbuf = mbuf; 2268 tx_info->num_of_bufs = 0; 2269 ebuf = tx_info->bufs; 2270 2271 /* Prepare TX context */ 2272 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2273 memset(&ena_tx_ctx.ena_meta, 0x0, 2274 sizeof(struct ena_com_tx_meta)); 2275 ena_tx_ctx.ena_bufs = ebuf; 2276 ena_tx_ctx.req_id = req_id; 2277 2278 delta = 0; 2279 seg_len = mbuf->data_len; 2280 2281 if (tx_ring->tx_mem_queue_type == 2282 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2283 push_len = RTE_MIN(mbuf->pkt_len, 2284 tx_ring->tx_max_header_size); 2285 ena_tx_ctx.header_len = push_len; 2286 2287 if (likely(push_len <= seg_len)) { 2288 /* If the push header is in the single segment, 2289 * then just point it to the 1st mbuf data. 2290 */ 2291 ena_tx_ctx.push_header = 2292 rte_pktmbuf_mtod(mbuf, uint8_t *); 2293 } else { 2294 /* If the push header lays in the several 2295 * segments, copy it to the intermediate buffer. 2296 */ 2297 rte_pktmbuf_read(mbuf, 0, push_len, 2298 tx_ring->push_buf_intermediate_buf); 2299 ena_tx_ctx.push_header = 2300 tx_ring->push_buf_intermediate_buf; 2301 delta = push_len - seg_len; 2302 } 2303 } /* there's no else as we take advantage of memset zeroing */ 2304 2305 /* Set TX offloads flags, if applicable */ 2306 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2307 2308 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2309 2310 /* Process first segment taking into 2311 * consideration pushed header 2312 */ 2313 if (seg_len > push_len) { 2314 ebuf->paddr = mbuf->buf_iova + 2315 mbuf->data_off + 2316 push_len; 2317 ebuf->len = seg_len - push_len; 2318 ebuf++; 2319 tx_info->num_of_bufs++; 2320 } 2321 total_length += mbuf->data_len; 2322 2323 while ((mbuf = mbuf->next) != NULL) { 2324 seg_len = mbuf->data_len; 2325 2326 /* Skip mbufs if whole data is pushed as a header */ 2327 if (unlikely(delta > seg_len)) { 2328 delta -= seg_len; 2329 continue; 2330 } 2331 2332 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2333 ebuf->len = seg_len - delta; 2334 total_length += ebuf->len; 2335 ebuf++; 2336 tx_info->num_of_bufs++; 2337 2338 delta = 0; 2339 } 2340 2341 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2342 2343 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2344 &ena_tx_ctx)) { 2345 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d" 2346 " achieved, writing doorbell to send burst\n", 2347 tx_ring->id); 2348 rte_wmb(); 2349 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2350 } 2351 2352 /* prepare the packet's descriptors to dma engine */ 2353 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2354 &ena_tx_ctx, &nb_hw_desc); 2355 if (unlikely(rc)) { 2356 ++tx_ring->tx_stats.prepare_ctx_err; 2357 break; 2358 } 2359 tx_info->tx_descs = nb_hw_desc; 2360 2361 next_to_use++; 2362 tx_ring->tx_stats.cnt++; 2363 tx_ring->tx_stats.bytes += total_length; 2364 } 2365 tx_ring->tx_stats.available_desc = 2366 ena_com_free_desc(tx_ring->ena_com_io_sq); 2367 2368 /* If there are ready packets to be xmitted... */ 2369 if (sent_idx > 0) { 2370 /* ...let HW do its best :-) */ 2371 rte_wmb(); 2372 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2373 tx_ring->tx_stats.doorbells++; 2374 tx_ring->next_to_use = next_to_use; 2375 } 2376 2377 /* Clear complete packets */ 2378 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2379 rc = validate_tx_req_id(tx_ring, req_id); 2380 if (rc) 2381 break; 2382 2383 /* Get Tx info & store how many descs were processed */ 2384 tx_info = &tx_ring->tx_buffer_info[req_id]; 2385 total_tx_descs += tx_info->tx_descs; 2386 2387 /* Free whole mbuf chain */ 2388 mbuf = tx_info->mbuf; 2389 rte_pktmbuf_free(mbuf); 2390 tx_info->mbuf = NULL; 2391 2392 /* Put back descriptor to the ring for reuse */ 2393 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2394 next_to_clean++; 2395 2396 /* If too many descs to clean, leave it for another run */ 2397 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2398 break; 2399 } 2400 tx_ring->tx_stats.available_desc = 2401 ena_com_free_desc(tx_ring->ena_com_io_sq); 2402 2403 if (total_tx_descs > 0) { 2404 /* acknowledge completion of sent packets */ 2405 tx_ring->next_to_clean = next_to_clean; 2406 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2407 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2408 } 2409 2410 tx_ring->tx_stats.tx_poll++; 2411 2412 return sent_idx; 2413 } 2414 2415 /** 2416 * DPDK callback to retrieve names of extended device statistics 2417 * 2418 * @param dev 2419 * Pointer to Ethernet device structure. 2420 * @param[out] xstats_names 2421 * Buffer to insert names into. 2422 * @param n 2423 * Number of names. 2424 * 2425 * @return 2426 * Number of xstats names. 2427 */ 2428 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2429 struct rte_eth_xstat_name *xstats_names, 2430 unsigned int n) 2431 { 2432 unsigned int xstats_count = ena_xstats_calc_num(dev); 2433 unsigned int stat, i, count = 0; 2434 2435 if (n < xstats_count || !xstats_names) 2436 return xstats_count; 2437 2438 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2439 strcpy(xstats_names[count].name, 2440 ena_stats_global_strings[stat].name); 2441 2442 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2443 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2444 snprintf(xstats_names[count].name, 2445 sizeof(xstats_names[count].name), 2446 "rx_q%d_%s", i, 2447 ena_stats_rx_strings[stat].name); 2448 2449 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2450 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2451 snprintf(xstats_names[count].name, 2452 sizeof(xstats_names[count].name), 2453 "tx_q%d_%s", i, 2454 ena_stats_tx_strings[stat].name); 2455 2456 return xstats_count; 2457 } 2458 2459 /** 2460 * DPDK callback to get extended device statistics. 2461 * 2462 * @param dev 2463 * Pointer to Ethernet device structure. 2464 * @param[out] stats 2465 * Stats table output buffer. 2466 * @param n 2467 * The size of the stats table. 2468 * 2469 * @return 2470 * Number of xstats on success, negative on failure. 2471 */ 2472 static int ena_xstats_get(struct rte_eth_dev *dev, 2473 struct rte_eth_xstat *xstats, 2474 unsigned int n) 2475 { 2476 struct ena_adapter *adapter = dev->data->dev_private; 2477 unsigned int xstats_count = ena_xstats_calc_num(dev); 2478 unsigned int stat, i, count = 0; 2479 int stat_offset; 2480 void *stats_begin; 2481 2482 if (n < xstats_count) 2483 return xstats_count; 2484 2485 if (!xstats) 2486 return 0; 2487 2488 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2489 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2490 stats_begin = &adapter->dev_stats; 2491 2492 xstats[count].id = count; 2493 xstats[count].value = *((uint64_t *) 2494 ((char *)stats_begin + stat_offset)); 2495 } 2496 2497 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2498 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2499 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2500 stats_begin = &adapter->rx_ring[i].rx_stats; 2501 2502 xstats[count].id = count; 2503 xstats[count].value = *((uint64_t *) 2504 ((char *)stats_begin + stat_offset)); 2505 } 2506 } 2507 2508 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2509 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2510 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2511 stats_begin = &adapter->tx_ring[i].rx_stats; 2512 2513 xstats[count].id = count; 2514 xstats[count].value = *((uint64_t *) 2515 ((char *)stats_begin + stat_offset)); 2516 } 2517 } 2518 2519 return count; 2520 } 2521 2522 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2523 const uint64_t *ids, 2524 uint64_t *values, 2525 unsigned int n) 2526 { 2527 struct ena_adapter *adapter = dev->data->dev_private; 2528 uint64_t id; 2529 uint64_t rx_entries, tx_entries; 2530 unsigned int i; 2531 int qid; 2532 int valid = 0; 2533 for (i = 0; i < n; ++i) { 2534 id = ids[i]; 2535 /* Check if id belongs to global statistics */ 2536 if (id < ENA_STATS_ARRAY_GLOBAL) { 2537 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2538 ++valid; 2539 continue; 2540 } 2541 2542 /* Check if id belongs to rx queue statistics */ 2543 id -= ENA_STATS_ARRAY_GLOBAL; 2544 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2545 if (id < rx_entries) { 2546 qid = id % dev->data->nb_rx_queues; 2547 id /= dev->data->nb_rx_queues; 2548 values[i] = *((uint64_t *) 2549 &adapter->rx_ring[qid].rx_stats + id); 2550 ++valid; 2551 continue; 2552 } 2553 /* Check if id belongs to rx queue statistics */ 2554 id -= rx_entries; 2555 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2556 if (id < tx_entries) { 2557 qid = id % dev->data->nb_tx_queues; 2558 id /= dev->data->nb_tx_queues; 2559 values[i] = *((uint64_t *) 2560 &adapter->tx_ring[qid].tx_stats + id); 2561 ++valid; 2562 continue; 2563 } 2564 } 2565 2566 return valid; 2567 } 2568 2569 /********************************************************************* 2570 * PMD configuration 2571 *********************************************************************/ 2572 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2573 struct rte_pci_device *pci_dev) 2574 { 2575 return rte_eth_dev_pci_generic_probe(pci_dev, 2576 sizeof(struct ena_adapter), eth_ena_dev_init); 2577 } 2578 2579 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2580 { 2581 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2582 } 2583 2584 static struct rte_pci_driver rte_ena_pmd = { 2585 .id_table = pci_id_ena_map, 2586 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2587 RTE_PCI_DRV_WC_ACTIVATE, 2588 .probe = eth_ena_pci_probe, 2589 .remove = eth_ena_pci_remove, 2590 }; 2591 2592 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2593 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2594 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2595 2596 RTE_INIT(ena_init_log) 2597 { 2598 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2599 if (ena_logtype_init >= 0) 2600 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2601 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2602 if (ena_logtype_driver >= 0) 2603 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2604 } 2605 2606 /****************************************************************************** 2607 ******************************** AENQ Handlers ******************************* 2608 *****************************************************************************/ 2609 static void ena_update_on_link_change(void *adapter_data, 2610 struct ena_admin_aenq_entry *aenq_e) 2611 { 2612 struct rte_eth_dev *eth_dev; 2613 struct ena_adapter *adapter; 2614 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2615 uint32_t status; 2616 2617 adapter = adapter_data; 2618 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2619 eth_dev = adapter->rte_dev; 2620 2621 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2622 adapter->link_status = status; 2623 2624 ena_link_update(eth_dev, 0); 2625 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2626 } 2627 2628 static void ena_notification(void *data, 2629 struct ena_admin_aenq_entry *aenq_e) 2630 { 2631 struct ena_adapter *adapter = data; 2632 struct ena_admin_ena_hw_hints *hints; 2633 2634 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2635 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n", 2636 aenq_e->aenq_common_desc.group, 2637 ENA_ADMIN_NOTIFICATION); 2638 2639 switch (aenq_e->aenq_common_desc.syndrom) { 2640 case ENA_ADMIN_UPDATE_HINTS: 2641 hints = (struct ena_admin_ena_hw_hints *) 2642 (&aenq_e->inline_data_w4); 2643 ena_update_hints(adapter, hints); 2644 break; 2645 default: 2646 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n", 2647 aenq_e->aenq_common_desc.syndrom); 2648 } 2649 } 2650 2651 static void ena_keep_alive(void *adapter_data, 2652 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2653 { 2654 struct ena_adapter *adapter = adapter_data; 2655 struct ena_admin_aenq_keep_alive_desc *desc; 2656 uint64_t rx_drops; 2657 2658 adapter->timestamp_wd = rte_get_timer_cycles(); 2659 2660 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2661 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2662 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2663 } 2664 2665 /** 2666 * This handler will called for unknown event group or unimplemented handlers 2667 **/ 2668 static void unimplemented_aenq_handler(__rte_unused void *data, 2669 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2670 { 2671 RTE_LOG(ERR, PMD, "Unknown event was received or event with " 2672 "unimplemented handler\n"); 2673 } 2674 2675 static struct ena_aenq_handlers aenq_handlers = { 2676 .handlers = { 2677 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2678 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2679 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2680 }, 2681 .unimplemented_handler = unimplemented_aenq_handler 2682 }; 2683