1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_ 7 #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_ 8 9 #include <stdbool.h> 10 #include <stdlib.h> 11 #include <pthread.h> 12 #include <stdint.h> 13 #include <inttypes.h> 14 #include <string.h> 15 #include <errno.h> 16 17 #include <ethdev_driver.h> 18 #include <rte_atomic.h> 19 #include <rte_branch_prediction.h> 20 #include <rte_cycles.h> 21 #include <rte_io.h> 22 #include <rte_log.h> 23 #include <rte_malloc.h> 24 #include <rte_memzone.h> 25 #include <rte_prefetch.h> 26 #include <rte_spinlock.h> 27 28 #include <sys/time.h> 29 30 typedef uint64_t u64; 31 typedef uint32_t u32; 32 typedef uint16_t u16; 33 typedef uint8_t u8; 34 35 typedef struct rte_eth_dev ena_netdev; 36 typedef uint64_t dma_addr_t; 37 38 #ifndef ETIME 39 #define ETIME ETIMEDOUT 40 #endif 41 42 #define ENA_PRIu64 PRIu64 43 #define ena_atomic32_t rte_atomic32_t 44 #define ena_mem_handle_t const struct rte_memzone * 45 46 #define SZ_256 (256U) 47 #define SZ_4K (4096U) 48 49 #define ENA_COM_OK 0 50 #define ENA_COM_NO_MEM -ENOMEM 51 #define ENA_COM_INVAL -EINVAL 52 #define ENA_COM_NO_SPACE -ENOSPC 53 #define ENA_COM_NO_DEVICE -ENODEV 54 #define ENA_COM_TIMER_EXPIRED -ETIME 55 #define ENA_COM_FAULT -EFAULT 56 #define ENA_COM_TRY_AGAIN -EAGAIN 57 #define ENA_COM_UNSUPPORTED -EOPNOTSUPP 58 #define ENA_COM_EIO -EIO 59 #define ENA_COM_DEVICE_BUSY -EBUSY 60 61 #define ____cacheline_aligned __rte_cache_aligned 62 63 #define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */ 64 65 #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000) 66 #define ENA_USLEEP(x) rte_delay_us_sleep(x) 67 #define ENA_UDELAY(x) rte_delay_us_block(x) 68 69 #define ENA_TOUCH(x) ((void)(x)) 70 71 #define wmb rte_wmb 72 #define rmb rte_rmb 73 #define mb rte_mb 74 #define mmiowb rte_io_wmb 75 #define __iomem 76 77 #ifndef READ_ONCE 78 #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) 79 #endif 80 81 #define READ_ONCE8(var) READ_ONCE(var) 82 #define READ_ONCE16(var) READ_ONCE(var) 83 #define READ_ONCE32(var) READ_ONCE(var) 84 85 #define US_PER_S 1000000 86 #define ENA_GET_SYSTEM_USECS() \ 87 (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) 88 89 extern int ena_logtype_com; 90 91 #define ENA_MAX_T(type, x, y) RTE_MAX((type)(x), (type)(y)) 92 #define ENA_MAX32(x, y) ENA_MAX_T(uint32_t, (x), (y)) 93 #define ENA_MAX16(x, y) ENA_MAX_T(uint16_t, (x), (y)) 94 #define ENA_MAX8(x, y) ENA_MAX_T(uint8_t, (x), (y)) 95 #define ENA_MIN_T(type, x, y) RTE_MIN((type)(x), (type)(y)) 96 #define ENA_MIN32(x, y) ENA_MIN_T(uint32_t, (x), (y)) 97 #define ENA_MIN16(x, y) ENA_MIN_T(uint16_t, (x), (y)) 98 #define ENA_MIN8(x, y) ENA_MIN_T(uint8_t, (x), (y)) 99 100 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8) 101 #define U64_C(x) x ## ULL 102 #define BIT(nr) RTE_BIT32(nr) 103 #define BIT64(nr) RTE_BIT64(nr) 104 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 105 #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 106 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ 107 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) 108 109 #define ena_trc_log(dev, level, fmt, ...) \ 110 ( \ 111 ENA_TOUCH(dev), \ 112 rte_log(RTE_LOG_ ## level, ena_logtype_com, \ 113 "[ENA_COM: %s]" fmt, __func__, ##__VA_ARGS__) \ 114 ) 115 116 #if (defined RTE_ETHDEV_DEBUG_TX) || (defined RTE_ETHDEV_DEBUG_RX) 117 #define ena_trc_dbg(dev, format, ...) ena_trc_log(dev, DEBUG, format, ##__VA_ARGS__) 118 #else 119 #define ena_trc_dbg(dev, format, ...) 120 #endif 121 #define ena_trc_info(dev, format, ...) ena_trc_log(dev, INFO, format, ##__VA_ARGS__) 122 #define ena_trc_warn(dev, format, ...) ena_trc_log(dev, WARNING, format, ##__VA_ARGS__) 123 #define ena_trc_err(dev, format, ...) ena_trc_log(dev, ERR, format, ##__VA_ARGS__) 124 125 #define ENA_WARN(cond, dev, format, ...) \ 126 do { \ 127 if (unlikely(cond)) { \ 128 ena_trc_err(dev, \ 129 "Warn failed on %s:%s:%d:" format, \ 130 __FILE__, __func__, __LINE__, ##__VA_ARGS__); \ 131 } \ 132 } while (0) 133 134 /* Spinlock related methods */ 135 #define ena_spinlock_t rte_spinlock_t 136 #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&(spinlock)) 137 #define ENA_SPINLOCK_LOCK(spinlock, flags) \ 138 __extension__ ({(void)(flags); rte_spinlock_lock(&(spinlock)); }) 139 #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ 140 __extension__ ({(void)(flags); rte_spinlock_unlock(&(spinlock)); }) 141 #define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock)) 142 143 typedef struct { 144 pthread_cond_t cond; 145 pthread_mutex_t mutex; 146 uint8_t flag; 147 } ena_wait_event_t; 148 149 #define ENA_WAIT_EVENT_INIT(waitevent) \ 150 do { \ 151 ena_wait_event_t *_we = &(waitevent); \ 152 pthread_mutex_init(&_we->mutex, NULL); \ 153 pthread_cond_init(&_we->cond, NULL); \ 154 _we->flag = 0; \ 155 } while (0) 156 157 #define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ 158 do { \ 159 ena_wait_event_t *_we = &(waitevent); \ 160 typeof(timeout) _tmo = (timeout); \ 161 int ret = 0; \ 162 struct timespec wait; \ 163 struct timeval now; \ 164 unsigned long timeout_us; \ 165 gettimeofday(&now, NULL); \ 166 wait.tv_sec = now.tv_sec + _tmo / 1000000UL; \ 167 timeout_us = _tmo % 1000000UL; \ 168 wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ 169 pthread_mutex_lock(&_we->mutex); \ 170 while (ret == 0 && !_we->flag) { \ 171 ret = pthread_cond_timedwait(&_we->cond, \ 172 &_we->mutex, &wait); \ 173 } \ 174 /* Asserts only if not working on ena_wait_event_t */ \ 175 if (unlikely(ret != 0 && ret != ETIMEDOUT)) \ 176 ena_trc_err(NULL, \ 177 "Invalid wait event. pthread ret: %d\n", ret); \ 178 else if (unlikely(ret == ETIMEDOUT)) \ 179 ena_trc_err(NULL, \ 180 "Timeout waiting for " #waitevent "\n"); \ 181 _we->flag = 0; \ 182 pthread_mutex_unlock(&_we->mutex); \ 183 } while (0) 184 #define ENA_WAIT_EVENT_SIGNAL(waitevent) \ 185 do { \ 186 ena_wait_event_t *_we = &(waitevent); \ 187 pthread_mutex_lock(&_we->mutex); \ 188 _we->flag = 1; \ 189 pthread_cond_signal(&_we->cond); \ 190 pthread_mutex_unlock(&_we->mutex); \ 191 } while (0) 192 /* pthread condition doesn't need to be rearmed after usage */ 193 #define ENA_WAIT_EVENT_CLEAR(...) 194 #define ENA_WAIT_EVENT_DESTROY(waitevent) ((void)(waitevent)) 195 196 #define ENA_MIGHT_SLEEP() 197 198 #define ena_time_t uint64_t 199 #define ena_time_high_res_t uint64_t 200 201 /* Note that high resolution timers are not used by the ENA PMD for now. 202 * Although these macro definitions compile, it shall fail the 203 * compilation in case the unimplemented API is called prematurely. 204 */ 205 #define ENA_TIME_EXPIRE(timeout) ((timeout) < rte_get_timer_cycles()) 206 #define ENA_TIME_EXPIRE_HIGH_RES(timeout) (RTE_SET_USED(timeout), 0) 207 #define ENA_TIME_INIT_HIGH_RES() 0 208 #define ENA_TIME_COMPARE_HIGH_RES(time1, time2) (RTE_SET_USED(time1), RTE_SET_USED(time2), 0) 209 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 210 ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) 211 #define ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(current_time, timeout_us) \ 212 (RTE_SET_USED(current_time), RTE_SET_USED(timeout_us), 0) 213 #define ENA_GET_SYSTEM_TIME_HIGH_RES() 0 214 215 const struct rte_memzone * 216 ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size, 217 int socket_id, unsigned int alignment, void **virt_addr, 218 dma_addr_t *phys_addr); 219 220 #define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ 221 dmadev, size, virt, phys, mem_handle, alignment) \ 222 do { \ 223 void *virt_addr; \ 224 dma_addr_t phys_addr; \ 225 (mem_handle) = ena_mem_alloc_coherent((dmadev), (size), \ 226 SOCKET_ID_ANY, (alignment), &virt_addr, &phys_addr); \ 227 (virt) = virt_addr; \ 228 (phys) = phys_addr; \ 229 } while (0) 230 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, mem_handle) \ 231 ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, \ 232 mem_handle, RTE_CACHE_LINE_SIZE) 233 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle) \ 234 __extension__ ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev); \ 235 rte_memzone_free(mem_handle); }) 236 237 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ 238 dmadev, size, virt, phys, mem_handle, node, alignment) \ 239 do { \ 240 void *virt_addr; \ 241 dma_addr_t phys_addr; \ 242 (mem_handle) = ena_mem_alloc_coherent((dmadev), (size), \ 243 (node), (alignment), &virt_addr, &phys_addr); \ 244 (virt) = virt_addr; \ 245 (phys) = phys_addr; \ 246 } while (0) 247 #define ENA_MEM_ALLOC_COHERENT_NODE( \ 248 dmadev, size, virt, phys, mem_handle, node) \ 249 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys, \ 250 mem_handle, node, RTE_CACHE_LINE_SIZE) 251 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node) \ 252 do { \ 253 ENA_TOUCH(dmadev); \ 254 virt = rte_zmalloc_socket(NULL, size, 0, node); \ 255 } while (0) 256 257 #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1) 258 #define ENA_MEM_FREE(dmadev, ptr, size) \ 259 __extension__ ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); }) 260 261 #define ENA_DB_SYNC(mem_handle) ((void)mem_handle) 262 263 #define ENA_REG_WRITE32(bus, value, reg) \ 264 __extension__ ({ (void)(bus); rte_write32((value), (reg)); }) 265 #define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ 266 __extension__ ({ (void)(bus); rte_write32_relaxed((value), (reg)); }) 267 #define ENA_REG_READ32(bus, reg) \ 268 __extension__ ({ (void)(bus); rte_read32_relaxed((reg)); }) 269 270 #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr) 271 #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr) 272 #define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val) 273 #define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr) 274 275 #define msleep(x) rte_delay_us(x * 1000) 276 #define udelay(x) rte_delay_us(x) 277 278 #define dma_rmb() rmb() 279 280 #define MAX_ERRNO 4095 281 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO) 282 #define ERR_PTR(error) ((void *)(long)error) 283 #define PTR_ERR(error) ((long)(void *)error) 284 #define might_sleep() 285 286 #define prefetch(x) rte_prefetch0(x) 287 #define prefetchw(x) rte_prefetch0_write(x) 288 289 #define lower_32_bits(x) ((uint32_t)(x)) 290 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) 291 292 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 293 ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) 294 #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue)) 295 296 /* The size must be 8 byte align */ 297 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ 298 do { \ 299 int count, i; \ 300 uint64_t *to = (uint64_t *)(dst); \ 301 const uint64_t *from = (const uint64_t *)(src); \ 302 count = (size) / 8; \ 303 for (i = 0; i < count; i++, from++, to++) \ 304 rte_write64_relaxed(*from, to); \ 305 } while(0) 306 307 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 308 309 #define ENA_FFS(x) ffs(x) 310 311 void ena_rss_key_fill(void *key, size_t size); 312 313 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) 314 315 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0 316 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS_PLAT 0 317 318 #include "ena_includes.h" 319 320 #define ENA_BITS_PER_U64(bitmap) (ena_bits_per_u64(bitmap)) 321 322 #define ENA_FIELD_GET(value, mask, offset) (((value) & (mask)) >> (offset)) 323 #define ENA_FIELD_PREP(value, mask, offset) (((value) << (offset)) & (mask)) 324 325 #define ENA_ZERO_SHIFT 0 326 327 static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap) 328 { 329 int count = 0; 330 331 while (bitmap) { 332 bitmap &= (bitmap - 1); 333 count++; 334 } 335 336 return count; 337 } 338 339 #define ENA_ADMIN_OS_DPDK 3 340 341 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ 342