1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2016-2020 NXP 5 * 6 */ 7 #ifndef _FSL_DPNI_CMD_H 8 #define _FSL_DPNI_CMD_H 9 10 /* DPNI Version */ 11 #define DPNI_VER_MAJOR 7 12 #define DPNI_VER_MINOR 13 13 14 #define DPNI_CMD_BASE_VERSION 1 15 #define DPNI_CMD_VERSION_2 2 16 #define DPNI_CMD_VERSION_3 3 17 #define DPNI_CMD_ID_OFFSET 4 18 19 #define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION) 20 #define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_2) 21 #define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_3) 22 23 /* Command IDs */ 24 #define DPNI_CMDID_OPEN DPNI_CMD(0x801) 25 #define DPNI_CMDID_CLOSE DPNI_CMD(0x800) 26 #define DPNI_CMDID_CREATE DPNI_CMD_V3(0x901) 27 #define DPNI_CMDID_DESTROY DPNI_CMD(0x981) 28 #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01) 29 30 #define DPNI_CMDID_ENABLE DPNI_CMD(0x002) 31 #define DPNI_CMDID_DISABLE DPNI_CMD(0x003) 32 #define DPNI_CMDID_GET_ATTR DPNI_CMD_V3(0x004) 33 #define DPNI_CMDID_RESET DPNI_CMD(0x005) 34 #define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006) 35 36 #define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012) 37 #define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013) 38 #define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014) 39 #define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015) 40 #define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016) 41 #define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017) 42 43 #define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200) 44 #define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B) 45 46 #define DPNI_CMDID_GET_QDID DPNI_CMD(0x210) 47 #define DPNI_CMDID_GET_SP_INFO DPNI_CMD(0x211) 48 #define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212) 49 #define DPNI_CMDID_GET_LINK_STATE DPNI_CMD_V2(0x215) 50 #define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216) 51 #define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217) 52 #define DPNI_CMDID_SET_LINK_CFG DPNI_CMD_V2(0x21A) 53 #define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V2(0x21B) 54 55 #define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220) 56 #define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221) 57 #define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222) 58 #define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223) 59 #define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224) 60 #define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225) 61 #define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD_V2(0x226) 62 #define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227) 63 #define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228) 64 65 #define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230) 66 #define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231) 67 #define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232) 68 #define DPNI_CMDID_CLR_VLAN_FILTERS DPNI_CMD(0x233) 69 70 #define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V3(0x235) 71 72 #define DPNI_CMDID_SET_RX_TC_POLICING DPNI_CMD(0x23E) 73 74 #define DPNI_CMDID_SET_QOS_TBL DPNI_CMD_V2(0x240) 75 #define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD_V2(0x241) 76 #define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242) 77 #define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243) 78 #define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244) 79 #define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245) 80 #define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246) 81 82 #define DPNI_CMDID_SET_TX_PRIORITIES DPNI_CMD_V2(0x250) 83 #define DPNI_CMDID_GET_RX_TC_POLICING DPNI_CMD(0x251) 84 85 #define DPNI_CMDID_GET_STATISTICS DPNI_CMD_V3(0x25D) 86 #define DPNI_CMDID_RESET_STATISTICS DPNI_CMD(0x25E) 87 #define DPNI_CMDID_GET_QUEUE DPNI_CMD_V2(0x25F) 88 #define DPNI_CMDID_SET_QUEUE DPNI_CMD_V2(0x260) 89 #define DPNI_CMDID_GET_TAILDROP DPNI_CMD_V2(0x261) 90 #define DPNI_CMDID_SET_TAILDROP DPNI_CMD_V2(0x262) 91 92 #define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263) 93 94 #define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD_V2(0x264) 95 #define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD_V2(0x265) 96 97 #define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD_V2(0x267) 98 #define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD_V2(0x268) 99 #define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD_V2(0x269) 100 #define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD_V2(0x26A) 101 #define DPNI_CMDID_GET_OFFLOAD DPNI_CMD(0x26B) 102 #define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C) 103 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266) 104 #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE DPNI_CMD(0x26D) 105 #define DPNI_CMDID_LOAD_SW_SEQUENCE DPNI_CMD(0x270) 106 #define DPNI_CMDID_ENABLE_SW_SEQUENCE DPNI_CMD(0x271) 107 #define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT DPNI_CMD(0x272) 108 #define DPNI_CMDID_SET_OPR DPNI_CMD(0x26e) 109 #define DPNI_CMDID_GET_OPR DPNI_CMD(0x26f) 110 #define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273) 111 #define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD(0x274) 112 #define DPNI_CMDID_ADD_CUSTOM_TPID DPNI_CMD(0x275) 113 #define DPNI_CMDID_REMOVE_CUSTOM_TPID DPNI_CMD(0x276) 114 #define DPNI_CMDID_GET_CUSTOM_TPID DPNI_CMD(0x277) 115 116 /* Macros for accessing command fields smaller than 1byte */ 117 #define DPNI_MASK(field) \ 118 GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ 119 DPNI_##field##_SHIFT) 120 #define dpni_set_field(var, field, val) \ 121 ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) 122 #define dpni_get_field(var, field) \ 123 (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) 124 125 #pragma pack(push, 1) 126 struct dpni_cmd_open { 127 uint32_t dpni_id; 128 }; 129 130 struct dpni_cmd_create { 131 uint32_t options; 132 uint8_t num_queues; 133 uint8_t num_tcs; 134 uint8_t mac_filter_entries; 135 uint8_t pad1; 136 uint8_t vlan_filter_entries; 137 uint8_t pad2; 138 uint8_t qos_entries; 139 uint8_t pad3; 140 uint16_t fs_entries; 141 uint8_t num_rx_tcs; 142 uint8_t pad4; 143 uint8_t num_cgs; 144 }; 145 146 struct dpni_cmd_destroy { 147 uint32_t dpsw_id; 148 }; 149 150 #define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) 151 152 struct dpni_cmd_pool { 153 uint16_t dpbp_id; 154 uint8_t priority_mask; 155 uint8_t pad; 156 }; 157 158 struct dpni_cmd_set_pools { 159 uint8_t num_dpbp; 160 uint8_t backup_pool_mask; 161 uint8_t pad; 162 uint8_t pool_options; 163 struct dpni_cmd_pool pool[8]; 164 uint16_t buffer_size[8]; 165 }; 166 167 /* The enable indication is always the least significant bit */ 168 #define DPNI_ENABLE_SHIFT 0 169 #define DPNI_ENABLE_SIZE 1 170 171 struct dpni_rsp_is_enabled { 172 uint8_t enabled; 173 }; 174 175 struct dpni_cmd_set_irq_enable { 176 uint8_t enable; 177 uint8_t pad[3]; 178 uint8_t irq_index; 179 }; 180 181 struct dpni_cmd_get_irq_enable { 182 uint32_t pad; 183 uint8_t irq_index; 184 }; 185 186 struct dpni_rsp_get_irq_enable { 187 uint8_t enabled; 188 }; 189 190 struct dpni_cmd_set_irq_mask { 191 uint32_t mask; 192 uint8_t irq_index; 193 }; 194 195 struct dpni_cmd_get_irq_mask { 196 uint32_t pad; 197 uint8_t irq_index; 198 }; 199 200 struct dpni_rsp_get_irq_mask { 201 uint32_t mask; 202 }; 203 204 struct dpni_cmd_get_irq_status { 205 uint32_t status; 206 uint8_t irq_index; 207 }; 208 209 struct dpni_rsp_get_irq_status { 210 uint32_t status; 211 }; 212 213 struct dpni_cmd_clear_irq_status { 214 uint32_t status; 215 uint8_t irq_index; 216 }; 217 218 struct dpni_rsp_get_attr { 219 /* response word 0 */ 220 uint32_t options; 221 uint8_t num_queues; 222 uint8_t num_rx_tcs; 223 uint8_t mac_filter_entries; 224 uint8_t num_tx_tcs; 225 /* response word 1 */ 226 uint8_t vlan_filter_entries; 227 uint8_t pad1; 228 uint8_t qos_entries; 229 uint8_t pad2; 230 uint16_t fs_entries; 231 uint16_t pad3; 232 /* response word 2 */ 233 uint8_t qos_key_size; 234 uint8_t fs_key_size; 235 uint16_t wriop_version; 236 uint8_t num_cgs; 237 }; 238 239 #define DPNI_ERROR_ACTION_SHIFT 0 240 #define DPNI_ERROR_ACTION_SIZE 4 241 #define DPNI_FRAME_ANN_SHIFT 4 242 #define DPNI_FRAME_ANN_SIZE 1 243 244 struct dpni_cmd_set_errors_behavior { 245 uint32_t errors; 246 /* from least significant bit: error_action:4, set_frame_annotation:1 */ 247 uint8_t flags; 248 }; 249 250 /* There are 3 separate commands for configuring Rx, Tx and Tx confirmation 251 * buffer layouts, but they all share the same parameters. 252 * If one of the functions changes, below structure needs to be split. 253 */ 254 255 #define DPNI_PASS_TS_SHIFT 0 256 #define DPNI_PASS_TS_SIZE 1 257 #define DPNI_PASS_PR_SHIFT 1 258 #define DPNI_PASS_PR_SIZE 1 259 #define DPNI_PASS_FS_SHIFT 2 260 #define DPNI_PASS_FS_SIZE 1 261 #define DPNI_PASS_SWO_SHIFT 3 262 #define DPNI_PASS_SWO_SIZE 1 263 264 struct dpni_cmd_get_buffer_layout { 265 uint8_t qtype; 266 }; 267 268 struct dpni_rsp_get_buffer_layout { 269 /* response word 0 */ 270 uint8_t pad0[6]; 271 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 272 uint8_t flags; 273 uint8_t pad1; 274 /* response word 1 */ 275 uint16_t private_data_size; 276 uint16_t data_align; 277 uint16_t head_room; 278 uint16_t tail_room; 279 }; 280 281 struct dpni_cmd_set_buffer_layout { 282 /* cmd word 0 */ 283 uint8_t qtype; 284 uint8_t pad0[3]; 285 uint16_t options; 286 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 287 uint8_t flags; 288 uint8_t pad1; 289 /* cmd word 1 */ 290 uint16_t private_data_size; 291 uint16_t data_align; 292 uint16_t head_room; 293 uint16_t tail_room; 294 }; 295 296 struct dpni_cmd_set_offload { 297 uint8_t pad[3]; 298 uint8_t dpni_offload; 299 uint32_t config; 300 }; 301 302 struct dpni_cmd_get_offload { 303 uint8_t pad[3]; 304 uint8_t dpni_offload; 305 }; 306 307 struct dpni_rsp_get_offload { 308 uint32_t pad; 309 uint32_t config; 310 }; 311 312 struct dpni_cmd_get_qdid { 313 uint8_t qtype; 314 }; 315 316 struct dpni_rsp_get_qdid { 317 uint16_t qdid; 318 }; 319 320 struct dpni_rsp_get_sp_info { 321 uint16_t spids[2]; 322 }; 323 324 struct dpni_rsp_get_tx_data_offset { 325 uint16_t data_offset; 326 }; 327 328 struct dpni_cmd_get_statistics { 329 uint8_t page_number; 330 uint16_t param; 331 }; 332 333 struct dpni_rsp_get_statistics { 334 uint64_t counter[7]; 335 }; 336 337 struct dpni_cmd_set_link_cfg { 338 uint64_t pad0; 339 uint32_t rate; 340 uint32_t pad1; 341 uint64_t options; 342 uint64_t advertising; 343 }; 344 345 #define DPNI_LINK_STATE_SHIFT 0 346 #define DPNI_LINK_STATE_SIZE 1 347 #define DPNI_STATE_VALID_SHIFT 1 348 #define DPNI_STATE_VALID_SIZE 1 349 350 struct dpni_rsp_get_link_state { 351 uint32_t pad0; 352 /* from LSB: up:1 */ 353 uint8_t flags; 354 uint8_t pad1[3]; 355 uint32_t rate; 356 uint32_t pad2; 357 uint64_t options; 358 uint64_t supported; 359 uint64_t advertising; 360 }; 361 362 #define DPNI_COUPLED_SHIFT 0 363 #define DPNI_COUPLED_SIZE 1 364 365 struct dpni_cmd_set_tx_shaping { 366 uint16_t tx_cr_max_burst_size; 367 uint16_t tx_er_max_burst_size; 368 uint32_t pad; 369 uint32_t tx_cr_rate_limit; 370 uint32_t tx_er_rate_limit; 371 /* from LSB: coupled:1 */ 372 uint8_t coupled; 373 }; 374 375 struct dpni_cmd_set_max_frame_length { 376 uint16_t max_frame_length; 377 }; 378 379 struct dpni_rsp_get_max_frame_length { 380 uint16_t max_frame_length; 381 }; 382 383 struct dpni_cmd_set_multicast_promisc { 384 uint8_t enable; 385 }; 386 387 struct dpni_rsp_get_multicast_promisc { 388 uint8_t enabled; 389 }; 390 391 struct dpni_cmd_set_unicast_promisc { 392 uint8_t enable; 393 }; 394 395 struct dpni_rsp_get_unicast_promisc { 396 uint8_t enabled; 397 }; 398 399 struct dpni_cmd_set_primary_mac_addr { 400 uint16_t pad; 401 uint8_t mac_addr[6]; 402 }; 403 404 struct dpni_rsp_get_primary_mac_addr { 405 uint16_t pad; 406 uint8_t mac_addr[6]; 407 }; 408 409 struct dpni_rsp_get_port_mac_addr { 410 uint16_t pad; 411 uint8_t mac_addr[6]; 412 }; 413 414 #define DPNI_MAC_SET_QUEUE_ACTION 1 415 416 struct dpni_cmd_add_mac_addr { 417 uint8_t flags; 418 uint8_t pad; 419 uint8_t mac_addr[6]; 420 uint8_t tc_id; 421 uint8_t fq_id; 422 }; 423 424 struct dpni_cmd_remove_mac_addr { 425 uint16_t pad; 426 uint8_t mac_addr[6]; 427 }; 428 429 #define DPNI_UNICAST_FILTERS_SHIFT 0 430 #define DPNI_UNICAST_FILTERS_SIZE 1 431 #define DPNI_MULTICAST_FILTERS_SHIFT 1 432 #define DPNI_MULTICAST_FILTERS_SIZE 1 433 434 struct dpni_cmd_clear_mac_filters { 435 /* from LSB: unicast:1, multicast:1 */ 436 uint8_t flags; 437 }; 438 439 struct dpni_cmd_enable_vlan_filter { 440 /* only the LSB */ 441 uint8_t en; 442 }; 443 444 #define DPNI_VLAN_SET_QUEUE_ACTION 1 445 446 struct dpni_cmd_vlan_id { 447 uint8_t flags; 448 uint8_t tc_id; 449 uint8_t flow_id; 450 uint8_t pad; 451 uint16_t vlan_id; 452 }; 453 454 #define DPNI_SEPARATE_GRP_SHIFT 0 455 #define DPNI_SEPARATE_GRP_SIZE 1 456 #define DPNI_MODE_1_SHIFT 0 457 #define DPNI_MODE_1_SIZE 4 458 #define DPNI_MODE_2_SHIFT 4 459 #define DPNI_MODE_2_SIZE 4 460 461 struct dpni_cmd_set_tx_priorities { 462 uint16_t flags; 463 uint8_t prio_group_A; 464 uint8_t prio_group_B; 465 uint32_t pad0; 466 uint8_t modes[4]; 467 uint32_t pad1; 468 uint64_t pad2; 469 uint16_t delta_bandwidth[8]; 470 }; 471 472 #define DPNI_DIST_MODE_SHIFT 0 473 #define DPNI_DIST_MODE_SIZE 4 474 #define DPNI_MISS_ACTION_SHIFT 4 475 #define DPNI_MISS_ACTION_SIZE 4 476 #define DPNI_KEEP_HASH_KEY_SHIFT 7 477 #define DPNI_KEEP_HASH_KEY_SIZE 1 478 #define DPNI_KEEP_ENTRIES_SHIFT 6 479 #define DPNI_KEEP_ENTRIES_SIZE 1 480 481 struct dpni_cmd_set_rx_tc_dist { 482 uint16_t dist_size; 483 uint8_t tc_id; 484 /* from LSB: dist_mode:4, miss_action:4 */ 485 uint8_t flags; 486 uint8_t pad0; 487 /* only the LSB */ 488 uint8_t keep_hash_key; 489 uint16_t default_flow_id; 490 uint64_t pad1[5]; 491 uint64_t key_cfg_iova; 492 }; 493 494 struct dpni_cmd_get_queue { 495 uint8_t qtype; 496 uint8_t tc; 497 uint8_t index; 498 }; 499 500 #define DPNI_DEST_TYPE_SHIFT 0 501 #define DPNI_DEST_TYPE_SIZE 4 502 #define DPNI_CGID_VALID_SHIFT 5 503 #define DPNI_CGID_VALID_SIZE 1 504 #define DPNI_STASH_CTRL_SHIFT 6 505 #define DPNI_STASH_CTRL_SIZE 1 506 #define DPNI_HOLD_ACTIVE_SHIFT 7 507 #define DPNI_HOLD_ACTIVE_SIZE 1 508 509 struct dpni_rsp_get_queue { 510 /* response word 0 */ 511 uint64_t pad0; 512 /* response word 1 */ 513 uint32_t dest_id; 514 uint16_t pad1; 515 uint8_t dest_prio; 516 /* From LSB: 517 * dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 518 */ 519 uint8_t flags; 520 /* response word 2 */ 521 uint64_t flc; 522 /* response word 3 */ 523 uint64_t user_context; 524 /* response word 4 */ 525 uint32_t fqid; 526 uint16_t qdbin; 527 uint16_t pad2; 528 /* response word 5*/ 529 uint8_t cgid; 530 }; 531 532 struct dpni_cmd_set_queue { 533 /* cmd word 0 */ 534 uint8_t qtype; 535 uint8_t tc; 536 uint8_t index; 537 uint8_t options; 538 uint32_t pad0; 539 /* cmd word 1 */ 540 uint32_t dest_id; 541 uint16_t pad1; 542 uint8_t dest_prio; 543 uint8_t flags; 544 /* cmd word 2 */ 545 uint64_t flc; 546 /* cmd word 3 */ 547 uint64_t user_context; 548 /* cmd word 4 */ 549 uint8_t cgid; 550 }; 551 552 #define DPNI_DISCARD_ON_MISS_SHIFT 0 553 #define DPNI_DISCARD_ON_MISS_SIZE 1 554 #define DPNI_KEEP_QOS_ENTRIES_SHIFT 1 555 #define DPNI_KEEP_QOS_ENTRIES_SIZE 1 556 557 struct dpni_cmd_set_qos_table { 558 uint32_t pad; 559 uint8_t default_tc; 560 /* only the LSB */ 561 uint8_t discard_on_miss; 562 uint16_t pad1[21]; 563 uint64_t key_cfg_iova; 564 }; 565 566 #define DPNI_QOS_OPT_SET_TC_ONLY 0x0 567 #define DPNI_QOS_OPT_SET_FLOW_ID 0x1 568 569 struct dpni_cmd_add_qos_entry { 570 uint8_t flags; 571 uint8_t flow_id; 572 uint8_t tc_id; 573 uint8_t key_size; 574 uint16_t index; 575 uint16_t pad2; 576 uint64_t key_iova; 577 uint64_t mask_iova; 578 }; 579 580 struct dpni_cmd_remove_qos_entry { 581 uint8_t pad1[3]; 582 uint8_t key_size; 583 uint32_t pad2; 584 uint64_t key_iova; 585 uint64_t mask_iova; 586 }; 587 588 struct dpni_cmd_add_fs_entry { 589 uint16_t options; 590 uint8_t tc_id; 591 uint8_t key_size; 592 uint16_t index; 593 uint16_t flow_id; 594 uint64_t key_iova; 595 uint64_t mask_iova; 596 uint64_t flc; 597 }; 598 599 struct dpni_cmd_remove_fs_entry { 600 uint16_t pad1; 601 uint8_t tc_id; 602 uint8_t key_size; 603 uint32_t pad2; 604 uint64_t key_iova; 605 uint64_t mask_iova; 606 }; 607 608 struct dpni_cmd_clear_fs_entries { 609 uint16_t pad; 610 uint8_t tc_id; 611 }; 612 613 #define DPNI_MODE_SHIFT 0 614 #define DPNI_MODE_SIZE 4 615 #define DPNI_COLOR_SHIFT 4 616 #define DPNI_COLOR_SIZE 4 617 #define DPNI_UNITS_SHIFT 0 618 #define DPNI_UNITS_SIZE 4 619 620 struct dpni_cmd_set_rx_tc_policing { 621 /* from LSB: mode:4 color:4 */ 622 uint8_t mode_color; 623 /* from LSB: units: 4 */ 624 uint8_t units; 625 uint8_t tc_id; 626 uint8_t pad; 627 uint32_t options; 628 uint32_t cir; 629 uint32_t cbs; 630 uint32_t eir; 631 uint32_t ebs; 632 }; 633 634 struct dpni_cmd_get_rx_tc_policing { 635 uint16_t pad; 636 uint8_t tc_id; 637 }; 638 639 struct dpni_rsp_get_rx_tc_policing { 640 /* from LSB: mode:4 color:4 */ 641 uint8_t mode_color; 642 /* from LSB: units: 4 */ 643 uint8_t units; 644 uint16_t pad; 645 uint32_t options; 646 uint32_t cir; 647 uint32_t cbs; 648 uint32_t eir; 649 uint32_t ebs; 650 }; 651 652 #define DPNI_DROP_ENABLE_SHIFT 0 653 #define DPNI_DROP_ENABLE_SIZE 1 654 #define DPNI_DROP_UNITS_SHIFT 2 655 #define DPNI_DROP_UNITS_SIZE 2 656 657 struct dpni_early_drop { 658 /* from LSB: enable:1 units:2 */ 659 uint8_t flags; 660 uint8_t pad0[3]; 661 uint32_t pad1; 662 uint8_t green_drop_probability; 663 uint8_t pad2[7]; 664 uint64_t green_max_threshold; 665 uint64_t green_min_threshold; 666 uint64_t pad3; 667 uint8_t yellow_drop_probability; 668 uint8_t pad4[7]; 669 uint64_t yellow_max_threshold; 670 uint64_t yellow_min_threshold; 671 uint64_t pad5; 672 uint8_t red_drop_probability; 673 uint8_t pad6[7]; 674 uint64_t red_max_threshold; 675 uint64_t red_min_threshold; 676 }; 677 678 struct dpni_cmd_early_drop { 679 uint8_t qtype; 680 uint8_t tc; 681 uint8_t pad[6]; 682 uint64_t early_drop_iova; 683 }; 684 685 struct dpni_rsp_get_api_version { 686 uint16_t major; 687 uint16_t minor; 688 }; 689 690 struct dpni_cmd_get_taildrop { 691 uint8_t congestion_point; 692 uint8_t qtype; 693 uint8_t tc; 694 uint8_t index; 695 }; 696 697 struct dpni_rsp_get_taildrop { 698 /* cmd word 0 */ 699 uint64_t pad0; 700 /* cmd word 1 */ 701 /* from LSB: enable:1 oal_lo:7 */ 702 uint8_t enable_oal_lo; 703 /* from LSB: oal_hi:5 */ 704 uint8_t oal_hi; 705 uint8_t units; 706 uint8_t pad2; 707 uint32_t threshold; 708 }; 709 710 #define DPNI_OAL_LO_SHIFT 1 711 #define DPNI_OAL_LO_SIZE 7 712 #define DPNI_OAL_HI_SHIFT 0 713 #define DPNI_OAL_HI_SIZE 5 714 715 struct dpni_cmd_set_taildrop { 716 /* cmd word 0 */ 717 uint8_t congestion_point; 718 uint8_t qtype; 719 uint8_t tc; 720 uint8_t index; 721 uint32_t pad0; 722 /* cmd word 1 */ 723 /* from LSB: enable:1 oal_lo:7 */ 724 uint8_t enable_oal_lo; 725 /* from LSB: oal_hi:5 */ 726 uint8_t oal_hi; 727 uint8_t units; 728 uint8_t pad2; 729 uint32_t threshold; 730 }; 731 732 struct dpni_tx_confirmation_mode { 733 uint32_t pad; 734 uint8_t confirmation_mode; 735 }; 736 737 #define DPNI_DEST_TYPE_SHIFT 0 738 #define DPNI_DEST_TYPE_SIZE 4 739 #define DPNI_CONG_UNITS_SHIFT 4 740 #define DPNI_CONG_UNITS_SIZE 2 741 742 struct dpni_cmd_set_congestion_notification { 743 uint8_t qtype; 744 uint8_t tc; 745 uint8_t pad; 746 uint8_t congestion_point; 747 uint8_t cgid; 748 uint8_t pad2[3]; 749 uint32_t dest_id; 750 uint16_t notification_mode; 751 uint8_t dest_priority; 752 /* from LSB: dest_type: 4 units:2 */ 753 uint8_t type_units; 754 uint64_t message_iova; 755 uint64_t message_ctx; 756 uint32_t threshold_entry; 757 uint32_t threshold_exit; 758 }; 759 760 struct dpni_cmd_get_congestion_notification { 761 uint8_t qtype; 762 uint8_t tc; 763 uint8_t pad; 764 uint8_t congestion_point; 765 uint8_t cgid; 766 }; 767 768 struct dpni_rsp_get_congestion_notification { 769 uint64_t pad; 770 uint32_t dest_id; 771 uint16_t notification_mode; 772 uint8_t dest_priority; 773 /* from LSB: dest_type: 4 units:2 */ 774 uint8_t type_units; 775 uint64_t message_iova; 776 uint64_t message_ctx; 777 uint32_t threshold_entry; 778 uint32_t threshold_exit; 779 }; 780 781 struct dpni_cmd_set_opr { 782 uint8_t pad0; 783 uint8_t tc_id; 784 uint8_t index; 785 uint8_t options; 786 uint8_t pad1[7]; 787 uint8_t oloe; 788 uint8_t oeane; 789 uint8_t olws; 790 uint8_t oa; 791 uint8_t oprrws; 792 }; 793 794 struct dpni_cmd_get_opr { 795 uint8_t pad; 796 uint8_t tc_id; 797 uint8_t index; 798 }; 799 800 #define DPNI_RIP_SHIFT 0 801 #define DPNI_RIP_SIZE 1 802 #define DPNI_OPR_ENABLE_SHIFT 1 803 #define DPNI_OPR_ENABLE_SIZE 1 804 #define DPNI_TSEQ_NLIS_SHIFT 0 805 #define DPNI_TSEQ_NLIS_SIZE 1 806 #define DPNI_HSEQ_NLIS_SHIFT 0 807 #define DPNI_HSEQ_NLIS_SIZE 1 808 809 struct dpni_rsp_get_opr { 810 uint64_t pad0; 811 /* from LSB: rip:1 enable:1 */ 812 uint8_t flags; 813 uint16_t pad1; 814 uint8_t oloe; 815 uint8_t oeane; 816 uint8_t olws; 817 uint8_t oa; 818 uint8_t oprrws; 819 uint16_t nesn; 820 uint16_t pad8; 821 uint16_t ndsn; 822 uint16_t pad2; 823 uint16_t ea_tseq; 824 /* only the LSB */ 825 uint8_t tseq_nlis; 826 uint8_t pad3; 827 uint16_t ea_hseq; 828 /* only the LSB */ 829 uint8_t hseq_nlis; 830 uint8_t pad4; 831 uint16_t ea_hptr; 832 uint16_t pad5; 833 uint16_t ea_tptr; 834 uint16_t pad6; 835 uint16_t opr_vid; 836 uint16_t pad7; 837 uint16_t opr_id; 838 }; 839 840 struct dpni_cmd_add_custom_tpid { 841 uint16_t pad; 842 uint16_t tpid; 843 }; 844 845 struct dpni_cmd_remove_custom_tpid { 846 uint16_t pad; 847 uint16_t tpid; 848 }; 849 850 struct dpni_rsp_get_custom_tpid { 851 uint16_t tpid1; 852 uint16_t tpid2; 853 }; 854 855 #define DPNI_RX_FS_DIST_ENABLE_SHIFT 0 856 #define DPNI_RX_FS_DIST_ENABLE_SIZE 1 857 struct dpni_cmd_set_rx_fs_dist { 858 uint16_t dist_size; 859 uint8_t enable; 860 uint8_t tc; 861 uint16_t miss_flow_id; 862 uint16_t pad1; 863 uint64_t key_cfg_iova; 864 }; 865 866 #define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0 867 #define DPNI_RX_HASH_DIST_ENABLE_SIZE 1 868 struct dpni_cmd_set_rx_hash_dist { 869 uint16_t dist_size; 870 uint8_t enable; 871 uint8_t tc_id; 872 uint32_t pad; 873 uint64_t key_cfg_iova; 874 }; 875 876 struct dpni_load_sw_sequence { 877 uint8_t dest; 878 uint8_t pad0[7]; 879 uint16_t ss_offset; 880 uint16_t pad1; 881 uint16_t ss_size; 882 uint16_t pad2; 883 uint64_t ss_iova; 884 }; 885 886 struct dpni_enable_sw_sequence { 887 uint8_t dest; 888 uint8_t pad0[7]; 889 uint16_t ss_offset; 890 uint16_t hxs; 891 uint8_t set_start; 892 uint8_t pad1[3]; 893 uint8_t param_offset; 894 uint8_t pad2[3]; 895 uint8_t param_size; 896 uint8_t pad3[3]; 897 uint64_t param_iova; 898 }; 899 900 struct dpni_get_sw_sequence_layout { 901 uint8_t src; 902 uint8_t pad0[7]; 903 uint64_t layout_iova; 904 }; 905 906 struct dpni_sw_sequence_layout_entry { 907 uint16_t ss_offset; 908 uint16_t ss_size; 909 uint8_t param_offset; 910 uint8_t param_size; 911 uint16_t pad; 912 }; 913 914 #pragma pack(pop) 915 #endif /* _FSL_DPNI_CMD_H */ 916