1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2022 NXP 4 * 5 */ 6 7 #ifndef _DPAA2_PARSE_DUMP_H 8 #define _DPAA2_PARSE_DUMP_H 9 10 #include <rte_event_eth_rx_adapter.h> 11 #include <rte_pmd_dpaa2.h> 12 13 #include <dpaa2_hw_pvt.h> 14 #include "dpaa2_tm.h" 15 16 #include <mc/fsl_dpni.h> 17 #include <mc/fsl_mc_sys.h> 18 19 #include "base/dpaa2_hw_dpni_annot.h" 20 21 #define DPAA2_PR_PRINT printf 22 23 struct dpaa2_faf_bit_info { 24 const char *name; 25 int position; 26 }; 27 28 struct dpaa2_fapr_field_info { 29 const char *name; 30 uint16_t value; 31 }; 32 33 struct dpaa2_fapr_array { 34 union { 35 uint64_t pr_64[DPAA2_FAPR_SIZE / 8]; 36 uint8_t pr[DPAA2_FAPR_SIZE]; 37 }; 38 }; 39 40 #define NEXT_HEADER_NAME "Next Header" 41 #define ETH_OFF_NAME "ETH OFFSET" 42 #define VLAN_TCI_OFF_NAME "VLAN TCI OFFSET" 43 #define LAST_ENTRY_OFF_NAME "LAST ETYPE Offset" 44 #define L3_OFF_NAME "L3 Offset" 45 #define L4_OFF_NAME "L4 Offset" 46 #define L5_OFF_NAME "L5 Offset" 47 #define NEXT_HEADER_OFF_NAME "Next Header Offset" 48 49 static const 50 struct dpaa2_fapr_field_info support_dump_fields[] = { 51 { 52 .name = NEXT_HEADER_NAME, 53 }, 54 { 55 .name = ETH_OFF_NAME, 56 }, 57 { 58 .name = VLAN_TCI_OFF_NAME, 59 }, 60 { 61 .name = LAST_ENTRY_OFF_NAME, 62 }, 63 { 64 .name = L3_OFF_NAME, 65 }, 66 { 67 .name = L4_OFF_NAME, 68 }, 69 { 70 .name = L5_OFF_NAME, 71 }, 72 { 73 .name = NEXT_HEADER_OFF_NAME, 74 } 75 }; 76 77 static inline void 78 dpaa2_print_faf(struct dpaa2_fapr_array *fapr) 79 { 80 const int faf_bit_len = DPAA2_FAF_TOTAL_SIZE * 8; 81 struct dpaa2_faf_bit_info faf_bits[faf_bit_len]; 82 int i, byte_pos, bit_pos, vxlan = 0, vxlan_vlan = 0; 83 struct rte_ether_hdr vxlan_in_eth; 84 uint16_t vxlan_vlan_tci; 85 86 for (i = 0; i < faf_bit_len; i++) { 87 faf_bits[i].position = i; 88 if (i == FAFE_VXLAN_IN_VLAN_FRAM) 89 faf_bits[i].name = "VXLAN VLAN Present"; 90 else if (i == FAFE_VXLAN_IN_IPV4_FRAM) 91 faf_bits[i].name = "VXLAN IPV4 Present"; 92 else if (i == FAFE_VXLAN_IN_IPV6_FRAM) 93 faf_bits[i].name = "VXLAN IPV6 Present"; 94 else if (i == FAFE_VXLAN_IN_UDP_FRAM) 95 faf_bits[i].name = "VXLAN UDP Present"; 96 else if (i == FAFE_VXLAN_IN_TCP_FRAM) 97 faf_bits[i].name = "VXLAN TCP Present"; 98 else if (i == FAF_VXLAN_FRAM) 99 faf_bits[i].name = "VXLAN Present"; 100 else if (i == FAF_ETH_FRAM) 101 faf_bits[i].name = "Ethernet MAC Present"; 102 else if (i == FAF_VLAN_FRAM) 103 faf_bits[i].name = "VLAN 1 Present"; 104 else if (i == FAF_IPV4_FRAM) 105 faf_bits[i].name = "IPv4 1 Present"; 106 else if (i == FAF_IPV6_FRAM) 107 faf_bits[i].name = "IPv6 1 Present"; 108 else if (i == FAF_IP_FRAG_FRAM) 109 faf_bits[i].name = "IP fragment Present"; 110 else if (i == FAF_UDP_FRAM) 111 faf_bits[i].name = "UDP Present"; 112 else if (i == FAF_TCP_FRAM) 113 faf_bits[i].name = "TCP Present"; 114 else 115 faf_bits[i].name = "Check RM for this unusual frame"; 116 } 117 118 DPAA2_PR_PRINT("Frame Annotation Flags:\r\n"); 119 for (i = 0; i < faf_bit_len; i++) { 120 byte_pos = i / 8 + DPAA2_FAFE_PSR_OFFSET; 121 bit_pos = i % 8; 122 if (fapr->pr[byte_pos] & (1 << (7 - bit_pos))) { 123 DPAA2_PR_PRINT("FAF bit %d : %s\r\n", 124 faf_bits[i].position, faf_bits[i].name); 125 if (i == FAF_VXLAN_FRAM) 126 vxlan = 1; 127 } 128 } 129 130 if (vxlan) { 131 vxlan_in_eth.dst_addr.addr_bytes[0] = 132 fapr->pr[DPAA2_VXLAN_IN_DADDR0_OFFSET]; 133 vxlan_in_eth.dst_addr.addr_bytes[1] = 134 fapr->pr[DPAA2_VXLAN_IN_DADDR1_OFFSET]; 135 vxlan_in_eth.dst_addr.addr_bytes[2] = 136 fapr->pr[DPAA2_VXLAN_IN_DADDR2_OFFSET]; 137 vxlan_in_eth.dst_addr.addr_bytes[3] = 138 fapr->pr[DPAA2_VXLAN_IN_DADDR3_OFFSET]; 139 vxlan_in_eth.dst_addr.addr_bytes[4] = 140 fapr->pr[DPAA2_VXLAN_IN_DADDR4_OFFSET]; 141 vxlan_in_eth.dst_addr.addr_bytes[5] = 142 fapr->pr[DPAA2_VXLAN_IN_DADDR5_OFFSET]; 143 144 vxlan_in_eth.src_addr.addr_bytes[0] = 145 fapr->pr[DPAA2_VXLAN_IN_SADDR0_OFFSET]; 146 vxlan_in_eth.src_addr.addr_bytes[1] = 147 fapr->pr[DPAA2_VXLAN_IN_SADDR1_OFFSET]; 148 vxlan_in_eth.src_addr.addr_bytes[2] = 149 fapr->pr[DPAA2_VXLAN_IN_SADDR2_OFFSET]; 150 vxlan_in_eth.src_addr.addr_bytes[3] = 151 fapr->pr[DPAA2_VXLAN_IN_SADDR3_OFFSET]; 152 vxlan_in_eth.src_addr.addr_bytes[4] = 153 fapr->pr[DPAA2_VXLAN_IN_SADDR4_OFFSET]; 154 vxlan_in_eth.src_addr.addr_bytes[5] = 155 fapr->pr[DPAA2_VXLAN_IN_SADDR5_OFFSET]; 156 157 vxlan_in_eth.ether_type = 158 fapr->pr[DPAA2_VXLAN_IN_TYPE_OFFSET]; 159 vxlan_in_eth.ether_type = 160 vxlan_in_eth.ether_type << 8; 161 vxlan_in_eth.ether_type |= 162 fapr->pr[DPAA2_VXLAN_IN_TYPE_OFFSET + 1]; 163 164 if (vxlan_in_eth.ether_type == RTE_ETHER_TYPE_VLAN) 165 vxlan_vlan = 1; 166 DPAA2_PR_PRINT("VXLAN inner eth:\r\n"); 167 DPAA2_PR_PRINT("dst addr: "); 168 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) { 169 if (i != 0) 170 DPAA2_PR_PRINT(":"); 171 DPAA2_PR_PRINT("%02x", 172 vxlan_in_eth.dst_addr.addr_bytes[i]); 173 } 174 DPAA2_PR_PRINT("\r\n"); 175 DPAA2_PR_PRINT("src addr: "); 176 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) { 177 if (i != 0) 178 DPAA2_PR_PRINT(":"); 179 DPAA2_PR_PRINT("%02x", 180 vxlan_in_eth.src_addr.addr_bytes[i]); 181 } 182 DPAA2_PR_PRINT("\r\n"); 183 DPAA2_PR_PRINT("type: 0x%04x\r\n", 184 vxlan_in_eth.ether_type); 185 if (vxlan_vlan) { 186 vxlan_vlan_tci = fapr->pr[DPAA2_VXLAN_IN_TCI_OFFSET]; 187 vxlan_vlan_tci = vxlan_vlan_tci << 8; 188 vxlan_vlan_tci |= 189 fapr->pr[DPAA2_VXLAN_IN_TCI_OFFSET + 1]; 190 191 DPAA2_PR_PRINT("vlan tci: 0x%04x\r\n", 192 vxlan_vlan_tci); 193 } 194 } 195 } 196 197 static inline void 198 dpaa2_print_parse_result(struct dpaa2_annot_hdr *annotation) 199 { 200 struct dpaa2_fapr_array fapr; 201 struct dpaa2_fapr_field_info 202 fapr_fields[sizeof(support_dump_fields) / 203 sizeof(struct dpaa2_fapr_field_info)]; 204 uint64_t len, i; 205 206 memcpy(&fapr, &annotation->word3, DPAA2_FAPR_SIZE); 207 for (i = 0; i < (DPAA2_FAPR_SIZE / 8); i++) 208 fapr.pr_64[i] = rte_cpu_to_be_64(fapr.pr_64[i]); 209 210 memcpy(fapr_fields, support_dump_fields, 211 sizeof(support_dump_fields)); 212 213 for (i = 0; 214 i < sizeof(fapr_fields) / 215 sizeof(struct dpaa2_fapr_field_info); 216 i++) { 217 if (!strcmp(fapr_fields[i].name, NEXT_HEADER_NAME)) { 218 fapr_fields[i].value = fapr.pr[DPAA2_PR_NXTHDR_OFFSET]; 219 fapr_fields[i].value = fapr_fields[i].value << 8; 220 fapr_fields[i].value |= 221 fapr.pr[DPAA2_PR_NXTHDR_OFFSET + 1]; 222 } else if (!strcmp(fapr_fields[i].name, ETH_OFF_NAME)) { 223 fapr_fields[i].value = fapr.pr[DPAA2_PR_ETH_OFF_OFFSET]; 224 } else if (!strcmp(fapr_fields[i].name, VLAN_TCI_OFF_NAME)) { 225 fapr_fields[i].value = fapr.pr[DPAA2_PR_TCI_OFF_OFFSET]; 226 } else if (!strcmp(fapr_fields[i].name, LAST_ENTRY_OFF_NAME)) { 227 fapr_fields[i].value = 228 fapr.pr[DPAA2_PR_LAST_ETYPE_OFFSET]; 229 } else if (!strcmp(fapr_fields[i].name, L3_OFF_NAME)) { 230 fapr_fields[i].value = fapr.pr[DPAA2_PR_L3_OFF_OFFSET]; 231 } else if (!strcmp(fapr_fields[i].name, L4_OFF_NAME)) { 232 fapr_fields[i].value = fapr.pr[DPAA2_PR_L4_OFF_OFFSET]; 233 } else if (!strcmp(fapr_fields[i].name, L5_OFF_NAME)) { 234 fapr_fields[i].value = fapr.pr[DPAA2_PR_L5_OFF_OFFSET]; 235 } else if (!strcmp(fapr_fields[i].name, NEXT_HEADER_OFF_NAME)) { 236 fapr_fields[i].value = 237 fapr.pr[DPAA2_PR_NXTHDR_OFF_OFFSET]; 238 } 239 } 240 241 len = sizeof(fapr_fields) / sizeof(struct dpaa2_fapr_field_info); 242 DPAA2_PR_PRINT("Parse Result:\r\n"); 243 for (i = 0; i < len; i++) { 244 DPAA2_PR_PRINT("%21s : 0x%02x\r\n", 245 fapr_fields[i].name, fapr_fields[i].value); 246 } 247 dpaa2_print_faf(&fapr); 248 } 249 250 #endif 251