xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.h (revision f5057be340e44f3edc0fe90fa875eb89a4c49b4f)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
4  *   Copyright 2017-2019 NXP
5  *
6  */
7 #ifndef __DPAA_ETHDEV_H__
8 #define __DPAA_ETHDEV_H__
9 
10 /* System headers */
11 #include <stdbool.h>
12 #include <rte_ethdev_driver.h>
13 #include <rte_event_eth_rx_adapter.h>
14 
15 #include <fsl_usd.h>
16 #include <fsl_qman.h>
17 #include <fsl_bman.h>
18 #include <dpaa_of.h>
19 #include <netcfg.h>
20 
21 #define MAX_DPAA_CORES			4
22 #define DPAA_MBUF_HW_ANNOTATION		64
23 #define DPAA_FD_PTA_SIZE		64
24 
25 /* mbuf->seqn will be used to store event entry index for
26  * driver specific usage. For parallel mode queues, invalid
27  * index will be set and for atomic mode queues, valid value
28  * ranging from 1 to 16.
29  */
30 #define DPAA_INVALID_MBUF_SEQN  0
31 
32 /* we will re-use the HEADROOM for annotation in RX */
33 #define DPAA_HW_BUF_RESERVE	0
34 #define DPAA_PACKET_LAYOUT_ALIGN	64
35 
36 /* Alignment to use for cpu-local structs to avoid coherency problems. */
37 #define MAX_CACHELINE			64
38 
39 #define DPAA_MAX_RX_PKT_LEN  10240
40 
41 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
42 
43 /* RX queue tail drop threshold (CGR Based) in frame count */
44 #define CGR_RX_PERFQ_THRESH 256
45 #define CGR_TX_CGR_THRESH 512
46 
47 /*max mac filter for memac(8) including primary mac addr*/
48 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
49 
50 /*Maximum number of slots available in TX ring*/
51 #define DPAA_TX_BURST_SIZE	7
52 
53 /* Optimal burst size for RX and TX as default */
54 #define DPAA_DEF_RX_BURST_SIZE 7
55 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE
56 
57 #ifndef VLAN_TAG_SIZE
58 #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
59 #endif
60 
61 /* PCD frame queues */
62 #define DPAA_DEFAULT_NUM_PCD_QUEUES	1
63 #define DPAA_VSP_PROFILE_MAX_NUM	8
64 #define DPAA_MAX_NUM_PCD_QUEUES	DPAA_VSP_PROFILE_MAX_NUM
65 /*Same as VSP profile number*/
66 
67 #define DPAA_IF_TX_PRIORITY		3
68 #define DPAA_IF_RX_PRIORITY		0
69 #define DPAA_IF_DEBUG_PRIORITY		7
70 
71 #define DPAA_IF_RX_ANNOTATION_STASH	1
72 #define DPAA_IF_RX_DATA_STASH		1
73 #define DPAA_IF_RX_CONTEXT_STASH		0
74 
75 /* Each "debug" FQ is represented by one of these */
76 #define DPAA_DEBUG_FQ_RX_ERROR   0
77 #define DPAA_DEBUG_FQ_TX_ERROR   1
78 
79 #define DPAA_RSS_OFFLOAD_ALL ( \
80 	ETH_RSS_L2_PAYLOAD | \
81 	ETH_RSS_IP | \
82 	ETH_RSS_UDP | \
83 	ETH_RSS_TCP | \
84 	ETH_RSS_SCTP)
85 
86 #define DPAA_TX_CKSUM_OFFLOAD_MASK (             \
87 		PKT_TX_IP_CKSUM |                \
88 		PKT_TX_TCP_CKSUM |               \
89 		PKT_TX_UDP_CKSUM)
90 
91 /* DPAA Frame descriptor macros */
92 
93 #define DPAA_FD_CMD_FCO			0x80000000
94 /**< Frame queue Context Override */
95 #define DPAA_FD_CMD_RPD			0x40000000
96 /**< Read Prepended Data */
97 #define DPAA_FD_CMD_UPD			0x20000000
98 /**< Update Prepended Data */
99 #define DPAA_FD_CMD_DTC			0x10000000
100 /**< Do IP/TCP/UDP Checksum */
101 #define DPAA_FD_CMD_DCL4C		0x10000000
102 /**< Didn't calculate L4 Checksum */
103 #define DPAA_FD_CMD_CFQ			0x00ffffff
104 /**< Confirmation Frame Queue */
105 
106 #define DPAA_DEFAULT_RXQ_VSP_ID		1
107 
108 #define FMC_FILE "/tmp/fmc.bin"
109 
110 /* Each network interface is represented by one of these */
111 struct dpaa_if {
112 	int valid;
113 	char *name;
114 	const struct fm_eth_port_cfg *cfg;
115 	struct qman_fq *rx_queues;
116 	struct qman_cgr *cgr_rx;
117 	struct qman_fq *tx_queues;
118 	struct qman_cgr *cgr_tx;
119 	struct qman_fq debug_queues[2];
120 	uint16_t nb_rx_queues;
121 	uint16_t nb_tx_queues;
122 	uint32_t ifid;
123 	struct dpaa_bp_info *bp_info;
124 	struct rte_eth_fc_conf *fc_conf;
125 	void *port_handle;
126 	void *netenv_handle;
127 	void *scheme_handle[2];
128 	uint32_t scheme_count;
129 
130 	void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM];
131 	uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM];
132 };
133 
134 struct dpaa_if_stats {
135 	/* Rx Statistics Counter */
136 	uint64_t reoct;		/**<Rx Eth Octets Counter */
137 	uint64_t roct;		/**<Rx Octet Counters */
138 	uint64_t raln;		/**<Rx Alignment Error Counter */
139 	uint64_t rxpf;		/**<Rx valid Pause Frame */
140 	uint64_t rfrm;		/**<Rx Frame counter */
141 	uint64_t rfcs;		/**<Rx frame check seq error */
142 	uint64_t rvlan;		/**<Rx Vlan Frame Counter */
143 	uint64_t rerr;		/**<Rx Frame error */
144 	uint64_t ruca;		/**<Rx Unicast */
145 	uint64_t rmca;		/**<Rx Multicast */
146 	uint64_t rbca;		/**<Rx Broadcast */
147 	uint64_t rdrp;		/**<Rx Dropped Packet */
148 	uint64_t rpkt;		/**<Rx packet */
149 	uint64_t rund;		/**<Rx undersized packets */
150 	uint32_t res_x[14];
151 	uint64_t rovr;		/**<Rx oversized but good */
152 	uint64_t rjbr;		/**<Rx oversized with bad csum */
153 	uint64_t rfrg;		/**<Rx fragment Packet */
154 	uint64_t rcnp;		/**<Rx control packets (0x8808 */
155 	uint64_t rdrntp;	/**<Rx dropped due to FIFO overflow */
156 	uint32_t res01d0[12];
157 	/* Tx Statistics Counter */
158 	uint64_t teoct;		/**<Tx eth octets */
159 	uint64_t toct;		/**<Tx Octets */
160 	uint32_t res0210[2];
161 	uint64_t txpf;		/**<Tx valid pause frame */
162 	uint64_t tfrm;		/**<Tx frame counter */
163 	uint64_t tfcs;		/**<Tx FCS error */
164 	uint64_t tvlan;		/**<Tx Vlan Frame */
165 	uint64_t terr;		/**<Tx frame error */
166 	uint64_t tuca;		/**<Tx Unicast */
167 	uint64_t tmca;		/**<Tx Multicast */
168 	uint64_t tbca;		/**<Tx Broadcast */
169 	uint32_t res0258[2];
170 	uint64_t tpkt;		/**<Tx Packet */
171 	uint64_t tund;		/**<Tx Undersized */
172 };
173 
174 __rte_internal
175 int
176 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
177 		int eth_rx_queue_id,
178 		u16 ch_id,
179 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
180 
181 __rte_internal
182 int
183 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
184 			   int eth_rx_queue_id);
185 
186 enum qman_cb_dqrr_result
187 dpaa_rx_cb_parallel(void *event,
188 		    struct qman_portal *qm __always_unused,
189 		    struct qman_fq *fq,
190 		    const struct qm_dqrr_entry *dqrr,
191 		    void **bufs);
192 enum qman_cb_dqrr_result
193 dpaa_rx_cb_atomic(void *event,
194 		  struct qman_portal *qm __always_unused,
195 		  struct qman_fq *fq,
196 		  const struct qm_dqrr_entry *dqrr,
197 		  void **bufs);
198 
199 /* PMD related logs */
200 extern int dpaa_logtype_pmd;
201 
202 #define DPAA_PMD_LOG(level, fmt, args...) \
203 	rte_log(RTE_LOG_ ## level, dpaa_logtype_pmd, "%s(): " fmt "\n", \
204 		__func__, ##args)
205 
206 #define PMD_INIT_FUNC_TRACE() DPAA_PMD_LOG(DEBUG, " >>")
207 
208 #define DPAA_PMD_DEBUG(fmt, args...) \
209 	DPAA_PMD_LOG(DEBUG, fmt, ## args)
210 #define DPAA_PMD_ERR(fmt, args...) \
211 	DPAA_PMD_LOG(ERR, fmt, ## args)
212 #define DPAA_PMD_INFO(fmt, args...) \
213 	DPAA_PMD_LOG(INFO, fmt, ## args)
214 #define DPAA_PMD_WARN(fmt, args...) \
215 	DPAA_PMD_LOG(WARNING, fmt, ## args)
216 
217 /* DP Logs, toggled out at compile time if level lower than current level */
218 #define DPAA_DP_LOG(level, fmt, args...) \
219 	RTE_LOG_DP(level, PMD, fmt, ## args)
220 
221 #endif
222