xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.h (revision fd51012de5369679e807be1d6a81d63ef15015ce)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
4  *   Copyright 2017-2024 NXP
5  *
6  */
7 #ifndef __DPAA_ETHDEV_H__
8 #define __DPAA_ETHDEV_H__
9 
10 /* System headers */
11 #include <stdbool.h>
12 #include <ethdev_driver.h>
13 #include <rte_compat.h>
14 #include <rte_event_eth_rx_adapter.h>
15 
16 #include <fsl_usd.h>
17 #include <fsl_qman.h>
18 #include <fsl_bman.h>
19 #include <dpaa_of.h>
20 #include <netcfg.h>
21 
22 #define MAX_DPAA_CORES			4
23 #define DPAA_MBUF_HW_ANNOTATION		64
24 #define DPAA_FD_PTA_SIZE		64
25 
26 /* we will re-use the HEADROOM for annotation in RX */
27 #define DPAA_HW_BUF_RESERVE	0
28 #define DPAA_PACKET_LAYOUT_ALIGN	64
29 
30 /* Alignment to use for cpu-local structs to avoid coherency problems. */
31 #define MAX_CACHELINE			64
32 
33 #define DPAA_MAX_RX_PKT_LEN  10240
34 
35 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
36 
37 /* Maximum SG segments supported on all cores*/
38 #define DPAA_MAX_SGS 128
39 /* SG pool size */
40 #define DPAA_POOL_SIZE 2048
41 /* SG pool cache size */
42 #define DPAA_POOL_CACHE_SIZE 256
43 
44 /* RX queue tail drop threshold (CGR Based) in frame count */
45 #define CGR_RX_PERFQ_THRESH 256
46 #define CGR_TX_CGR_THRESH 512
47 
48 /*max mac filter for memac(8) including primary mac addr*/
49 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
50 
51 /*Maximum number of slots available in TX ring*/
52 #define DPAA_TX_BURST_SIZE	7
53 
54 /* Optimal burst size for RX and TX as default */
55 #define DPAA_DEF_RX_BURST_SIZE 7
56 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE
57 
58 #ifndef VLAN_TAG_SIZE
59 #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
60 #endif
61 
62 #define DPAA_ETH_MAX_LEN (RTE_ETHER_MTU + \
63 			  RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
64 			  VLAN_TAG_SIZE)
65 
66 /* PCD frame queues */
67 #define DPAA_DEFAULT_NUM_PCD_QUEUES	1
68 #define DPAA_VSP_PROFILE_MAX_NUM	8
69 #define DPAA_MAX_NUM_PCD_QUEUES	DPAA_VSP_PROFILE_MAX_NUM
70 /*Same as VSP profile number*/
71 
72 #define DPAA_IF_TX_PRIORITY		3
73 #define DPAA_IF_RX_PRIORITY		0
74 #define DPAA_IF_DEBUG_PRIORITY		7
75 
76 #define DPAA_IF_RX_ANNOTATION_STASH	1
77 #define DPAA_IF_RX_DATA_STASH		1
78 #define DPAA_IF_RX_CONTEXT_STASH		0
79 
80 /* Each "debug" FQ is represented by one of these */
81 enum {
82 	DPAA_DEBUG_FQ_RX_ERROR,
83 	DPAA_DEBUG_FQ_TX_ERROR,
84 	DPAA_DEBUG_FQ_MAX_NUM
85 };
86 
87 #define DPAA_RSS_OFFLOAD_ALL ( \
88 	RTE_ETH_RSS_L2_PAYLOAD | \
89 	RTE_ETH_RSS_IP | \
90 	RTE_ETH_RSS_UDP | \
91 	RTE_ETH_RSS_TCP | \
92 	RTE_ETH_RSS_SCTP)
93 
94 #define DPAA_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |                \
95 		RTE_MBUF_F_TX_TCP_CKSUM |               \
96 		RTE_MBUF_F_TX_UDP_CKSUM)
97 
98 /* DPAA Frame descriptor macros */
99 
100 #define DPAA_FD_CMD_FCO			0x80000000
101 /**< Frame queue Context Override */
102 #define DPAA_FD_CMD_RPD			0x40000000
103 /**< Read Prepended Data */
104 #define DPAA_FD_CMD_UPD			0x20000000
105 /**< Update Prepended Data */
106 #define DPAA_FD_CMD_DTC			0x10000000
107 /**< Do IP/TCP/UDP Checksum */
108 #define DPAA_FD_CMD_DCL4C		0x10000000
109 /**< Didn't calculate L4 Checksum */
110 #define DPAA_FD_CMD_CFQ			0x00ffffff
111 /**< Confirmation Frame Queue */
112 
113 #define DPAA_1G_MAC_START_IDX 1
114 #define DPAA_10G_MAC_START_IDX 9
115 #define DPAA_2_5G_MAC_START_IDX DPAA_10G_MAC_START_IDX
116 
117 #define DPAA_DEFAULT_RXQ_VSP_ID		1
118 
119 #define FMC_FILE "/tmp/fmc.bin"
120 
121 extern struct rte_mempool *dpaa_tx_sg_pool;
122 extern int dpaa_ieee_1588;
123 
124 /* PMD related logs */
125 extern int dpaa_logtype_pmd;
126 
127 /* structure to free external and indirect
128  * buffers.
129  */
130 struct dpaa_sw_buf_free {
131 	/* To which packet this segment belongs */
132 	uint16_t pkt_id;
133 	/* The actual segment */
134 	struct rte_mbuf *seg;
135 };
136 
137 /* Each network interface is represented by one of these */
138 struct dpaa_if {
139 	int valid;
140 	char *name;
141 	const struct fm_eth_port_cfg *cfg;
142 	struct qman_fq *rx_queues;
143 	struct qman_cgr *cgr_rx;
144 	struct qman_fq *tx_queues;
145 	struct qman_fq *tx_conf_queues;
146 	struct qman_cgr *cgr_tx;
147 	struct qman_fq debug_queues[DPAA_DEBUG_FQ_MAX_NUM];
148 	uint16_t nb_rx_queues;
149 	uint16_t nb_tx_queues;
150 	uint32_t ifid;
151 	struct dpaa_bp_info *bp_info;
152 	struct rte_eth_fc_conf *fc_conf;
153 	void *port_handle;
154 	void *netenv_handle;
155 	void *scheme_handle[2];
156 	uint32_t scheme_count;
157 	/*stores timestamp of last received packet on dev*/
158 	uint64_t rx_timestamp;
159 	/*stores timestamp of last received tx confirmation packet on dev*/
160 	uint64_t tx_timestamp;
161 	/* stores pointer to next tx_conf queue that should be processed,
162 	 * it corresponds to last packet transmitted
163 	 */
164 	struct qman_fq *next_tx_conf_queue;
165 
166 	void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM];
167 	uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM];
168 };
169 
170 struct dpaa_if_stats {
171 	/* Rx Statistics Counter */
172 	uint64_t reoct;		/**<Rx Eth Octets Counter */
173 	uint64_t roct;		/**<Rx Octet Counters */
174 	uint64_t raln;		/**<Rx Alignment Error Counter */
175 	uint64_t rxpf;		/**<Rx valid Pause Frame */
176 	uint64_t rfrm;		/**<Rx Frame counter */
177 	uint64_t rfcs;		/**<Rx frame check seq error */
178 	uint64_t rvlan;		/**<Rx Vlan Frame Counter */
179 	uint64_t rerr;		/**<Rx Frame error */
180 	uint64_t ruca;		/**<Rx Unicast */
181 	uint64_t rmca;		/**<Rx Multicast */
182 	uint64_t rbca;		/**<Rx Broadcast */
183 	uint64_t rdrp;		/**<Rx Dropped Packet */
184 	uint64_t rpkt;		/**<Rx packet */
185 	uint64_t rund;		/**<Rx undersized packets */
186 	uint32_t res_x[14];
187 	uint64_t rovr;		/**<Rx oversized but good */
188 	uint64_t rjbr;		/**<Rx oversized with bad csum */
189 	uint64_t rfrg;		/**<Rx fragment Packet */
190 	uint64_t rcnp;		/**<Rx control packets (0x8808 */
191 	uint64_t rdrntp;	/**<Rx dropped due to FIFO overflow */
192 	uint32_t res01d0[12];
193 	/* Tx Statistics Counter */
194 	uint64_t teoct;		/**<Tx eth octets */
195 	uint64_t toct;		/**<Tx Octets */
196 	uint32_t res0210[2];
197 	uint64_t txpf;		/**<Tx valid pause frame */
198 	uint64_t tfrm;		/**<Tx frame counter */
199 	uint64_t tfcs;		/**<Tx FCS error */
200 	uint64_t tvlan;		/**<Tx Vlan Frame */
201 	uint64_t terr;		/**<Tx frame error */
202 	uint64_t tuca;		/**<Tx Unicast */
203 	uint64_t tmca;		/**<Tx Multicast */
204 	uint64_t tbca;		/**<Tx Broadcast */
205 	uint32_t res0258[2];
206 	uint64_t tpkt;		/**<Tx Packet */
207 	uint64_t tund;		/**<Tx Undersized */
208 };
209 
210 __rte_internal
211 int
212 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
213 		int eth_rx_queue_id,
214 		u16 ch_id,
215 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
216 
217 __rte_internal
218 int
219 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
220 			   int eth_rx_queue_id);
221 
222 enum qman_cb_dqrr_result
223 dpaa_rx_cb_parallel(void *event,
224 		    struct qman_portal *qm __always_unused,
225 		    struct qman_fq *fq,
226 		    const struct qm_dqrr_entry *dqrr,
227 		    void **bufs);
228 enum qman_cb_dqrr_result
229 dpaa_rx_cb_atomic(void *event,
230 		  struct qman_portal *qm __always_unused,
231 		  struct qman_fq *fq,
232 		  const struct qm_dqrr_entry *dqrr,
233 		  void **bufs);
234 
235 struct dpaa_if_rx_bmi_stats {
236 	uint32_t fmbm_rstc;		/**< Rx Statistics Counters*/
237 	uint32_t fmbm_rfrc;		/**< Rx Frame Counter*/
238 	uint32_t fmbm_rfbc;		/**< Rx Bad Frames Counter*/
239 	uint32_t fmbm_rlfc;		/**< Rx Large Frames Counter*/
240 	uint32_t fmbm_rffc;		/**< Rx Filter Frames Counter*/
241 	uint32_t fmbm_rfdc;		/**< Rx Frame Discard Counter*/
242 	uint32_t fmbm_rfldec;		/**< Rx Frames List DMA Error Counter*/
243 	uint32_t fmbm_rodc;		/**< Rx Out of Buffers Discard nntr*/
244 	uint32_t fmbm_rbdc;		/**< Rx Buffers Deallocate Counter*/
245 };
246 
247 int
248 dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
249 		struct timespec *timestamp);
250 
251 int
252 dpaa_timesync_enable(struct rte_eth_dev *dev);
253 
254 int
255 dpaa_timesync_disable(struct rte_eth_dev *dev);
256 
257 int
258 dpaa_timesync_read_time(struct rte_eth_dev *dev,
259 		struct timespec *timestamp);
260 
261 int
262 dpaa_timesync_write_time(struct rte_eth_dev *dev,
263 		const struct timespec *timestamp);
264 int
265 dpaa_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
266 
267 int
268 dpaa_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
269 		struct timespec *timestamp,
270 		uint32_t flags __rte_unused);
271 
272 uint8_t
273 fm_default_vsp_id(struct fman_if *fif);
274 
275 /* PMD related logs */
276 extern int dpaa_logtype_pmd;
277 #define RTE_LOGTYPE_DPAA_PMD dpaa_logtype_pmd
278 
279 #define DPAA_PMD_LOG(level, ...) \
280 	RTE_LOG_LINE_PREFIX(level, DPAA_PMD, "%s(): ", __func__, __VA_ARGS__)
281 
282 #define PMD_INIT_FUNC_TRACE() DPAA_PMD_LOG(DEBUG, " >>")
283 
284 #define DPAA_PMD_DEBUG(fmt, ...) \
285 	DPAA_PMD_LOG(DEBUG, fmt, ## __VA_ARGS__)
286 #define DPAA_PMD_ERR(fmt, ...) \
287 	DPAA_PMD_LOG(ERR, fmt, ## __VA_ARGS__)
288 #define DPAA_PMD_INFO(fmt, ...) \
289 	DPAA_PMD_LOG(INFO, fmt, ## __VA_ARGS__)
290 #define DPAA_PMD_WARN(fmt, ...) \
291 	DPAA_PMD_LOG(WARNING, fmt, ## __VA_ARGS__)
292 
293 /* DP Logs, toggled out at compile time if level lower than current level */
294 #define DPAA_DP_LOG(level, ...) \
295 	RTE_LOG_DP_LINE(level, DPAA_PMD, __VA_ARGS__)
296 
297 #endif
298