1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 #ifndef __DPAA_ETHDEV_H__ 8 #define __DPAA_ETHDEV_H__ 9 10 /* System headers */ 11 #include <stdbool.h> 12 #include <rte_ethdev.h> 13 14 #include <fsl_usd.h> 15 #include <fsl_qman.h> 16 #include <fsl_bman.h> 17 #include <of.h> 18 #include <netcfg.h> 19 20 /* DPAA SoC identifier; If this is not available, it can be concluded 21 * that board is non-DPAA. Single slot is currently supported. 22 */ 23 #define DPAA_SOC_ID_FILE "sys/devices/soc0/soc_id" 24 25 #define DPAA_MBUF_HW_ANNOTATION 64 26 #define DPAA_FD_PTA_SIZE 64 27 28 #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM 29 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" 30 #endif 31 32 /* we will re-use the HEADROOM for annotation in RX */ 33 #define DPAA_HW_BUF_RESERVE 0 34 #define DPAA_PACKET_LAYOUT_ALIGN 64 35 36 /* Alignment to use for cpu-local structs to avoid coherency problems. */ 37 #define MAX_CACHELINE 64 38 39 #define DPAA_MIN_RX_BUF_SIZE 512 40 #define DPAA_MAX_RX_PKT_LEN 10240 41 42 /* RX queue tail drop threshold 43 * currently considering 32 KB packets. 44 */ 45 #define CONG_THRESHOLD_RX_Q (32 * 1024) 46 47 /*max mac filter for memac(8) including primary mac addr*/ 48 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 49 50 /*Maximum number of slots available in TX ring*/ 51 #define MAX_TX_RING_SLOTS 8 52 53 /* PCD frame queues */ 54 #define DPAA_PCD_FQID_START 0x400 55 #define DPAA_PCD_FQID_MULTIPLIER 0x100 56 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 57 58 #define DPAA_IF_TX_PRIORITY 3 59 #define DPAA_IF_RX_PRIORITY 4 60 #define DPAA_IF_DEBUG_PRIORITY 7 61 62 #define DPAA_IF_RX_ANNOTATION_STASH 1 63 #define DPAA_IF_RX_DATA_STASH 1 64 #define DPAA_IF_RX_CONTEXT_STASH 0 65 66 /* Each "debug" FQ is represented by one of these */ 67 #define DPAA_DEBUG_FQ_RX_ERROR 0 68 #define DPAA_DEBUG_FQ_TX_ERROR 1 69 70 #define DPAA_RSS_OFFLOAD_ALL ( \ 71 ETH_RSS_FRAG_IPV4 | \ 72 ETH_RSS_NONFRAG_IPV4_TCP | \ 73 ETH_RSS_NONFRAG_IPV4_UDP | \ 74 ETH_RSS_NONFRAG_IPV4_SCTP | \ 75 ETH_RSS_FRAG_IPV6 | \ 76 ETH_RSS_NONFRAG_IPV6_TCP | \ 77 ETH_RSS_NONFRAG_IPV6_UDP | \ 78 ETH_RSS_NONFRAG_IPV6_SCTP) 79 80 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 81 PKT_TX_IP_CKSUM | \ 82 PKT_TX_TCP_CKSUM | \ 83 PKT_TX_UDP_CKSUM) 84 85 /* DPAA Frame descriptor macros */ 86 87 #define DPAA_FD_CMD_FCO 0x80000000 88 /**< Frame queue Context Override */ 89 #define DPAA_FD_CMD_RPD 0x40000000 90 /**< Read Prepended Data */ 91 #define DPAA_FD_CMD_UPD 0x20000000 92 /**< Update Prepended Data */ 93 #define DPAA_FD_CMD_DTC 0x10000000 94 /**< Do IP/TCP/UDP Checksum */ 95 #define DPAA_FD_CMD_DCL4C 0x10000000 96 /**< Didn't calculate L4 Checksum */ 97 #define DPAA_FD_CMD_CFQ 0x00ffffff 98 /**< Confirmation Frame Queue */ 99 100 /* Each network interface is represented by one of these */ 101 struct dpaa_if { 102 int valid; 103 char *name; 104 const struct fm_eth_port_cfg *cfg; 105 struct qman_fq *rx_queues; 106 struct qman_fq *tx_queues; 107 struct qman_fq debug_queues[2]; 108 uint16_t nb_rx_queues; 109 uint16_t nb_tx_queues; 110 uint32_t ifid; 111 struct fman_if *fif; 112 struct dpaa_bp_info *bp_info; 113 struct rte_eth_fc_conf *fc_conf; 114 }; 115 116 struct dpaa_if_stats { 117 /* Rx Statistics Counter */ 118 uint64_t reoct; /**<Rx Eth Octets Counter */ 119 uint64_t roct; /**<Rx Octet Counters */ 120 uint64_t raln; /**<Rx Alignment Error Counter */ 121 uint64_t rxpf; /**<Rx valid Pause Frame */ 122 uint64_t rfrm; /**<Rx Frame counter */ 123 uint64_t rfcs; /**<Rx frame check seq error */ 124 uint64_t rvlan; /**<Rx Vlan Frame Counter */ 125 uint64_t rerr; /**<Rx Frame error */ 126 uint64_t ruca; /**<Rx Unicast */ 127 uint64_t rmca; /**<Rx Multicast */ 128 uint64_t rbca; /**<Rx Broadcast */ 129 uint64_t rdrp; /**<Rx Dropped Packet */ 130 uint64_t rpkt; /**<Rx packet */ 131 uint64_t rund; /**<Rx undersized packets */ 132 uint32_t res_x[14]; 133 uint64_t rovr; /**<Rx oversized but good */ 134 uint64_t rjbr; /**<Rx oversized with bad csum */ 135 uint64_t rfrg; /**<Rx fragment Packet */ 136 uint64_t rcnp; /**<Rx control packets (0x8808 */ 137 uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 138 uint32_t res01d0[12]; 139 /* Tx Statistics Counter */ 140 uint64_t teoct; /**<Tx eth octets */ 141 uint64_t toct; /**<Tx Octets */ 142 uint32_t res0210[2]; 143 uint64_t txpf; /**<Tx valid pause frame */ 144 uint64_t tfrm; /**<Tx frame counter */ 145 uint64_t tfcs; /**<Tx FCS error */ 146 uint64_t tvlan; /**<Tx Vlan Frame */ 147 uint64_t terr; /**<Tx frame error */ 148 uint64_t tuca; /**<Tx Unicast */ 149 uint64_t tmca; /**<Tx Multicast */ 150 uint64_t tbca; /**<Tx Broadcast */ 151 uint32_t res0258[2]; 152 uint64_t tpkt; /**<Tx Packet */ 153 uint64_t tund; /**<Tx Undersized */ 154 }; 155 156 #endif 157