1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 #ifndef __DPAA_ETHDEV_H__ 8 #define __DPAA_ETHDEV_H__ 9 10 /* System headers */ 11 #include <stdbool.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_event_eth_rx_adapter.h> 14 15 #include <fsl_usd.h> 16 #include <fsl_qman.h> 17 #include <fsl_bman.h> 18 #include <of.h> 19 #include <netcfg.h> 20 21 #define MAX_DPAA_CORES 4 22 #define DPAA_MBUF_HW_ANNOTATION 64 23 #define DPAA_FD_PTA_SIZE 64 24 25 /* mbuf->seqn will be used to store event entry index for 26 * driver specific usage. For parallel mode queues, invalid 27 * index will be set and for atomic mode queues, valid value 28 * ranging from 1 to 16. 29 */ 30 #define DPAA_INVALID_MBUF_SEQN 0 31 32 /* we will re-use the HEADROOM for annotation in RX */ 33 #define DPAA_HW_BUF_RESERVE 0 34 #define DPAA_PACKET_LAYOUT_ALIGN 64 35 36 /* Alignment to use for cpu-local structs to avoid coherency problems. */ 37 #define MAX_CACHELINE 64 38 39 #define DPAA_MAX_RX_PKT_LEN 10240 40 41 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 42 43 /* RX queue tail drop threshold (CGR Based) in frame count */ 44 #define CGR_RX_PERFQ_THRESH 256 45 46 /*max mac filter for memac(8) including primary mac addr*/ 47 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 48 49 /*Maximum number of slots available in TX ring*/ 50 #define DPAA_TX_BURST_SIZE 7 51 52 /* Optimal burst size for RX and TX as default */ 53 #define DPAA_DEF_RX_BURST_SIZE 7 54 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE 55 56 #ifndef VLAN_TAG_SIZE 57 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ 58 #endif 59 60 /* PCD frame queues */ 61 #define DPAA_PCD_FQID_START 0x400 62 #define DPAA_PCD_FQID_MULTIPLIER 0x100 63 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 64 #define DPAA_MAX_NUM_PCD_QUEUES 4 65 66 #define DPAA_IF_TX_PRIORITY 3 67 #define DPAA_IF_RX_PRIORITY 0 68 #define DPAA_IF_DEBUG_PRIORITY 7 69 70 #define DPAA_IF_RX_ANNOTATION_STASH 1 71 #define DPAA_IF_RX_DATA_STASH 1 72 #define DPAA_IF_RX_CONTEXT_STASH 0 73 74 /* Each "debug" FQ is represented by one of these */ 75 #define DPAA_DEBUG_FQ_RX_ERROR 0 76 #define DPAA_DEBUG_FQ_TX_ERROR 1 77 78 #define DPAA_RSS_OFFLOAD_ALL ( \ 79 ETH_RSS_FRAG_IPV4 | \ 80 ETH_RSS_NONFRAG_IPV4_TCP | \ 81 ETH_RSS_NONFRAG_IPV4_UDP | \ 82 ETH_RSS_NONFRAG_IPV4_SCTP | \ 83 ETH_RSS_FRAG_IPV6 | \ 84 ETH_RSS_NONFRAG_IPV6_TCP | \ 85 ETH_RSS_NONFRAG_IPV6_UDP | \ 86 ETH_RSS_NONFRAG_IPV6_SCTP) 87 88 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 89 PKT_TX_IP_CKSUM | \ 90 PKT_TX_TCP_CKSUM | \ 91 PKT_TX_UDP_CKSUM) 92 93 /* DPAA Frame descriptor macros */ 94 95 #define DPAA_FD_CMD_FCO 0x80000000 96 /**< Frame queue Context Override */ 97 #define DPAA_FD_CMD_RPD 0x40000000 98 /**< Read Prepended Data */ 99 #define DPAA_FD_CMD_UPD 0x20000000 100 /**< Update Prepended Data */ 101 #define DPAA_FD_CMD_DTC 0x10000000 102 /**< Do IP/TCP/UDP Checksum */ 103 #define DPAA_FD_CMD_DCL4C 0x10000000 104 /**< Didn't calculate L4 Checksum */ 105 #define DPAA_FD_CMD_CFQ 0x00ffffff 106 /**< Confirmation Frame Queue */ 107 108 /* Each network interface is represented by one of these */ 109 struct dpaa_if { 110 int valid; 111 char *name; 112 const struct fm_eth_port_cfg *cfg; 113 struct qman_fq *rx_queues; 114 struct qman_cgr *cgr_rx; 115 struct qman_fq *tx_queues; 116 struct qman_fq debug_queues[2]; 117 uint16_t nb_rx_queues; 118 uint16_t nb_tx_queues; 119 uint32_t ifid; 120 struct fman_if *fif; 121 struct dpaa_bp_info *bp_info; 122 struct rte_eth_fc_conf *fc_conf; 123 }; 124 125 struct dpaa_if_stats { 126 /* Rx Statistics Counter */ 127 uint64_t reoct; /**<Rx Eth Octets Counter */ 128 uint64_t roct; /**<Rx Octet Counters */ 129 uint64_t raln; /**<Rx Alignment Error Counter */ 130 uint64_t rxpf; /**<Rx valid Pause Frame */ 131 uint64_t rfrm; /**<Rx Frame counter */ 132 uint64_t rfcs; /**<Rx frame check seq error */ 133 uint64_t rvlan; /**<Rx Vlan Frame Counter */ 134 uint64_t rerr; /**<Rx Frame error */ 135 uint64_t ruca; /**<Rx Unicast */ 136 uint64_t rmca; /**<Rx Multicast */ 137 uint64_t rbca; /**<Rx Broadcast */ 138 uint64_t rdrp; /**<Rx Dropped Packet */ 139 uint64_t rpkt; /**<Rx packet */ 140 uint64_t rund; /**<Rx undersized packets */ 141 uint32_t res_x[14]; 142 uint64_t rovr; /**<Rx oversized but good */ 143 uint64_t rjbr; /**<Rx oversized with bad csum */ 144 uint64_t rfrg; /**<Rx fragment Packet */ 145 uint64_t rcnp; /**<Rx control packets (0x8808 */ 146 uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 147 uint32_t res01d0[12]; 148 /* Tx Statistics Counter */ 149 uint64_t teoct; /**<Tx eth octets */ 150 uint64_t toct; /**<Tx Octets */ 151 uint32_t res0210[2]; 152 uint64_t txpf; /**<Tx valid pause frame */ 153 uint64_t tfrm; /**<Tx frame counter */ 154 uint64_t tfcs; /**<Tx FCS error */ 155 uint64_t tvlan; /**<Tx Vlan Frame */ 156 uint64_t terr; /**<Tx frame error */ 157 uint64_t tuca; /**<Tx Unicast */ 158 uint64_t tmca; /**<Tx Multicast */ 159 uint64_t tbca; /**<Tx Broadcast */ 160 uint32_t res0258[2]; 161 uint64_t tpkt; /**<Tx Packet */ 162 uint64_t tund; /**<Tx Undersized */ 163 }; 164 165 int 166 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 167 int eth_rx_queue_id, 168 u16 ch_id, 169 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 170 171 int 172 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 173 int eth_rx_queue_id); 174 175 enum qman_cb_dqrr_result 176 dpaa_rx_cb_parallel(void *event, 177 struct qman_portal *qm __always_unused, 178 struct qman_fq *fq, 179 const struct qm_dqrr_entry *dqrr, 180 void **bufs); 181 enum qman_cb_dqrr_result 182 dpaa_rx_cb_atomic(void *event, 183 struct qman_portal *qm __always_unused, 184 struct qman_fq *fq, 185 const struct qm_dqrr_entry *dqrr, 186 void **bufs); 187 188 #endif 189