xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.h (revision b53d106d34b5c638f5a2cbdfee0da5bd42d4383f)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
4  *   Copyright 2017-2019 NXP
5  *
6  */
7 #ifndef __DPAA_ETHDEV_H__
8 #define __DPAA_ETHDEV_H__
9 
10 /* System headers */
11 #include <stdbool.h>
12 #include <ethdev_driver.h>
13 #include <rte_event_eth_rx_adapter.h>
14 
15 #include <fsl_usd.h>
16 #include <fsl_qman.h>
17 #include <fsl_bman.h>
18 #include <dpaa_of.h>
19 #include <netcfg.h>
20 
21 #define MAX_DPAA_CORES			4
22 #define DPAA_MBUF_HW_ANNOTATION		64
23 #define DPAA_FD_PTA_SIZE		64
24 
25 /* we will re-use the HEADROOM for annotation in RX */
26 #define DPAA_HW_BUF_RESERVE	0
27 #define DPAA_PACKET_LAYOUT_ALIGN	64
28 
29 /* Alignment to use for cpu-local structs to avoid coherency problems. */
30 #define MAX_CACHELINE			64
31 
32 #define DPAA_MAX_RX_PKT_LEN  10240
33 
34 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
35 
36 /* RX queue tail drop threshold (CGR Based) in frame count */
37 #define CGR_RX_PERFQ_THRESH 256
38 #define CGR_TX_CGR_THRESH 512
39 
40 /*max mac filter for memac(8) including primary mac addr*/
41 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
42 
43 /*Maximum number of slots available in TX ring*/
44 #define DPAA_TX_BURST_SIZE	7
45 
46 /* Optimal burst size for RX and TX as default */
47 #define DPAA_DEF_RX_BURST_SIZE 7
48 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE
49 
50 #ifndef VLAN_TAG_SIZE
51 #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
52 #endif
53 
54 #define DPAA_ETH_MAX_LEN (RTE_ETHER_MTU + \
55 			  RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
56 			  VLAN_TAG_SIZE)
57 
58 /* PCD frame queues */
59 #define DPAA_DEFAULT_NUM_PCD_QUEUES	1
60 #define DPAA_VSP_PROFILE_MAX_NUM	8
61 #define DPAA_MAX_NUM_PCD_QUEUES	DPAA_VSP_PROFILE_MAX_NUM
62 /*Same as VSP profile number*/
63 
64 #define DPAA_IF_TX_PRIORITY		3
65 #define DPAA_IF_RX_PRIORITY		0
66 #define DPAA_IF_DEBUG_PRIORITY		7
67 
68 #define DPAA_IF_RX_ANNOTATION_STASH	1
69 #define DPAA_IF_RX_DATA_STASH		1
70 #define DPAA_IF_RX_CONTEXT_STASH		0
71 
72 /* Each "debug" FQ is represented by one of these */
73 #define DPAA_DEBUG_FQ_RX_ERROR   0
74 #define DPAA_DEBUG_FQ_TX_ERROR   1
75 
76 #define DPAA_RSS_OFFLOAD_ALL ( \
77 	RTE_ETH_RSS_L2_PAYLOAD | \
78 	RTE_ETH_RSS_IP | \
79 	RTE_ETH_RSS_UDP | \
80 	RTE_ETH_RSS_TCP | \
81 	RTE_ETH_RSS_SCTP)
82 
83 #define DPAA_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |                \
84 		RTE_MBUF_F_TX_TCP_CKSUM |               \
85 		RTE_MBUF_F_TX_UDP_CKSUM)
86 
87 /* DPAA Frame descriptor macros */
88 
89 #define DPAA_FD_CMD_FCO			0x80000000
90 /**< Frame queue Context Override */
91 #define DPAA_FD_CMD_RPD			0x40000000
92 /**< Read Prepended Data */
93 #define DPAA_FD_CMD_UPD			0x20000000
94 /**< Update Prepended Data */
95 #define DPAA_FD_CMD_DTC			0x10000000
96 /**< Do IP/TCP/UDP Checksum */
97 #define DPAA_FD_CMD_DCL4C		0x10000000
98 /**< Didn't calculate L4 Checksum */
99 #define DPAA_FD_CMD_CFQ			0x00ffffff
100 /**< Confirmation Frame Queue */
101 
102 #define DPAA_DEFAULT_RXQ_VSP_ID		1
103 
104 #define FMC_FILE "/tmp/fmc.bin"
105 
106 /* Each network interface is represented by one of these */
107 struct dpaa_if {
108 	int valid;
109 	char *name;
110 	const struct fm_eth_port_cfg *cfg;
111 	struct qman_fq *rx_queues;
112 	struct qman_cgr *cgr_rx;
113 	struct qman_fq *tx_queues;
114 	struct qman_cgr *cgr_tx;
115 	struct qman_fq debug_queues[2];
116 	uint16_t nb_rx_queues;
117 	uint16_t nb_tx_queues;
118 	uint32_t ifid;
119 	struct dpaa_bp_info *bp_info;
120 	struct rte_eth_fc_conf *fc_conf;
121 	void *port_handle;
122 	void *netenv_handle;
123 	void *scheme_handle[2];
124 	uint32_t scheme_count;
125 
126 	void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM];
127 	uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM];
128 };
129 
130 struct dpaa_if_stats {
131 	/* Rx Statistics Counter */
132 	uint64_t reoct;		/**<Rx Eth Octets Counter */
133 	uint64_t roct;		/**<Rx Octet Counters */
134 	uint64_t raln;		/**<Rx Alignment Error Counter */
135 	uint64_t rxpf;		/**<Rx valid Pause Frame */
136 	uint64_t rfrm;		/**<Rx Frame counter */
137 	uint64_t rfcs;		/**<Rx frame check seq error */
138 	uint64_t rvlan;		/**<Rx Vlan Frame Counter */
139 	uint64_t rerr;		/**<Rx Frame error */
140 	uint64_t ruca;		/**<Rx Unicast */
141 	uint64_t rmca;		/**<Rx Multicast */
142 	uint64_t rbca;		/**<Rx Broadcast */
143 	uint64_t rdrp;		/**<Rx Dropped Packet */
144 	uint64_t rpkt;		/**<Rx packet */
145 	uint64_t rund;		/**<Rx undersized packets */
146 	uint32_t res_x[14];
147 	uint64_t rovr;		/**<Rx oversized but good */
148 	uint64_t rjbr;		/**<Rx oversized with bad csum */
149 	uint64_t rfrg;		/**<Rx fragment Packet */
150 	uint64_t rcnp;		/**<Rx control packets (0x8808 */
151 	uint64_t rdrntp;	/**<Rx dropped due to FIFO overflow */
152 	uint32_t res01d0[12];
153 	/* Tx Statistics Counter */
154 	uint64_t teoct;		/**<Tx eth octets */
155 	uint64_t toct;		/**<Tx Octets */
156 	uint32_t res0210[2];
157 	uint64_t txpf;		/**<Tx valid pause frame */
158 	uint64_t tfrm;		/**<Tx frame counter */
159 	uint64_t tfcs;		/**<Tx FCS error */
160 	uint64_t tvlan;		/**<Tx Vlan Frame */
161 	uint64_t terr;		/**<Tx frame error */
162 	uint64_t tuca;		/**<Tx Unicast */
163 	uint64_t tmca;		/**<Tx Multicast */
164 	uint64_t tbca;		/**<Tx Broadcast */
165 	uint32_t res0258[2];
166 	uint64_t tpkt;		/**<Tx Packet */
167 	uint64_t tund;		/**<Tx Undersized */
168 };
169 
170 __rte_internal
171 int
172 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
173 		int eth_rx_queue_id,
174 		u16 ch_id,
175 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
176 
177 __rte_internal
178 int
179 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
180 			   int eth_rx_queue_id);
181 
182 enum qman_cb_dqrr_result
183 dpaa_rx_cb_parallel(void *event,
184 		    struct qman_portal *qm __always_unused,
185 		    struct qman_fq *fq,
186 		    const struct qm_dqrr_entry *dqrr,
187 		    void **bufs);
188 enum qman_cb_dqrr_result
189 dpaa_rx_cb_atomic(void *event,
190 		  struct qman_portal *qm __always_unused,
191 		  struct qman_fq *fq,
192 		  const struct qm_dqrr_entry *dqrr,
193 		  void **bufs);
194 
195 /* PMD related logs */
196 extern int dpaa_logtype_pmd;
197 
198 #define DPAA_PMD_LOG(level, fmt, args...) \
199 	rte_log(RTE_LOG_ ## level, dpaa_logtype_pmd, "%s(): " fmt "\n", \
200 		__func__, ##args)
201 
202 #define PMD_INIT_FUNC_TRACE() DPAA_PMD_LOG(DEBUG, " >>")
203 
204 #define DPAA_PMD_DEBUG(fmt, args...) \
205 	DPAA_PMD_LOG(DEBUG, fmt, ## args)
206 #define DPAA_PMD_ERR(fmt, args...) \
207 	DPAA_PMD_LOG(ERR, fmt, ## args)
208 #define DPAA_PMD_INFO(fmt, args...) \
209 	DPAA_PMD_LOG(INFO, fmt, ## args)
210 #define DPAA_PMD_WARN(fmt, args...) \
211 	DPAA_PMD_LOG(WARNING, fmt, ## args)
212 
213 /* DP Logs, toggled out at compile time if level lower than current level */
214 #define DPAA_DP_LOG(level, fmt, args...) \
215 	RTE_LOG_DP(level, PMD, fmt, ## args)
216 
217 #endif
218