1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 5 * Copyright 2017 NXP. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef __DPAA_ETHDEV_H__ 34 #define __DPAA_ETHDEV_H__ 35 36 /* System headers */ 37 #include <stdbool.h> 38 #include <rte_ethdev.h> 39 40 #include <fsl_usd.h> 41 #include <fsl_qman.h> 42 #include <fsl_bman.h> 43 #include <of.h> 44 #include <netcfg.h> 45 46 /* DPAA SoC identifier; If this is not available, it can be concluded 47 * that board is non-DPAA. Single slot is currently supported. 48 */ 49 #define DPAA_SOC_ID_FILE "sys/devices/soc0/soc_id" 50 51 #define DPAA_MBUF_HW_ANNOTATION 64 52 #define DPAA_FD_PTA_SIZE 64 53 54 #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM 55 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" 56 #endif 57 58 /* we will re-use the HEADROOM for annotation in RX */ 59 #define DPAA_HW_BUF_RESERVE 0 60 #define DPAA_PACKET_LAYOUT_ALIGN 64 61 62 /* Alignment to use for cpu-local structs to avoid coherency problems. */ 63 #define MAX_CACHELINE 64 64 65 #define DPAA_MIN_RX_BUF_SIZE 512 66 #define DPAA_MAX_RX_PKT_LEN 10240 67 68 /* RX queue tail drop threshold 69 * currently considering 32 KB packets. 70 */ 71 #define CONG_THRESHOLD_RX_Q (32 * 1024) 72 73 /*max mac filter for memac(8) including primary mac addr*/ 74 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 75 76 /*Maximum number of slots available in TX ring*/ 77 #define MAX_TX_RING_SLOTS 8 78 79 /* PCD frame queues */ 80 #define DPAA_PCD_FQID_START 0x400 81 #define DPAA_PCD_FQID_MULTIPLIER 0x100 82 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 83 84 #define DPAA_IF_TX_PRIORITY 3 85 #define DPAA_IF_RX_PRIORITY 4 86 #define DPAA_IF_DEBUG_PRIORITY 7 87 88 #define DPAA_IF_RX_ANNOTATION_STASH 1 89 #define DPAA_IF_RX_DATA_STASH 1 90 #define DPAA_IF_RX_CONTEXT_STASH 0 91 92 /* Each "debug" FQ is represented by one of these */ 93 #define DPAA_DEBUG_FQ_RX_ERROR 0 94 #define DPAA_DEBUG_FQ_TX_ERROR 1 95 96 #define DPAA_RSS_OFFLOAD_ALL ( \ 97 ETH_RSS_FRAG_IPV4 | \ 98 ETH_RSS_NONFRAG_IPV4_TCP | \ 99 ETH_RSS_NONFRAG_IPV4_UDP | \ 100 ETH_RSS_NONFRAG_IPV4_SCTP | \ 101 ETH_RSS_FRAG_IPV6 | \ 102 ETH_RSS_NONFRAG_IPV6_TCP | \ 103 ETH_RSS_NONFRAG_IPV6_UDP | \ 104 ETH_RSS_NONFRAG_IPV6_SCTP) 105 106 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 107 PKT_TX_IP_CKSUM | \ 108 PKT_TX_TCP_CKSUM | \ 109 PKT_TX_UDP_CKSUM) 110 111 /* DPAA Frame descriptor macros */ 112 113 #define DPAA_FD_CMD_FCO 0x80000000 114 /**< Frame queue Context Override */ 115 #define DPAA_FD_CMD_RPD 0x40000000 116 /**< Read Prepended Data */ 117 #define DPAA_FD_CMD_UPD 0x20000000 118 /**< Update Prepended Data */ 119 #define DPAA_FD_CMD_DTC 0x10000000 120 /**< Do IP/TCP/UDP Checksum */ 121 #define DPAA_FD_CMD_DCL4C 0x10000000 122 /**< Didn't calculate L4 Checksum */ 123 #define DPAA_FD_CMD_CFQ 0x00ffffff 124 /**< Confirmation Frame Queue */ 125 126 /* Each network interface is represented by one of these */ 127 struct dpaa_if { 128 int valid; 129 char *name; 130 const struct fm_eth_port_cfg *cfg; 131 struct qman_fq *rx_queues; 132 struct qman_fq *tx_queues; 133 struct qman_fq debug_queues[2]; 134 uint16_t nb_rx_queues; 135 uint16_t nb_tx_queues; 136 uint32_t ifid; 137 struct fman_if *fif; 138 struct dpaa_bp_info *bp_info; 139 struct rte_eth_fc_conf *fc_conf; 140 }; 141 142 struct dpaa_if_stats { 143 /* Rx Statistics Counter */ 144 uint64_t reoct; /**<Rx Eth Octets Counter */ 145 uint64_t roct; /**<Rx Octet Counters */ 146 uint64_t raln; /**<Rx Alignment Error Counter */ 147 uint64_t rxpf; /**<Rx valid Pause Frame */ 148 uint64_t rfrm; /**<Rx Frame counter */ 149 uint64_t rfcs; /**<Rx frame check seq error */ 150 uint64_t rvlan; /**<Rx Vlan Frame Counter */ 151 uint64_t rerr; /**<Rx Frame error */ 152 uint64_t ruca; /**<Rx Unicast */ 153 uint64_t rmca; /**<Rx Multicast */ 154 uint64_t rbca; /**<Rx Broadcast */ 155 uint64_t rdrp; /**<Rx Dropped Packet */ 156 uint64_t rpkt; /**<Rx packet */ 157 uint64_t rund; /**<Rx undersized packets */ 158 uint32_t res_x[14]; 159 uint64_t rovr; /**<Rx oversized but good */ 160 uint64_t rjbr; /**<Rx oversized with bad csum */ 161 uint64_t rfrg; /**<Rx fragment Packet */ 162 uint64_t rcnp; /**<Rx control packets (0x8808 */ 163 uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 164 uint32_t res01d0[12]; 165 /* Tx Statistics Counter */ 166 uint64_t teoct; /**<Tx eth octets */ 167 uint64_t toct; /**<Tx Octets */ 168 uint32_t res0210[2]; 169 uint64_t txpf; /**<Tx valid pause frame */ 170 uint64_t tfrm; /**<Tx frame counter */ 171 uint64_t tfcs; /**<Tx FCS error */ 172 uint64_t tvlan; /**<Tx Vlan Frame */ 173 uint64_t terr; /**<Tx frame error */ 174 uint64_t tuca; /**<Tx Unicast */ 175 uint64_t tmca; /**<Tx Multicast */ 176 uint64_t tbca; /**<Tx Broadcast */ 177 uint32_t res0258[2]; 178 uint64_t tpkt; /**<Tx Packet */ 179 uint64_t tund; /**<Tx Undersized */ 180 }; 181 182 #endif 183