1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 #ifndef __DPAA_ETHDEV_H__ 8 #define __DPAA_ETHDEV_H__ 9 10 /* System headers */ 11 #include <stdbool.h> 12 #include <rte_ethdev.h> 13 14 #include <fsl_usd.h> 15 #include <fsl_qman.h> 16 #include <fsl_bman.h> 17 #include <of.h> 18 #include <netcfg.h> 19 20 #define DPAA_MBUF_HW_ANNOTATION 64 21 #define DPAA_FD_PTA_SIZE 64 22 23 #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM 24 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" 25 #endif 26 27 /* we will re-use the HEADROOM for annotation in RX */ 28 #define DPAA_HW_BUF_RESERVE 0 29 #define DPAA_PACKET_LAYOUT_ALIGN 64 30 31 /* Alignment to use for cpu-local structs to avoid coherency problems. */ 32 #define MAX_CACHELINE 64 33 34 #define DPAA_MIN_RX_BUF_SIZE 512 35 #define DPAA_MAX_RX_PKT_LEN 10240 36 37 /* RX queue tail drop threshold (CGR Based) in frame count */ 38 #define CGR_RX_PERFQ_THRESH 256 39 40 /*max mac filter for memac(8) including primary mac addr*/ 41 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 42 43 /*Maximum number of slots available in TX ring*/ 44 #define DPAA_TX_BURST_SIZE 7 45 46 #ifndef VLAN_TAG_SIZE 47 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ 48 #endif 49 50 /* PCD frame queues */ 51 #define DPAA_PCD_FQID_START 0x400 52 #define DPAA_PCD_FQID_MULTIPLIER 0x100 53 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 54 #define DPAA_MAX_NUM_PCD_QUEUES 32 55 56 #define DPAA_IF_TX_PRIORITY 3 57 #define DPAA_IF_RX_PRIORITY 0 58 #define DPAA_IF_DEBUG_PRIORITY 7 59 60 #define DPAA_IF_RX_ANNOTATION_STASH 1 61 #define DPAA_IF_RX_DATA_STASH 1 62 #define DPAA_IF_RX_CONTEXT_STASH 0 63 64 /* Each "debug" FQ is represented by one of these */ 65 #define DPAA_DEBUG_FQ_RX_ERROR 0 66 #define DPAA_DEBUG_FQ_TX_ERROR 1 67 68 #define DPAA_RSS_OFFLOAD_ALL ( \ 69 ETH_RSS_FRAG_IPV4 | \ 70 ETH_RSS_NONFRAG_IPV4_TCP | \ 71 ETH_RSS_NONFRAG_IPV4_UDP | \ 72 ETH_RSS_NONFRAG_IPV4_SCTP | \ 73 ETH_RSS_FRAG_IPV6 | \ 74 ETH_RSS_NONFRAG_IPV6_TCP | \ 75 ETH_RSS_NONFRAG_IPV6_UDP | \ 76 ETH_RSS_NONFRAG_IPV6_SCTP) 77 78 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 79 PKT_TX_IP_CKSUM | \ 80 PKT_TX_TCP_CKSUM | \ 81 PKT_TX_UDP_CKSUM) 82 83 /* DPAA Frame descriptor macros */ 84 85 #define DPAA_FD_CMD_FCO 0x80000000 86 /**< Frame queue Context Override */ 87 #define DPAA_FD_CMD_RPD 0x40000000 88 /**< Read Prepended Data */ 89 #define DPAA_FD_CMD_UPD 0x20000000 90 /**< Update Prepended Data */ 91 #define DPAA_FD_CMD_DTC 0x10000000 92 /**< Do IP/TCP/UDP Checksum */ 93 #define DPAA_FD_CMD_DCL4C 0x10000000 94 /**< Didn't calculate L4 Checksum */ 95 #define DPAA_FD_CMD_CFQ 0x00ffffff 96 /**< Confirmation Frame Queue */ 97 98 /* Each network interface is represented by one of these */ 99 struct dpaa_if { 100 int valid; 101 char *name; 102 const struct fm_eth_port_cfg *cfg; 103 struct qman_fq *rx_queues; 104 struct qman_cgr *cgr_rx; 105 struct qman_fq *tx_queues; 106 struct qman_fq debug_queues[2]; 107 uint16_t nb_rx_queues; 108 uint16_t nb_tx_queues; 109 uint32_t ifid; 110 struct fman_if *fif; 111 struct dpaa_bp_info *bp_info; 112 struct rte_eth_fc_conf *fc_conf; 113 }; 114 115 struct dpaa_if_stats { 116 /* Rx Statistics Counter */ 117 uint64_t reoct; /**<Rx Eth Octets Counter */ 118 uint64_t roct; /**<Rx Octet Counters */ 119 uint64_t raln; /**<Rx Alignment Error Counter */ 120 uint64_t rxpf; /**<Rx valid Pause Frame */ 121 uint64_t rfrm; /**<Rx Frame counter */ 122 uint64_t rfcs; /**<Rx frame check seq error */ 123 uint64_t rvlan; /**<Rx Vlan Frame Counter */ 124 uint64_t rerr; /**<Rx Frame error */ 125 uint64_t ruca; /**<Rx Unicast */ 126 uint64_t rmca; /**<Rx Multicast */ 127 uint64_t rbca; /**<Rx Broadcast */ 128 uint64_t rdrp; /**<Rx Dropped Packet */ 129 uint64_t rpkt; /**<Rx packet */ 130 uint64_t rund; /**<Rx undersized packets */ 131 uint32_t res_x[14]; 132 uint64_t rovr; /**<Rx oversized but good */ 133 uint64_t rjbr; /**<Rx oversized with bad csum */ 134 uint64_t rfrg; /**<Rx fragment Packet */ 135 uint64_t rcnp; /**<Rx control packets (0x8808 */ 136 uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 137 uint32_t res01d0[12]; 138 /* Tx Statistics Counter */ 139 uint64_t teoct; /**<Tx eth octets */ 140 uint64_t toct; /**<Tx Octets */ 141 uint32_t res0210[2]; 142 uint64_t txpf; /**<Tx valid pause frame */ 143 uint64_t tfrm; /**<Tx frame counter */ 144 uint64_t tfcs; /**<Tx FCS error */ 145 uint64_t tvlan; /**<Tx Vlan Frame */ 146 uint64_t terr; /**<Tx frame error */ 147 uint64_t tuca; /**<Tx Unicast */ 148 uint64_t tmca; /**<Tx Multicast */ 149 uint64_t tbca; /**<Tx Broadcast */ 150 uint32_t res0258[2]; 151 uint64_t tpkt; /**<Tx Packet */ 152 uint64_t tund; /**<Tx Undersized */ 153 }; 154 155 #endif 156