1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 #ifndef __DPAA_ETHDEV_H__ 8 #define __DPAA_ETHDEV_H__ 9 10 /* System headers */ 11 #include <stdbool.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_event_eth_rx_adapter.h> 14 15 #include <fsl_usd.h> 16 #include <fsl_qman.h> 17 #include <fsl_bman.h> 18 #include <dpaa_of.h> 19 #include <netcfg.h> 20 21 #define MAX_DPAA_CORES 4 22 #define DPAA_MBUF_HW_ANNOTATION 64 23 #define DPAA_FD_PTA_SIZE 64 24 25 /* mbuf->seqn will be used to store event entry index for 26 * driver specific usage. For parallel mode queues, invalid 27 * index will be set and for atomic mode queues, valid value 28 * ranging from 1 to 16. 29 */ 30 #define DPAA_INVALID_MBUF_SEQN 0 31 32 /* we will re-use the HEADROOM for annotation in RX */ 33 #define DPAA_HW_BUF_RESERVE 0 34 #define DPAA_PACKET_LAYOUT_ALIGN 64 35 36 /* Alignment to use for cpu-local structs to avoid coherency problems. */ 37 #define MAX_CACHELINE 64 38 39 #define DPAA_MAX_RX_PKT_LEN 10240 40 41 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 42 43 /* RX queue tail drop threshold (CGR Based) in frame count */ 44 #define CGR_RX_PERFQ_THRESH 256 45 46 /*max mac filter for memac(8) including primary mac addr*/ 47 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 48 49 /*Maximum number of slots available in TX ring*/ 50 #define DPAA_TX_BURST_SIZE 7 51 52 /* Optimal burst size for RX and TX as default */ 53 #define DPAA_DEF_RX_BURST_SIZE 7 54 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE 55 56 #ifndef VLAN_TAG_SIZE 57 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ 58 #endif 59 60 /* PCD frame queues */ 61 #define DPAA_PCD_FQID_START 0x400 62 #define DPAA_PCD_FQID_MULTIPLIER 0x100 63 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 64 #define DPAA_MAX_NUM_PCD_QUEUES 4 65 66 #define DPAA_IF_TX_PRIORITY 3 67 #define DPAA_IF_RX_PRIORITY 0 68 #define DPAA_IF_DEBUG_PRIORITY 7 69 70 #define DPAA_IF_RX_ANNOTATION_STASH 1 71 #define DPAA_IF_RX_DATA_STASH 1 72 #define DPAA_IF_RX_CONTEXT_STASH 0 73 74 /* Each "debug" FQ is represented by one of these */ 75 #define DPAA_DEBUG_FQ_RX_ERROR 0 76 #define DPAA_DEBUG_FQ_TX_ERROR 1 77 78 #define DPAA_RSS_OFFLOAD_ALL ( \ 79 ETH_RSS_L2_PAYLOAD | \ 80 ETH_RSS_IP | \ 81 ETH_RSS_UDP | \ 82 ETH_RSS_TCP | \ 83 ETH_RSS_SCTP) 84 85 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 86 PKT_TX_IP_CKSUM | \ 87 PKT_TX_TCP_CKSUM | \ 88 PKT_TX_UDP_CKSUM) 89 90 /* DPAA Frame descriptor macros */ 91 92 #define DPAA_FD_CMD_FCO 0x80000000 93 /**< Frame queue Context Override */ 94 #define DPAA_FD_CMD_RPD 0x40000000 95 /**< Read Prepended Data */ 96 #define DPAA_FD_CMD_UPD 0x20000000 97 /**< Update Prepended Data */ 98 #define DPAA_FD_CMD_DTC 0x10000000 99 /**< Do IP/TCP/UDP Checksum */ 100 #define DPAA_FD_CMD_DCL4C 0x10000000 101 /**< Didn't calculate L4 Checksum */ 102 #define DPAA_FD_CMD_CFQ 0x00ffffff 103 /**< Confirmation Frame Queue */ 104 105 /* Each network interface is represented by one of these */ 106 struct dpaa_if { 107 int valid; 108 char *name; 109 const struct fm_eth_port_cfg *cfg; 110 struct qman_fq *rx_queues; 111 struct qman_cgr *cgr_rx; 112 struct qman_fq *tx_queues; 113 struct qman_fq debug_queues[2]; 114 uint16_t nb_rx_queues; 115 uint16_t nb_tx_queues; 116 uint32_t ifid; 117 struct fman_if *fif; 118 struct dpaa_bp_info *bp_info; 119 struct rte_eth_fc_conf *fc_conf; 120 }; 121 122 struct dpaa_if_stats { 123 /* Rx Statistics Counter */ 124 uint64_t reoct; /**<Rx Eth Octets Counter */ 125 uint64_t roct; /**<Rx Octet Counters */ 126 uint64_t raln; /**<Rx Alignment Error Counter */ 127 uint64_t rxpf; /**<Rx valid Pause Frame */ 128 uint64_t rfrm; /**<Rx Frame counter */ 129 uint64_t rfcs; /**<Rx frame check seq error */ 130 uint64_t rvlan; /**<Rx Vlan Frame Counter */ 131 uint64_t rerr; /**<Rx Frame error */ 132 uint64_t ruca; /**<Rx Unicast */ 133 uint64_t rmca; /**<Rx Multicast */ 134 uint64_t rbca; /**<Rx Broadcast */ 135 uint64_t rdrp; /**<Rx Dropped Packet */ 136 uint64_t rpkt; /**<Rx packet */ 137 uint64_t rund; /**<Rx undersized packets */ 138 uint32_t res_x[14]; 139 uint64_t rovr; /**<Rx oversized but good */ 140 uint64_t rjbr; /**<Rx oversized with bad csum */ 141 uint64_t rfrg; /**<Rx fragment Packet */ 142 uint64_t rcnp; /**<Rx control packets (0x8808 */ 143 uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 144 uint32_t res01d0[12]; 145 /* Tx Statistics Counter */ 146 uint64_t teoct; /**<Tx eth octets */ 147 uint64_t toct; /**<Tx Octets */ 148 uint32_t res0210[2]; 149 uint64_t txpf; /**<Tx valid pause frame */ 150 uint64_t tfrm; /**<Tx frame counter */ 151 uint64_t tfcs; /**<Tx FCS error */ 152 uint64_t tvlan; /**<Tx Vlan Frame */ 153 uint64_t terr; /**<Tx frame error */ 154 uint64_t tuca; /**<Tx Unicast */ 155 uint64_t tmca; /**<Tx Multicast */ 156 uint64_t tbca; /**<Tx Broadcast */ 157 uint32_t res0258[2]; 158 uint64_t tpkt; /**<Tx Packet */ 159 uint64_t tund; /**<Tx Undersized */ 160 }; 161 162 int 163 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 164 int eth_rx_queue_id, 165 u16 ch_id, 166 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 167 168 int 169 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 170 int eth_rx_queue_id); 171 172 enum qman_cb_dqrr_result 173 dpaa_rx_cb_parallel(void *event, 174 struct qman_portal *qm __always_unused, 175 struct qman_fq *fq, 176 const struct qm_dqrr_entry *dqrr, 177 void **bufs); 178 enum qman_cb_dqrr_result 179 dpaa_rx_cb_atomic(void *event, 180 struct qman_portal *qm __always_unused, 181 struct qman_fq *fq, 182 const struct qm_dqrr_entry *dqrr, 183 void **bufs); 184 185 #endif 186