1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <bus_dpaa_driver.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 RTE_ETH_RX_OFFLOAD_SCATTER; 58 59 /* Rx offloads which cannot be disabled */ 60 static uint64_t dev_rx_offloads_nodis = 61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_RSS_HASH; 66 67 /* Supported Tx offloads */ 68 static uint64_t dev_tx_offloads_sup = 69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 71 72 /* Tx offloads which cannot be disabled */ 73 static uint64_t dev_tx_offloads_nodis = 74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 80 81 /* Keep track of whether QMAN and BMAN have been globally initialized */ 82 static int is_global_init; 83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 84 static int default_q; /* use default queue - FMC is not executed*/ 85 /* At present we only allow up to 4 push mode queues as default - as each of 86 * this queue need dedicated portal and we are short of portals. 87 */ 88 #define DPAA_MAX_PUSH_MODE_QUEUE 8 89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 90 91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 93 94 95 /* Per RX FQ Taildrop in frame count */ 96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 97 98 /* Per TX FQ Taildrop in frame count, disabled by default */ 99 static unsigned int td_tx_threshold; 100 101 struct rte_dpaa_xstats_name_off { 102 char name[RTE_ETH_XSTATS_NAME_SIZE]; 103 uint32_t offset; 104 }; 105 106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 107 {"rx_align_err", 108 offsetof(struct dpaa_if_stats, raln)}, 109 {"rx_valid_pause", 110 offsetof(struct dpaa_if_stats, rxpf)}, 111 {"rx_fcs_err", 112 offsetof(struct dpaa_if_stats, rfcs)}, 113 {"rx_vlan_frame", 114 offsetof(struct dpaa_if_stats, rvlan)}, 115 {"rx_frame_err", 116 offsetof(struct dpaa_if_stats, rerr)}, 117 {"rx_drop_err", 118 offsetof(struct dpaa_if_stats, rdrp)}, 119 {"rx_undersized", 120 offsetof(struct dpaa_if_stats, rund)}, 121 {"rx_oversize_err", 122 offsetof(struct dpaa_if_stats, rovr)}, 123 {"rx_fragment_pkt", 124 offsetof(struct dpaa_if_stats, rfrg)}, 125 {"tx_valid_pause", 126 offsetof(struct dpaa_if_stats, txpf)}, 127 {"tx_fcs_err", 128 offsetof(struct dpaa_if_stats, terr)}, 129 {"tx_vlan_frame", 130 offsetof(struct dpaa_if_stats, tvlan)}, 131 {"rx_undersized", 132 offsetof(struct dpaa_if_stats, tund)}, 133 }; 134 135 static struct rte_dpaa_driver rte_dpaa_pmd; 136 int dpaa_valid_dev; 137 struct rte_mempool *dpaa_tx_sg_pool; 138 139 static int 140 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 141 142 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 143 int wait_to_complete __rte_unused); 144 145 static void dpaa_interrupt_handler(void *param); 146 147 static inline void 148 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 149 { 150 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 151 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 152 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 153 QM_FQCTRL_PREFERINCACHE; 154 opts->fqd.context_a.stashing.exclusive = 0; 155 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 156 opts->fqd.context_a.stashing.annotation_cl = 157 DPAA_IF_RX_ANNOTATION_STASH; 158 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 159 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 160 } 161 162 static int 163 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 164 { 165 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 166 + VLAN_TAG_SIZE; 167 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 168 169 PMD_INIT_FUNC_TRACE(); 170 171 /* 172 * Refuse mtu that requires the support of scattered packets 173 * when this feature has not been enabled before. 174 */ 175 if (dev->data->min_rx_buf_size && 176 !dev->data->scattered_rx && frame_size > buffsz) { 177 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 178 return -EINVAL; 179 } 180 181 /* check <seg size> * <max_seg> >= max_frame */ 182 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 183 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 184 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 185 buffsz * DPAA_SGT_MAX_ENTRIES); 186 return -EINVAL; 187 } 188 189 fman_if_set_maxfrm(dev->process_private, frame_size); 190 191 return 0; 192 } 193 194 static int 195 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 196 { 197 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 198 uint64_t rx_offloads = eth_conf->rxmode.offloads; 199 uint64_t tx_offloads = eth_conf->txmode.offloads; 200 struct dpaa_if *dpaa_intf = dev->data->dev_private; 201 struct rte_device *rdev = dev->device; 202 struct rte_eth_link *link = &dev->data->dev_link; 203 struct rte_dpaa_device *dpaa_dev; 204 struct fman_if *fif = dev->process_private; 205 struct __fman_if *__fif; 206 struct rte_intr_handle *intr_handle; 207 uint32_t max_rx_pktlen; 208 int speed, duplex; 209 int ret, rx_status; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 214 intr_handle = dpaa_dev->intr_handle; 215 __fif = container_of(fif, struct __fman_if, __if); 216 217 /* Check if interface is enabled in case of shared MAC */ 218 if (fif->is_shared_mac) { 219 rx_status = fman_if_get_rx_status(fif); 220 if (!rx_status) { 221 DPAA_PMD_ERR("%s Interface not enabled in kernel!", 222 dpaa_intf->name); 223 return -EHOSTDOWN; 224 } 225 } 226 227 /* Rx offloads which are enabled by default */ 228 if (dev_rx_offloads_nodis & ~rx_offloads) { 229 DPAA_PMD_INFO( 230 "Some of rx offloads enabled by default - requested 0x%" PRIx64 231 " fixed are 0x%" PRIx64, 232 rx_offloads, dev_rx_offloads_nodis); 233 } 234 235 /* Tx offloads which are enabled by default */ 236 if (dev_tx_offloads_nodis & ~tx_offloads) { 237 DPAA_PMD_INFO( 238 "Some of tx offloads enabled by default - requested 0x%" PRIx64 239 " fixed are 0x%" PRIx64, 240 tx_offloads, dev_tx_offloads_nodis); 241 } 242 243 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 244 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 245 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 246 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 247 "supported is %d", 248 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 249 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 250 } 251 252 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 253 254 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 255 DPAA_PMD_DEBUG("enabling scatter mode"); 256 fman_if_set_sg(dev->process_private, 1); 257 dev->data->scattered_rx = 1; 258 } 259 260 if (!(default_q || fmc_q)) { 261 if (dpaa_fm_config(dev, 262 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 263 dpaa_write_fm_config_to_file(); 264 DPAA_PMD_ERR("FM port configuration: Failed\n"); 265 return -1; 266 } 267 dpaa_write_fm_config_to_file(); 268 } 269 270 /* if the interrupts were configured on this devices*/ 271 if (intr_handle && rte_intr_fd_get(intr_handle)) { 272 if (dev->data->dev_conf.intr_conf.lsc != 0) 273 rte_intr_callback_register(intr_handle, 274 dpaa_interrupt_handler, 275 (void *)dev); 276 277 ret = dpaa_intr_enable(__fif->node_name, 278 rte_intr_fd_get(intr_handle)); 279 if (ret) { 280 if (dev->data->dev_conf.intr_conf.lsc != 0) { 281 rte_intr_callback_unregister(intr_handle, 282 dpaa_interrupt_handler, 283 (void *)dev); 284 if (ret == EINVAL) 285 printf("Failed to enable interrupt: Not Supported\n"); 286 else 287 printf("Failed to enable interrupt\n"); 288 } 289 dev->data->dev_conf.intr_conf.lsc = 0; 290 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 291 } 292 } 293 294 /* Wait for link status to get updated */ 295 if (!link->link_status) 296 sleep(1); 297 298 /* Configure link only if link is UP*/ 299 if (link->link_status) { 300 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 301 /* Start autoneg only if link is not in autoneg mode */ 302 if (!link->link_autoneg) 303 dpaa_restart_link_autoneg(__fif->node_name); 304 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 305 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 306 case RTE_ETH_LINK_SPEED_10M_HD: 307 speed = RTE_ETH_SPEED_NUM_10M; 308 duplex = RTE_ETH_LINK_HALF_DUPLEX; 309 break; 310 case RTE_ETH_LINK_SPEED_10M: 311 speed = RTE_ETH_SPEED_NUM_10M; 312 duplex = RTE_ETH_LINK_FULL_DUPLEX; 313 break; 314 case RTE_ETH_LINK_SPEED_100M_HD: 315 speed = RTE_ETH_SPEED_NUM_100M; 316 duplex = RTE_ETH_LINK_HALF_DUPLEX; 317 break; 318 case RTE_ETH_LINK_SPEED_100M: 319 speed = RTE_ETH_SPEED_NUM_100M; 320 duplex = RTE_ETH_LINK_FULL_DUPLEX; 321 break; 322 case RTE_ETH_LINK_SPEED_1G: 323 speed = RTE_ETH_SPEED_NUM_1G; 324 duplex = RTE_ETH_LINK_FULL_DUPLEX; 325 break; 326 case RTE_ETH_LINK_SPEED_2_5G: 327 speed = RTE_ETH_SPEED_NUM_2_5G; 328 duplex = RTE_ETH_LINK_FULL_DUPLEX; 329 break; 330 case RTE_ETH_LINK_SPEED_10G: 331 speed = RTE_ETH_SPEED_NUM_10G; 332 duplex = RTE_ETH_LINK_FULL_DUPLEX; 333 break; 334 default: 335 speed = RTE_ETH_SPEED_NUM_NONE; 336 duplex = RTE_ETH_LINK_FULL_DUPLEX; 337 break; 338 } 339 /* Set link speed */ 340 dpaa_update_link_speed(__fif->node_name, speed, duplex); 341 } else { 342 /* Manual autoneg - custom advertisement speed. */ 343 printf("Custom Advertisement speeds not supported\n"); 344 } 345 } 346 347 return 0; 348 } 349 350 static const uint32_t * 351 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 352 { 353 static const uint32_t ptypes[] = { 354 RTE_PTYPE_L2_ETHER, 355 RTE_PTYPE_L2_ETHER_VLAN, 356 RTE_PTYPE_L2_ETHER_ARP, 357 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 358 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 359 RTE_PTYPE_L4_ICMP, 360 RTE_PTYPE_L4_TCP, 361 RTE_PTYPE_L4_UDP, 362 RTE_PTYPE_L4_FRAG, 363 RTE_PTYPE_L4_TCP, 364 RTE_PTYPE_L4_UDP, 365 RTE_PTYPE_L4_SCTP, 366 RTE_PTYPE_TUNNEL_ESP 367 }; 368 369 PMD_INIT_FUNC_TRACE(); 370 371 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 372 return ptypes; 373 return NULL; 374 } 375 376 static void dpaa_interrupt_handler(void *param) 377 { 378 struct rte_eth_dev *dev = param; 379 struct rte_device *rdev = dev->device; 380 struct rte_dpaa_device *dpaa_dev; 381 struct rte_intr_handle *intr_handle; 382 uint64_t buf; 383 int bytes_read; 384 385 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 386 intr_handle = dpaa_dev->intr_handle; 387 388 if (rte_intr_fd_get(intr_handle) < 0) 389 return; 390 391 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 392 sizeof(uint64_t)); 393 if (bytes_read < 0) 394 DPAA_PMD_ERR("Error reading eventfd\n"); 395 dpaa_eth_link_update(dev, 0); 396 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 397 } 398 399 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 400 { 401 struct dpaa_if *dpaa_intf = dev->data->dev_private; 402 403 PMD_INIT_FUNC_TRACE(); 404 405 if (!(default_q || fmc_q)) 406 dpaa_write_fm_config_to_file(); 407 408 /* Change tx callback to the real one */ 409 if (dpaa_intf->cgr_tx) 410 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 411 else 412 dev->tx_pkt_burst = dpaa_eth_queue_tx; 413 414 fman_if_enable_rx(dev->process_private); 415 416 return 0; 417 } 418 419 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 420 { 421 struct fman_if *fif = dev->process_private; 422 423 PMD_INIT_FUNC_TRACE(); 424 dev->data->dev_started = 0; 425 426 if (!fif->is_shared_mac) 427 fman_if_disable_rx(fif); 428 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 429 430 return 0; 431 } 432 433 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 434 { 435 struct fman_if *fif = dev->process_private; 436 struct __fman_if *__fif; 437 struct rte_device *rdev = dev->device; 438 struct rte_dpaa_device *dpaa_dev; 439 struct rte_intr_handle *intr_handle; 440 struct rte_eth_link *link = &dev->data->dev_link; 441 struct dpaa_if *dpaa_intf = dev->data->dev_private; 442 int loop; 443 int ret; 444 445 PMD_INIT_FUNC_TRACE(); 446 447 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 448 return 0; 449 450 if (!dpaa_intf) { 451 DPAA_PMD_WARN("Already closed or not started"); 452 return -1; 453 } 454 455 /* DPAA FM deconfig */ 456 if (!(default_q || fmc_q)) { 457 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 458 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 459 } 460 461 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 462 intr_handle = dpaa_dev->intr_handle; 463 __fif = container_of(fif, struct __fman_if, __if); 464 465 ret = dpaa_eth_dev_stop(dev); 466 467 /* Reset link to autoneg */ 468 if (link->link_status && !link->link_autoneg) 469 dpaa_restart_link_autoneg(__fif->node_name); 470 471 if (intr_handle && rte_intr_fd_get(intr_handle) && 472 dev->data->dev_conf.intr_conf.lsc != 0) { 473 dpaa_intr_disable(__fif->node_name); 474 rte_intr_callback_unregister(intr_handle, 475 dpaa_interrupt_handler, 476 (void *)dev); 477 } 478 479 /* release configuration memory */ 480 rte_free(dpaa_intf->fc_conf); 481 482 /* Release RX congestion Groups */ 483 if (dpaa_intf->cgr_rx) { 484 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 485 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 486 } 487 488 rte_free(dpaa_intf->cgr_rx); 489 dpaa_intf->cgr_rx = NULL; 490 /* Release TX congestion Groups */ 491 if (dpaa_intf->cgr_tx) { 492 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 493 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 494 rte_free(dpaa_intf->cgr_tx); 495 dpaa_intf->cgr_tx = NULL; 496 } 497 498 rte_free(dpaa_intf->rx_queues); 499 dpaa_intf->rx_queues = NULL; 500 501 rte_free(dpaa_intf->tx_queues); 502 dpaa_intf->tx_queues = NULL; 503 504 return ret; 505 } 506 507 static int 508 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 509 char *fw_version, 510 size_t fw_size) 511 { 512 int ret; 513 FILE *svr_file = NULL; 514 unsigned int svr_ver = 0; 515 516 PMD_INIT_FUNC_TRACE(); 517 518 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 519 if (!svr_file) { 520 DPAA_PMD_ERR("Unable to open SoC device"); 521 return -ENOTSUP; /* Not supported on this infra */ 522 } 523 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 524 dpaa_svr_family = svr_ver & SVR_MASK; 525 else 526 DPAA_PMD_ERR("Unable to read SoC device"); 527 528 fclose(svr_file); 529 530 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 531 svr_ver, fman_ip_rev); 532 if (ret < 0) 533 return -EINVAL; 534 535 ret += 1; /* add the size of '\0' */ 536 if (fw_size < (size_t)ret) 537 return ret; 538 else 539 return 0; 540 } 541 542 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 543 struct rte_eth_dev_info *dev_info) 544 { 545 struct dpaa_if *dpaa_intf = dev->data->dev_private; 546 struct fman_if *fif = dev->process_private; 547 548 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 549 550 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 551 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 552 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 553 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 554 dev_info->max_hash_mac_addrs = 0; 555 dev_info->max_vfs = 0; 556 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 557 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 558 559 if (fif->mac_type == fman_mac_1g) { 560 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 561 | RTE_ETH_LINK_SPEED_10M 562 | RTE_ETH_LINK_SPEED_100M_HD 563 | RTE_ETH_LINK_SPEED_100M 564 | RTE_ETH_LINK_SPEED_1G; 565 } else if (fif->mac_type == fman_mac_2_5g) { 566 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 567 | RTE_ETH_LINK_SPEED_10M 568 | RTE_ETH_LINK_SPEED_100M_HD 569 | RTE_ETH_LINK_SPEED_100M 570 | RTE_ETH_LINK_SPEED_1G 571 | RTE_ETH_LINK_SPEED_2_5G; 572 } else if (fif->mac_type == fman_mac_10g) { 573 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 574 | RTE_ETH_LINK_SPEED_10M 575 | RTE_ETH_LINK_SPEED_100M_HD 576 | RTE_ETH_LINK_SPEED_100M 577 | RTE_ETH_LINK_SPEED_1G 578 | RTE_ETH_LINK_SPEED_2_5G 579 | RTE_ETH_LINK_SPEED_10G; 580 } else { 581 DPAA_PMD_ERR("invalid link_speed: %s, %d", 582 dpaa_intf->name, fif->mac_type); 583 return -EINVAL; 584 } 585 586 dev_info->rx_offload_capa = dev_rx_offloads_sup | 587 dev_rx_offloads_nodis; 588 dev_info->tx_offload_capa = dev_tx_offloads_sup | 589 dev_tx_offloads_nodis; 590 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 591 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 592 dev_info->default_rxportconf.nb_queues = 1; 593 dev_info->default_txportconf.nb_queues = 1; 594 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 595 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 596 597 return 0; 598 } 599 600 static int 601 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 602 __rte_unused uint16_t queue_id, 603 struct rte_eth_burst_mode *mode) 604 { 605 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 606 int ret = -EINVAL; 607 unsigned int i; 608 const struct burst_info { 609 uint64_t flags; 610 const char *output; 611 } rx_offload_map[] = { 612 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 613 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 614 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 615 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 616 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 617 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 618 }; 619 620 /* Update Rx offload info */ 621 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 622 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 623 snprintf(mode->info, sizeof(mode->info), "%s", 624 rx_offload_map[i].output); 625 ret = 0; 626 break; 627 } 628 } 629 return ret; 630 } 631 632 static int 633 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 634 __rte_unused uint16_t queue_id, 635 struct rte_eth_burst_mode *mode) 636 { 637 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 638 int ret = -EINVAL; 639 unsigned int i; 640 const struct burst_info { 641 uint64_t flags; 642 const char *output; 643 } tx_offload_map[] = { 644 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 645 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 646 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 647 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 648 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 649 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 650 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 651 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 652 }; 653 654 /* Update Tx offload info */ 655 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 656 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 657 snprintf(mode->info, sizeof(mode->info), "%s", 658 tx_offload_map[i].output); 659 ret = 0; 660 break; 661 } 662 } 663 return ret; 664 } 665 666 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 667 int wait_to_complete) 668 { 669 struct dpaa_if *dpaa_intf = dev->data->dev_private; 670 struct rte_eth_link *link = &dev->data->dev_link; 671 struct fman_if *fif = dev->process_private; 672 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 673 int ret, ioctl_version; 674 uint8_t count; 675 676 PMD_INIT_FUNC_TRACE(); 677 678 ioctl_version = dpaa_get_ioctl_version_number(); 679 680 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 681 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 682 ret = dpaa_get_link_status(__fif->node_name, link); 683 if (ret) 684 return ret; 685 if (link->link_status == RTE_ETH_LINK_DOWN && 686 wait_to_complete) 687 rte_delay_ms(CHECK_INTERVAL); 688 else 689 break; 690 } 691 } else { 692 link->link_status = dpaa_intf->valid; 693 } 694 695 if (ioctl_version < 2) { 696 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 697 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 698 699 if (fif->mac_type == fman_mac_1g) 700 link->link_speed = RTE_ETH_SPEED_NUM_1G; 701 else if (fif->mac_type == fman_mac_2_5g) 702 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 703 else if (fif->mac_type == fman_mac_10g) 704 link->link_speed = RTE_ETH_SPEED_NUM_10G; 705 else 706 DPAA_PMD_ERR("invalid link_speed: %s, %d", 707 dpaa_intf->name, fif->mac_type); 708 } 709 710 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 711 link->link_status ? "Up" : "Down"); 712 return 0; 713 } 714 715 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 716 struct rte_eth_stats *stats) 717 { 718 PMD_INIT_FUNC_TRACE(); 719 720 fman_if_stats_get(dev->process_private, stats); 721 return 0; 722 } 723 724 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 725 { 726 PMD_INIT_FUNC_TRACE(); 727 728 fman_if_stats_reset(dev->process_private); 729 730 return 0; 731 } 732 733 static int 734 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 735 unsigned int n) 736 { 737 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 738 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 739 740 if (n < num) 741 return num; 742 743 if (xstats == NULL) 744 return 0; 745 746 fman_if_stats_get_all(dev->process_private, values, 747 sizeof(struct dpaa_if_stats) / 8); 748 749 for (i = 0; i < num; i++) { 750 xstats[i].id = i; 751 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 752 } 753 return i; 754 } 755 756 static int 757 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 758 struct rte_eth_xstat_name *xstats_names, 759 unsigned int limit) 760 { 761 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 762 763 if (limit < stat_cnt) 764 return stat_cnt; 765 766 if (xstats_names != NULL) 767 for (i = 0; i < stat_cnt; i++) 768 strlcpy(xstats_names[i].name, 769 dpaa_xstats_strings[i].name, 770 sizeof(xstats_names[i].name)); 771 772 return stat_cnt; 773 } 774 775 static int 776 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 777 uint64_t *values, unsigned int n) 778 { 779 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 780 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 781 782 if (!ids) { 783 if (n < stat_cnt) 784 return stat_cnt; 785 786 if (!values) 787 return 0; 788 789 fman_if_stats_get_all(dev->process_private, values_copy, 790 sizeof(struct dpaa_if_stats) / 8); 791 792 for (i = 0; i < stat_cnt; i++) 793 values[i] = 794 values_copy[dpaa_xstats_strings[i].offset / 8]; 795 796 return stat_cnt; 797 } 798 799 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 800 801 for (i = 0; i < n; i++) { 802 if (ids[i] >= stat_cnt) { 803 DPAA_PMD_ERR("id value isn't valid"); 804 return -1; 805 } 806 values[i] = values_copy[ids[i]]; 807 } 808 return n; 809 } 810 811 static int 812 dpaa_xstats_get_names_by_id( 813 struct rte_eth_dev *dev, 814 const uint64_t *ids, 815 struct rte_eth_xstat_name *xstats_names, 816 unsigned int limit) 817 { 818 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 819 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 820 821 if (!ids) 822 return dpaa_xstats_get_names(dev, xstats_names, limit); 823 824 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 825 826 for (i = 0; i < limit; i++) { 827 if (ids[i] >= stat_cnt) { 828 DPAA_PMD_ERR("id value isn't valid"); 829 return -1; 830 } 831 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 832 } 833 return limit; 834 } 835 836 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 837 { 838 PMD_INIT_FUNC_TRACE(); 839 840 fman_if_promiscuous_enable(dev->process_private); 841 842 return 0; 843 } 844 845 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 846 { 847 PMD_INIT_FUNC_TRACE(); 848 849 fman_if_promiscuous_disable(dev->process_private); 850 851 return 0; 852 } 853 854 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 855 { 856 PMD_INIT_FUNC_TRACE(); 857 858 fman_if_set_mcast_filter_table(dev->process_private); 859 860 return 0; 861 } 862 863 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 864 { 865 PMD_INIT_FUNC_TRACE(); 866 867 fman_if_reset_mcast_filter_table(dev->process_private); 868 869 return 0; 870 } 871 872 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 873 { 874 struct dpaa_if *dpaa_intf = dev->data->dev_private; 875 struct fman_if_ic_params icp; 876 uint32_t fd_offset; 877 uint32_t bp_size; 878 879 memset(&icp, 0, sizeof(icp)); 880 /* set ICEOF for to the default value , which is 0*/ 881 icp.iciof = DEFAULT_ICIOF; 882 icp.iceof = DEFAULT_RX_ICEOF; 883 icp.icsz = DEFAULT_ICSZ; 884 fman_if_set_ic_params(dev->process_private, &icp); 885 886 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 887 fman_if_set_fdoff(dev->process_private, fd_offset); 888 889 /* Buffer pool size should be equal to Dataroom Size*/ 890 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 891 892 fman_if_set_bp(dev->process_private, 893 dpaa_intf->bp_info->mp->size, 894 dpaa_intf->bp_info->bpid, bp_size); 895 } 896 897 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 898 int8_t vsp_id, uint32_t bpid) 899 { 900 struct dpaa_if *dpaa_intf = dev->data->dev_private; 901 struct fman_if *fif = dev->process_private; 902 903 if (fif->num_profiles) { 904 if (vsp_id < 0) 905 vsp_id = fif->base_profile_id; 906 } else { 907 if (vsp_id < 0) 908 vsp_id = 0; 909 } 910 911 if (dpaa_intf->vsp_bpid[vsp_id] && 912 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 913 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 914 915 return -1; 916 } 917 918 return 0; 919 } 920 921 static 922 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 923 uint16_t nb_desc, 924 unsigned int socket_id __rte_unused, 925 const struct rte_eth_rxconf *rx_conf, 926 struct rte_mempool *mp) 927 { 928 struct dpaa_if *dpaa_intf = dev->data->dev_private; 929 struct fman_if *fif = dev->process_private; 930 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 931 struct qm_mcc_initfq opts = {0}; 932 u32 flags = 0; 933 int ret; 934 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 935 uint32_t max_rx_pktlen; 936 937 PMD_INIT_FUNC_TRACE(); 938 939 if (queue_idx >= dev->data->nb_rx_queues) { 940 rte_errno = EOVERFLOW; 941 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 942 (void *)dev, queue_idx, dev->data->nb_rx_queues); 943 return -rte_errno; 944 } 945 946 /* Rx deferred start is not supported */ 947 if (rx_conf->rx_deferred_start) { 948 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 949 return -EINVAL; 950 } 951 rxq->nb_desc = UINT16_MAX; 952 rxq->offloads = rx_conf->offloads; 953 954 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 955 queue_idx, rxq->fqid); 956 957 if (!fif->num_profiles) { 958 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 959 dpaa_intf->bp_info->mp != mp) { 960 DPAA_PMD_WARN("Multiple pools on same interface not" 961 " supported"); 962 return -EINVAL; 963 } 964 } else { 965 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 966 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 967 return -EINVAL; 968 } 969 } 970 971 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 972 dpaa_intf->bp_info->mp != mp) { 973 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 974 return -EINVAL; 975 } 976 977 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 978 VLAN_TAG_SIZE; 979 /* Max packet can fit in single buffer */ 980 if (max_rx_pktlen <= buffsz) { 981 ; 982 } else if (dev->data->dev_conf.rxmode.offloads & 983 RTE_ETH_RX_OFFLOAD_SCATTER) { 984 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 985 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 986 "MaxSGlist %d", 987 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 988 rte_errno = EOVERFLOW; 989 return -rte_errno; 990 } 991 } else { 992 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 993 " larger than a single mbuf (%u) and scattered" 994 " mode has not been requested", max_rx_pktlen, buffsz); 995 } 996 997 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 998 999 /* For shared interface, it's done in kernel, skip.*/ 1000 if (!fif->is_shared_mac) 1001 dpaa_fman_if_pool_setup(dev); 1002 1003 if (fif->num_profiles) { 1004 int8_t vsp_id = rxq->vsp_id; 1005 1006 if (vsp_id >= 0) { 1007 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 1008 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 1009 fif, buffsz + RTE_PKTMBUF_HEADROOM); 1010 if (ret) { 1011 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1012 return ret; 1013 } 1014 } else { 1015 DPAA_PMD_INFO("Base profile is associated to" 1016 " RXQ fqid:%d\r\n", rxq->fqid); 1017 if (fif->is_shared_mac) { 1018 DPAA_PMD_ERR("Fatal: Base profile is associated" 1019 " to shared interface on DPDK."); 1020 return -EINVAL; 1021 } 1022 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1023 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1024 } 1025 } else { 1026 dpaa_intf->vsp_bpid[0] = 1027 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1028 } 1029 1030 dpaa_intf->valid = 1; 1031 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1032 fman_if_get_sg_enable(fif), max_rx_pktlen); 1033 /* checking if push mode only, no error check for now */ 1034 if (!rxq->is_static && 1035 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1036 struct qman_portal *qp; 1037 int q_fd; 1038 1039 dpaa_push_queue_idx++; 1040 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1041 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1042 QM_FQCTRL_CTXASTASHING | 1043 QM_FQCTRL_PREFERINCACHE; 1044 opts.fqd.context_a.stashing.exclusive = 0; 1045 /* In multicore scenario stashing becomes a bottleneck on LS1046. 1046 * So do not enable stashing in this case 1047 */ 1048 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1049 opts.fqd.context_a.stashing.annotation_cl = 1050 DPAA_IF_RX_ANNOTATION_STASH; 1051 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1052 opts.fqd.context_a.stashing.context_cl = 1053 DPAA_IF_RX_CONTEXT_STASH; 1054 1055 /*Create a channel and associate given queue with the channel*/ 1056 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1057 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1058 opts.fqd.dest.channel = rxq->ch_id; 1059 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1060 flags = QMAN_INITFQ_FLAG_SCHED; 1061 1062 /* Configure tail drop */ 1063 if (dpaa_intf->cgr_rx) { 1064 opts.we_mask |= QM_INITFQ_WE_CGID; 1065 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1066 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1067 } 1068 ret = qman_init_fq(rxq, flags, &opts); 1069 if (ret) { 1070 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1071 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1072 return ret; 1073 } 1074 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1075 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1076 } else { 1077 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1078 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1079 } 1080 1081 rxq->is_static = true; 1082 1083 /* Allocate qman specific portals */ 1084 qp = fsl_qman_fq_portal_create(&q_fd); 1085 if (!qp) { 1086 DPAA_PMD_ERR("Unable to alloc fq portal"); 1087 return -1; 1088 } 1089 rxq->qp = qp; 1090 1091 /* Set up the device interrupt handler */ 1092 if (dev->intr_handle == NULL) { 1093 struct rte_dpaa_device *dpaa_dev; 1094 struct rte_device *rdev = dev->device; 1095 1096 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1097 device); 1098 dev->intr_handle = dpaa_dev->intr_handle; 1099 if (rte_intr_vec_list_alloc(dev->intr_handle, 1100 NULL, dpaa_push_mode_max_queue)) { 1101 DPAA_PMD_ERR("intr_vec alloc failed"); 1102 return -ENOMEM; 1103 } 1104 if (rte_intr_nb_efd_set(dev->intr_handle, 1105 dpaa_push_mode_max_queue)) 1106 return -rte_errno; 1107 1108 if (rte_intr_max_intr_set(dev->intr_handle, 1109 dpaa_push_mode_max_queue)) 1110 return -rte_errno; 1111 } 1112 1113 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1114 return -rte_errno; 1115 1116 if (rte_intr_vec_list_index_set(dev->intr_handle, 1117 queue_idx, queue_idx + 1)) 1118 return -rte_errno; 1119 1120 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1121 q_fd)) 1122 return -rte_errno; 1123 1124 rxq->q_fd = q_fd; 1125 } 1126 rxq->bp_array = rte_dpaa_bpid_info; 1127 dev->data->rx_queues[queue_idx] = rxq; 1128 1129 /* configure the CGR size as per the desc size */ 1130 if (dpaa_intf->cgr_rx) { 1131 struct qm_mcc_initcgr cgr_opts = {0}; 1132 1133 rxq->nb_desc = nb_desc; 1134 /* Enable tail drop with cgr on this queue */ 1135 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1136 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1137 if (ret) { 1138 DPAA_PMD_WARN( 1139 "rx taildrop modify fail on fqid %d (ret=%d)", 1140 rxq->fqid, ret); 1141 } 1142 } 1143 /* Enable main queue to receive error packets also by default */ 1144 fman_if_set_err_fqid(fif, rxq->fqid); 1145 return 0; 1146 } 1147 1148 int 1149 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1150 int eth_rx_queue_id, 1151 u16 ch_id, 1152 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1153 { 1154 int ret; 1155 u32 flags = 0; 1156 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1157 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1158 struct qm_mcc_initfq opts = {0}; 1159 1160 if (dpaa_push_mode_max_queue) 1161 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1162 "PUSH mode already enabled for first %d queues.\n" 1163 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1164 dpaa_push_mode_max_queue); 1165 1166 dpaa_poll_queue_default_config(&opts); 1167 1168 switch (queue_conf->ev.sched_type) { 1169 case RTE_SCHED_TYPE_ATOMIC: 1170 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1171 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1172 * configuration with HOLD_ACTIVE setting 1173 */ 1174 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1175 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1176 break; 1177 case RTE_SCHED_TYPE_ORDERED: 1178 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1179 return -1; 1180 default: 1181 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1182 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1183 break; 1184 } 1185 1186 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1187 opts.fqd.dest.channel = ch_id; 1188 opts.fqd.dest.wq = queue_conf->ev.priority; 1189 1190 if (dpaa_intf->cgr_rx) { 1191 opts.we_mask |= QM_INITFQ_WE_CGID; 1192 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1193 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1194 } 1195 1196 flags = QMAN_INITFQ_FLAG_SCHED; 1197 1198 ret = qman_init_fq(rxq, flags, &opts); 1199 if (ret) { 1200 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1201 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1202 return ret; 1203 } 1204 1205 /* copy configuration which needs to be filled during dequeue */ 1206 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1207 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1208 1209 return ret; 1210 } 1211 1212 int 1213 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1214 int eth_rx_queue_id) 1215 { 1216 struct qm_mcc_initfq opts = {0}; 1217 int ret; 1218 u32 flags = 0; 1219 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1220 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1221 1222 qman_retire_fq(rxq, NULL); 1223 qman_oos_fq(rxq); 1224 ret = qman_init_fq(rxq, flags, &opts); 1225 if (ret) { 1226 DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d", 1227 rxq->fqid, ret); 1228 } 1229 1230 rxq->cb.dqrr_dpdk_cb = NULL; 1231 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1232 1233 return 0; 1234 } 1235 1236 static 1237 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1238 uint16_t nb_desc __rte_unused, 1239 unsigned int socket_id __rte_unused, 1240 const struct rte_eth_txconf *tx_conf) 1241 { 1242 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1243 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1244 1245 PMD_INIT_FUNC_TRACE(); 1246 1247 /* Tx deferred start is not supported */ 1248 if (tx_conf->tx_deferred_start) { 1249 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1250 return -EINVAL; 1251 } 1252 txq->nb_desc = UINT16_MAX; 1253 txq->offloads = tx_conf->offloads; 1254 1255 if (queue_idx >= dev->data->nb_tx_queues) { 1256 rte_errno = EOVERFLOW; 1257 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1258 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1259 return -rte_errno; 1260 } 1261 1262 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1263 queue_idx, txq->fqid); 1264 dev->data->tx_queues[queue_idx] = txq; 1265 1266 return 0; 1267 } 1268 1269 static uint32_t 1270 dpaa_dev_rx_queue_count(void *rx_queue) 1271 { 1272 struct qman_fq *rxq = rx_queue; 1273 u32 frm_cnt = 0; 1274 1275 PMD_INIT_FUNC_TRACE(); 1276 1277 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1278 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1279 rx_queue, frm_cnt); 1280 } 1281 return frm_cnt; 1282 } 1283 1284 static int dpaa_link_down(struct rte_eth_dev *dev) 1285 { 1286 struct fman_if *fif = dev->process_private; 1287 struct __fman_if *__fif; 1288 1289 PMD_INIT_FUNC_TRACE(); 1290 1291 __fif = container_of(fif, struct __fman_if, __if); 1292 1293 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1294 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1295 else 1296 return dpaa_eth_dev_stop(dev); 1297 return 0; 1298 } 1299 1300 static int dpaa_link_up(struct rte_eth_dev *dev) 1301 { 1302 struct fman_if *fif = dev->process_private; 1303 struct __fman_if *__fif; 1304 1305 PMD_INIT_FUNC_TRACE(); 1306 1307 __fif = container_of(fif, struct __fman_if, __if); 1308 1309 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1310 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1311 else 1312 dpaa_eth_dev_start(dev); 1313 return 0; 1314 } 1315 1316 static int 1317 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1318 struct rte_eth_fc_conf *fc_conf) 1319 { 1320 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1321 struct rte_eth_fc_conf *net_fc; 1322 1323 PMD_INIT_FUNC_TRACE(); 1324 1325 if (!(dpaa_intf->fc_conf)) { 1326 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1327 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1328 if (!dpaa_intf->fc_conf) { 1329 DPAA_PMD_ERR("unable to save flow control info"); 1330 return -ENOMEM; 1331 } 1332 } 1333 net_fc = dpaa_intf->fc_conf; 1334 1335 if (fc_conf->high_water < fc_conf->low_water) { 1336 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1337 return -EINVAL; 1338 } 1339 1340 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1341 return 0; 1342 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1343 fc_conf->mode == RTE_ETH_FC_FULL) { 1344 fman_if_set_fc_threshold(dev->process_private, 1345 fc_conf->high_water, 1346 fc_conf->low_water, 1347 dpaa_intf->bp_info->bpid); 1348 if (fc_conf->pause_time) 1349 fman_if_set_fc_quanta(dev->process_private, 1350 fc_conf->pause_time); 1351 } 1352 1353 /* Save the information in dpaa device */ 1354 net_fc->pause_time = fc_conf->pause_time; 1355 net_fc->high_water = fc_conf->high_water; 1356 net_fc->low_water = fc_conf->low_water; 1357 net_fc->send_xon = fc_conf->send_xon; 1358 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1359 net_fc->mode = fc_conf->mode; 1360 net_fc->autoneg = fc_conf->autoneg; 1361 1362 return 0; 1363 } 1364 1365 static int 1366 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1367 struct rte_eth_fc_conf *fc_conf) 1368 { 1369 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1370 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1371 int ret; 1372 1373 PMD_INIT_FUNC_TRACE(); 1374 1375 if (net_fc) { 1376 fc_conf->pause_time = net_fc->pause_time; 1377 fc_conf->high_water = net_fc->high_water; 1378 fc_conf->low_water = net_fc->low_water; 1379 fc_conf->send_xon = net_fc->send_xon; 1380 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1381 fc_conf->mode = net_fc->mode; 1382 fc_conf->autoneg = net_fc->autoneg; 1383 return 0; 1384 } 1385 ret = fman_if_get_fc_threshold(dev->process_private); 1386 if (ret) { 1387 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1388 fc_conf->pause_time = 1389 fman_if_get_fc_quanta(dev->process_private); 1390 } else { 1391 fc_conf->mode = RTE_ETH_FC_NONE; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int 1398 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1399 struct rte_ether_addr *addr, 1400 uint32_t index, 1401 __rte_unused uint32_t pool) 1402 { 1403 int ret; 1404 1405 PMD_INIT_FUNC_TRACE(); 1406 1407 ret = fman_if_add_mac_addr(dev->process_private, 1408 addr->addr_bytes, index); 1409 1410 if (ret) 1411 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1412 return 0; 1413 } 1414 1415 static void 1416 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1417 uint32_t index) 1418 { 1419 PMD_INIT_FUNC_TRACE(); 1420 1421 fman_if_clear_mac_addr(dev->process_private, index); 1422 } 1423 1424 static int 1425 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1426 struct rte_ether_addr *addr) 1427 { 1428 int ret; 1429 1430 PMD_INIT_FUNC_TRACE(); 1431 1432 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1433 if (ret) 1434 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1435 1436 return ret; 1437 } 1438 1439 static int 1440 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1441 struct rte_eth_rss_conf *rss_conf) 1442 { 1443 struct rte_eth_dev_data *data = dev->data; 1444 struct rte_eth_conf *eth_conf = &data->dev_conf; 1445 1446 PMD_INIT_FUNC_TRACE(); 1447 1448 if (!(default_q || fmc_q)) { 1449 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1450 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1451 return -1; 1452 } 1453 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1454 } else { 1455 DPAA_PMD_ERR("Function not supported\n"); 1456 return -ENOTSUP; 1457 } 1458 return 0; 1459 } 1460 1461 static int 1462 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1463 struct rte_eth_rss_conf *rss_conf) 1464 { 1465 struct rte_eth_dev_data *data = dev->data; 1466 struct rte_eth_conf *eth_conf = &data->dev_conf; 1467 1468 /* dpaa does not support rss_key, so length should be 0*/ 1469 rss_conf->rss_key_len = 0; 1470 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1471 return 0; 1472 } 1473 1474 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1475 uint16_t queue_id) 1476 { 1477 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1478 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1479 1480 if (!rxq->is_static) 1481 return -EINVAL; 1482 1483 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1484 } 1485 1486 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1487 uint16_t queue_id) 1488 { 1489 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1490 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1491 uint32_t temp; 1492 ssize_t temp1; 1493 1494 if (!rxq->is_static) 1495 return -EINVAL; 1496 1497 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1498 1499 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1500 if (temp1 != sizeof(temp)) 1501 DPAA_PMD_DEBUG("read did not return anything"); 1502 1503 qman_fq_portal_thread_irq(rxq->qp); 1504 1505 return 0; 1506 } 1507 1508 static void 1509 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1510 struct rte_eth_rxq_info *qinfo) 1511 { 1512 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1513 struct qman_fq *rxq; 1514 int ret; 1515 1516 rxq = dev->data->rx_queues[queue_id]; 1517 1518 qinfo->mp = dpaa_intf->bp_info->mp; 1519 qinfo->scattered_rx = dev->data->scattered_rx; 1520 qinfo->nb_desc = rxq->nb_desc; 1521 1522 /* Report the HW Rx buffer length to user */ 1523 ret = fman_if_get_maxfrm(dev->process_private); 1524 if (ret > 0) 1525 qinfo->rx_buf_size = ret; 1526 1527 qinfo->conf.rx_free_thresh = 1; 1528 qinfo->conf.rx_drop_en = 1; 1529 qinfo->conf.rx_deferred_start = 0; 1530 qinfo->conf.offloads = rxq->offloads; 1531 } 1532 1533 static void 1534 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1535 struct rte_eth_txq_info *qinfo) 1536 { 1537 struct qman_fq *txq; 1538 1539 txq = dev->data->tx_queues[queue_id]; 1540 1541 qinfo->nb_desc = txq->nb_desc; 1542 qinfo->conf.tx_thresh.pthresh = 0; 1543 qinfo->conf.tx_thresh.hthresh = 0; 1544 qinfo->conf.tx_thresh.wthresh = 0; 1545 1546 qinfo->conf.tx_free_thresh = 0; 1547 qinfo->conf.tx_rs_thresh = 0; 1548 qinfo->conf.offloads = txq->offloads; 1549 qinfo->conf.tx_deferred_start = 0; 1550 } 1551 1552 static struct eth_dev_ops dpaa_devops = { 1553 .dev_configure = dpaa_eth_dev_configure, 1554 .dev_start = dpaa_eth_dev_start, 1555 .dev_stop = dpaa_eth_dev_stop, 1556 .dev_close = dpaa_eth_dev_close, 1557 .dev_infos_get = dpaa_eth_dev_info, 1558 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1559 1560 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1561 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1562 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1563 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1564 .rxq_info_get = dpaa_rxq_info_get, 1565 .txq_info_get = dpaa_txq_info_get, 1566 1567 .flow_ctrl_get = dpaa_flow_ctrl_get, 1568 .flow_ctrl_set = dpaa_flow_ctrl_set, 1569 1570 .link_update = dpaa_eth_link_update, 1571 .stats_get = dpaa_eth_stats_get, 1572 .xstats_get = dpaa_dev_xstats_get, 1573 .xstats_get_by_id = dpaa_xstats_get_by_id, 1574 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1575 .xstats_get_names = dpaa_xstats_get_names, 1576 .xstats_reset = dpaa_eth_stats_reset, 1577 .stats_reset = dpaa_eth_stats_reset, 1578 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1579 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1580 .allmulticast_enable = dpaa_eth_multicast_enable, 1581 .allmulticast_disable = dpaa_eth_multicast_disable, 1582 .mtu_set = dpaa_mtu_set, 1583 .dev_set_link_down = dpaa_link_down, 1584 .dev_set_link_up = dpaa_link_up, 1585 .mac_addr_add = dpaa_dev_add_mac_addr, 1586 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1587 .mac_addr_set = dpaa_dev_set_mac_addr, 1588 1589 .fw_version_get = dpaa_fw_version_get, 1590 1591 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1592 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1593 .rss_hash_update = dpaa_dev_rss_hash_update, 1594 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1595 }; 1596 1597 static bool 1598 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1599 { 1600 if (strcmp(dev->device->driver->name, 1601 drv->driver.name)) 1602 return false; 1603 1604 return true; 1605 } 1606 1607 static bool 1608 is_dpaa_supported(struct rte_eth_dev *dev) 1609 { 1610 return is_device_supported(dev, &rte_dpaa_pmd); 1611 } 1612 1613 int 1614 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1615 { 1616 struct rte_eth_dev *dev; 1617 1618 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1619 1620 dev = &rte_eth_devices[port]; 1621 1622 if (!is_dpaa_supported(dev)) 1623 return -ENOTSUP; 1624 1625 if (on) 1626 fman_if_loopback_enable(dev->process_private); 1627 else 1628 fman_if_loopback_disable(dev->process_private); 1629 1630 return 0; 1631 } 1632 1633 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1634 struct fman_if *fman_intf) 1635 { 1636 struct rte_eth_fc_conf *fc_conf; 1637 int ret; 1638 1639 PMD_INIT_FUNC_TRACE(); 1640 1641 if (!(dpaa_intf->fc_conf)) { 1642 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1643 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1644 if (!dpaa_intf->fc_conf) { 1645 DPAA_PMD_ERR("unable to save flow control info"); 1646 return -ENOMEM; 1647 } 1648 } 1649 fc_conf = dpaa_intf->fc_conf; 1650 ret = fman_if_get_fc_threshold(fman_intf); 1651 if (ret) { 1652 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1653 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1654 } else { 1655 fc_conf->mode = RTE_ETH_FC_NONE; 1656 } 1657 1658 return 0; 1659 } 1660 1661 /* Initialise an Rx FQ */ 1662 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1663 uint32_t fqid) 1664 { 1665 struct qm_mcc_initfq opts = {0}; 1666 int ret; 1667 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1668 struct qm_mcc_initcgr cgr_opts = { 1669 .we_mask = QM_CGR_WE_CS_THRES | 1670 QM_CGR_WE_CSTD_EN | 1671 QM_CGR_WE_MODE, 1672 .cgr = { 1673 .cstd_en = QM_CGR_EN, 1674 .mode = QMAN_CGR_MODE_FRAME 1675 } 1676 }; 1677 1678 if (fmc_q || default_q) { 1679 ret = qman_reserve_fqid(fqid); 1680 if (ret) { 1681 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1682 fqid, ret); 1683 return -EINVAL; 1684 } 1685 } 1686 1687 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1688 ret = qman_create_fq(fqid, flags, fq); 1689 if (ret) { 1690 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1691 fqid, ret); 1692 return ret; 1693 } 1694 fq->is_static = false; 1695 1696 dpaa_poll_queue_default_config(&opts); 1697 1698 if (cgr_rx) { 1699 /* Enable tail drop with cgr on this queue */ 1700 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1701 cgr_rx->cb = NULL; 1702 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1703 &cgr_opts); 1704 if (ret) { 1705 DPAA_PMD_WARN( 1706 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1707 fq->fqid, ret); 1708 goto without_cgr; 1709 } 1710 opts.we_mask |= QM_INITFQ_WE_CGID; 1711 opts.fqd.cgid = cgr_rx->cgrid; 1712 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1713 } 1714 without_cgr: 1715 ret = qman_init_fq(fq, 0, &opts); 1716 if (ret) 1717 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1718 return ret; 1719 } 1720 1721 /* Initialise a Tx FQ */ 1722 static int dpaa_tx_queue_init(struct qman_fq *fq, 1723 struct fman_if *fman_intf, 1724 struct qman_cgr *cgr_tx) 1725 { 1726 struct qm_mcc_initfq opts = {0}; 1727 struct qm_mcc_initcgr cgr_opts = { 1728 .we_mask = QM_CGR_WE_CS_THRES | 1729 QM_CGR_WE_CSTD_EN | 1730 QM_CGR_WE_MODE, 1731 .cgr = { 1732 .cstd_en = QM_CGR_EN, 1733 .mode = QMAN_CGR_MODE_FRAME 1734 } 1735 }; 1736 int ret; 1737 1738 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1739 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1740 if (ret) { 1741 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1742 return ret; 1743 } 1744 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1745 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1746 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1747 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1748 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1749 opts.fqd.context_b = 0; 1750 /* no tx-confirmation */ 1751 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1752 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1753 if (fman_ip_rev >= FMAN_V3) { 1754 /* Set B0V bit in contextA to set ASPID to 0 */ 1755 opts.fqd.context_a.hi |= 0x04000000; 1756 } 1757 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1758 1759 if (cgr_tx) { 1760 /* Enable tail drop with cgr on this queue */ 1761 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1762 td_tx_threshold, 0); 1763 cgr_tx->cb = NULL; 1764 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1765 &cgr_opts); 1766 if (ret) { 1767 DPAA_PMD_WARN( 1768 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1769 fq->fqid, ret); 1770 goto without_cgr; 1771 } 1772 opts.we_mask |= QM_INITFQ_WE_CGID; 1773 opts.fqd.cgid = cgr_tx->cgrid; 1774 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1775 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1776 td_tx_threshold); 1777 } 1778 without_cgr: 1779 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1780 if (ret) 1781 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1782 return ret; 1783 } 1784 1785 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1786 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1787 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1788 { 1789 struct qm_mcc_initfq opts = {0}; 1790 int ret; 1791 1792 PMD_INIT_FUNC_TRACE(); 1793 1794 ret = qman_reserve_fqid(fqid); 1795 if (ret) { 1796 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1797 fqid, ret); 1798 return -EINVAL; 1799 } 1800 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1801 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1802 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1803 if (ret) { 1804 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1805 fqid, ret); 1806 return ret; 1807 } 1808 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1809 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1810 ret = qman_init_fq(fq, 0, &opts); 1811 if (ret) 1812 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1813 fqid, ret); 1814 return ret; 1815 } 1816 #endif 1817 1818 /* Initialise a network interface */ 1819 static int 1820 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1821 { 1822 struct rte_dpaa_device *dpaa_device; 1823 struct fm_eth_port_cfg *cfg; 1824 struct dpaa_if *dpaa_intf; 1825 struct fman_if *fman_intf; 1826 int dev_id; 1827 1828 PMD_INIT_FUNC_TRACE(); 1829 1830 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1831 dev_id = dpaa_device->id.dev_id; 1832 cfg = dpaa_get_eth_port_cfg(dev_id); 1833 fman_intf = cfg->fman_if; 1834 eth_dev->process_private = fman_intf; 1835 1836 /* Plugging of UCODE burst API not supported in Secondary */ 1837 dpaa_intf = eth_dev->data->dev_private; 1838 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1839 if (dpaa_intf->cgr_tx) 1840 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1841 else 1842 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1843 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1844 qman_set_fq_lookup_table( 1845 dpaa_intf->rx_queues->qman_fq_lookup_table); 1846 #endif 1847 1848 return 0; 1849 } 1850 1851 /* Initialise a network interface */ 1852 static int 1853 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1854 { 1855 int num_rx_fqs, fqid; 1856 int loop, ret = 0; 1857 int dev_id; 1858 struct rte_dpaa_device *dpaa_device; 1859 struct dpaa_if *dpaa_intf; 1860 struct fm_eth_port_cfg *cfg; 1861 struct fman_if *fman_intf; 1862 struct fman_if_bpool *bp, *tmp_bp; 1863 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1864 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1865 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1866 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1867 int8_t vsp_id = -1; 1868 1869 PMD_INIT_FUNC_TRACE(); 1870 1871 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1872 dev_id = dpaa_device->id.dev_id; 1873 dpaa_intf = eth_dev->data->dev_private; 1874 cfg = dpaa_get_eth_port_cfg(dev_id); 1875 fman_intf = cfg->fman_if; 1876 1877 dpaa_intf->name = dpaa_device->name; 1878 1879 /* save fman_if & cfg in the interface structure */ 1880 eth_dev->process_private = fman_intf; 1881 dpaa_intf->ifid = dev_id; 1882 dpaa_intf->cfg = cfg; 1883 1884 memset((char *)dev_rx_fqids, 0, 1885 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1886 1887 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1888 1889 /* Initialize Rx FQ's */ 1890 if (default_q) { 1891 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1892 } else if (fmc_q) { 1893 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1894 dev_vspids, 1895 DPAA_MAX_NUM_PCD_QUEUES); 1896 if (num_rx_fqs < 0) { 1897 DPAA_PMD_ERR("%s FMC initializes failed!", 1898 dpaa_intf->name); 1899 goto free_rx; 1900 } 1901 if (!num_rx_fqs) { 1902 DPAA_PMD_WARN("%s is not configured by FMC.", 1903 dpaa_intf->name); 1904 } 1905 } else { 1906 /* FMCLESS mode, load balance to multiple cores.*/ 1907 num_rx_fqs = rte_lcore_count(); 1908 } 1909 1910 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1911 * queues. 1912 */ 1913 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1914 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1915 return -EINVAL; 1916 } 1917 1918 if (num_rx_fqs > 0) { 1919 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1920 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1921 if (!dpaa_intf->rx_queues) { 1922 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1923 return -ENOMEM; 1924 } 1925 } else { 1926 dpaa_intf->rx_queues = NULL; 1927 } 1928 1929 memset(cgrid, 0, sizeof(cgrid)); 1930 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1931 1932 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1933 * Tx tail drop is disabled. 1934 */ 1935 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1936 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1937 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1938 td_tx_threshold); 1939 /* if a very large value is being configured */ 1940 if (td_tx_threshold > UINT16_MAX) 1941 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1942 } 1943 1944 /* If congestion control is enabled globally*/ 1945 if (num_rx_fqs > 0 && td_threshold) { 1946 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1947 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1948 if (!dpaa_intf->cgr_rx) { 1949 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1950 ret = -ENOMEM; 1951 goto free_rx; 1952 } 1953 1954 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1955 if (ret != num_rx_fqs) { 1956 DPAA_PMD_WARN("insufficient CGRIDs available"); 1957 ret = -EINVAL; 1958 goto free_rx; 1959 } 1960 } else { 1961 dpaa_intf->cgr_rx = NULL; 1962 } 1963 1964 if (!fmc_q && !default_q) { 1965 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1966 num_rx_fqs, 0); 1967 if (ret < 0) { 1968 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1969 goto free_rx; 1970 } 1971 } 1972 1973 for (loop = 0; loop < num_rx_fqs; loop++) { 1974 if (default_q) 1975 fqid = cfg->rx_def; 1976 else 1977 fqid = dev_rx_fqids[loop]; 1978 1979 vsp_id = dev_vspids[loop]; 1980 1981 if (dpaa_intf->cgr_rx) 1982 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1983 1984 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1985 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1986 fqid); 1987 if (ret) 1988 goto free_rx; 1989 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 1990 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1991 } 1992 dpaa_intf->nb_rx_queues = num_rx_fqs; 1993 1994 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1995 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1996 MAX_DPAA_CORES, MAX_CACHELINE); 1997 if (!dpaa_intf->tx_queues) { 1998 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1999 ret = -ENOMEM; 2000 goto free_rx; 2001 } 2002 2003 /* If congestion control is enabled globally*/ 2004 if (td_tx_threshold) { 2005 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 2006 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 2007 MAX_CACHELINE); 2008 if (!dpaa_intf->cgr_tx) { 2009 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 2010 ret = -ENOMEM; 2011 goto free_rx; 2012 } 2013 2014 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2015 1, 0); 2016 if (ret != MAX_DPAA_CORES) { 2017 DPAA_PMD_WARN("insufficient CGRIDs available"); 2018 ret = -EINVAL; 2019 goto free_rx; 2020 } 2021 } else { 2022 dpaa_intf->cgr_tx = NULL; 2023 } 2024 2025 2026 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2027 if (dpaa_intf->cgr_tx) 2028 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2029 2030 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2031 fman_intf, 2032 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2033 if (ret) 2034 goto free_tx; 2035 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2036 } 2037 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2038 2039 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2040 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2041 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2042 if (ret) { 2043 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2044 goto free_tx; 2045 } 2046 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2047 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2048 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2049 if (ret) { 2050 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2051 goto free_tx; 2052 } 2053 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2054 #endif 2055 2056 DPAA_PMD_DEBUG("All frame queues created"); 2057 2058 /* Get the initial configuration for flow control */ 2059 dpaa_fc_set_default(dpaa_intf, fman_intf); 2060 2061 /* reset bpool list, initialize bpool dynamically */ 2062 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2063 list_del(&bp->node); 2064 rte_free(bp); 2065 } 2066 2067 /* Populate ethdev structure */ 2068 eth_dev->dev_ops = &dpaa_devops; 2069 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2070 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2071 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2072 2073 /* Allocate memory for storing MAC addresses */ 2074 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2075 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2076 if (eth_dev->data->mac_addrs == NULL) { 2077 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2078 "store MAC addresses", 2079 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2080 ret = -ENOMEM; 2081 goto free_tx; 2082 } 2083 2084 /* copy the primary mac address */ 2085 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2086 2087 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n", 2088 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2089 2090 if (!fman_intf->is_shared_mac) { 2091 /* Configure error packet handling */ 2092 fman_if_receive_rx_errors(fman_intf, 2093 FM_FD_RX_STATUS_ERR_MASK); 2094 /* Disable RX mode */ 2095 fman_if_disable_rx(fman_intf); 2096 /* Disable promiscuous mode */ 2097 fman_if_promiscuous_disable(fman_intf); 2098 /* Disable multicast */ 2099 fman_if_reset_mcast_filter_table(fman_intf); 2100 /* Reset interface statistics */ 2101 fman_if_stats_reset(fman_intf); 2102 /* Disable SG by default */ 2103 fman_if_set_sg(fman_intf, 0); 2104 fman_if_set_maxfrm(fman_intf, 2105 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2106 } 2107 2108 return 0; 2109 2110 free_tx: 2111 rte_free(dpaa_intf->tx_queues); 2112 dpaa_intf->tx_queues = NULL; 2113 dpaa_intf->nb_tx_queues = 0; 2114 2115 free_rx: 2116 rte_free(dpaa_intf->cgr_rx); 2117 rte_free(dpaa_intf->cgr_tx); 2118 rte_free(dpaa_intf->rx_queues); 2119 dpaa_intf->rx_queues = NULL; 2120 dpaa_intf->nb_rx_queues = 0; 2121 return ret; 2122 } 2123 2124 static int 2125 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2126 struct rte_dpaa_device *dpaa_dev) 2127 { 2128 int diag; 2129 int ret; 2130 struct rte_eth_dev *eth_dev; 2131 2132 PMD_INIT_FUNC_TRACE(); 2133 2134 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2135 RTE_PKTMBUF_HEADROOM) { 2136 DPAA_PMD_ERR( 2137 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2138 RTE_PKTMBUF_HEADROOM, 2139 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2140 2141 return -1; 2142 } 2143 2144 /* In case of secondary process, the device is already configured 2145 * and no further action is required, except portal initialization 2146 * and verifying secondary attachment to port name. 2147 */ 2148 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2149 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2150 if (!eth_dev) 2151 return -ENOMEM; 2152 eth_dev->device = &dpaa_dev->device; 2153 eth_dev->dev_ops = &dpaa_devops; 2154 2155 ret = dpaa_dev_init_secondary(eth_dev); 2156 if (ret != 0) { 2157 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 2158 return ret; 2159 } 2160 2161 rte_eth_dev_probing_finish(eth_dev); 2162 return 0; 2163 } 2164 2165 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2166 if (access("/tmp/fmc.bin", F_OK) == -1) { 2167 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2168 default_q = 1; 2169 } 2170 2171 if (!(default_q || fmc_q)) { 2172 if (dpaa_fm_init()) { 2173 DPAA_PMD_ERR("FM init failed\n"); 2174 return -1; 2175 } 2176 } 2177 2178 /* disabling the default push mode for LS1043 */ 2179 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2180 dpaa_push_mode_max_queue = 0; 2181 2182 /* if push mode queues to be enabled. Currently we are allowing 2183 * only one queue per thread. 2184 */ 2185 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2186 dpaa_push_mode_max_queue = 2187 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2188 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2189 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2190 } 2191 2192 is_global_init = 1; 2193 } 2194 2195 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2196 ret = rte_dpaa_portal_init((void *)1); 2197 if (ret) { 2198 DPAA_PMD_ERR("Unable to initialize portal"); 2199 return ret; 2200 } 2201 } 2202 2203 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2204 if (!eth_dev) 2205 return -ENOMEM; 2206 2207 eth_dev->data->dev_private = 2208 rte_zmalloc("ethdev private structure", 2209 sizeof(struct dpaa_if), 2210 RTE_CACHE_LINE_SIZE); 2211 if (!eth_dev->data->dev_private) { 2212 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2213 rte_eth_dev_release_port(eth_dev); 2214 return -ENOMEM; 2215 } 2216 2217 eth_dev->device = &dpaa_dev->device; 2218 dpaa_dev->eth_dev = eth_dev; 2219 2220 qman_ern_register_cb(dpaa_free_mbuf); 2221 2222 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2223 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2224 2225 /* Invoke PMD device initialization function */ 2226 diag = dpaa_dev_init(eth_dev); 2227 if (diag == 0) { 2228 if (!dpaa_tx_sg_pool) { 2229 dpaa_tx_sg_pool = 2230 rte_pktmbuf_pool_create("dpaa_mbuf_tx_sg_pool", 2231 DPAA_POOL_SIZE, 2232 DPAA_POOL_CACHE_SIZE, 0, 2233 DPAA_MAX_SGS * sizeof(struct qm_sg_entry), 2234 rte_socket_id()); 2235 if (dpaa_tx_sg_pool == NULL) { 2236 DPAA_PMD_ERR("SG pool creation failed\n"); 2237 return -ENOMEM; 2238 } 2239 } 2240 rte_eth_dev_probing_finish(eth_dev); 2241 dpaa_valid_dev++; 2242 return 0; 2243 } 2244 2245 rte_eth_dev_release_port(eth_dev); 2246 return diag; 2247 } 2248 2249 static int 2250 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2251 { 2252 struct rte_eth_dev *eth_dev; 2253 int ret; 2254 2255 PMD_INIT_FUNC_TRACE(); 2256 2257 eth_dev = dpaa_dev->eth_dev; 2258 dpaa_eth_dev_close(eth_dev); 2259 dpaa_valid_dev--; 2260 if (!dpaa_valid_dev) 2261 rte_mempool_free(dpaa_tx_sg_pool); 2262 ret = rte_eth_dev_release_port(eth_dev); 2263 2264 return ret; 2265 } 2266 2267 static void __attribute__((destructor(102))) dpaa_finish(void) 2268 { 2269 /* For secondary, primary will do all the cleanup */ 2270 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2271 return; 2272 2273 if (!(default_q || fmc_q)) { 2274 unsigned int i; 2275 2276 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2277 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2278 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2279 struct dpaa_if *dpaa_intf = 2280 dev->data->dev_private; 2281 struct fman_if *fif = 2282 dev->process_private; 2283 if (dpaa_intf->port_handle) 2284 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2285 DPAA_PMD_WARN("DPAA FM " 2286 "deconfig failed\n"); 2287 if (fif->num_profiles) { 2288 if (dpaa_port_vsp_cleanup(dpaa_intf, 2289 fif)) 2290 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2291 } 2292 } 2293 } 2294 if (is_global_init) 2295 if (dpaa_fm_term()) 2296 DPAA_PMD_WARN("DPAA FM term failed\n"); 2297 2298 is_global_init = 0; 2299 2300 DPAA_PMD_INFO("DPAA fman cleaned up"); 2301 } 2302 } 2303 2304 static struct rte_dpaa_driver rte_dpaa_pmd = { 2305 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2306 .drv_type = FSL_DPAA_ETH, 2307 .probe = rte_dpaa_probe, 2308 .remove = rte_dpaa_remove, 2309 }; 2310 2311 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2312 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2313