1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <rte_ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 51 /* Supported Rx offloads */ 52 static uint64_t dev_rx_offloads_sup = 53 DEV_RX_OFFLOAD_JUMBO_FRAME | 54 DEV_RX_OFFLOAD_SCATTER; 55 56 /* Rx offloads which cannot be disabled */ 57 static uint64_t dev_rx_offloads_nodis = 58 DEV_RX_OFFLOAD_IPV4_CKSUM | 59 DEV_RX_OFFLOAD_UDP_CKSUM | 60 DEV_RX_OFFLOAD_TCP_CKSUM | 61 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 62 DEV_RX_OFFLOAD_RSS_HASH; 63 64 /* Supported Tx offloads */ 65 static uint64_t dev_tx_offloads_sup = 66 DEV_TX_OFFLOAD_MT_LOCKFREE | 67 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 68 69 /* Tx offloads which cannot be disabled */ 70 static uint64_t dev_tx_offloads_nodis = 71 DEV_TX_OFFLOAD_IPV4_CKSUM | 72 DEV_TX_OFFLOAD_UDP_CKSUM | 73 DEV_TX_OFFLOAD_TCP_CKSUM | 74 DEV_TX_OFFLOAD_SCTP_CKSUM | 75 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 76 DEV_TX_OFFLOAD_MULTI_SEGS; 77 78 /* Keep track of whether QMAN and BMAN have been globally initialized */ 79 static int is_global_init; 80 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 81 static int default_q; /* use default queue - FMC is not executed*/ 82 /* At present we only allow up to 4 push mode queues as default - as each of 83 * this queue need dedicated portal and we are short of portals. 84 */ 85 #define DPAA_MAX_PUSH_MODE_QUEUE 8 86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 87 88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 90 91 92 /* Per RX FQ Taildrop in frame count */ 93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 94 95 /* Per TX FQ Taildrop in frame count, disabled by default */ 96 static unsigned int td_tx_threshold; 97 98 struct rte_dpaa_xstats_name_off { 99 char name[RTE_ETH_XSTATS_NAME_SIZE]; 100 uint32_t offset; 101 }; 102 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 104 {"rx_align_err", 105 offsetof(struct dpaa_if_stats, raln)}, 106 {"rx_valid_pause", 107 offsetof(struct dpaa_if_stats, rxpf)}, 108 {"rx_fcs_err", 109 offsetof(struct dpaa_if_stats, rfcs)}, 110 {"rx_vlan_frame", 111 offsetof(struct dpaa_if_stats, rvlan)}, 112 {"rx_frame_err", 113 offsetof(struct dpaa_if_stats, rerr)}, 114 {"rx_drop_err", 115 offsetof(struct dpaa_if_stats, rdrp)}, 116 {"rx_undersized", 117 offsetof(struct dpaa_if_stats, rund)}, 118 {"rx_oversize_err", 119 offsetof(struct dpaa_if_stats, rovr)}, 120 {"rx_fragment_pkt", 121 offsetof(struct dpaa_if_stats, rfrg)}, 122 {"tx_valid_pause", 123 offsetof(struct dpaa_if_stats, txpf)}, 124 {"tx_fcs_err", 125 offsetof(struct dpaa_if_stats, terr)}, 126 {"tx_vlan_frame", 127 offsetof(struct dpaa_if_stats, tvlan)}, 128 {"rx_undersized", 129 offsetof(struct dpaa_if_stats, tund)}, 130 }; 131 132 static struct rte_dpaa_driver rte_dpaa_pmd; 133 134 static int 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 136 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 138 int wait_to_complete __rte_unused); 139 140 static void dpaa_interrupt_handler(void *param); 141 142 static inline void 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 144 { 145 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 146 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 147 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 148 QM_FQCTRL_PREFERINCACHE; 149 opts->fqd.context_a.stashing.exclusive = 0; 150 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 151 opts->fqd.context_a.stashing.annotation_cl = 152 DPAA_IF_RX_ANNOTATION_STASH; 153 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 154 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 155 } 156 157 static int 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 159 { 160 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 161 + VLAN_TAG_SIZE; 162 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 163 164 PMD_INIT_FUNC_TRACE(); 165 166 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 167 return -EINVAL; 168 /* 169 * Refuse mtu that requires the support of scattered packets 170 * when this feature has not been enabled before. 171 */ 172 if (dev->data->min_rx_buf_size && 173 !dev->data->scattered_rx && frame_size > buffsz) { 174 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 175 return -EINVAL; 176 } 177 178 /* check <seg size> * <max_seg> >= max_frame */ 179 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 180 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 181 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 182 buffsz * DPAA_SGT_MAX_ENTRIES); 183 return -EINVAL; 184 } 185 186 if (frame_size > RTE_ETHER_MAX_LEN) 187 dev->data->dev_conf.rxmode.offloads |= 188 DEV_RX_OFFLOAD_JUMBO_FRAME; 189 else 190 dev->data->dev_conf.rxmode.offloads &= 191 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 192 193 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 194 195 fman_if_set_maxfrm(dev->process_private, frame_size); 196 197 return 0; 198 } 199 200 static int 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 202 { 203 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 204 uint64_t rx_offloads = eth_conf->rxmode.offloads; 205 uint64_t tx_offloads = eth_conf->txmode.offloads; 206 struct rte_device *rdev = dev->device; 207 struct rte_dpaa_device *dpaa_dev; 208 struct fman_if *fif = dev->process_private; 209 struct __fman_if *__fif; 210 struct rte_intr_handle *intr_handle; 211 int ret; 212 213 PMD_INIT_FUNC_TRACE(); 214 215 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 216 intr_handle = &dpaa_dev->intr_handle; 217 __fif = container_of(fif, struct __fman_if, __if); 218 219 /* Rx offloads which are enabled by default */ 220 if (dev_rx_offloads_nodis & ~rx_offloads) { 221 DPAA_PMD_INFO( 222 "Some of rx offloads enabled by default - requested 0x%" PRIx64 223 " fixed are 0x%" PRIx64, 224 rx_offloads, dev_rx_offloads_nodis); 225 } 226 227 /* Tx offloads which are enabled by default */ 228 if (dev_tx_offloads_nodis & ~tx_offloads) { 229 DPAA_PMD_INFO( 230 "Some of tx offloads enabled by default - requested 0x%" PRIx64 231 " fixed are 0x%" PRIx64, 232 tx_offloads, dev_tx_offloads_nodis); 233 } 234 235 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 236 uint32_t max_len; 237 238 DPAA_PMD_DEBUG("enabling jumbo"); 239 240 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 241 DPAA_MAX_RX_PKT_LEN) 242 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 243 else { 244 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 245 "supported is %d", 246 dev->data->dev_conf.rxmode.max_rx_pkt_len, 247 DPAA_MAX_RX_PKT_LEN); 248 max_len = DPAA_MAX_RX_PKT_LEN; 249 } 250 251 fman_if_set_maxfrm(dev->process_private, max_len); 252 dev->data->mtu = max_len 253 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE; 254 } 255 256 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 257 DPAA_PMD_DEBUG("enabling scatter mode"); 258 fman_if_set_sg(dev->process_private, 1); 259 dev->data->scattered_rx = 1; 260 } 261 262 if (!(default_q || fmc_q)) { 263 if (dpaa_fm_config(dev, 264 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 265 dpaa_write_fm_config_to_file(); 266 DPAA_PMD_ERR("FM port configuration: Failed\n"); 267 return -1; 268 } 269 dpaa_write_fm_config_to_file(); 270 } 271 272 /* if the interrupts were configured on this devices*/ 273 if (intr_handle && intr_handle->fd) { 274 if (dev->data->dev_conf.intr_conf.lsc != 0) 275 rte_intr_callback_register(intr_handle, 276 dpaa_interrupt_handler, 277 (void *)dev); 278 279 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd); 280 if (ret) { 281 if (dev->data->dev_conf.intr_conf.lsc != 0) { 282 rte_intr_callback_unregister(intr_handle, 283 dpaa_interrupt_handler, 284 (void *)dev); 285 if (ret == EINVAL) 286 printf("Failed to enable interrupt: Not Supported\n"); 287 else 288 printf("Failed to enable interrupt\n"); 289 } 290 dev->data->dev_conf.intr_conf.lsc = 0; 291 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 292 } 293 } 294 return 0; 295 } 296 297 static const uint32_t * 298 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 299 { 300 static const uint32_t ptypes[] = { 301 RTE_PTYPE_L2_ETHER, 302 RTE_PTYPE_L2_ETHER_VLAN, 303 RTE_PTYPE_L2_ETHER_ARP, 304 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 305 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 306 RTE_PTYPE_L4_ICMP, 307 RTE_PTYPE_L4_TCP, 308 RTE_PTYPE_L4_UDP, 309 RTE_PTYPE_L4_FRAG, 310 RTE_PTYPE_L4_TCP, 311 RTE_PTYPE_L4_UDP, 312 RTE_PTYPE_L4_SCTP 313 }; 314 315 PMD_INIT_FUNC_TRACE(); 316 317 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 318 return ptypes; 319 return NULL; 320 } 321 322 static void dpaa_interrupt_handler(void *param) 323 { 324 struct rte_eth_dev *dev = param; 325 struct rte_device *rdev = dev->device; 326 struct rte_dpaa_device *dpaa_dev; 327 struct rte_intr_handle *intr_handle; 328 uint64_t buf; 329 int bytes_read; 330 331 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 332 intr_handle = &dpaa_dev->intr_handle; 333 334 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t)); 335 if (bytes_read < 0) 336 DPAA_PMD_ERR("Error reading eventfd\n"); 337 dpaa_eth_link_update(dev, 0); 338 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 339 } 340 341 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 342 { 343 struct dpaa_if *dpaa_intf = dev->data->dev_private; 344 345 PMD_INIT_FUNC_TRACE(); 346 347 if (!(default_q || fmc_q)) 348 dpaa_write_fm_config_to_file(); 349 350 /* Change tx callback to the real one */ 351 if (dpaa_intf->cgr_tx) 352 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 353 else 354 dev->tx_pkt_burst = dpaa_eth_queue_tx; 355 356 fman_if_enable_rx(dev->process_private); 357 358 return 0; 359 } 360 361 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 362 { 363 struct fman_if *fif = dev->process_private; 364 365 PMD_INIT_FUNC_TRACE(); 366 367 if (!fif->is_shared_mac) 368 fman_if_disable_rx(fif); 369 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 370 } 371 372 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 373 { 374 struct fman_if *fif = dev->process_private; 375 struct __fman_if *__fif; 376 struct rte_device *rdev = dev->device; 377 struct rte_dpaa_device *dpaa_dev; 378 struct rte_intr_handle *intr_handle; 379 struct dpaa_if *dpaa_intf = dev->data->dev_private; 380 int loop; 381 382 PMD_INIT_FUNC_TRACE(); 383 384 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 385 return 0; 386 387 if (!dpaa_intf) { 388 DPAA_PMD_WARN("Already closed or not started"); 389 return -1; 390 } 391 392 /* DPAA FM deconfig */ 393 if (!(default_q || fmc_q)) { 394 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 395 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 396 } 397 398 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 399 intr_handle = &dpaa_dev->intr_handle; 400 __fif = container_of(fif, struct __fman_if, __if); 401 402 dpaa_eth_dev_stop(dev); 403 404 if (intr_handle && intr_handle->fd && 405 dev->data->dev_conf.intr_conf.lsc != 0) { 406 dpaa_intr_disable(__fif->node_name); 407 rte_intr_callback_unregister(intr_handle, 408 dpaa_interrupt_handler, 409 (void *)dev); 410 } 411 412 /* release configuration memory */ 413 if (dpaa_intf->fc_conf) 414 rte_free(dpaa_intf->fc_conf); 415 416 /* Release RX congestion Groups */ 417 if (dpaa_intf->cgr_rx) { 418 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 419 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 420 421 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 422 dpaa_intf->nb_rx_queues); 423 } 424 425 rte_free(dpaa_intf->cgr_rx); 426 dpaa_intf->cgr_rx = NULL; 427 /* Release TX congestion Groups */ 428 if (dpaa_intf->cgr_tx) { 429 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 430 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 431 432 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid, 433 MAX_DPAA_CORES); 434 rte_free(dpaa_intf->cgr_tx); 435 dpaa_intf->cgr_tx = NULL; 436 } 437 438 rte_free(dpaa_intf->rx_queues); 439 dpaa_intf->rx_queues = NULL; 440 441 rte_free(dpaa_intf->tx_queues); 442 dpaa_intf->tx_queues = NULL; 443 444 dev->dev_ops = NULL; 445 dev->rx_pkt_burst = NULL; 446 dev->tx_pkt_burst = NULL; 447 448 return 0; 449 } 450 451 static int 452 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 453 char *fw_version, 454 size_t fw_size) 455 { 456 int ret; 457 FILE *svr_file = NULL; 458 unsigned int svr_ver = 0; 459 460 PMD_INIT_FUNC_TRACE(); 461 462 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 463 if (!svr_file) { 464 DPAA_PMD_ERR("Unable to open SoC device"); 465 return -ENOTSUP; /* Not supported on this infra */ 466 } 467 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 468 dpaa_svr_family = svr_ver & SVR_MASK; 469 else 470 DPAA_PMD_ERR("Unable to read SoC device"); 471 472 fclose(svr_file); 473 474 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 475 svr_ver, fman_ip_rev); 476 ret += 1; /* add the size of '\0' */ 477 478 if (fw_size < (uint32_t)ret) 479 return ret; 480 else 481 return 0; 482 } 483 484 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 485 struct rte_eth_dev_info *dev_info) 486 { 487 struct dpaa_if *dpaa_intf = dev->data->dev_private; 488 struct fman_if *fif = dev->process_private; 489 490 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 491 492 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 493 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 494 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 495 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 496 dev_info->max_hash_mac_addrs = 0; 497 dev_info->max_vfs = 0; 498 dev_info->max_vmdq_pools = ETH_16_POOLS; 499 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 500 501 if (fif->mac_type == fman_mac_1g) { 502 dev_info->speed_capa = ETH_LINK_SPEED_1G; 503 } else if (fif->mac_type == fman_mac_2_5g) { 504 dev_info->speed_capa = ETH_LINK_SPEED_1G 505 | ETH_LINK_SPEED_2_5G; 506 } else if (fif->mac_type == fman_mac_10g) { 507 dev_info->speed_capa = ETH_LINK_SPEED_1G 508 | ETH_LINK_SPEED_2_5G 509 | ETH_LINK_SPEED_10G; 510 } else { 511 DPAA_PMD_ERR("invalid link_speed: %s, %d", 512 dpaa_intf->name, fif->mac_type); 513 return -EINVAL; 514 } 515 516 dev_info->rx_offload_capa = dev_rx_offloads_sup | 517 dev_rx_offloads_nodis; 518 dev_info->tx_offload_capa = dev_tx_offloads_sup | 519 dev_tx_offloads_nodis; 520 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 521 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 522 dev_info->default_rxportconf.nb_queues = 1; 523 dev_info->default_txportconf.nb_queues = 1; 524 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 525 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 526 527 return 0; 528 } 529 530 static int 531 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 532 __rte_unused uint16_t queue_id, 533 struct rte_eth_burst_mode *mode) 534 { 535 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 536 int ret = -EINVAL; 537 unsigned int i; 538 const struct burst_info { 539 uint64_t flags; 540 const char *output; 541 } rx_offload_map[] = { 542 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 543 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}, 544 {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 545 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 546 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 547 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 548 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"} 549 }; 550 551 /* Update Rx offload info */ 552 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 553 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 554 snprintf(mode->info, sizeof(mode->info), "%s", 555 rx_offload_map[i].output); 556 ret = 0; 557 break; 558 } 559 } 560 return ret; 561 } 562 563 static int 564 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 565 __rte_unused uint16_t queue_id, 566 struct rte_eth_burst_mode *mode) 567 { 568 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 569 int ret = -EINVAL; 570 unsigned int i; 571 const struct burst_info { 572 uint64_t flags; 573 const char *output; 574 } tx_offload_map[] = { 575 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 576 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 577 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 578 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 579 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 580 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 581 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 582 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 583 }; 584 585 /* Update Tx offload info */ 586 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 587 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 588 snprintf(mode->info, sizeof(mode->info), "%s", 589 tx_offload_map[i].output); 590 ret = 0; 591 break; 592 } 593 } 594 return ret; 595 } 596 597 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 598 int wait_to_complete __rte_unused) 599 { 600 struct dpaa_if *dpaa_intf = dev->data->dev_private; 601 struct rte_eth_link *link = &dev->data->dev_link; 602 struct fman_if *fif = dev->process_private; 603 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 604 int ret; 605 606 PMD_INIT_FUNC_TRACE(); 607 608 if (fif->mac_type == fman_mac_1g) 609 link->link_speed = ETH_SPEED_NUM_1G; 610 else if (fif->mac_type == fman_mac_2_5g) 611 link->link_speed = ETH_SPEED_NUM_2_5G; 612 else if (fif->mac_type == fman_mac_10g) 613 link->link_speed = ETH_SPEED_NUM_10G; 614 else 615 DPAA_PMD_ERR("invalid link_speed: %s, %d", 616 dpaa_intf->name, fif->mac_type); 617 618 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 619 ret = dpaa_get_link_status(__fif->node_name); 620 if (ret < 0) 621 return ret; 622 link->link_status = ret; 623 } else { 624 link->link_status = dpaa_intf->valid; 625 } 626 627 link->link_duplex = ETH_LINK_FULL_DUPLEX; 628 link->link_autoneg = ETH_LINK_AUTONEG; 629 630 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 631 link->link_status ? "Up" : "Down"); 632 return 0; 633 } 634 635 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 636 struct rte_eth_stats *stats) 637 { 638 PMD_INIT_FUNC_TRACE(); 639 640 fman_if_stats_get(dev->process_private, stats); 641 return 0; 642 } 643 644 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 645 { 646 PMD_INIT_FUNC_TRACE(); 647 648 fman_if_stats_reset(dev->process_private); 649 650 return 0; 651 } 652 653 static int 654 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 655 unsigned int n) 656 { 657 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 658 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 659 660 if (n < num) 661 return num; 662 663 if (xstats == NULL) 664 return 0; 665 666 fman_if_stats_get_all(dev->process_private, values, 667 sizeof(struct dpaa_if_stats) / 8); 668 669 for (i = 0; i < num; i++) { 670 xstats[i].id = i; 671 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 672 } 673 return i; 674 } 675 676 static int 677 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 678 struct rte_eth_xstat_name *xstats_names, 679 unsigned int limit) 680 { 681 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 682 683 if (limit < stat_cnt) 684 return stat_cnt; 685 686 if (xstats_names != NULL) 687 for (i = 0; i < stat_cnt; i++) 688 strlcpy(xstats_names[i].name, 689 dpaa_xstats_strings[i].name, 690 sizeof(xstats_names[i].name)); 691 692 return stat_cnt; 693 } 694 695 static int 696 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 697 uint64_t *values, unsigned int n) 698 { 699 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 700 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 701 702 if (!ids) { 703 if (n < stat_cnt) 704 return stat_cnt; 705 706 if (!values) 707 return 0; 708 709 fman_if_stats_get_all(dev->process_private, values_copy, 710 sizeof(struct dpaa_if_stats) / 8); 711 712 for (i = 0; i < stat_cnt; i++) 713 values[i] = 714 values_copy[dpaa_xstats_strings[i].offset / 8]; 715 716 return stat_cnt; 717 } 718 719 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 720 721 for (i = 0; i < n; i++) { 722 if (ids[i] >= stat_cnt) { 723 DPAA_PMD_ERR("id value isn't valid"); 724 return -1; 725 } 726 values[i] = values_copy[ids[i]]; 727 } 728 return n; 729 } 730 731 static int 732 dpaa_xstats_get_names_by_id( 733 struct rte_eth_dev *dev, 734 struct rte_eth_xstat_name *xstats_names, 735 const uint64_t *ids, 736 unsigned int limit) 737 { 738 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 739 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 740 741 if (!ids) 742 return dpaa_xstats_get_names(dev, xstats_names, limit); 743 744 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 745 746 for (i = 0; i < limit; i++) { 747 if (ids[i] >= stat_cnt) { 748 DPAA_PMD_ERR("id value isn't valid"); 749 return -1; 750 } 751 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 752 } 753 return limit; 754 } 755 756 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 757 { 758 PMD_INIT_FUNC_TRACE(); 759 760 fman_if_promiscuous_enable(dev->process_private); 761 762 return 0; 763 } 764 765 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 766 { 767 PMD_INIT_FUNC_TRACE(); 768 769 fman_if_promiscuous_disable(dev->process_private); 770 771 return 0; 772 } 773 774 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 775 { 776 PMD_INIT_FUNC_TRACE(); 777 778 fman_if_set_mcast_filter_table(dev->process_private); 779 780 return 0; 781 } 782 783 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 784 { 785 PMD_INIT_FUNC_TRACE(); 786 787 fman_if_reset_mcast_filter_table(dev->process_private); 788 789 return 0; 790 } 791 792 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 793 { 794 struct dpaa_if *dpaa_intf = dev->data->dev_private; 795 struct fman_if_ic_params icp; 796 uint32_t fd_offset; 797 uint32_t bp_size; 798 799 memset(&icp, 0, sizeof(icp)); 800 /* set ICEOF for to the default value , which is 0*/ 801 icp.iciof = DEFAULT_ICIOF; 802 icp.iceof = DEFAULT_RX_ICEOF; 803 icp.icsz = DEFAULT_ICSZ; 804 fman_if_set_ic_params(dev->process_private, &icp); 805 806 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 807 fman_if_set_fdoff(dev->process_private, fd_offset); 808 809 /* Buffer pool size should be equal to Dataroom Size*/ 810 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 811 812 fman_if_set_bp(dev->process_private, 813 dpaa_intf->bp_info->mp->size, 814 dpaa_intf->bp_info->bpid, bp_size); 815 } 816 817 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 818 int8_t vsp_id, uint32_t bpid) 819 { 820 struct dpaa_if *dpaa_intf = dev->data->dev_private; 821 struct fman_if *fif = dev->process_private; 822 823 if (fif->num_profiles) { 824 if (vsp_id < 0) 825 vsp_id = fif->base_profile_id; 826 } else { 827 if (vsp_id < 0) 828 vsp_id = 0; 829 } 830 831 if (dpaa_intf->vsp_bpid[vsp_id] && 832 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 833 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 834 835 return -1; 836 } 837 838 return 0; 839 } 840 841 static 842 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 843 uint16_t nb_desc, 844 unsigned int socket_id __rte_unused, 845 const struct rte_eth_rxconf *rx_conf, 846 struct rte_mempool *mp) 847 { 848 struct dpaa_if *dpaa_intf = dev->data->dev_private; 849 struct fman_if *fif = dev->process_private; 850 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 851 struct qm_mcc_initfq opts = {0}; 852 u32 flags = 0; 853 int ret; 854 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 855 856 PMD_INIT_FUNC_TRACE(); 857 858 if (queue_idx >= dev->data->nb_rx_queues) { 859 rte_errno = EOVERFLOW; 860 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 861 (void *)dev, queue_idx, dev->data->nb_rx_queues); 862 return -rte_errno; 863 } 864 865 /* Rx deferred start is not supported */ 866 if (rx_conf->rx_deferred_start) { 867 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 868 return -EINVAL; 869 } 870 rxq->nb_desc = UINT16_MAX; 871 rxq->offloads = rx_conf->offloads; 872 873 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 874 queue_idx, rxq->fqid); 875 876 if (!fif->num_profiles) { 877 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 878 dpaa_intf->bp_info->mp != mp) { 879 DPAA_PMD_WARN("Multiple pools on same interface not" 880 " supported"); 881 return -EINVAL; 882 } 883 } else { 884 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 885 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 886 return -EINVAL; 887 } 888 } 889 890 /* Max packet can fit in single buffer */ 891 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { 892 ; 893 } else if (dev->data->dev_conf.rxmode.offloads & 894 DEV_RX_OFFLOAD_SCATTER) { 895 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > 896 buffsz * DPAA_SGT_MAX_ENTRIES) { 897 DPAA_PMD_ERR("max RxPkt size %d too big to fit " 898 "MaxSGlist %d", 899 dev->data->dev_conf.rxmode.max_rx_pkt_len, 900 buffsz * DPAA_SGT_MAX_ENTRIES); 901 rte_errno = EOVERFLOW; 902 return -rte_errno; 903 } 904 } else { 905 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 906 " larger than a single mbuf (%u) and scattered" 907 " mode has not been requested", 908 dev->data->dev_conf.rxmode.max_rx_pkt_len, 909 buffsz - RTE_PKTMBUF_HEADROOM); 910 } 911 912 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 913 914 /* For shared interface, it's done in kernel, skip.*/ 915 if (!fif->is_shared_mac) 916 dpaa_fman_if_pool_setup(dev); 917 918 if (fif->num_profiles) { 919 int8_t vsp_id = rxq->vsp_id; 920 921 if (vsp_id >= 0) { 922 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 923 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 924 fif); 925 if (ret) { 926 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 927 return ret; 928 } 929 } else { 930 DPAA_PMD_INFO("Base profile is associated to" 931 " RXQ fqid:%d\r\n", rxq->fqid); 932 if (fif->is_shared_mac) { 933 DPAA_PMD_ERR("Fatal: Base profile is associated" 934 " to shared interface on DPDK."); 935 return -EINVAL; 936 } 937 dpaa_intf->vsp_bpid[fif->base_profile_id] = 938 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 939 } 940 } else { 941 dpaa_intf->vsp_bpid[0] = 942 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 943 } 944 945 dpaa_intf->valid = 1; 946 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 947 fman_if_get_sg_enable(fif), 948 dev->data->dev_conf.rxmode.max_rx_pkt_len); 949 /* checking if push mode only, no error check for now */ 950 if (!rxq->is_static && 951 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 952 struct qman_portal *qp; 953 int q_fd; 954 955 dpaa_push_queue_idx++; 956 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 957 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 958 QM_FQCTRL_CTXASTASHING | 959 QM_FQCTRL_PREFERINCACHE; 960 opts.fqd.context_a.stashing.exclusive = 0; 961 /* In muticore scenario stashing becomes a bottleneck on LS1046. 962 * So do not enable stashing in this case 963 */ 964 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 965 opts.fqd.context_a.stashing.annotation_cl = 966 DPAA_IF_RX_ANNOTATION_STASH; 967 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 968 opts.fqd.context_a.stashing.context_cl = 969 DPAA_IF_RX_CONTEXT_STASH; 970 971 /*Create a channel and associate given queue with the channel*/ 972 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 973 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 974 opts.fqd.dest.channel = rxq->ch_id; 975 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 976 flags = QMAN_INITFQ_FLAG_SCHED; 977 978 /* Configure tail drop */ 979 if (dpaa_intf->cgr_rx) { 980 opts.we_mask |= QM_INITFQ_WE_CGID; 981 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 982 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 983 } 984 ret = qman_init_fq(rxq, flags, &opts); 985 if (ret) { 986 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 987 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 988 return ret; 989 } 990 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 991 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 992 } else { 993 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 994 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 995 } 996 997 rxq->is_static = true; 998 999 /* Allocate qman specific portals */ 1000 qp = fsl_qman_fq_portal_create(&q_fd); 1001 if (!qp) { 1002 DPAA_PMD_ERR("Unable to alloc fq portal"); 1003 return -1; 1004 } 1005 rxq->qp = qp; 1006 1007 /* Set up the device interrupt handler */ 1008 if (!dev->intr_handle) { 1009 struct rte_dpaa_device *dpaa_dev; 1010 struct rte_device *rdev = dev->device; 1011 1012 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1013 device); 1014 dev->intr_handle = &dpaa_dev->intr_handle; 1015 dev->intr_handle->intr_vec = rte_zmalloc(NULL, 1016 dpaa_push_mode_max_queue, 0); 1017 if (!dev->intr_handle->intr_vec) { 1018 DPAA_PMD_ERR("intr_vec alloc failed"); 1019 return -ENOMEM; 1020 } 1021 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue; 1022 dev->intr_handle->max_intr = dpaa_push_mode_max_queue; 1023 } 1024 1025 dev->intr_handle->type = RTE_INTR_HANDLE_EXT; 1026 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1; 1027 dev->intr_handle->efds[queue_idx] = q_fd; 1028 rxq->q_fd = q_fd; 1029 } 1030 rxq->bp_array = rte_dpaa_bpid_info; 1031 dev->data->rx_queues[queue_idx] = rxq; 1032 1033 /* configure the CGR size as per the desc size */ 1034 if (dpaa_intf->cgr_rx) { 1035 struct qm_mcc_initcgr cgr_opts = {0}; 1036 1037 rxq->nb_desc = nb_desc; 1038 /* Enable tail drop with cgr on this queue */ 1039 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1040 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1041 if (ret) { 1042 DPAA_PMD_WARN( 1043 "rx taildrop modify fail on fqid %d (ret=%d)", 1044 rxq->fqid, ret); 1045 } 1046 } 1047 1048 return 0; 1049 } 1050 1051 int 1052 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1053 int eth_rx_queue_id, 1054 u16 ch_id, 1055 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1056 { 1057 int ret; 1058 u32 flags = 0; 1059 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1060 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1061 struct qm_mcc_initfq opts = {0}; 1062 1063 if (dpaa_push_mode_max_queue) 1064 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1065 "PUSH mode already enabled for first %d queues.\n" 1066 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1067 dpaa_push_mode_max_queue); 1068 1069 dpaa_poll_queue_default_config(&opts); 1070 1071 switch (queue_conf->ev.sched_type) { 1072 case RTE_SCHED_TYPE_ATOMIC: 1073 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1074 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1075 * configuration with HOLD_ACTIVE setting 1076 */ 1077 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1078 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1079 break; 1080 case RTE_SCHED_TYPE_ORDERED: 1081 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1082 return -1; 1083 default: 1084 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1085 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1086 break; 1087 } 1088 1089 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1090 opts.fqd.dest.channel = ch_id; 1091 opts.fqd.dest.wq = queue_conf->ev.priority; 1092 1093 if (dpaa_intf->cgr_rx) { 1094 opts.we_mask |= QM_INITFQ_WE_CGID; 1095 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1096 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1097 } 1098 1099 flags = QMAN_INITFQ_FLAG_SCHED; 1100 1101 ret = qman_init_fq(rxq, flags, &opts); 1102 if (ret) { 1103 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1104 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1105 return ret; 1106 } 1107 1108 /* copy configuration which needs to be filled during dequeue */ 1109 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1110 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1111 1112 return ret; 1113 } 1114 1115 int 1116 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1117 int eth_rx_queue_id) 1118 { 1119 struct qm_mcc_initfq opts; 1120 int ret; 1121 u32 flags = 0; 1122 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1123 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1124 1125 dpaa_poll_queue_default_config(&opts); 1126 1127 if (dpaa_intf->cgr_rx) { 1128 opts.we_mask |= QM_INITFQ_WE_CGID; 1129 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1130 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1131 } 1132 1133 ret = qman_init_fq(rxq, flags, &opts); 1134 if (ret) { 1135 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 1136 rxq->fqid, ret); 1137 } 1138 1139 rxq->cb.dqrr_dpdk_cb = NULL; 1140 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1141 1142 return 0; 1143 } 1144 1145 static 1146 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 1147 { 1148 PMD_INIT_FUNC_TRACE(); 1149 } 1150 1151 static 1152 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1153 uint16_t nb_desc __rte_unused, 1154 unsigned int socket_id __rte_unused, 1155 const struct rte_eth_txconf *tx_conf) 1156 { 1157 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1158 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1159 1160 PMD_INIT_FUNC_TRACE(); 1161 1162 /* Tx deferred start is not supported */ 1163 if (tx_conf->tx_deferred_start) { 1164 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1165 return -EINVAL; 1166 } 1167 txq->nb_desc = UINT16_MAX; 1168 txq->offloads = tx_conf->offloads; 1169 1170 if (queue_idx >= dev->data->nb_tx_queues) { 1171 rte_errno = EOVERFLOW; 1172 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1173 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1174 return -rte_errno; 1175 } 1176 1177 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1178 queue_idx, txq->fqid); 1179 dev->data->tx_queues[queue_idx] = txq; 1180 1181 return 0; 1182 } 1183 1184 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 1185 { 1186 PMD_INIT_FUNC_TRACE(); 1187 } 1188 1189 static uint32_t 1190 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1191 { 1192 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1193 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 1194 u32 frm_cnt = 0; 1195 1196 PMD_INIT_FUNC_TRACE(); 1197 1198 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1199 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u", 1200 rx_queue_id, frm_cnt); 1201 } 1202 return frm_cnt; 1203 } 1204 1205 static int dpaa_link_down(struct rte_eth_dev *dev) 1206 { 1207 struct fman_if *fif = dev->process_private; 1208 struct __fman_if *__fif; 1209 1210 PMD_INIT_FUNC_TRACE(); 1211 1212 __fif = container_of(fif, struct __fman_if, __if); 1213 1214 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1215 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN); 1216 else 1217 dpaa_eth_dev_stop(dev); 1218 return 0; 1219 } 1220 1221 static int dpaa_link_up(struct rte_eth_dev *dev) 1222 { 1223 struct fman_if *fif = dev->process_private; 1224 struct __fman_if *__fif; 1225 1226 PMD_INIT_FUNC_TRACE(); 1227 1228 __fif = container_of(fif, struct __fman_if, __if); 1229 1230 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1231 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP); 1232 else 1233 dpaa_eth_dev_start(dev); 1234 return 0; 1235 } 1236 1237 static int 1238 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1239 struct rte_eth_fc_conf *fc_conf) 1240 { 1241 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1242 struct rte_eth_fc_conf *net_fc; 1243 1244 PMD_INIT_FUNC_TRACE(); 1245 1246 if (!(dpaa_intf->fc_conf)) { 1247 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1248 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1249 if (!dpaa_intf->fc_conf) { 1250 DPAA_PMD_ERR("unable to save flow control info"); 1251 return -ENOMEM; 1252 } 1253 } 1254 net_fc = dpaa_intf->fc_conf; 1255 1256 if (fc_conf->high_water < fc_conf->low_water) { 1257 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1258 return -EINVAL; 1259 } 1260 1261 if (fc_conf->mode == RTE_FC_NONE) { 1262 return 0; 1263 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 1264 fc_conf->mode == RTE_FC_FULL) { 1265 fman_if_set_fc_threshold(dev->process_private, 1266 fc_conf->high_water, 1267 fc_conf->low_water, 1268 dpaa_intf->bp_info->bpid); 1269 if (fc_conf->pause_time) 1270 fman_if_set_fc_quanta(dev->process_private, 1271 fc_conf->pause_time); 1272 } 1273 1274 /* Save the information in dpaa device */ 1275 net_fc->pause_time = fc_conf->pause_time; 1276 net_fc->high_water = fc_conf->high_water; 1277 net_fc->low_water = fc_conf->low_water; 1278 net_fc->send_xon = fc_conf->send_xon; 1279 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1280 net_fc->mode = fc_conf->mode; 1281 net_fc->autoneg = fc_conf->autoneg; 1282 1283 return 0; 1284 } 1285 1286 static int 1287 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1288 struct rte_eth_fc_conf *fc_conf) 1289 { 1290 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1291 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1292 int ret; 1293 1294 PMD_INIT_FUNC_TRACE(); 1295 1296 if (net_fc) { 1297 fc_conf->pause_time = net_fc->pause_time; 1298 fc_conf->high_water = net_fc->high_water; 1299 fc_conf->low_water = net_fc->low_water; 1300 fc_conf->send_xon = net_fc->send_xon; 1301 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1302 fc_conf->mode = net_fc->mode; 1303 fc_conf->autoneg = net_fc->autoneg; 1304 return 0; 1305 } 1306 ret = fman_if_get_fc_threshold(dev->process_private); 1307 if (ret) { 1308 fc_conf->mode = RTE_FC_TX_PAUSE; 1309 fc_conf->pause_time = 1310 fman_if_get_fc_quanta(dev->process_private); 1311 } else { 1312 fc_conf->mode = RTE_FC_NONE; 1313 } 1314 1315 return 0; 1316 } 1317 1318 static int 1319 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1320 struct rte_ether_addr *addr, 1321 uint32_t index, 1322 __rte_unused uint32_t pool) 1323 { 1324 int ret; 1325 1326 PMD_INIT_FUNC_TRACE(); 1327 1328 ret = fman_if_add_mac_addr(dev->process_private, 1329 addr->addr_bytes, index); 1330 1331 if (ret) 1332 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1333 return 0; 1334 } 1335 1336 static void 1337 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1338 uint32_t index) 1339 { 1340 PMD_INIT_FUNC_TRACE(); 1341 1342 fman_if_clear_mac_addr(dev->process_private, index); 1343 } 1344 1345 static int 1346 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1347 struct rte_ether_addr *addr) 1348 { 1349 int ret; 1350 1351 PMD_INIT_FUNC_TRACE(); 1352 1353 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1354 if (ret) 1355 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1356 1357 return ret; 1358 } 1359 1360 static int 1361 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1362 struct rte_eth_rss_conf *rss_conf) 1363 { 1364 struct rte_eth_dev_data *data = dev->data; 1365 struct rte_eth_conf *eth_conf = &data->dev_conf; 1366 1367 PMD_INIT_FUNC_TRACE(); 1368 1369 if (!(default_q || fmc_q)) { 1370 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1371 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1372 return -1; 1373 } 1374 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1375 } else { 1376 DPAA_PMD_ERR("Function not supported\n"); 1377 return -ENOTSUP; 1378 } 1379 return 0; 1380 } 1381 1382 static int 1383 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1384 struct rte_eth_rss_conf *rss_conf) 1385 { 1386 struct rte_eth_dev_data *data = dev->data; 1387 struct rte_eth_conf *eth_conf = &data->dev_conf; 1388 1389 /* dpaa does not support rss_key, so length should be 0*/ 1390 rss_conf->rss_key_len = 0; 1391 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1392 return 0; 1393 } 1394 1395 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1396 uint16_t queue_id) 1397 { 1398 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1399 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1400 1401 if (!rxq->is_static) 1402 return -EINVAL; 1403 1404 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1405 } 1406 1407 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1408 uint16_t queue_id) 1409 { 1410 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1411 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1412 uint32_t temp; 1413 ssize_t temp1; 1414 1415 if (!rxq->is_static) 1416 return -EINVAL; 1417 1418 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1419 1420 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1421 if (temp1 != sizeof(temp)) 1422 DPAA_PMD_ERR("irq read error"); 1423 1424 qman_fq_portal_thread_irq(rxq->qp); 1425 1426 return 0; 1427 } 1428 1429 static void 1430 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1431 struct rte_eth_rxq_info *qinfo) 1432 { 1433 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1434 struct qman_fq *rxq; 1435 1436 rxq = dev->data->rx_queues[queue_id]; 1437 1438 qinfo->mp = dpaa_intf->bp_info->mp; 1439 qinfo->scattered_rx = dev->data->scattered_rx; 1440 qinfo->nb_desc = rxq->nb_desc; 1441 qinfo->conf.rx_free_thresh = 1; 1442 qinfo->conf.rx_drop_en = 1; 1443 qinfo->conf.rx_deferred_start = 0; 1444 qinfo->conf.offloads = rxq->offloads; 1445 } 1446 1447 static void 1448 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1449 struct rte_eth_txq_info *qinfo) 1450 { 1451 struct qman_fq *txq; 1452 1453 txq = dev->data->tx_queues[queue_id]; 1454 1455 qinfo->nb_desc = txq->nb_desc; 1456 qinfo->conf.tx_thresh.pthresh = 0; 1457 qinfo->conf.tx_thresh.hthresh = 0; 1458 qinfo->conf.tx_thresh.wthresh = 0; 1459 1460 qinfo->conf.tx_free_thresh = 0; 1461 qinfo->conf.tx_rs_thresh = 0; 1462 qinfo->conf.offloads = txq->offloads; 1463 qinfo->conf.tx_deferred_start = 0; 1464 } 1465 1466 static struct eth_dev_ops dpaa_devops = { 1467 .dev_configure = dpaa_eth_dev_configure, 1468 .dev_start = dpaa_eth_dev_start, 1469 .dev_stop = dpaa_eth_dev_stop, 1470 .dev_close = dpaa_eth_dev_close, 1471 .dev_infos_get = dpaa_eth_dev_info, 1472 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1473 1474 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1475 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1476 .rx_queue_release = dpaa_eth_rx_queue_release, 1477 .tx_queue_release = dpaa_eth_tx_queue_release, 1478 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1479 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1480 .rxq_info_get = dpaa_rxq_info_get, 1481 .txq_info_get = dpaa_txq_info_get, 1482 1483 .flow_ctrl_get = dpaa_flow_ctrl_get, 1484 .flow_ctrl_set = dpaa_flow_ctrl_set, 1485 1486 .link_update = dpaa_eth_link_update, 1487 .stats_get = dpaa_eth_stats_get, 1488 .xstats_get = dpaa_dev_xstats_get, 1489 .xstats_get_by_id = dpaa_xstats_get_by_id, 1490 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1491 .xstats_get_names = dpaa_xstats_get_names, 1492 .xstats_reset = dpaa_eth_stats_reset, 1493 .stats_reset = dpaa_eth_stats_reset, 1494 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1495 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1496 .allmulticast_enable = dpaa_eth_multicast_enable, 1497 .allmulticast_disable = dpaa_eth_multicast_disable, 1498 .mtu_set = dpaa_mtu_set, 1499 .dev_set_link_down = dpaa_link_down, 1500 .dev_set_link_up = dpaa_link_up, 1501 .mac_addr_add = dpaa_dev_add_mac_addr, 1502 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1503 .mac_addr_set = dpaa_dev_set_mac_addr, 1504 1505 .fw_version_get = dpaa_fw_version_get, 1506 1507 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1508 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1509 .rss_hash_update = dpaa_dev_rss_hash_update, 1510 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1511 }; 1512 1513 static bool 1514 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1515 { 1516 if (strcmp(dev->device->driver->name, 1517 drv->driver.name)) 1518 return false; 1519 1520 return true; 1521 } 1522 1523 static bool 1524 is_dpaa_supported(struct rte_eth_dev *dev) 1525 { 1526 return is_device_supported(dev, &rte_dpaa_pmd); 1527 } 1528 1529 int 1530 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1531 { 1532 struct rte_eth_dev *dev; 1533 1534 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1535 1536 dev = &rte_eth_devices[port]; 1537 1538 if (!is_dpaa_supported(dev)) 1539 return -ENOTSUP; 1540 1541 if (on) 1542 fman_if_loopback_enable(dev->process_private); 1543 else 1544 fman_if_loopback_disable(dev->process_private); 1545 1546 return 0; 1547 } 1548 1549 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1550 struct fman_if *fman_intf) 1551 { 1552 struct rte_eth_fc_conf *fc_conf; 1553 int ret; 1554 1555 PMD_INIT_FUNC_TRACE(); 1556 1557 if (!(dpaa_intf->fc_conf)) { 1558 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1559 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1560 if (!dpaa_intf->fc_conf) { 1561 DPAA_PMD_ERR("unable to save flow control info"); 1562 return -ENOMEM; 1563 } 1564 } 1565 fc_conf = dpaa_intf->fc_conf; 1566 ret = fman_if_get_fc_threshold(fman_intf); 1567 if (ret) { 1568 fc_conf->mode = RTE_FC_TX_PAUSE; 1569 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1570 } else { 1571 fc_conf->mode = RTE_FC_NONE; 1572 } 1573 1574 return 0; 1575 } 1576 1577 /* Initialise an Rx FQ */ 1578 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1579 uint32_t fqid) 1580 { 1581 struct qm_mcc_initfq opts = {0}; 1582 int ret; 1583 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1584 struct qm_mcc_initcgr cgr_opts = { 1585 .we_mask = QM_CGR_WE_CS_THRES | 1586 QM_CGR_WE_CSTD_EN | 1587 QM_CGR_WE_MODE, 1588 .cgr = { 1589 .cstd_en = QM_CGR_EN, 1590 .mode = QMAN_CGR_MODE_FRAME 1591 } 1592 }; 1593 1594 if (fmc_q || default_q) { 1595 ret = qman_reserve_fqid(fqid); 1596 if (ret) { 1597 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1598 fqid, ret); 1599 return -EINVAL; 1600 } 1601 } 1602 1603 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1604 ret = qman_create_fq(fqid, flags, fq); 1605 if (ret) { 1606 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1607 fqid, ret); 1608 return ret; 1609 } 1610 fq->is_static = false; 1611 1612 dpaa_poll_queue_default_config(&opts); 1613 1614 if (cgr_rx) { 1615 /* Enable tail drop with cgr on this queue */ 1616 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1617 cgr_rx->cb = NULL; 1618 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1619 &cgr_opts); 1620 if (ret) { 1621 DPAA_PMD_WARN( 1622 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1623 fq->fqid, ret); 1624 goto without_cgr; 1625 } 1626 opts.we_mask |= QM_INITFQ_WE_CGID; 1627 opts.fqd.cgid = cgr_rx->cgrid; 1628 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1629 } 1630 without_cgr: 1631 ret = qman_init_fq(fq, 0, &opts); 1632 if (ret) 1633 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1634 return ret; 1635 } 1636 1637 /* Initialise a Tx FQ */ 1638 static int dpaa_tx_queue_init(struct qman_fq *fq, 1639 struct fman_if *fman_intf, 1640 struct qman_cgr *cgr_tx) 1641 { 1642 struct qm_mcc_initfq opts = {0}; 1643 struct qm_mcc_initcgr cgr_opts = { 1644 .we_mask = QM_CGR_WE_CS_THRES | 1645 QM_CGR_WE_CSTD_EN | 1646 QM_CGR_WE_MODE, 1647 .cgr = { 1648 .cstd_en = QM_CGR_EN, 1649 .mode = QMAN_CGR_MODE_FRAME 1650 } 1651 }; 1652 int ret; 1653 1654 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1655 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1656 if (ret) { 1657 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1658 return ret; 1659 } 1660 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1661 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1662 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1663 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1664 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1665 opts.fqd.context_b = 0; 1666 /* no tx-confirmation */ 1667 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1668 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1669 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1670 1671 if (cgr_tx) { 1672 /* Enable tail drop with cgr on this queue */ 1673 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1674 td_tx_threshold, 0); 1675 cgr_tx->cb = NULL; 1676 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1677 &cgr_opts); 1678 if (ret) { 1679 DPAA_PMD_WARN( 1680 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1681 fq->fqid, ret); 1682 goto without_cgr; 1683 } 1684 opts.we_mask |= QM_INITFQ_WE_CGID; 1685 opts.fqd.cgid = cgr_tx->cgrid; 1686 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1687 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1688 td_tx_threshold); 1689 } 1690 without_cgr: 1691 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1692 if (ret) 1693 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1694 return ret; 1695 } 1696 1697 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1698 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1699 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1700 { 1701 struct qm_mcc_initfq opts = {0}; 1702 int ret; 1703 1704 PMD_INIT_FUNC_TRACE(); 1705 1706 ret = qman_reserve_fqid(fqid); 1707 if (ret) { 1708 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1709 fqid, ret); 1710 return -EINVAL; 1711 } 1712 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1713 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1714 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1715 if (ret) { 1716 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1717 fqid, ret); 1718 return ret; 1719 } 1720 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1721 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1722 ret = qman_init_fq(fq, 0, &opts); 1723 if (ret) 1724 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1725 fqid, ret); 1726 return ret; 1727 } 1728 #endif 1729 1730 /* Initialise a network interface */ 1731 static int 1732 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1733 { 1734 struct rte_dpaa_device *dpaa_device; 1735 struct fm_eth_port_cfg *cfg; 1736 struct dpaa_if *dpaa_intf; 1737 struct fman_if *fman_intf; 1738 int dev_id; 1739 1740 PMD_INIT_FUNC_TRACE(); 1741 1742 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1743 dev_id = dpaa_device->id.dev_id; 1744 cfg = dpaa_get_eth_port_cfg(dev_id); 1745 fman_intf = cfg->fman_if; 1746 eth_dev->process_private = fman_intf; 1747 1748 /* Plugging of UCODE burst API not supported in Secondary */ 1749 dpaa_intf = eth_dev->data->dev_private; 1750 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1751 if (dpaa_intf->cgr_tx) 1752 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1753 else 1754 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1755 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1756 qman_set_fq_lookup_table( 1757 dpaa_intf->rx_queues->qman_fq_lookup_table); 1758 #endif 1759 1760 return 0; 1761 } 1762 1763 /* Initialise a network interface */ 1764 static int 1765 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1766 { 1767 int num_rx_fqs, fqid; 1768 int loop, ret = 0; 1769 int dev_id; 1770 struct rte_dpaa_device *dpaa_device; 1771 struct dpaa_if *dpaa_intf; 1772 struct fm_eth_port_cfg *cfg; 1773 struct fman_if *fman_intf; 1774 struct fman_if_bpool *bp, *tmp_bp; 1775 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1776 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1777 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1778 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1779 int8_t vsp_id = -1; 1780 1781 PMD_INIT_FUNC_TRACE(); 1782 1783 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1784 dev_id = dpaa_device->id.dev_id; 1785 dpaa_intf = eth_dev->data->dev_private; 1786 cfg = dpaa_get_eth_port_cfg(dev_id); 1787 fman_intf = cfg->fman_if; 1788 1789 dpaa_intf->name = dpaa_device->name; 1790 1791 /* save fman_if & cfg in the interface struture */ 1792 eth_dev->process_private = fman_intf; 1793 dpaa_intf->ifid = dev_id; 1794 dpaa_intf->cfg = cfg; 1795 1796 memset((char *)dev_rx_fqids, 0, 1797 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1798 1799 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1800 1801 /* Initialize Rx FQ's */ 1802 if (default_q) { 1803 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1804 } else if (fmc_q) { 1805 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1806 dev_vspids, 1807 DPAA_MAX_NUM_PCD_QUEUES); 1808 if (num_rx_fqs < 0) { 1809 DPAA_PMD_ERR("%s FMC initializes failed!", 1810 dpaa_intf->name); 1811 goto free_rx; 1812 } 1813 if (!num_rx_fqs) { 1814 DPAA_PMD_WARN("%s is not configured by FMC.", 1815 dpaa_intf->name); 1816 } 1817 } else { 1818 /* FMCLESS mode, load balance to multiple cores.*/ 1819 num_rx_fqs = rte_lcore_count(); 1820 } 1821 1822 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1823 * queues. 1824 */ 1825 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1826 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1827 return -EINVAL; 1828 } 1829 1830 if (num_rx_fqs > 0) { 1831 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1832 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1833 if (!dpaa_intf->rx_queues) { 1834 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1835 return -ENOMEM; 1836 } 1837 } else { 1838 dpaa_intf->rx_queues = NULL; 1839 } 1840 1841 memset(cgrid, 0, sizeof(cgrid)); 1842 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1843 1844 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1845 * Tx tail drop is disabled. 1846 */ 1847 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1848 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1849 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1850 td_tx_threshold); 1851 /* if a very large value is being configured */ 1852 if (td_tx_threshold > UINT16_MAX) 1853 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1854 } 1855 1856 /* If congestion control is enabled globally*/ 1857 if (num_rx_fqs > 0 && td_threshold) { 1858 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1859 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1860 if (!dpaa_intf->cgr_rx) { 1861 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1862 ret = -ENOMEM; 1863 goto free_rx; 1864 } 1865 1866 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1867 if (ret != num_rx_fqs) { 1868 DPAA_PMD_WARN("insufficient CGRIDs available"); 1869 ret = -EINVAL; 1870 goto free_rx; 1871 } 1872 } else { 1873 dpaa_intf->cgr_rx = NULL; 1874 } 1875 1876 if (!fmc_q && !default_q) { 1877 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1878 num_rx_fqs, 0); 1879 if (ret < 0) { 1880 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1881 goto free_rx; 1882 } 1883 } 1884 1885 for (loop = 0; loop < num_rx_fqs; loop++) { 1886 if (default_q) 1887 fqid = cfg->rx_def; 1888 else 1889 fqid = dev_rx_fqids[loop]; 1890 1891 vsp_id = dev_vspids[loop]; 1892 1893 if (dpaa_intf->cgr_rx) 1894 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1895 1896 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1897 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1898 fqid); 1899 if (ret) 1900 goto free_rx; 1901 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 1902 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1903 } 1904 dpaa_intf->nb_rx_queues = num_rx_fqs; 1905 1906 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1907 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1908 MAX_DPAA_CORES, MAX_CACHELINE); 1909 if (!dpaa_intf->tx_queues) { 1910 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1911 ret = -ENOMEM; 1912 goto free_rx; 1913 } 1914 1915 /* If congestion control is enabled globally*/ 1916 if (td_tx_threshold) { 1917 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 1918 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 1919 MAX_CACHELINE); 1920 if (!dpaa_intf->cgr_tx) { 1921 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 1922 ret = -ENOMEM; 1923 goto free_rx; 1924 } 1925 1926 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 1927 1, 0); 1928 if (ret != MAX_DPAA_CORES) { 1929 DPAA_PMD_WARN("insufficient CGRIDs available"); 1930 ret = -EINVAL; 1931 goto free_rx; 1932 } 1933 } else { 1934 dpaa_intf->cgr_tx = NULL; 1935 } 1936 1937 1938 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 1939 if (dpaa_intf->cgr_tx) 1940 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 1941 1942 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1943 fman_intf, 1944 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 1945 if (ret) 1946 goto free_tx; 1947 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1948 } 1949 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 1950 1951 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1952 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1953 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1954 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1955 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1956 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1957 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1958 #endif 1959 1960 DPAA_PMD_DEBUG("All frame queues created"); 1961 1962 /* Get the initial configuration for flow control */ 1963 dpaa_fc_set_default(dpaa_intf, fman_intf); 1964 1965 /* reset bpool list, initialize bpool dynamically */ 1966 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1967 list_del(&bp->node); 1968 rte_free(bp); 1969 } 1970 1971 /* Populate ethdev structure */ 1972 eth_dev->dev_ops = &dpaa_devops; 1973 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 1974 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1975 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1976 1977 /* Allocate memory for storing MAC addresses */ 1978 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1979 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1980 if (eth_dev->data->mac_addrs == NULL) { 1981 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1982 "store MAC addresses", 1983 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1984 ret = -ENOMEM; 1985 goto free_tx; 1986 } 1987 1988 /* copy the primary mac address */ 1989 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1990 1991 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1992 dpaa_device->name, 1993 fman_intf->mac_addr.addr_bytes[0], 1994 fman_intf->mac_addr.addr_bytes[1], 1995 fman_intf->mac_addr.addr_bytes[2], 1996 fman_intf->mac_addr.addr_bytes[3], 1997 fman_intf->mac_addr.addr_bytes[4], 1998 fman_intf->mac_addr.addr_bytes[5]); 1999 2000 if (!fman_intf->is_shared_mac) { 2001 /* Disable RX mode */ 2002 fman_if_discard_rx_errors(fman_intf); 2003 fman_if_disable_rx(fman_intf); 2004 /* Disable promiscuous mode */ 2005 fman_if_promiscuous_disable(fman_intf); 2006 /* Disable multicast */ 2007 fman_if_reset_mcast_filter_table(fman_intf); 2008 /* Reset interface statistics */ 2009 fman_if_stats_reset(fman_intf); 2010 /* Disable SG by default */ 2011 fman_if_set_sg(fman_intf, 0); 2012 fman_if_set_maxfrm(fman_intf, 2013 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2014 } 2015 2016 return 0; 2017 2018 free_tx: 2019 rte_free(dpaa_intf->tx_queues); 2020 dpaa_intf->tx_queues = NULL; 2021 dpaa_intf->nb_tx_queues = 0; 2022 2023 free_rx: 2024 rte_free(dpaa_intf->cgr_rx); 2025 rte_free(dpaa_intf->cgr_tx); 2026 rte_free(dpaa_intf->rx_queues); 2027 dpaa_intf->rx_queues = NULL; 2028 dpaa_intf->nb_rx_queues = 0; 2029 return ret; 2030 } 2031 2032 static int 2033 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2034 struct rte_dpaa_device *dpaa_dev) 2035 { 2036 int diag; 2037 int ret; 2038 struct rte_eth_dev *eth_dev; 2039 2040 PMD_INIT_FUNC_TRACE(); 2041 2042 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2043 RTE_PKTMBUF_HEADROOM) { 2044 DPAA_PMD_ERR( 2045 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2046 RTE_PKTMBUF_HEADROOM, 2047 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2048 2049 return -1; 2050 } 2051 2052 /* In case of secondary process, the device is already configured 2053 * and no further action is required, except portal initialization 2054 * and verifying secondary attachment to port name. 2055 */ 2056 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2057 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2058 if (!eth_dev) 2059 return -ENOMEM; 2060 eth_dev->device = &dpaa_dev->device; 2061 eth_dev->dev_ops = &dpaa_devops; 2062 2063 ret = dpaa_dev_init_secondary(eth_dev); 2064 if (ret != 0) { 2065 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 2066 return ret; 2067 } 2068 2069 rte_eth_dev_probing_finish(eth_dev); 2070 return 0; 2071 } 2072 2073 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2074 if (access("/tmp/fmc.bin", F_OK) == -1) { 2075 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2076 default_q = 1; 2077 } 2078 2079 if (!(default_q || fmc_q)) { 2080 if (dpaa_fm_init()) { 2081 DPAA_PMD_ERR("FM init failed\n"); 2082 return -1; 2083 } 2084 } 2085 2086 /* disabling the default push mode for LS1043 */ 2087 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2088 dpaa_push_mode_max_queue = 0; 2089 2090 /* if push mode queues to be enabled. Currenly we are allowing 2091 * only one queue per thread. 2092 */ 2093 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2094 dpaa_push_mode_max_queue = 2095 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2096 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2097 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2098 } 2099 2100 is_global_init = 1; 2101 } 2102 2103 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2104 ret = rte_dpaa_portal_init((void *)1); 2105 if (ret) { 2106 DPAA_PMD_ERR("Unable to initialize portal"); 2107 return ret; 2108 } 2109 } 2110 2111 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2112 if (!eth_dev) 2113 return -ENOMEM; 2114 2115 eth_dev->data->dev_private = 2116 rte_zmalloc("ethdev private structure", 2117 sizeof(struct dpaa_if), 2118 RTE_CACHE_LINE_SIZE); 2119 if (!eth_dev->data->dev_private) { 2120 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2121 rte_eth_dev_release_port(eth_dev); 2122 return -ENOMEM; 2123 } 2124 2125 eth_dev->device = &dpaa_dev->device; 2126 dpaa_dev->eth_dev = eth_dev; 2127 2128 qman_ern_register_cb(dpaa_free_mbuf); 2129 2130 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2131 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2132 2133 /* Invoke PMD device initialization function */ 2134 diag = dpaa_dev_init(eth_dev); 2135 if (diag == 0) { 2136 rte_eth_dev_probing_finish(eth_dev); 2137 return 0; 2138 } 2139 2140 rte_eth_dev_release_port(eth_dev); 2141 return diag; 2142 } 2143 2144 static int 2145 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2146 { 2147 struct rte_eth_dev *eth_dev; 2148 int ret; 2149 2150 PMD_INIT_FUNC_TRACE(); 2151 2152 eth_dev = dpaa_dev->eth_dev; 2153 dpaa_eth_dev_close(eth_dev); 2154 ret = rte_eth_dev_release_port(eth_dev); 2155 2156 return ret; 2157 } 2158 2159 static void __attribute__((destructor(102))) dpaa_finish(void) 2160 { 2161 /* For secondary, primary will do all the cleanup */ 2162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2163 return; 2164 2165 if (!(default_q || fmc_q)) { 2166 unsigned int i; 2167 2168 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2169 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2170 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2171 struct dpaa_if *dpaa_intf = 2172 dev->data->dev_private; 2173 struct fman_if *fif = 2174 dev->process_private; 2175 if (dpaa_intf->port_handle) 2176 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2177 DPAA_PMD_WARN("DPAA FM " 2178 "deconfig failed\n"); 2179 if (fif->num_profiles) { 2180 if (dpaa_port_vsp_cleanup(dpaa_intf, 2181 fif)) 2182 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2183 } 2184 } 2185 } 2186 if (is_global_init) 2187 if (dpaa_fm_term()) 2188 DPAA_PMD_WARN("DPAA FM term failed\n"); 2189 2190 is_global_init = 0; 2191 2192 DPAA_PMD_INFO("DPAA fman cleaned up"); 2193 } 2194 } 2195 2196 static struct rte_dpaa_driver rte_dpaa_pmd = { 2197 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2198 .drv_type = FSL_DPAA_ETH, 2199 .probe = rte_dpaa_probe, 2200 .remove = rte_dpaa_remove, 2201 }; 2202 2203 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2204 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE); 2205