1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 RTE_ETH_RX_OFFLOAD_SCATTER; 58 59 /* Rx offloads which cannot be disabled */ 60 static uint64_t dev_rx_offloads_nodis = 61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_RSS_HASH; 66 67 /* Supported Tx offloads */ 68 static uint64_t dev_tx_offloads_sup = 69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 71 72 /* Tx offloads which cannot be disabled */ 73 static uint64_t dev_tx_offloads_nodis = 74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 80 81 /* Keep track of whether QMAN and BMAN have been globally initialized */ 82 static int is_global_init; 83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 84 static int default_q; /* use default queue - FMC is not executed*/ 85 /* At present we only allow up to 4 push mode queues as default - as each of 86 * this queue need dedicated portal and we are short of portals. 87 */ 88 #define DPAA_MAX_PUSH_MODE_QUEUE 8 89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 90 91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 93 94 95 /* Per RX FQ Taildrop in frame count */ 96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 97 98 /* Per TX FQ Taildrop in frame count, disabled by default */ 99 static unsigned int td_tx_threshold; 100 101 struct rte_dpaa_xstats_name_off { 102 char name[RTE_ETH_XSTATS_NAME_SIZE]; 103 uint32_t offset; 104 }; 105 106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 107 {"rx_align_err", 108 offsetof(struct dpaa_if_stats, raln)}, 109 {"rx_valid_pause", 110 offsetof(struct dpaa_if_stats, rxpf)}, 111 {"rx_fcs_err", 112 offsetof(struct dpaa_if_stats, rfcs)}, 113 {"rx_vlan_frame", 114 offsetof(struct dpaa_if_stats, rvlan)}, 115 {"rx_frame_err", 116 offsetof(struct dpaa_if_stats, rerr)}, 117 {"rx_drop_err", 118 offsetof(struct dpaa_if_stats, rdrp)}, 119 {"rx_undersized", 120 offsetof(struct dpaa_if_stats, rund)}, 121 {"rx_oversize_err", 122 offsetof(struct dpaa_if_stats, rovr)}, 123 {"rx_fragment_pkt", 124 offsetof(struct dpaa_if_stats, rfrg)}, 125 {"tx_valid_pause", 126 offsetof(struct dpaa_if_stats, txpf)}, 127 {"tx_fcs_err", 128 offsetof(struct dpaa_if_stats, terr)}, 129 {"tx_vlan_frame", 130 offsetof(struct dpaa_if_stats, tvlan)}, 131 {"rx_undersized", 132 offsetof(struct dpaa_if_stats, tund)}, 133 }; 134 135 static struct rte_dpaa_driver rte_dpaa_pmd; 136 137 static int 138 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 139 140 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 141 int wait_to_complete __rte_unused); 142 143 static void dpaa_interrupt_handler(void *param); 144 145 static inline void 146 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 147 { 148 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 149 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 150 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 151 QM_FQCTRL_PREFERINCACHE; 152 opts->fqd.context_a.stashing.exclusive = 0; 153 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 154 opts->fqd.context_a.stashing.annotation_cl = 155 DPAA_IF_RX_ANNOTATION_STASH; 156 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 157 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 158 } 159 160 static int 161 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 162 { 163 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 164 + VLAN_TAG_SIZE; 165 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 166 167 PMD_INIT_FUNC_TRACE(); 168 169 /* 170 * Refuse mtu that requires the support of scattered packets 171 * when this feature has not been enabled before. 172 */ 173 if (dev->data->min_rx_buf_size && 174 !dev->data->scattered_rx && frame_size > buffsz) { 175 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 176 return -EINVAL; 177 } 178 179 /* check <seg size> * <max_seg> >= max_frame */ 180 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 181 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 182 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 183 buffsz * DPAA_SGT_MAX_ENTRIES); 184 return -EINVAL; 185 } 186 187 fman_if_set_maxfrm(dev->process_private, frame_size); 188 189 return 0; 190 } 191 192 static int 193 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 194 { 195 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 196 uint64_t rx_offloads = eth_conf->rxmode.offloads; 197 uint64_t tx_offloads = eth_conf->txmode.offloads; 198 struct rte_device *rdev = dev->device; 199 struct rte_eth_link *link = &dev->data->dev_link; 200 struct rte_dpaa_device *dpaa_dev; 201 struct fman_if *fif = dev->process_private; 202 struct __fman_if *__fif; 203 struct rte_intr_handle *intr_handle; 204 uint32_t max_rx_pktlen; 205 int speed, duplex; 206 int ret; 207 208 PMD_INIT_FUNC_TRACE(); 209 210 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 211 intr_handle = &dpaa_dev->intr_handle; 212 __fif = container_of(fif, struct __fman_if, __if); 213 214 /* Rx offloads which are enabled by default */ 215 if (dev_rx_offloads_nodis & ~rx_offloads) { 216 DPAA_PMD_INFO( 217 "Some of rx offloads enabled by default - requested 0x%" PRIx64 218 " fixed are 0x%" PRIx64, 219 rx_offloads, dev_rx_offloads_nodis); 220 } 221 222 /* Tx offloads which are enabled by default */ 223 if (dev_tx_offloads_nodis & ~tx_offloads) { 224 DPAA_PMD_INFO( 225 "Some of tx offloads enabled by default - requested 0x%" PRIx64 226 " fixed are 0x%" PRIx64, 227 tx_offloads, dev_tx_offloads_nodis); 228 } 229 230 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 231 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 232 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 233 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 234 "supported is %d", 235 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 236 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 237 } 238 239 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 240 241 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 242 DPAA_PMD_DEBUG("enabling scatter mode"); 243 fman_if_set_sg(dev->process_private, 1); 244 dev->data->scattered_rx = 1; 245 } 246 247 if (!(default_q || fmc_q)) { 248 if (dpaa_fm_config(dev, 249 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 250 dpaa_write_fm_config_to_file(); 251 DPAA_PMD_ERR("FM port configuration: Failed\n"); 252 return -1; 253 } 254 dpaa_write_fm_config_to_file(); 255 } 256 257 /* if the interrupts were configured on this devices*/ 258 if (intr_handle && intr_handle->fd) { 259 if (dev->data->dev_conf.intr_conf.lsc != 0) 260 rte_intr_callback_register(intr_handle, 261 dpaa_interrupt_handler, 262 (void *)dev); 263 264 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd); 265 if (ret) { 266 if (dev->data->dev_conf.intr_conf.lsc != 0) { 267 rte_intr_callback_unregister(intr_handle, 268 dpaa_interrupt_handler, 269 (void *)dev); 270 if (ret == EINVAL) 271 printf("Failed to enable interrupt: Not Supported\n"); 272 else 273 printf("Failed to enable interrupt\n"); 274 } 275 dev->data->dev_conf.intr_conf.lsc = 0; 276 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 277 } 278 } 279 280 /* Wait for link status to get updated */ 281 if (!link->link_status) 282 sleep(1); 283 284 /* Configure link only if link is UP*/ 285 if (link->link_status) { 286 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 287 /* Start autoneg only if link is not in autoneg mode */ 288 if (!link->link_autoneg) 289 dpaa_restart_link_autoneg(__fif->node_name); 290 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 291 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 292 case RTE_ETH_LINK_SPEED_10M_HD: 293 speed = RTE_ETH_SPEED_NUM_10M; 294 duplex = RTE_ETH_LINK_HALF_DUPLEX; 295 break; 296 case RTE_ETH_LINK_SPEED_10M: 297 speed = RTE_ETH_SPEED_NUM_10M; 298 duplex = RTE_ETH_LINK_FULL_DUPLEX; 299 break; 300 case RTE_ETH_LINK_SPEED_100M_HD: 301 speed = RTE_ETH_SPEED_NUM_100M; 302 duplex = RTE_ETH_LINK_HALF_DUPLEX; 303 break; 304 case RTE_ETH_LINK_SPEED_100M: 305 speed = RTE_ETH_SPEED_NUM_100M; 306 duplex = RTE_ETH_LINK_FULL_DUPLEX; 307 break; 308 case RTE_ETH_LINK_SPEED_1G: 309 speed = RTE_ETH_SPEED_NUM_1G; 310 duplex = RTE_ETH_LINK_FULL_DUPLEX; 311 break; 312 case RTE_ETH_LINK_SPEED_2_5G: 313 speed = RTE_ETH_SPEED_NUM_2_5G; 314 duplex = RTE_ETH_LINK_FULL_DUPLEX; 315 break; 316 case RTE_ETH_LINK_SPEED_10G: 317 speed = RTE_ETH_SPEED_NUM_10G; 318 duplex = RTE_ETH_LINK_FULL_DUPLEX; 319 break; 320 default: 321 speed = RTE_ETH_SPEED_NUM_NONE; 322 duplex = RTE_ETH_LINK_FULL_DUPLEX; 323 break; 324 } 325 /* Set link speed */ 326 dpaa_update_link_speed(__fif->node_name, speed, duplex); 327 } else { 328 /* Manual autoneg - custom advertisement speed. */ 329 printf("Custom Advertisement speeds not supported\n"); 330 } 331 } 332 333 return 0; 334 } 335 336 static const uint32_t * 337 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 338 { 339 static const uint32_t ptypes[] = { 340 RTE_PTYPE_L2_ETHER, 341 RTE_PTYPE_L2_ETHER_VLAN, 342 RTE_PTYPE_L2_ETHER_ARP, 343 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 344 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 345 RTE_PTYPE_L4_ICMP, 346 RTE_PTYPE_L4_TCP, 347 RTE_PTYPE_L4_UDP, 348 RTE_PTYPE_L4_FRAG, 349 RTE_PTYPE_L4_TCP, 350 RTE_PTYPE_L4_UDP, 351 RTE_PTYPE_L4_SCTP 352 }; 353 354 PMD_INIT_FUNC_TRACE(); 355 356 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 357 return ptypes; 358 return NULL; 359 } 360 361 static void dpaa_interrupt_handler(void *param) 362 { 363 struct rte_eth_dev *dev = param; 364 struct rte_device *rdev = dev->device; 365 struct rte_dpaa_device *dpaa_dev; 366 struct rte_intr_handle *intr_handle; 367 uint64_t buf; 368 int bytes_read; 369 370 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 371 intr_handle = &dpaa_dev->intr_handle; 372 373 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t)); 374 if (bytes_read < 0) 375 DPAA_PMD_ERR("Error reading eventfd\n"); 376 dpaa_eth_link_update(dev, 0); 377 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 378 } 379 380 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 381 { 382 struct dpaa_if *dpaa_intf = dev->data->dev_private; 383 384 PMD_INIT_FUNC_TRACE(); 385 386 if (!(default_q || fmc_q)) 387 dpaa_write_fm_config_to_file(); 388 389 /* Change tx callback to the real one */ 390 if (dpaa_intf->cgr_tx) 391 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 392 else 393 dev->tx_pkt_burst = dpaa_eth_queue_tx; 394 395 fman_if_enable_rx(dev->process_private); 396 397 return 0; 398 } 399 400 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 401 { 402 struct fman_if *fif = dev->process_private; 403 404 PMD_INIT_FUNC_TRACE(); 405 dev->data->dev_started = 0; 406 407 if (!fif->is_shared_mac) 408 fman_if_disable_rx(fif); 409 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 410 411 return 0; 412 } 413 414 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 415 { 416 struct fman_if *fif = dev->process_private; 417 struct __fman_if *__fif; 418 struct rte_device *rdev = dev->device; 419 struct rte_dpaa_device *dpaa_dev; 420 struct rte_intr_handle *intr_handle; 421 struct rte_eth_link *link = &dev->data->dev_link; 422 struct dpaa_if *dpaa_intf = dev->data->dev_private; 423 int loop; 424 int ret; 425 426 PMD_INIT_FUNC_TRACE(); 427 428 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 429 return 0; 430 431 if (!dpaa_intf) { 432 DPAA_PMD_WARN("Already closed or not started"); 433 return -1; 434 } 435 436 /* DPAA FM deconfig */ 437 if (!(default_q || fmc_q)) { 438 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 439 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 440 } 441 442 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 443 intr_handle = &dpaa_dev->intr_handle; 444 __fif = container_of(fif, struct __fman_if, __if); 445 446 ret = dpaa_eth_dev_stop(dev); 447 448 /* Reset link to autoneg */ 449 if (link->link_status && !link->link_autoneg) 450 dpaa_restart_link_autoneg(__fif->node_name); 451 452 if (intr_handle && intr_handle->fd && 453 dev->data->dev_conf.intr_conf.lsc != 0) { 454 dpaa_intr_disable(__fif->node_name); 455 rte_intr_callback_unregister(intr_handle, 456 dpaa_interrupt_handler, 457 (void *)dev); 458 } 459 460 /* release configuration memory */ 461 if (dpaa_intf->fc_conf) 462 rte_free(dpaa_intf->fc_conf); 463 464 /* Release RX congestion Groups */ 465 if (dpaa_intf->cgr_rx) { 466 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 467 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 468 } 469 470 rte_free(dpaa_intf->cgr_rx); 471 dpaa_intf->cgr_rx = NULL; 472 /* Release TX congestion Groups */ 473 if (dpaa_intf->cgr_tx) { 474 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 475 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 476 rte_free(dpaa_intf->cgr_tx); 477 dpaa_intf->cgr_tx = NULL; 478 } 479 480 rte_free(dpaa_intf->rx_queues); 481 dpaa_intf->rx_queues = NULL; 482 483 rte_free(dpaa_intf->tx_queues); 484 dpaa_intf->tx_queues = NULL; 485 486 return ret; 487 } 488 489 static int 490 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 491 char *fw_version, 492 size_t fw_size) 493 { 494 int ret; 495 FILE *svr_file = NULL; 496 unsigned int svr_ver = 0; 497 498 PMD_INIT_FUNC_TRACE(); 499 500 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 501 if (!svr_file) { 502 DPAA_PMD_ERR("Unable to open SoC device"); 503 return -ENOTSUP; /* Not supported on this infra */ 504 } 505 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 506 dpaa_svr_family = svr_ver & SVR_MASK; 507 else 508 DPAA_PMD_ERR("Unable to read SoC device"); 509 510 fclose(svr_file); 511 512 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 513 svr_ver, fman_ip_rev); 514 if (ret < 0) 515 return -EINVAL; 516 517 ret += 1; /* add the size of '\0' */ 518 if (fw_size < (size_t)ret) 519 return ret; 520 else 521 return 0; 522 } 523 524 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 525 struct rte_eth_dev_info *dev_info) 526 { 527 struct dpaa_if *dpaa_intf = dev->data->dev_private; 528 struct fman_if *fif = dev->process_private; 529 530 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 531 532 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 533 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 534 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 535 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 536 dev_info->max_hash_mac_addrs = 0; 537 dev_info->max_vfs = 0; 538 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 539 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 540 541 if (fif->mac_type == fman_mac_1g) { 542 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 543 | RTE_ETH_LINK_SPEED_10M 544 | RTE_ETH_LINK_SPEED_100M_HD 545 | RTE_ETH_LINK_SPEED_100M 546 | RTE_ETH_LINK_SPEED_1G; 547 } else if (fif->mac_type == fman_mac_2_5g) { 548 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 549 | RTE_ETH_LINK_SPEED_10M 550 | RTE_ETH_LINK_SPEED_100M_HD 551 | RTE_ETH_LINK_SPEED_100M 552 | RTE_ETH_LINK_SPEED_1G 553 | RTE_ETH_LINK_SPEED_2_5G; 554 } else if (fif->mac_type == fman_mac_10g) { 555 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 556 | RTE_ETH_LINK_SPEED_10M 557 | RTE_ETH_LINK_SPEED_100M_HD 558 | RTE_ETH_LINK_SPEED_100M 559 | RTE_ETH_LINK_SPEED_1G 560 | RTE_ETH_LINK_SPEED_2_5G 561 | RTE_ETH_LINK_SPEED_10G; 562 } else { 563 DPAA_PMD_ERR("invalid link_speed: %s, %d", 564 dpaa_intf->name, fif->mac_type); 565 return -EINVAL; 566 } 567 568 dev_info->rx_offload_capa = dev_rx_offloads_sup | 569 dev_rx_offloads_nodis; 570 dev_info->tx_offload_capa = dev_tx_offloads_sup | 571 dev_tx_offloads_nodis; 572 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 573 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 574 dev_info->default_rxportconf.nb_queues = 1; 575 dev_info->default_txportconf.nb_queues = 1; 576 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 577 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 578 579 return 0; 580 } 581 582 static int 583 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 584 __rte_unused uint16_t queue_id, 585 struct rte_eth_burst_mode *mode) 586 { 587 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 588 int ret = -EINVAL; 589 unsigned int i; 590 const struct burst_info { 591 uint64_t flags; 592 const char *output; 593 } rx_offload_map[] = { 594 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 595 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 596 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 597 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 598 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 599 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 600 }; 601 602 /* Update Rx offload info */ 603 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 604 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 605 snprintf(mode->info, sizeof(mode->info), "%s", 606 rx_offload_map[i].output); 607 ret = 0; 608 break; 609 } 610 } 611 return ret; 612 } 613 614 static int 615 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 616 __rte_unused uint16_t queue_id, 617 struct rte_eth_burst_mode *mode) 618 { 619 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 620 int ret = -EINVAL; 621 unsigned int i; 622 const struct burst_info { 623 uint64_t flags; 624 const char *output; 625 } tx_offload_map[] = { 626 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 627 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 628 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 629 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 630 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 631 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 632 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 633 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 634 }; 635 636 /* Update Tx offload info */ 637 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 638 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 639 snprintf(mode->info, sizeof(mode->info), "%s", 640 tx_offload_map[i].output); 641 ret = 0; 642 break; 643 } 644 } 645 return ret; 646 } 647 648 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 649 int wait_to_complete) 650 { 651 struct dpaa_if *dpaa_intf = dev->data->dev_private; 652 struct rte_eth_link *link = &dev->data->dev_link; 653 struct fman_if *fif = dev->process_private; 654 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 655 int ret, ioctl_version; 656 uint8_t count; 657 658 PMD_INIT_FUNC_TRACE(); 659 660 ioctl_version = dpaa_get_ioctl_version_number(); 661 662 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 663 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 664 ret = dpaa_get_link_status(__fif->node_name, link); 665 if (ret) 666 return ret; 667 if (link->link_status == RTE_ETH_LINK_DOWN && 668 wait_to_complete) 669 rte_delay_ms(CHECK_INTERVAL); 670 else 671 break; 672 } 673 } else { 674 link->link_status = dpaa_intf->valid; 675 } 676 677 if (ioctl_version < 2) { 678 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 679 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 680 681 if (fif->mac_type == fman_mac_1g) 682 link->link_speed = RTE_ETH_SPEED_NUM_1G; 683 else if (fif->mac_type == fman_mac_2_5g) 684 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 685 else if (fif->mac_type == fman_mac_10g) 686 link->link_speed = RTE_ETH_SPEED_NUM_10G; 687 else 688 DPAA_PMD_ERR("invalid link_speed: %s, %d", 689 dpaa_intf->name, fif->mac_type); 690 } 691 692 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 693 link->link_status ? "Up" : "Down"); 694 return 0; 695 } 696 697 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 698 struct rte_eth_stats *stats) 699 { 700 PMD_INIT_FUNC_TRACE(); 701 702 fman_if_stats_get(dev->process_private, stats); 703 return 0; 704 } 705 706 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 707 { 708 PMD_INIT_FUNC_TRACE(); 709 710 fman_if_stats_reset(dev->process_private); 711 712 return 0; 713 } 714 715 static int 716 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 717 unsigned int n) 718 { 719 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 720 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 721 722 if (n < num) 723 return num; 724 725 if (xstats == NULL) 726 return 0; 727 728 fman_if_stats_get_all(dev->process_private, values, 729 sizeof(struct dpaa_if_stats) / 8); 730 731 for (i = 0; i < num; i++) { 732 xstats[i].id = i; 733 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 734 } 735 return i; 736 } 737 738 static int 739 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 740 struct rte_eth_xstat_name *xstats_names, 741 unsigned int limit) 742 { 743 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 744 745 if (limit < stat_cnt) 746 return stat_cnt; 747 748 if (xstats_names != NULL) 749 for (i = 0; i < stat_cnt; i++) 750 strlcpy(xstats_names[i].name, 751 dpaa_xstats_strings[i].name, 752 sizeof(xstats_names[i].name)); 753 754 return stat_cnt; 755 } 756 757 static int 758 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 759 uint64_t *values, unsigned int n) 760 { 761 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 762 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 763 764 if (!ids) { 765 if (n < stat_cnt) 766 return stat_cnt; 767 768 if (!values) 769 return 0; 770 771 fman_if_stats_get_all(dev->process_private, values_copy, 772 sizeof(struct dpaa_if_stats) / 8); 773 774 for (i = 0; i < stat_cnt; i++) 775 values[i] = 776 values_copy[dpaa_xstats_strings[i].offset / 8]; 777 778 return stat_cnt; 779 } 780 781 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 782 783 for (i = 0; i < n; i++) { 784 if (ids[i] >= stat_cnt) { 785 DPAA_PMD_ERR("id value isn't valid"); 786 return -1; 787 } 788 values[i] = values_copy[ids[i]]; 789 } 790 return n; 791 } 792 793 static int 794 dpaa_xstats_get_names_by_id( 795 struct rte_eth_dev *dev, 796 const uint64_t *ids, 797 struct rte_eth_xstat_name *xstats_names, 798 unsigned int limit) 799 { 800 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 801 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 802 803 if (!ids) 804 return dpaa_xstats_get_names(dev, xstats_names, limit); 805 806 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 807 808 for (i = 0; i < limit; i++) { 809 if (ids[i] >= stat_cnt) { 810 DPAA_PMD_ERR("id value isn't valid"); 811 return -1; 812 } 813 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 814 } 815 return limit; 816 } 817 818 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 819 { 820 PMD_INIT_FUNC_TRACE(); 821 822 fman_if_promiscuous_enable(dev->process_private); 823 824 return 0; 825 } 826 827 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 828 { 829 PMD_INIT_FUNC_TRACE(); 830 831 fman_if_promiscuous_disable(dev->process_private); 832 833 return 0; 834 } 835 836 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 837 { 838 PMD_INIT_FUNC_TRACE(); 839 840 fman_if_set_mcast_filter_table(dev->process_private); 841 842 return 0; 843 } 844 845 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 846 { 847 PMD_INIT_FUNC_TRACE(); 848 849 fman_if_reset_mcast_filter_table(dev->process_private); 850 851 return 0; 852 } 853 854 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 855 { 856 struct dpaa_if *dpaa_intf = dev->data->dev_private; 857 struct fman_if_ic_params icp; 858 uint32_t fd_offset; 859 uint32_t bp_size; 860 861 memset(&icp, 0, sizeof(icp)); 862 /* set ICEOF for to the default value , which is 0*/ 863 icp.iciof = DEFAULT_ICIOF; 864 icp.iceof = DEFAULT_RX_ICEOF; 865 icp.icsz = DEFAULT_ICSZ; 866 fman_if_set_ic_params(dev->process_private, &icp); 867 868 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 869 fman_if_set_fdoff(dev->process_private, fd_offset); 870 871 /* Buffer pool size should be equal to Dataroom Size*/ 872 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 873 874 fman_if_set_bp(dev->process_private, 875 dpaa_intf->bp_info->mp->size, 876 dpaa_intf->bp_info->bpid, bp_size); 877 } 878 879 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 880 int8_t vsp_id, uint32_t bpid) 881 { 882 struct dpaa_if *dpaa_intf = dev->data->dev_private; 883 struct fman_if *fif = dev->process_private; 884 885 if (fif->num_profiles) { 886 if (vsp_id < 0) 887 vsp_id = fif->base_profile_id; 888 } else { 889 if (vsp_id < 0) 890 vsp_id = 0; 891 } 892 893 if (dpaa_intf->vsp_bpid[vsp_id] && 894 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 895 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 896 897 return -1; 898 } 899 900 return 0; 901 } 902 903 static 904 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 905 uint16_t nb_desc, 906 unsigned int socket_id __rte_unused, 907 const struct rte_eth_rxconf *rx_conf, 908 struct rte_mempool *mp) 909 { 910 struct dpaa_if *dpaa_intf = dev->data->dev_private; 911 struct fman_if *fif = dev->process_private; 912 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 913 struct qm_mcc_initfq opts = {0}; 914 u32 flags = 0; 915 int ret; 916 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 917 uint32_t max_rx_pktlen; 918 919 PMD_INIT_FUNC_TRACE(); 920 921 if (queue_idx >= dev->data->nb_rx_queues) { 922 rte_errno = EOVERFLOW; 923 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 924 (void *)dev, queue_idx, dev->data->nb_rx_queues); 925 return -rte_errno; 926 } 927 928 /* Rx deferred start is not supported */ 929 if (rx_conf->rx_deferred_start) { 930 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 931 return -EINVAL; 932 } 933 rxq->nb_desc = UINT16_MAX; 934 rxq->offloads = rx_conf->offloads; 935 936 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 937 queue_idx, rxq->fqid); 938 939 if (!fif->num_profiles) { 940 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 941 dpaa_intf->bp_info->mp != mp) { 942 DPAA_PMD_WARN("Multiple pools on same interface not" 943 " supported"); 944 return -EINVAL; 945 } 946 } else { 947 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 948 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 949 return -EINVAL; 950 } 951 } 952 953 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 954 dpaa_intf->bp_info->mp != mp) { 955 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 956 return -EINVAL; 957 } 958 959 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 960 VLAN_TAG_SIZE; 961 /* Max packet can fit in single buffer */ 962 if (max_rx_pktlen <= buffsz) { 963 ; 964 } else if (dev->data->dev_conf.rxmode.offloads & 965 RTE_ETH_RX_OFFLOAD_SCATTER) { 966 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 967 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 968 "MaxSGlist %d", 969 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 970 rte_errno = EOVERFLOW; 971 return -rte_errno; 972 } 973 } else { 974 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 975 " larger than a single mbuf (%u) and scattered" 976 " mode has not been requested", 977 max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM); 978 } 979 980 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 981 982 /* For shared interface, it's done in kernel, skip.*/ 983 if (!fif->is_shared_mac) 984 dpaa_fman_if_pool_setup(dev); 985 986 if (fif->num_profiles) { 987 int8_t vsp_id = rxq->vsp_id; 988 989 if (vsp_id >= 0) { 990 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 991 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 992 fif); 993 if (ret) { 994 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 995 return ret; 996 } 997 } else { 998 DPAA_PMD_INFO("Base profile is associated to" 999 " RXQ fqid:%d\r\n", rxq->fqid); 1000 if (fif->is_shared_mac) { 1001 DPAA_PMD_ERR("Fatal: Base profile is associated" 1002 " to shared interface on DPDK."); 1003 return -EINVAL; 1004 } 1005 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1006 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1007 } 1008 } else { 1009 dpaa_intf->vsp_bpid[0] = 1010 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1011 } 1012 1013 dpaa_intf->valid = 1; 1014 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1015 fman_if_get_sg_enable(fif), max_rx_pktlen); 1016 /* checking if push mode only, no error check for now */ 1017 if (!rxq->is_static && 1018 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1019 struct qman_portal *qp; 1020 int q_fd; 1021 1022 dpaa_push_queue_idx++; 1023 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1024 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1025 QM_FQCTRL_CTXASTASHING | 1026 QM_FQCTRL_PREFERINCACHE; 1027 opts.fqd.context_a.stashing.exclusive = 0; 1028 /* In muticore scenario stashing becomes a bottleneck on LS1046. 1029 * So do not enable stashing in this case 1030 */ 1031 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1032 opts.fqd.context_a.stashing.annotation_cl = 1033 DPAA_IF_RX_ANNOTATION_STASH; 1034 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1035 opts.fqd.context_a.stashing.context_cl = 1036 DPAA_IF_RX_CONTEXT_STASH; 1037 1038 /*Create a channel and associate given queue with the channel*/ 1039 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1040 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1041 opts.fqd.dest.channel = rxq->ch_id; 1042 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1043 flags = QMAN_INITFQ_FLAG_SCHED; 1044 1045 /* Configure tail drop */ 1046 if (dpaa_intf->cgr_rx) { 1047 opts.we_mask |= QM_INITFQ_WE_CGID; 1048 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1049 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1050 } 1051 ret = qman_init_fq(rxq, flags, &opts); 1052 if (ret) { 1053 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1054 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1055 return ret; 1056 } 1057 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1058 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1059 } else { 1060 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1061 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1062 } 1063 1064 rxq->is_static = true; 1065 1066 /* Allocate qman specific portals */ 1067 qp = fsl_qman_fq_portal_create(&q_fd); 1068 if (!qp) { 1069 DPAA_PMD_ERR("Unable to alloc fq portal"); 1070 return -1; 1071 } 1072 rxq->qp = qp; 1073 1074 /* Set up the device interrupt handler */ 1075 if (!dev->intr_handle) { 1076 struct rte_dpaa_device *dpaa_dev; 1077 struct rte_device *rdev = dev->device; 1078 1079 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1080 device); 1081 dev->intr_handle = &dpaa_dev->intr_handle; 1082 dev->intr_handle->intr_vec = rte_zmalloc(NULL, 1083 dpaa_push_mode_max_queue, 0); 1084 if (!dev->intr_handle->intr_vec) { 1085 DPAA_PMD_ERR("intr_vec alloc failed"); 1086 return -ENOMEM; 1087 } 1088 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue; 1089 dev->intr_handle->max_intr = dpaa_push_mode_max_queue; 1090 } 1091 1092 dev->intr_handle->type = RTE_INTR_HANDLE_EXT; 1093 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1; 1094 dev->intr_handle->efds[queue_idx] = q_fd; 1095 rxq->q_fd = q_fd; 1096 } 1097 rxq->bp_array = rte_dpaa_bpid_info; 1098 dev->data->rx_queues[queue_idx] = rxq; 1099 1100 /* configure the CGR size as per the desc size */ 1101 if (dpaa_intf->cgr_rx) { 1102 struct qm_mcc_initcgr cgr_opts = {0}; 1103 1104 rxq->nb_desc = nb_desc; 1105 /* Enable tail drop with cgr on this queue */ 1106 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1107 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1108 if (ret) { 1109 DPAA_PMD_WARN( 1110 "rx taildrop modify fail on fqid %d (ret=%d)", 1111 rxq->fqid, ret); 1112 } 1113 } 1114 /* Enable main queue to receive error packets also by default */ 1115 fman_if_set_err_fqid(fif, rxq->fqid); 1116 return 0; 1117 } 1118 1119 int 1120 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1121 int eth_rx_queue_id, 1122 u16 ch_id, 1123 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1124 { 1125 int ret; 1126 u32 flags = 0; 1127 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1128 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1129 struct qm_mcc_initfq opts = {0}; 1130 1131 if (dpaa_push_mode_max_queue) 1132 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1133 "PUSH mode already enabled for first %d queues.\n" 1134 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1135 dpaa_push_mode_max_queue); 1136 1137 dpaa_poll_queue_default_config(&opts); 1138 1139 switch (queue_conf->ev.sched_type) { 1140 case RTE_SCHED_TYPE_ATOMIC: 1141 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1142 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1143 * configuration with HOLD_ACTIVE setting 1144 */ 1145 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1146 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1147 break; 1148 case RTE_SCHED_TYPE_ORDERED: 1149 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1150 return -1; 1151 default: 1152 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1153 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1154 break; 1155 } 1156 1157 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1158 opts.fqd.dest.channel = ch_id; 1159 opts.fqd.dest.wq = queue_conf->ev.priority; 1160 1161 if (dpaa_intf->cgr_rx) { 1162 opts.we_mask |= QM_INITFQ_WE_CGID; 1163 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1164 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1165 } 1166 1167 flags = QMAN_INITFQ_FLAG_SCHED; 1168 1169 ret = qman_init_fq(rxq, flags, &opts); 1170 if (ret) { 1171 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1172 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1173 return ret; 1174 } 1175 1176 /* copy configuration which needs to be filled during dequeue */ 1177 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1178 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1179 1180 return ret; 1181 } 1182 1183 int 1184 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1185 int eth_rx_queue_id) 1186 { 1187 struct qm_mcc_initfq opts; 1188 int ret; 1189 u32 flags = 0; 1190 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1191 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1192 1193 dpaa_poll_queue_default_config(&opts); 1194 1195 if (dpaa_intf->cgr_rx) { 1196 opts.we_mask |= QM_INITFQ_WE_CGID; 1197 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1198 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1199 } 1200 1201 ret = qman_init_fq(rxq, flags, &opts); 1202 if (ret) { 1203 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 1204 rxq->fqid, ret); 1205 } 1206 1207 rxq->cb.dqrr_dpdk_cb = NULL; 1208 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1209 1210 return 0; 1211 } 1212 1213 static 1214 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1215 uint16_t nb_desc __rte_unused, 1216 unsigned int socket_id __rte_unused, 1217 const struct rte_eth_txconf *tx_conf) 1218 { 1219 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1220 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1221 1222 PMD_INIT_FUNC_TRACE(); 1223 1224 /* Tx deferred start is not supported */ 1225 if (tx_conf->tx_deferred_start) { 1226 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1227 return -EINVAL; 1228 } 1229 txq->nb_desc = UINT16_MAX; 1230 txq->offloads = tx_conf->offloads; 1231 1232 if (queue_idx >= dev->data->nb_tx_queues) { 1233 rte_errno = EOVERFLOW; 1234 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1235 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1236 return -rte_errno; 1237 } 1238 1239 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1240 queue_idx, txq->fqid); 1241 dev->data->tx_queues[queue_idx] = txq; 1242 1243 return 0; 1244 } 1245 1246 static uint32_t 1247 dpaa_dev_rx_queue_count(void *rx_queue) 1248 { 1249 struct qman_fq *rxq = rx_queue; 1250 u32 frm_cnt = 0; 1251 1252 PMD_INIT_FUNC_TRACE(); 1253 1254 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1255 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1256 rx_queue, frm_cnt); 1257 } 1258 return frm_cnt; 1259 } 1260 1261 static int dpaa_link_down(struct rte_eth_dev *dev) 1262 { 1263 struct fman_if *fif = dev->process_private; 1264 struct __fman_if *__fif; 1265 1266 PMD_INIT_FUNC_TRACE(); 1267 1268 __fif = container_of(fif, struct __fman_if, __if); 1269 1270 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1271 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1272 else 1273 return dpaa_eth_dev_stop(dev); 1274 return 0; 1275 } 1276 1277 static int dpaa_link_up(struct rte_eth_dev *dev) 1278 { 1279 struct fman_if *fif = dev->process_private; 1280 struct __fman_if *__fif; 1281 1282 PMD_INIT_FUNC_TRACE(); 1283 1284 __fif = container_of(fif, struct __fman_if, __if); 1285 1286 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1287 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1288 else 1289 dpaa_eth_dev_start(dev); 1290 return 0; 1291 } 1292 1293 static int 1294 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1295 struct rte_eth_fc_conf *fc_conf) 1296 { 1297 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1298 struct rte_eth_fc_conf *net_fc; 1299 1300 PMD_INIT_FUNC_TRACE(); 1301 1302 if (!(dpaa_intf->fc_conf)) { 1303 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1304 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1305 if (!dpaa_intf->fc_conf) { 1306 DPAA_PMD_ERR("unable to save flow control info"); 1307 return -ENOMEM; 1308 } 1309 } 1310 net_fc = dpaa_intf->fc_conf; 1311 1312 if (fc_conf->high_water < fc_conf->low_water) { 1313 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1314 return -EINVAL; 1315 } 1316 1317 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1318 return 0; 1319 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1320 fc_conf->mode == RTE_ETH_FC_FULL) { 1321 fman_if_set_fc_threshold(dev->process_private, 1322 fc_conf->high_water, 1323 fc_conf->low_water, 1324 dpaa_intf->bp_info->bpid); 1325 if (fc_conf->pause_time) 1326 fman_if_set_fc_quanta(dev->process_private, 1327 fc_conf->pause_time); 1328 } 1329 1330 /* Save the information in dpaa device */ 1331 net_fc->pause_time = fc_conf->pause_time; 1332 net_fc->high_water = fc_conf->high_water; 1333 net_fc->low_water = fc_conf->low_water; 1334 net_fc->send_xon = fc_conf->send_xon; 1335 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1336 net_fc->mode = fc_conf->mode; 1337 net_fc->autoneg = fc_conf->autoneg; 1338 1339 return 0; 1340 } 1341 1342 static int 1343 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1344 struct rte_eth_fc_conf *fc_conf) 1345 { 1346 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1347 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1348 int ret; 1349 1350 PMD_INIT_FUNC_TRACE(); 1351 1352 if (net_fc) { 1353 fc_conf->pause_time = net_fc->pause_time; 1354 fc_conf->high_water = net_fc->high_water; 1355 fc_conf->low_water = net_fc->low_water; 1356 fc_conf->send_xon = net_fc->send_xon; 1357 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1358 fc_conf->mode = net_fc->mode; 1359 fc_conf->autoneg = net_fc->autoneg; 1360 return 0; 1361 } 1362 ret = fman_if_get_fc_threshold(dev->process_private); 1363 if (ret) { 1364 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1365 fc_conf->pause_time = 1366 fman_if_get_fc_quanta(dev->process_private); 1367 } else { 1368 fc_conf->mode = RTE_ETH_FC_NONE; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static int 1375 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1376 struct rte_ether_addr *addr, 1377 uint32_t index, 1378 __rte_unused uint32_t pool) 1379 { 1380 int ret; 1381 1382 PMD_INIT_FUNC_TRACE(); 1383 1384 ret = fman_if_add_mac_addr(dev->process_private, 1385 addr->addr_bytes, index); 1386 1387 if (ret) 1388 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1389 return 0; 1390 } 1391 1392 static void 1393 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1394 uint32_t index) 1395 { 1396 PMD_INIT_FUNC_TRACE(); 1397 1398 fman_if_clear_mac_addr(dev->process_private, index); 1399 } 1400 1401 static int 1402 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1403 struct rte_ether_addr *addr) 1404 { 1405 int ret; 1406 1407 PMD_INIT_FUNC_TRACE(); 1408 1409 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1410 if (ret) 1411 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1412 1413 return ret; 1414 } 1415 1416 static int 1417 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1418 struct rte_eth_rss_conf *rss_conf) 1419 { 1420 struct rte_eth_dev_data *data = dev->data; 1421 struct rte_eth_conf *eth_conf = &data->dev_conf; 1422 1423 PMD_INIT_FUNC_TRACE(); 1424 1425 if (!(default_q || fmc_q)) { 1426 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1427 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1428 return -1; 1429 } 1430 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1431 } else { 1432 DPAA_PMD_ERR("Function not supported\n"); 1433 return -ENOTSUP; 1434 } 1435 return 0; 1436 } 1437 1438 static int 1439 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1440 struct rte_eth_rss_conf *rss_conf) 1441 { 1442 struct rte_eth_dev_data *data = dev->data; 1443 struct rte_eth_conf *eth_conf = &data->dev_conf; 1444 1445 /* dpaa does not support rss_key, so length should be 0*/ 1446 rss_conf->rss_key_len = 0; 1447 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1448 return 0; 1449 } 1450 1451 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1452 uint16_t queue_id) 1453 { 1454 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1455 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1456 1457 if (!rxq->is_static) 1458 return -EINVAL; 1459 1460 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1461 } 1462 1463 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1464 uint16_t queue_id) 1465 { 1466 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1467 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1468 uint32_t temp; 1469 ssize_t temp1; 1470 1471 if (!rxq->is_static) 1472 return -EINVAL; 1473 1474 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1475 1476 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1477 if (temp1 != sizeof(temp)) 1478 DPAA_PMD_ERR("irq read error"); 1479 1480 qman_fq_portal_thread_irq(rxq->qp); 1481 1482 return 0; 1483 } 1484 1485 static void 1486 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1487 struct rte_eth_rxq_info *qinfo) 1488 { 1489 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1490 struct qman_fq *rxq; 1491 int ret; 1492 1493 rxq = dev->data->rx_queues[queue_id]; 1494 1495 qinfo->mp = dpaa_intf->bp_info->mp; 1496 qinfo->scattered_rx = dev->data->scattered_rx; 1497 qinfo->nb_desc = rxq->nb_desc; 1498 1499 /* Report the HW Rx buffer length to user */ 1500 ret = fman_if_get_maxfrm(dev->process_private); 1501 if (ret > 0) 1502 qinfo->rx_buf_size = ret; 1503 1504 qinfo->conf.rx_free_thresh = 1; 1505 qinfo->conf.rx_drop_en = 1; 1506 qinfo->conf.rx_deferred_start = 0; 1507 qinfo->conf.offloads = rxq->offloads; 1508 } 1509 1510 static void 1511 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1512 struct rte_eth_txq_info *qinfo) 1513 { 1514 struct qman_fq *txq; 1515 1516 txq = dev->data->tx_queues[queue_id]; 1517 1518 qinfo->nb_desc = txq->nb_desc; 1519 qinfo->conf.tx_thresh.pthresh = 0; 1520 qinfo->conf.tx_thresh.hthresh = 0; 1521 qinfo->conf.tx_thresh.wthresh = 0; 1522 1523 qinfo->conf.tx_free_thresh = 0; 1524 qinfo->conf.tx_rs_thresh = 0; 1525 qinfo->conf.offloads = txq->offloads; 1526 qinfo->conf.tx_deferred_start = 0; 1527 } 1528 1529 static struct eth_dev_ops dpaa_devops = { 1530 .dev_configure = dpaa_eth_dev_configure, 1531 .dev_start = dpaa_eth_dev_start, 1532 .dev_stop = dpaa_eth_dev_stop, 1533 .dev_close = dpaa_eth_dev_close, 1534 .dev_infos_get = dpaa_eth_dev_info, 1535 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1536 1537 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1538 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1539 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1540 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1541 .rxq_info_get = dpaa_rxq_info_get, 1542 .txq_info_get = dpaa_txq_info_get, 1543 1544 .flow_ctrl_get = dpaa_flow_ctrl_get, 1545 .flow_ctrl_set = dpaa_flow_ctrl_set, 1546 1547 .link_update = dpaa_eth_link_update, 1548 .stats_get = dpaa_eth_stats_get, 1549 .xstats_get = dpaa_dev_xstats_get, 1550 .xstats_get_by_id = dpaa_xstats_get_by_id, 1551 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1552 .xstats_get_names = dpaa_xstats_get_names, 1553 .xstats_reset = dpaa_eth_stats_reset, 1554 .stats_reset = dpaa_eth_stats_reset, 1555 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1556 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1557 .allmulticast_enable = dpaa_eth_multicast_enable, 1558 .allmulticast_disable = dpaa_eth_multicast_disable, 1559 .mtu_set = dpaa_mtu_set, 1560 .dev_set_link_down = dpaa_link_down, 1561 .dev_set_link_up = dpaa_link_up, 1562 .mac_addr_add = dpaa_dev_add_mac_addr, 1563 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1564 .mac_addr_set = dpaa_dev_set_mac_addr, 1565 1566 .fw_version_get = dpaa_fw_version_get, 1567 1568 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1569 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1570 .rss_hash_update = dpaa_dev_rss_hash_update, 1571 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1572 }; 1573 1574 static bool 1575 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1576 { 1577 if (strcmp(dev->device->driver->name, 1578 drv->driver.name)) 1579 return false; 1580 1581 return true; 1582 } 1583 1584 static bool 1585 is_dpaa_supported(struct rte_eth_dev *dev) 1586 { 1587 return is_device_supported(dev, &rte_dpaa_pmd); 1588 } 1589 1590 int 1591 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1592 { 1593 struct rte_eth_dev *dev; 1594 1595 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1596 1597 dev = &rte_eth_devices[port]; 1598 1599 if (!is_dpaa_supported(dev)) 1600 return -ENOTSUP; 1601 1602 if (on) 1603 fman_if_loopback_enable(dev->process_private); 1604 else 1605 fman_if_loopback_disable(dev->process_private); 1606 1607 return 0; 1608 } 1609 1610 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1611 struct fman_if *fman_intf) 1612 { 1613 struct rte_eth_fc_conf *fc_conf; 1614 int ret; 1615 1616 PMD_INIT_FUNC_TRACE(); 1617 1618 if (!(dpaa_intf->fc_conf)) { 1619 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1620 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1621 if (!dpaa_intf->fc_conf) { 1622 DPAA_PMD_ERR("unable to save flow control info"); 1623 return -ENOMEM; 1624 } 1625 } 1626 fc_conf = dpaa_intf->fc_conf; 1627 ret = fman_if_get_fc_threshold(fman_intf); 1628 if (ret) { 1629 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1630 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1631 } else { 1632 fc_conf->mode = RTE_ETH_FC_NONE; 1633 } 1634 1635 return 0; 1636 } 1637 1638 /* Initialise an Rx FQ */ 1639 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1640 uint32_t fqid) 1641 { 1642 struct qm_mcc_initfq opts = {0}; 1643 int ret; 1644 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1645 struct qm_mcc_initcgr cgr_opts = { 1646 .we_mask = QM_CGR_WE_CS_THRES | 1647 QM_CGR_WE_CSTD_EN | 1648 QM_CGR_WE_MODE, 1649 .cgr = { 1650 .cstd_en = QM_CGR_EN, 1651 .mode = QMAN_CGR_MODE_FRAME 1652 } 1653 }; 1654 1655 if (fmc_q || default_q) { 1656 ret = qman_reserve_fqid(fqid); 1657 if (ret) { 1658 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1659 fqid, ret); 1660 return -EINVAL; 1661 } 1662 } 1663 1664 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1665 ret = qman_create_fq(fqid, flags, fq); 1666 if (ret) { 1667 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1668 fqid, ret); 1669 return ret; 1670 } 1671 fq->is_static = false; 1672 1673 dpaa_poll_queue_default_config(&opts); 1674 1675 if (cgr_rx) { 1676 /* Enable tail drop with cgr on this queue */ 1677 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1678 cgr_rx->cb = NULL; 1679 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1680 &cgr_opts); 1681 if (ret) { 1682 DPAA_PMD_WARN( 1683 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1684 fq->fqid, ret); 1685 goto without_cgr; 1686 } 1687 opts.we_mask |= QM_INITFQ_WE_CGID; 1688 opts.fqd.cgid = cgr_rx->cgrid; 1689 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1690 } 1691 without_cgr: 1692 ret = qman_init_fq(fq, 0, &opts); 1693 if (ret) 1694 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1695 return ret; 1696 } 1697 1698 /* Initialise a Tx FQ */ 1699 static int dpaa_tx_queue_init(struct qman_fq *fq, 1700 struct fman_if *fman_intf, 1701 struct qman_cgr *cgr_tx) 1702 { 1703 struct qm_mcc_initfq opts = {0}; 1704 struct qm_mcc_initcgr cgr_opts = { 1705 .we_mask = QM_CGR_WE_CS_THRES | 1706 QM_CGR_WE_CSTD_EN | 1707 QM_CGR_WE_MODE, 1708 .cgr = { 1709 .cstd_en = QM_CGR_EN, 1710 .mode = QMAN_CGR_MODE_FRAME 1711 } 1712 }; 1713 int ret; 1714 1715 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1716 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1717 if (ret) { 1718 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1719 return ret; 1720 } 1721 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1722 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1723 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1724 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1725 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1726 opts.fqd.context_b = 0; 1727 /* no tx-confirmation */ 1728 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1729 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1730 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1731 1732 if (cgr_tx) { 1733 /* Enable tail drop with cgr on this queue */ 1734 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1735 td_tx_threshold, 0); 1736 cgr_tx->cb = NULL; 1737 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1738 &cgr_opts); 1739 if (ret) { 1740 DPAA_PMD_WARN( 1741 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1742 fq->fqid, ret); 1743 goto without_cgr; 1744 } 1745 opts.we_mask |= QM_INITFQ_WE_CGID; 1746 opts.fqd.cgid = cgr_tx->cgrid; 1747 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1748 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1749 td_tx_threshold); 1750 } 1751 without_cgr: 1752 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1753 if (ret) 1754 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1755 return ret; 1756 } 1757 1758 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1759 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1760 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1761 { 1762 struct qm_mcc_initfq opts = {0}; 1763 int ret; 1764 1765 PMD_INIT_FUNC_TRACE(); 1766 1767 ret = qman_reserve_fqid(fqid); 1768 if (ret) { 1769 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1770 fqid, ret); 1771 return -EINVAL; 1772 } 1773 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1774 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1775 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1776 if (ret) { 1777 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1778 fqid, ret); 1779 return ret; 1780 } 1781 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1782 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1783 ret = qman_init_fq(fq, 0, &opts); 1784 if (ret) 1785 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1786 fqid, ret); 1787 return ret; 1788 } 1789 #endif 1790 1791 /* Initialise a network interface */ 1792 static int 1793 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1794 { 1795 struct rte_dpaa_device *dpaa_device; 1796 struct fm_eth_port_cfg *cfg; 1797 struct dpaa_if *dpaa_intf; 1798 struct fman_if *fman_intf; 1799 int dev_id; 1800 1801 PMD_INIT_FUNC_TRACE(); 1802 1803 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1804 dev_id = dpaa_device->id.dev_id; 1805 cfg = dpaa_get_eth_port_cfg(dev_id); 1806 fman_intf = cfg->fman_if; 1807 eth_dev->process_private = fman_intf; 1808 1809 /* Plugging of UCODE burst API not supported in Secondary */ 1810 dpaa_intf = eth_dev->data->dev_private; 1811 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1812 if (dpaa_intf->cgr_tx) 1813 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1814 else 1815 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1816 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1817 qman_set_fq_lookup_table( 1818 dpaa_intf->rx_queues->qman_fq_lookup_table); 1819 #endif 1820 1821 return 0; 1822 } 1823 1824 /* Initialise a network interface */ 1825 static int 1826 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1827 { 1828 int num_rx_fqs, fqid; 1829 int loop, ret = 0; 1830 int dev_id; 1831 struct rte_dpaa_device *dpaa_device; 1832 struct dpaa_if *dpaa_intf; 1833 struct fm_eth_port_cfg *cfg; 1834 struct fman_if *fman_intf; 1835 struct fman_if_bpool *bp, *tmp_bp; 1836 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1837 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1838 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1839 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1840 int8_t vsp_id = -1; 1841 1842 PMD_INIT_FUNC_TRACE(); 1843 1844 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1845 dev_id = dpaa_device->id.dev_id; 1846 dpaa_intf = eth_dev->data->dev_private; 1847 cfg = dpaa_get_eth_port_cfg(dev_id); 1848 fman_intf = cfg->fman_if; 1849 1850 dpaa_intf->name = dpaa_device->name; 1851 1852 /* save fman_if & cfg in the interface struture */ 1853 eth_dev->process_private = fman_intf; 1854 dpaa_intf->ifid = dev_id; 1855 dpaa_intf->cfg = cfg; 1856 1857 memset((char *)dev_rx_fqids, 0, 1858 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1859 1860 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1861 1862 /* Initialize Rx FQ's */ 1863 if (default_q) { 1864 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1865 } else if (fmc_q) { 1866 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1867 dev_vspids, 1868 DPAA_MAX_NUM_PCD_QUEUES); 1869 if (num_rx_fqs < 0) { 1870 DPAA_PMD_ERR("%s FMC initializes failed!", 1871 dpaa_intf->name); 1872 goto free_rx; 1873 } 1874 if (!num_rx_fqs) { 1875 DPAA_PMD_WARN("%s is not configured by FMC.", 1876 dpaa_intf->name); 1877 } 1878 } else { 1879 /* FMCLESS mode, load balance to multiple cores.*/ 1880 num_rx_fqs = rte_lcore_count(); 1881 } 1882 1883 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1884 * queues. 1885 */ 1886 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1887 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1888 return -EINVAL; 1889 } 1890 1891 if (num_rx_fqs > 0) { 1892 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1893 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1894 if (!dpaa_intf->rx_queues) { 1895 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1896 return -ENOMEM; 1897 } 1898 } else { 1899 dpaa_intf->rx_queues = NULL; 1900 } 1901 1902 memset(cgrid, 0, sizeof(cgrid)); 1903 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1904 1905 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1906 * Tx tail drop is disabled. 1907 */ 1908 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1909 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1910 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1911 td_tx_threshold); 1912 /* if a very large value is being configured */ 1913 if (td_tx_threshold > UINT16_MAX) 1914 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1915 } 1916 1917 /* If congestion control is enabled globally*/ 1918 if (num_rx_fqs > 0 && td_threshold) { 1919 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1920 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1921 if (!dpaa_intf->cgr_rx) { 1922 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1923 ret = -ENOMEM; 1924 goto free_rx; 1925 } 1926 1927 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1928 if (ret != num_rx_fqs) { 1929 DPAA_PMD_WARN("insufficient CGRIDs available"); 1930 ret = -EINVAL; 1931 goto free_rx; 1932 } 1933 } else { 1934 dpaa_intf->cgr_rx = NULL; 1935 } 1936 1937 if (!fmc_q && !default_q) { 1938 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1939 num_rx_fqs, 0); 1940 if (ret < 0) { 1941 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1942 goto free_rx; 1943 } 1944 } 1945 1946 for (loop = 0; loop < num_rx_fqs; loop++) { 1947 if (default_q) 1948 fqid = cfg->rx_def; 1949 else 1950 fqid = dev_rx_fqids[loop]; 1951 1952 vsp_id = dev_vspids[loop]; 1953 1954 if (dpaa_intf->cgr_rx) 1955 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1956 1957 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1958 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1959 fqid); 1960 if (ret) 1961 goto free_rx; 1962 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 1963 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1964 } 1965 dpaa_intf->nb_rx_queues = num_rx_fqs; 1966 1967 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1968 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1969 MAX_DPAA_CORES, MAX_CACHELINE); 1970 if (!dpaa_intf->tx_queues) { 1971 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1972 ret = -ENOMEM; 1973 goto free_rx; 1974 } 1975 1976 /* If congestion control is enabled globally*/ 1977 if (td_tx_threshold) { 1978 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 1979 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 1980 MAX_CACHELINE); 1981 if (!dpaa_intf->cgr_tx) { 1982 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 1983 ret = -ENOMEM; 1984 goto free_rx; 1985 } 1986 1987 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 1988 1, 0); 1989 if (ret != MAX_DPAA_CORES) { 1990 DPAA_PMD_WARN("insufficient CGRIDs available"); 1991 ret = -EINVAL; 1992 goto free_rx; 1993 } 1994 } else { 1995 dpaa_intf->cgr_tx = NULL; 1996 } 1997 1998 1999 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2000 if (dpaa_intf->cgr_tx) 2001 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2002 2003 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2004 fman_intf, 2005 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2006 if (ret) 2007 goto free_tx; 2008 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2009 } 2010 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2011 2012 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2013 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2014 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2015 if (ret) { 2016 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2017 goto free_tx; 2018 } 2019 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2020 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2021 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2022 if (ret) { 2023 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2024 goto free_tx; 2025 } 2026 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2027 #endif 2028 2029 DPAA_PMD_DEBUG("All frame queues created"); 2030 2031 /* Get the initial configuration for flow control */ 2032 dpaa_fc_set_default(dpaa_intf, fman_intf); 2033 2034 /* reset bpool list, initialize bpool dynamically */ 2035 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2036 list_del(&bp->node); 2037 rte_free(bp); 2038 } 2039 2040 /* Populate ethdev structure */ 2041 eth_dev->dev_ops = &dpaa_devops; 2042 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2043 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2044 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2045 2046 /* Allocate memory for storing MAC addresses */ 2047 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2048 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2049 if (eth_dev->data->mac_addrs == NULL) { 2050 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2051 "store MAC addresses", 2052 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2053 ret = -ENOMEM; 2054 goto free_tx; 2055 } 2056 2057 /* copy the primary mac address */ 2058 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2059 2060 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n", 2061 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2062 2063 if (!fman_intf->is_shared_mac) { 2064 /* Configure error packet handling */ 2065 fman_if_receive_rx_errors(fman_intf, 2066 FM_FD_RX_STATUS_ERR_MASK); 2067 /* Disable RX mode */ 2068 fman_if_disable_rx(fman_intf); 2069 /* Disable promiscuous mode */ 2070 fman_if_promiscuous_disable(fman_intf); 2071 /* Disable multicast */ 2072 fman_if_reset_mcast_filter_table(fman_intf); 2073 /* Reset interface statistics */ 2074 fman_if_stats_reset(fman_intf); 2075 /* Disable SG by default */ 2076 fman_if_set_sg(fman_intf, 0); 2077 fman_if_set_maxfrm(fman_intf, 2078 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2079 } 2080 2081 return 0; 2082 2083 free_tx: 2084 rte_free(dpaa_intf->tx_queues); 2085 dpaa_intf->tx_queues = NULL; 2086 dpaa_intf->nb_tx_queues = 0; 2087 2088 free_rx: 2089 rte_free(dpaa_intf->cgr_rx); 2090 rte_free(dpaa_intf->cgr_tx); 2091 rte_free(dpaa_intf->rx_queues); 2092 dpaa_intf->rx_queues = NULL; 2093 dpaa_intf->nb_rx_queues = 0; 2094 return ret; 2095 } 2096 2097 static int 2098 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2099 struct rte_dpaa_device *dpaa_dev) 2100 { 2101 int diag; 2102 int ret; 2103 struct rte_eth_dev *eth_dev; 2104 2105 PMD_INIT_FUNC_TRACE(); 2106 2107 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2108 RTE_PKTMBUF_HEADROOM) { 2109 DPAA_PMD_ERR( 2110 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2111 RTE_PKTMBUF_HEADROOM, 2112 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2113 2114 return -1; 2115 } 2116 2117 /* In case of secondary process, the device is already configured 2118 * and no further action is required, except portal initialization 2119 * and verifying secondary attachment to port name. 2120 */ 2121 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2122 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2123 if (!eth_dev) 2124 return -ENOMEM; 2125 eth_dev->device = &dpaa_dev->device; 2126 eth_dev->dev_ops = &dpaa_devops; 2127 2128 ret = dpaa_dev_init_secondary(eth_dev); 2129 if (ret != 0) { 2130 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 2131 return ret; 2132 } 2133 2134 rte_eth_dev_probing_finish(eth_dev); 2135 return 0; 2136 } 2137 2138 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2139 if (access("/tmp/fmc.bin", F_OK) == -1) { 2140 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2141 default_q = 1; 2142 } 2143 2144 if (!(default_q || fmc_q)) { 2145 if (dpaa_fm_init()) { 2146 DPAA_PMD_ERR("FM init failed\n"); 2147 return -1; 2148 } 2149 } 2150 2151 /* disabling the default push mode for LS1043 */ 2152 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2153 dpaa_push_mode_max_queue = 0; 2154 2155 /* if push mode queues to be enabled. Currenly we are allowing 2156 * only one queue per thread. 2157 */ 2158 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2159 dpaa_push_mode_max_queue = 2160 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2161 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2162 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2163 } 2164 2165 is_global_init = 1; 2166 } 2167 2168 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2169 ret = rte_dpaa_portal_init((void *)1); 2170 if (ret) { 2171 DPAA_PMD_ERR("Unable to initialize portal"); 2172 return ret; 2173 } 2174 } 2175 2176 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2177 if (!eth_dev) 2178 return -ENOMEM; 2179 2180 eth_dev->data->dev_private = 2181 rte_zmalloc("ethdev private structure", 2182 sizeof(struct dpaa_if), 2183 RTE_CACHE_LINE_SIZE); 2184 if (!eth_dev->data->dev_private) { 2185 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2186 rte_eth_dev_release_port(eth_dev); 2187 return -ENOMEM; 2188 } 2189 2190 eth_dev->device = &dpaa_dev->device; 2191 dpaa_dev->eth_dev = eth_dev; 2192 2193 qman_ern_register_cb(dpaa_free_mbuf); 2194 2195 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2196 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2197 2198 /* Invoke PMD device initialization function */ 2199 diag = dpaa_dev_init(eth_dev); 2200 if (diag == 0) { 2201 rte_eth_dev_probing_finish(eth_dev); 2202 return 0; 2203 } 2204 2205 rte_eth_dev_release_port(eth_dev); 2206 return diag; 2207 } 2208 2209 static int 2210 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2211 { 2212 struct rte_eth_dev *eth_dev; 2213 int ret; 2214 2215 PMD_INIT_FUNC_TRACE(); 2216 2217 eth_dev = dpaa_dev->eth_dev; 2218 dpaa_eth_dev_close(eth_dev); 2219 ret = rte_eth_dev_release_port(eth_dev); 2220 2221 return ret; 2222 } 2223 2224 static void __attribute__((destructor(102))) dpaa_finish(void) 2225 { 2226 /* For secondary, primary will do all the cleanup */ 2227 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2228 return; 2229 2230 if (!(default_q || fmc_q)) { 2231 unsigned int i; 2232 2233 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2234 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2235 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2236 struct dpaa_if *dpaa_intf = 2237 dev->data->dev_private; 2238 struct fman_if *fif = 2239 dev->process_private; 2240 if (dpaa_intf->port_handle) 2241 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2242 DPAA_PMD_WARN("DPAA FM " 2243 "deconfig failed\n"); 2244 if (fif->num_profiles) { 2245 if (dpaa_port_vsp_cleanup(dpaa_intf, 2246 fif)) 2247 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2248 } 2249 } 2250 } 2251 if (is_global_init) 2252 if (dpaa_fm_term()) 2253 DPAA_PMD_WARN("DPAA FM term failed\n"); 2254 2255 is_global_init = 0; 2256 2257 DPAA_PMD_INFO("DPAA fman cleaned up"); 2258 } 2259 } 2260 2261 static struct rte_dpaa_driver rte_dpaa_pmd = { 2262 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2263 .drv_type = FSL_DPAA_ETH, 2264 .probe = rte_dpaa_probe, 2265 .remove = rte_dpaa_remove, 2266 }; 2267 2268 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2269 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2270