1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <bus_dpaa_driver.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 RTE_ETH_RX_OFFLOAD_SCATTER; 58 59 /* Rx offloads which cannot be disabled */ 60 static uint64_t dev_rx_offloads_nodis = 61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_RSS_HASH; 66 67 /* Supported Tx offloads */ 68 static uint64_t dev_tx_offloads_sup = 69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 71 72 /* Tx offloads which cannot be disabled */ 73 static uint64_t dev_tx_offloads_nodis = 74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 80 81 /* Keep track of whether QMAN and BMAN have been globally initialized */ 82 static int is_global_init; 83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 84 static int default_q; /* use default queue - FMC is not executed*/ 85 /* At present we only allow up to 4 push mode queues as default - as each of 86 * this queue need dedicated portal and we are short of portals. 87 */ 88 #define DPAA_MAX_PUSH_MODE_QUEUE 8 89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 90 91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 93 94 95 /* Per RX FQ Taildrop in frame count */ 96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 97 98 /* Per TX FQ Taildrop in frame count, disabled by default */ 99 static unsigned int td_tx_threshold; 100 101 struct rte_dpaa_xstats_name_off { 102 char name[RTE_ETH_XSTATS_NAME_SIZE]; 103 uint32_t offset; 104 }; 105 106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 107 {"rx_align_err", 108 offsetof(struct dpaa_if_stats, raln)}, 109 {"rx_valid_pause", 110 offsetof(struct dpaa_if_stats, rxpf)}, 111 {"rx_fcs_err", 112 offsetof(struct dpaa_if_stats, rfcs)}, 113 {"rx_vlan_frame", 114 offsetof(struct dpaa_if_stats, rvlan)}, 115 {"rx_frame_err", 116 offsetof(struct dpaa_if_stats, rerr)}, 117 {"rx_drop_err", 118 offsetof(struct dpaa_if_stats, rdrp)}, 119 {"rx_undersized", 120 offsetof(struct dpaa_if_stats, rund)}, 121 {"rx_oversize_err", 122 offsetof(struct dpaa_if_stats, rovr)}, 123 {"rx_fragment_pkt", 124 offsetof(struct dpaa_if_stats, rfrg)}, 125 {"tx_valid_pause", 126 offsetof(struct dpaa_if_stats, txpf)}, 127 {"tx_fcs_err", 128 offsetof(struct dpaa_if_stats, terr)}, 129 {"tx_vlan_frame", 130 offsetof(struct dpaa_if_stats, tvlan)}, 131 {"rx_undersized", 132 offsetof(struct dpaa_if_stats, tund)}, 133 }; 134 135 static struct rte_dpaa_driver rte_dpaa_pmd; 136 int dpaa_valid_dev; 137 struct rte_mempool *dpaa_tx_sg_pool; 138 139 static int 140 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 141 142 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 143 int wait_to_complete __rte_unused); 144 145 static void dpaa_interrupt_handler(void *param); 146 147 static inline void 148 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 149 { 150 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 151 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 152 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 153 QM_FQCTRL_PREFERINCACHE; 154 opts->fqd.context_a.stashing.exclusive = 0; 155 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 156 opts->fqd.context_a.stashing.annotation_cl = 157 DPAA_IF_RX_ANNOTATION_STASH; 158 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 159 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 160 } 161 162 static int 163 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 164 { 165 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 166 + VLAN_TAG_SIZE; 167 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 168 169 PMD_INIT_FUNC_TRACE(); 170 171 /* 172 * Refuse mtu that requires the support of scattered packets 173 * when this feature has not been enabled before. 174 */ 175 if (dev->data->min_rx_buf_size && 176 !dev->data->scattered_rx && frame_size > buffsz) { 177 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 178 return -EINVAL; 179 } 180 181 /* check <seg size> * <max_seg> >= max_frame */ 182 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 183 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 184 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 185 buffsz * DPAA_SGT_MAX_ENTRIES); 186 return -EINVAL; 187 } 188 189 fman_if_set_maxfrm(dev->process_private, frame_size); 190 191 return 0; 192 } 193 194 static int 195 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 196 { 197 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 198 uint64_t rx_offloads = eth_conf->rxmode.offloads; 199 uint64_t tx_offloads = eth_conf->txmode.offloads; 200 struct dpaa_if *dpaa_intf = dev->data->dev_private; 201 struct rte_device *rdev = dev->device; 202 struct rte_eth_link *link = &dev->data->dev_link; 203 struct rte_dpaa_device *dpaa_dev; 204 struct fman_if *fif = dev->process_private; 205 struct __fman_if *__fif; 206 struct rte_intr_handle *intr_handle; 207 uint32_t max_rx_pktlen; 208 int speed, duplex; 209 int ret, rx_status; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 214 intr_handle = dpaa_dev->intr_handle; 215 __fif = container_of(fif, struct __fman_if, __if); 216 217 /* Check if interface is enabled in case of shared MAC */ 218 if (fif->is_shared_mac) { 219 rx_status = fman_if_get_rx_status(fif); 220 if (!rx_status) { 221 DPAA_PMD_ERR("%s Interface not enabled in kernel!", 222 dpaa_intf->name); 223 return -EHOSTDOWN; 224 } 225 } 226 227 /* Rx offloads which are enabled by default */ 228 if (dev_rx_offloads_nodis & ~rx_offloads) { 229 DPAA_PMD_INFO( 230 "Some of rx offloads enabled by default - requested 0x%" PRIx64 231 " fixed are 0x%" PRIx64, 232 rx_offloads, dev_rx_offloads_nodis); 233 } 234 235 /* Tx offloads which are enabled by default */ 236 if (dev_tx_offloads_nodis & ~tx_offloads) { 237 DPAA_PMD_INFO( 238 "Some of tx offloads enabled by default - requested 0x%" PRIx64 239 " fixed are 0x%" PRIx64, 240 tx_offloads, dev_tx_offloads_nodis); 241 } 242 243 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 244 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 245 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 246 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 247 "supported is %d", 248 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 249 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 250 } 251 252 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 253 254 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 255 DPAA_PMD_DEBUG("enabling scatter mode"); 256 fman_if_set_sg(dev->process_private, 1); 257 dev->data->scattered_rx = 1; 258 } 259 260 if (!(default_q || fmc_q)) { 261 if (dpaa_fm_config(dev, 262 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 263 dpaa_write_fm_config_to_file(); 264 DPAA_PMD_ERR("FM port configuration: Failed\n"); 265 return -1; 266 } 267 dpaa_write_fm_config_to_file(); 268 } 269 270 /* if the interrupts were configured on this devices*/ 271 if (intr_handle && rte_intr_fd_get(intr_handle)) { 272 if (dev->data->dev_conf.intr_conf.lsc != 0) 273 rte_intr_callback_register(intr_handle, 274 dpaa_interrupt_handler, 275 (void *)dev); 276 277 ret = dpaa_intr_enable(__fif->node_name, 278 rte_intr_fd_get(intr_handle)); 279 if (ret) { 280 if (dev->data->dev_conf.intr_conf.lsc != 0) { 281 rte_intr_callback_unregister(intr_handle, 282 dpaa_interrupt_handler, 283 (void *)dev); 284 if (ret == EINVAL) 285 printf("Failed to enable interrupt: Not Supported\n"); 286 else 287 printf("Failed to enable interrupt\n"); 288 } 289 dev->data->dev_conf.intr_conf.lsc = 0; 290 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 291 } 292 } 293 294 /* Wait for link status to get updated */ 295 if (!link->link_status) 296 sleep(1); 297 298 /* Configure link only if link is UP*/ 299 if (link->link_status) { 300 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 301 /* Start autoneg only if link is not in autoneg mode */ 302 if (!link->link_autoneg) 303 dpaa_restart_link_autoneg(__fif->node_name); 304 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 305 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 306 case RTE_ETH_LINK_SPEED_10M_HD: 307 speed = RTE_ETH_SPEED_NUM_10M; 308 duplex = RTE_ETH_LINK_HALF_DUPLEX; 309 break; 310 case RTE_ETH_LINK_SPEED_10M: 311 speed = RTE_ETH_SPEED_NUM_10M; 312 duplex = RTE_ETH_LINK_FULL_DUPLEX; 313 break; 314 case RTE_ETH_LINK_SPEED_100M_HD: 315 speed = RTE_ETH_SPEED_NUM_100M; 316 duplex = RTE_ETH_LINK_HALF_DUPLEX; 317 break; 318 case RTE_ETH_LINK_SPEED_100M: 319 speed = RTE_ETH_SPEED_NUM_100M; 320 duplex = RTE_ETH_LINK_FULL_DUPLEX; 321 break; 322 case RTE_ETH_LINK_SPEED_1G: 323 speed = RTE_ETH_SPEED_NUM_1G; 324 duplex = RTE_ETH_LINK_FULL_DUPLEX; 325 break; 326 case RTE_ETH_LINK_SPEED_2_5G: 327 speed = RTE_ETH_SPEED_NUM_2_5G; 328 duplex = RTE_ETH_LINK_FULL_DUPLEX; 329 break; 330 case RTE_ETH_LINK_SPEED_10G: 331 speed = RTE_ETH_SPEED_NUM_10G; 332 duplex = RTE_ETH_LINK_FULL_DUPLEX; 333 break; 334 default: 335 speed = RTE_ETH_SPEED_NUM_NONE; 336 duplex = RTE_ETH_LINK_FULL_DUPLEX; 337 break; 338 } 339 /* Set link speed */ 340 dpaa_update_link_speed(__fif->node_name, speed, duplex); 341 } else { 342 /* Manual autoneg - custom advertisement speed. */ 343 printf("Custom Advertisement speeds not supported\n"); 344 } 345 } 346 347 return 0; 348 } 349 350 static const uint32_t * 351 dpaa_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 352 { 353 static const uint32_t ptypes[] = { 354 RTE_PTYPE_L2_ETHER, 355 RTE_PTYPE_L2_ETHER_VLAN, 356 RTE_PTYPE_L2_ETHER_ARP, 357 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 358 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 359 RTE_PTYPE_L4_ICMP, 360 RTE_PTYPE_L4_TCP, 361 RTE_PTYPE_L4_UDP, 362 RTE_PTYPE_L4_FRAG, 363 RTE_PTYPE_L4_TCP, 364 RTE_PTYPE_L4_UDP, 365 RTE_PTYPE_L4_SCTP, 366 RTE_PTYPE_TUNNEL_ESP, 367 }; 368 369 PMD_INIT_FUNC_TRACE(); 370 371 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) { 372 *no_of_elements = RTE_DIM(ptypes); 373 return ptypes; 374 } 375 return NULL; 376 } 377 378 static void dpaa_interrupt_handler(void *param) 379 { 380 struct rte_eth_dev *dev = param; 381 struct rte_device *rdev = dev->device; 382 struct rte_dpaa_device *dpaa_dev; 383 struct rte_intr_handle *intr_handle; 384 uint64_t buf; 385 int bytes_read; 386 387 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 388 intr_handle = dpaa_dev->intr_handle; 389 390 if (rte_intr_fd_get(intr_handle) < 0) 391 return; 392 393 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 394 sizeof(uint64_t)); 395 if (bytes_read < 0) 396 DPAA_PMD_ERR("Error reading eventfd\n"); 397 dpaa_eth_link_update(dev, 0); 398 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 399 } 400 401 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 402 { 403 struct dpaa_if *dpaa_intf = dev->data->dev_private; 404 uint16_t i; 405 406 PMD_INIT_FUNC_TRACE(); 407 408 if (!(default_q || fmc_q)) 409 dpaa_write_fm_config_to_file(); 410 411 /* Change tx callback to the real one */ 412 if (dpaa_intf->cgr_tx) 413 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 414 else 415 dev->tx_pkt_burst = dpaa_eth_queue_tx; 416 417 fman_if_enable_rx(dev->process_private); 418 419 for (i = 0; i < dev->data->nb_rx_queues; i++) 420 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 421 for (i = 0; i < dev->data->nb_tx_queues; i++) 422 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 423 424 return 0; 425 } 426 427 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 428 { 429 struct fman_if *fif = dev->process_private; 430 uint16_t i; 431 432 PMD_INIT_FUNC_TRACE(); 433 dev->data->dev_started = 0; 434 435 if (!fif->is_shared_mac) 436 fman_if_disable_rx(fif); 437 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 438 439 for (i = 0; i < dev->data->nb_rx_queues; i++) 440 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 441 for (i = 0; i < dev->data->nb_tx_queues; i++) 442 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 443 444 return 0; 445 } 446 447 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 448 { 449 struct fman_if *fif = dev->process_private; 450 struct __fman_if *__fif; 451 struct rte_device *rdev = dev->device; 452 struct rte_dpaa_device *dpaa_dev; 453 struct rte_intr_handle *intr_handle; 454 struct rte_eth_link *link = &dev->data->dev_link; 455 struct dpaa_if *dpaa_intf = dev->data->dev_private; 456 int loop; 457 int ret; 458 459 PMD_INIT_FUNC_TRACE(); 460 461 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 462 return 0; 463 464 if (!dpaa_intf) { 465 DPAA_PMD_WARN("Already closed or not started"); 466 return -1; 467 } 468 469 /* DPAA FM deconfig */ 470 if (!(default_q || fmc_q)) { 471 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 472 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 473 } 474 475 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 476 intr_handle = dpaa_dev->intr_handle; 477 __fif = container_of(fif, struct __fman_if, __if); 478 479 ret = dpaa_eth_dev_stop(dev); 480 481 /* Reset link to autoneg */ 482 if (link->link_status && !link->link_autoneg) 483 dpaa_restart_link_autoneg(__fif->node_name); 484 485 if (intr_handle && rte_intr_fd_get(intr_handle) && 486 dev->data->dev_conf.intr_conf.lsc != 0) { 487 dpaa_intr_disable(__fif->node_name); 488 rte_intr_callback_unregister(intr_handle, 489 dpaa_interrupt_handler, 490 (void *)dev); 491 } 492 493 /* release configuration memory */ 494 rte_free(dpaa_intf->fc_conf); 495 496 /* Release RX congestion Groups */ 497 if (dpaa_intf->cgr_rx) { 498 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 499 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 500 } 501 502 rte_free(dpaa_intf->cgr_rx); 503 dpaa_intf->cgr_rx = NULL; 504 /* Release TX congestion Groups */ 505 if (dpaa_intf->cgr_tx) { 506 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 507 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 508 rte_free(dpaa_intf->cgr_tx); 509 dpaa_intf->cgr_tx = NULL; 510 } 511 512 rte_free(dpaa_intf->rx_queues); 513 dpaa_intf->rx_queues = NULL; 514 515 rte_free(dpaa_intf->tx_queues); 516 dpaa_intf->tx_queues = NULL; 517 518 return ret; 519 } 520 521 static int 522 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 523 char *fw_version, 524 size_t fw_size) 525 { 526 int ret; 527 FILE *svr_file = NULL; 528 unsigned int svr_ver = 0; 529 530 PMD_INIT_FUNC_TRACE(); 531 532 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 533 if (!svr_file) { 534 DPAA_PMD_ERR("Unable to open SoC device"); 535 return -ENOTSUP; /* Not supported on this infra */ 536 } 537 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 538 dpaa_svr_family = svr_ver & SVR_MASK; 539 else 540 DPAA_PMD_ERR("Unable to read SoC device"); 541 542 fclose(svr_file); 543 544 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 545 svr_ver, fman_ip_rev); 546 if (ret < 0) 547 return -EINVAL; 548 549 ret += 1; /* add the size of '\0' */ 550 if (fw_size < (size_t)ret) 551 return ret; 552 else 553 return 0; 554 } 555 556 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 557 struct rte_eth_dev_info *dev_info) 558 { 559 struct dpaa_if *dpaa_intf = dev->data->dev_private; 560 struct fman_if *fif = dev->process_private; 561 562 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 563 564 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 565 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 566 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 567 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 568 dev_info->max_hash_mac_addrs = 0; 569 dev_info->max_vfs = 0; 570 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 571 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 572 573 if (fif->mac_type == fman_mac_1g) { 574 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 575 | RTE_ETH_LINK_SPEED_10M 576 | RTE_ETH_LINK_SPEED_100M_HD 577 | RTE_ETH_LINK_SPEED_100M 578 | RTE_ETH_LINK_SPEED_1G; 579 } else if (fif->mac_type == fman_mac_2_5g) { 580 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 581 | RTE_ETH_LINK_SPEED_10M 582 | RTE_ETH_LINK_SPEED_100M_HD 583 | RTE_ETH_LINK_SPEED_100M 584 | RTE_ETH_LINK_SPEED_1G 585 | RTE_ETH_LINK_SPEED_2_5G; 586 } else if (fif->mac_type == fman_mac_10g) { 587 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 588 | RTE_ETH_LINK_SPEED_10M 589 | RTE_ETH_LINK_SPEED_100M_HD 590 | RTE_ETH_LINK_SPEED_100M 591 | RTE_ETH_LINK_SPEED_1G 592 | RTE_ETH_LINK_SPEED_2_5G 593 | RTE_ETH_LINK_SPEED_10G; 594 } else { 595 DPAA_PMD_ERR("invalid link_speed: %s, %d", 596 dpaa_intf->name, fif->mac_type); 597 return -EINVAL; 598 } 599 600 dev_info->rx_offload_capa = dev_rx_offloads_sup | 601 dev_rx_offloads_nodis; 602 dev_info->tx_offload_capa = dev_tx_offloads_sup | 603 dev_tx_offloads_nodis; 604 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 605 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 606 dev_info->default_rxportconf.nb_queues = 1; 607 dev_info->default_txportconf.nb_queues = 1; 608 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 609 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 610 611 return 0; 612 } 613 614 static int 615 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 616 __rte_unused uint16_t queue_id, 617 struct rte_eth_burst_mode *mode) 618 { 619 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 620 int ret = -EINVAL; 621 unsigned int i; 622 const struct burst_info { 623 uint64_t flags; 624 const char *output; 625 } rx_offload_map[] = { 626 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 627 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 628 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 629 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 630 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 631 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 632 }; 633 634 /* Update Rx offload info */ 635 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 636 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 637 snprintf(mode->info, sizeof(mode->info), "%s", 638 rx_offload_map[i].output); 639 ret = 0; 640 break; 641 } 642 } 643 return ret; 644 } 645 646 static int 647 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 648 __rte_unused uint16_t queue_id, 649 struct rte_eth_burst_mode *mode) 650 { 651 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 652 int ret = -EINVAL; 653 unsigned int i; 654 const struct burst_info { 655 uint64_t flags; 656 const char *output; 657 } tx_offload_map[] = { 658 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 659 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 660 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 661 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 662 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 663 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 664 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 665 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 666 }; 667 668 /* Update Tx offload info */ 669 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 670 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 671 snprintf(mode->info, sizeof(mode->info), "%s", 672 tx_offload_map[i].output); 673 ret = 0; 674 break; 675 } 676 } 677 return ret; 678 } 679 680 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 681 int wait_to_complete) 682 { 683 struct dpaa_if *dpaa_intf = dev->data->dev_private; 684 struct rte_eth_link *link = &dev->data->dev_link; 685 struct fman_if *fif = dev->process_private; 686 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 687 int ret, ioctl_version; 688 uint8_t count; 689 690 PMD_INIT_FUNC_TRACE(); 691 692 ioctl_version = dpaa_get_ioctl_version_number(); 693 694 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 695 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 696 ret = dpaa_get_link_status(__fif->node_name, link); 697 if (ret) 698 return ret; 699 if (link->link_status == RTE_ETH_LINK_DOWN && 700 wait_to_complete) 701 rte_delay_ms(CHECK_INTERVAL); 702 else 703 break; 704 } 705 } else { 706 link->link_status = dpaa_intf->valid; 707 } 708 709 if (ioctl_version < 2) { 710 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 711 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 712 713 if (fif->mac_type == fman_mac_1g) 714 link->link_speed = RTE_ETH_SPEED_NUM_1G; 715 else if (fif->mac_type == fman_mac_2_5g) 716 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 717 else if (fif->mac_type == fman_mac_10g) 718 link->link_speed = RTE_ETH_SPEED_NUM_10G; 719 else 720 DPAA_PMD_ERR("invalid link_speed: %s, %d", 721 dpaa_intf->name, fif->mac_type); 722 } 723 724 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 725 link->link_status ? "Up" : "Down"); 726 return 0; 727 } 728 729 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 730 struct rte_eth_stats *stats) 731 { 732 PMD_INIT_FUNC_TRACE(); 733 734 fman_if_stats_get(dev->process_private, stats); 735 return 0; 736 } 737 738 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 739 { 740 PMD_INIT_FUNC_TRACE(); 741 742 fman_if_stats_reset(dev->process_private); 743 744 return 0; 745 } 746 747 static int 748 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 749 unsigned int n) 750 { 751 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 752 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 753 754 if (n < num) 755 return num; 756 757 if (xstats == NULL) 758 return 0; 759 760 fman_if_stats_get_all(dev->process_private, values, 761 sizeof(struct dpaa_if_stats) / 8); 762 763 for (i = 0; i < num; i++) { 764 xstats[i].id = i; 765 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 766 } 767 return i; 768 } 769 770 static int 771 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 772 struct rte_eth_xstat_name *xstats_names, 773 unsigned int limit) 774 { 775 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 776 777 if (limit < stat_cnt) 778 return stat_cnt; 779 780 if (xstats_names != NULL) 781 for (i = 0; i < stat_cnt; i++) 782 strlcpy(xstats_names[i].name, 783 dpaa_xstats_strings[i].name, 784 sizeof(xstats_names[i].name)); 785 786 return stat_cnt; 787 } 788 789 static int 790 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 791 uint64_t *values, unsigned int n) 792 { 793 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 794 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 795 796 if (!ids) { 797 if (n < stat_cnt) 798 return stat_cnt; 799 800 if (!values) 801 return 0; 802 803 fman_if_stats_get_all(dev->process_private, values_copy, 804 sizeof(struct dpaa_if_stats) / 8); 805 806 for (i = 0; i < stat_cnt; i++) 807 values[i] = 808 values_copy[dpaa_xstats_strings[i].offset / 8]; 809 810 return stat_cnt; 811 } 812 813 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 814 815 for (i = 0; i < n; i++) { 816 if (ids[i] >= stat_cnt) { 817 DPAA_PMD_ERR("id value isn't valid"); 818 return -1; 819 } 820 values[i] = values_copy[ids[i]]; 821 } 822 return n; 823 } 824 825 static int 826 dpaa_xstats_get_names_by_id( 827 struct rte_eth_dev *dev, 828 const uint64_t *ids, 829 struct rte_eth_xstat_name *xstats_names, 830 unsigned int limit) 831 { 832 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 833 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 834 835 if (!ids) 836 return dpaa_xstats_get_names(dev, xstats_names, limit); 837 838 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 839 840 for (i = 0; i < limit; i++) { 841 if (ids[i] >= stat_cnt) { 842 DPAA_PMD_ERR("id value isn't valid"); 843 return -1; 844 } 845 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 846 } 847 return limit; 848 } 849 850 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 851 { 852 PMD_INIT_FUNC_TRACE(); 853 854 fman_if_promiscuous_enable(dev->process_private); 855 856 return 0; 857 } 858 859 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 860 { 861 PMD_INIT_FUNC_TRACE(); 862 863 fman_if_promiscuous_disable(dev->process_private); 864 865 return 0; 866 } 867 868 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 869 { 870 PMD_INIT_FUNC_TRACE(); 871 872 fman_if_set_mcast_filter_table(dev->process_private); 873 874 return 0; 875 } 876 877 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 878 { 879 PMD_INIT_FUNC_TRACE(); 880 881 fman_if_reset_mcast_filter_table(dev->process_private); 882 883 return 0; 884 } 885 886 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 887 { 888 struct dpaa_if *dpaa_intf = dev->data->dev_private; 889 struct fman_if_ic_params icp; 890 uint32_t fd_offset; 891 uint32_t bp_size; 892 893 memset(&icp, 0, sizeof(icp)); 894 /* set ICEOF for to the default value , which is 0*/ 895 icp.iciof = DEFAULT_ICIOF; 896 icp.iceof = DEFAULT_RX_ICEOF; 897 icp.icsz = DEFAULT_ICSZ; 898 fman_if_set_ic_params(dev->process_private, &icp); 899 900 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 901 fman_if_set_fdoff(dev->process_private, fd_offset); 902 903 /* Buffer pool size should be equal to Dataroom Size*/ 904 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 905 906 fman_if_set_bp(dev->process_private, 907 dpaa_intf->bp_info->mp->size, 908 dpaa_intf->bp_info->bpid, bp_size); 909 } 910 911 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 912 int8_t vsp_id, uint32_t bpid) 913 { 914 struct dpaa_if *dpaa_intf = dev->data->dev_private; 915 struct fman_if *fif = dev->process_private; 916 917 if (fif->num_profiles) { 918 if (vsp_id < 0) 919 vsp_id = fif->base_profile_id; 920 } else { 921 if (vsp_id < 0) 922 vsp_id = 0; 923 } 924 925 if (dpaa_intf->vsp_bpid[vsp_id] && 926 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 927 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 928 929 return -1; 930 } 931 932 return 0; 933 } 934 935 static 936 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 937 uint16_t nb_desc, 938 unsigned int socket_id __rte_unused, 939 const struct rte_eth_rxconf *rx_conf, 940 struct rte_mempool *mp) 941 { 942 struct dpaa_if *dpaa_intf = dev->data->dev_private; 943 struct fman_if *fif = dev->process_private; 944 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 945 struct qm_mcc_initfq opts = {0}; 946 u32 flags = 0; 947 int ret; 948 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 949 uint32_t max_rx_pktlen; 950 951 PMD_INIT_FUNC_TRACE(); 952 953 if (queue_idx >= dev->data->nb_rx_queues) { 954 rte_errno = EOVERFLOW; 955 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 956 (void *)dev, queue_idx, dev->data->nb_rx_queues); 957 return -rte_errno; 958 } 959 960 /* Rx deferred start is not supported */ 961 if (rx_conf->rx_deferred_start) { 962 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 963 return -EINVAL; 964 } 965 rxq->nb_desc = UINT16_MAX; 966 rxq->offloads = rx_conf->offloads; 967 968 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 969 queue_idx, rxq->fqid); 970 971 if (!fif->num_profiles) { 972 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 973 dpaa_intf->bp_info->mp != mp) { 974 DPAA_PMD_WARN("Multiple pools on same interface not" 975 " supported"); 976 return -EINVAL; 977 } 978 } else { 979 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 980 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 981 return -EINVAL; 982 } 983 } 984 985 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 986 dpaa_intf->bp_info->mp != mp) { 987 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 988 return -EINVAL; 989 } 990 991 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 992 VLAN_TAG_SIZE; 993 /* Max packet can fit in single buffer */ 994 if (max_rx_pktlen <= buffsz) { 995 ; 996 } else if (dev->data->dev_conf.rxmode.offloads & 997 RTE_ETH_RX_OFFLOAD_SCATTER) { 998 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 999 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 1000 "MaxSGlist %d", 1001 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 1002 rte_errno = EOVERFLOW; 1003 return -rte_errno; 1004 } 1005 } else { 1006 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 1007 " larger than a single mbuf (%u) and scattered" 1008 " mode has not been requested", max_rx_pktlen, buffsz); 1009 } 1010 1011 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 1012 1013 /* For shared interface, it's done in kernel, skip.*/ 1014 if (!fif->is_shared_mac) 1015 dpaa_fman_if_pool_setup(dev); 1016 1017 if (fif->num_profiles) { 1018 int8_t vsp_id = rxq->vsp_id; 1019 1020 if (vsp_id >= 0) { 1021 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 1022 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 1023 fif, buffsz + RTE_PKTMBUF_HEADROOM); 1024 if (ret) { 1025 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1026 return ret; 1027 } 1028 } else { 1029 DPAA_PMD_INFO("Base profile is associated to" 1030 " RXQ fqid:%d\r\n", rxq->fqid); 1031 if (fif->is_shared_mac) { 1032 DPAA_PMD_ERR("Fatal: Base profile is associated" 1033 " to shared interface on DPDK."); 1034 return -EINVAL; 1035 } 1036 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1037 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1038 } 1039 } else { 1040 dpaa_intf->vsp_bpid[0] = 1041 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1042 } 1043 1044 dpaa_intf->valid = 1; 1045 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1046 fman_if_get_sg_enable(fif), max_rx_pktlen); 1047 /* checking if push mode only, no error check for now */ 1048 if (!rxq->is_static && 1049 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1050 struct qman_portal *qp; 1051 int q_fd; 1052 1053 dpaa_push_queue_idx++; 1054 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1055 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1056 QM_FQCTRL_CTXASTASHING | 1057 QM_FQCTRL_PREFERINCACHE; 1058 opts.fqd.context_a.stashing.exclusive = 0; 1059 /* In multicore scenario stashing becomes a bottleneck on LS1046. 1060 * So do not enable stashing in this case 1061 */ 1062 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1063 opts.fqd.context_a.stashing.annotation_cl = 1064 DPAA_IF_RX_ANNOTATION_STASH; 1065 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1066 opts.fqd.context_a.stashing.context_cl = 1067 DPAA_IF_RX_CONTEXT_STASH; 1068 1069 /*Create a channel and associate given queue with the channel*/ 1070 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1071 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1072 opts.fqd.dest.channel = rxq->ch_id; 1073 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1074 flags = QMAN_INITFQ_FLAG_SCHED; 1075 1076 /* Configure tail drop */ 1077 if (dpaa_intf->cgr_rx) { 1078 opts.we_mask |= QM_INITFQ_WE_CGID; 1079 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1080 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1081 } 1082 ret = qman_init_fq(rxq, flags, &opts); 1083 if (ret) { 1084 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1085 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1086 return ret; 1087 } 1088 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1089 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1090 } else { 1091 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1092 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1093 } 1094 1095 rxq->is_static = true; 1096 1097 /* Allocate qman specific portals */ 1098 qp = fsl_qman_fq_portal_create(&q_fd); 1099 if (!qp) { 1100 DPAA_PMD_ERR("Unable to alloc fq portal"); 1101 return -1; 1102 } 1103 rxq->qp = qp; 1104 1105 /* Set up the device interrupt handler */ 1106 if (dev->intr_handle == NULL) { 1107 struct rte_dpaa_device *dpaa_dev; 1108 struct rte_device *rdev = dev->device; 1109 1110 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1111 device); 1112 dev->intr_handle = dpaa_dev->intr_handle; 1113 if (rte_intr_vec_list_alloc(dev->intr_handle, 1114 NULL, dpaa_push_mode_max_queue)) { 1115 DPAA_PMD_ERR("intr_vec alloc failed"); 1116 return -ENOMEM; 1117 } 1118 if (rte_intr_nb_efd_set(dev->intr_handle, 1119 dpaa_push_mode_max_queue)) 1120 return -rte_errno; 1121 1122 if (rte_intr_max_intr_set(dev->intr_handle, 1123 dpaa_push_mode_max_queue)) 1124 return -rte_errno; 1125 } 1126 1127 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1128 return -rte_errno; 1129 1130 if (rte_intr_vec_list_index_set(dev->intr_handle, 1131 queue_idx, queue_idx + 1)) 1132 return -rte_errno; 1133 1134 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1135 q_fd)) 1136 return -rte_errno; 1137 1138 rxq->q_fd = q_fd; 1139 } 1140 rxq->bp_array = rte_dpaa_bpid_info; 1141 dev->data->rx_queues[queue_idx] = rxq; 1142 1143 /* configure the CGR size as per the desc size */ 1144 if (dpaa_intf->cgr_rx) { 1145 struct qm_mcc_initcgr cgr_opts = {0}; 1146 1147 rxq->nb_desc = nb_desc; 1148 /* Enable tail drop with cgr on this queue */ 1149 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1150 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1151 if (ret) { 1152 DPAA_PMD_WARN( 1153 "rx taildrop modify fail on fqid %d (ret=%d)", 1154 rxq->fqid, ret); 1155 } 1156 } 1157 /* Enable main queue to receive error packets also by default */ 1158 fman_if_set_err_fqid(fif, rxq->fqid); 1159 return 0; 1160 } 1161 1162 int 1163 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1164 int eth_rx_queue_id, 1165 u16 ch_id, 1166 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1167 { 1168 int ret; 1169 u32 flags = 0; 1170 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1171 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1172 struct qm_mcc_initfq opts = {0}; 1173 1174 if (dpaa_push_mode_max_queue) 1175 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1176 "PUSH mode already enabled for first %d queues.\n" 1177 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1178 dpaa_push_mode_max_queue); 1179 1180 dpaa_poll_queue_default_config(&opts); 1181 1182 switch (queue_conf->ev.sched_type) { 1183 case RTE_SCHED_TYPE_ATOMIC: 1184 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1185 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1186 * configuration with HOLD_ACTIVE setting 1187 */ 1188 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1189 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1190 break; 1191 case RTE_SCHED_TYPE_ORDERED: 1192 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1193 return -1; 1194 default: 1195 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1196 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1197 break; 1198 } 1199 1200 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1201 opts.fqd.dest.channel = ch_id; 1202 opts.fqd.dest.wq = queue_conf->ev.priority; 1203 1204 if (dpaa_intf->cgr_rx) { 1205 opts.we_mask |= QM_INITFQ_WE_CGID; 1206 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1207 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1208 } 1209 1210 flags = QMAN_INITFQ_FLAG_SCHED; 1211 1212 ret = qman_init_fq(rxq, flags, &opts); 1213 if (ret) { 1214 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1215 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1216 return ret; 1217 } 1218 1219 /* copy configuration which needs to be filled during dequeue */ 1220 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1221 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1222 1223 return ret; 1224 } 1225 1226 int 1227 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1228 int eth_rx_queue_id) 1229 { 1230 struct qm_mcc_initfq opts = {0}; 1231 int ret; 1232 u32 flags = 0; 1233 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1234 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1235 1236 qman_retire_fq(rxq, NULL); 1237 qman_oos_fq(rxq); 1238 ret = qman_init_fq(rxq, flags, &opts); 1239 if (ret) { 1240 DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d", 1241 rxq->fqid, ret); 1242 } 1243 1244 rxq->cb.dqrr_dpdk_cb = NULL; 1245 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1246 1247 return 0; 1248 } 1249 1250 static 1251 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1252 uint16_t nb_desc __rte_unused, 1253 unsigned int socket_id __rte_unused, 1254 const struct rte_eth_txconf *tx_conf) 1255 { 1256 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1257 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1258 1259 PMD_INIT_FUNC_TRACE(); 1260 1261 /* Tx deferred start is not supported */ 1262 if (tx_conf->tx_deferred_start) { 1263 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1264 return -EINVAL; 1265 } 1266 txq->nb_desc = UINT16_MAX; 1267 txq->offloads = tx_conf->offloads; 1268 1269 if (queue_idx >= dev->data->nb_tx_queues) { 1270 rte_errno = EOVERFLOW; 1271 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1272 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1273 return -rte_errno; 1274 } 1275 1276 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1277 queue_idx, txq->fqid); 1278 dev->data->tx_queues[queue_idx] = txq; 1279 1280 return 0; 1281 } 1282 1283 static uint32_t 1284 dpaa_dev_rx_queue_count(void *rx_queue) 1285 { 1286 struct qman_fq *rxq = rx_queue; 1287 u32 frm_cnt = 0; 1288 1289 PMD_INIT_FUNC_TRACE(); 1290 1291 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1292 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1293 rx_queue, frm_cnt); 1294 } 1295 return frm_cnt; 1296 } 1297 1298 static int dpaa_link_down(struct rte_eth_dev *dev) 1299 { 1300 struct fman_if *fif = dev->process_private; 1301 struct __fman_if *__fif; 1302 1303 PMD_INIT_FUNC_TRACE(); 1304 1305 __fif = container_of(fif, struct __fman_if, __if); 1306 1307 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1308 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1309 else 1310 return dpaa_eth_dev_stop(dev); 1311 return 0; 1312 } 1313 1314 static int dpaa_link_up(struct rte_eth_dev *dev) 1315 { 1316 struct fman_if *fif = dev->process_private; 1317 struct __fman_if *__fif; 1318 1319 PMD_INIT_FUNC_TRACE(); 1320 1321 __fif = container_of(fif, struct __fman_if, __if); 1322 1323 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1324 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1325 else 1326 dpaa_eth_dev_start(dev); 1327 return 0; 1328 } 1329 1330 static int 1331 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1332 struct rte_eth_fc_conf *fc_conf) 1333 { 1334 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1335 struct rte_eth_fc_conf *net_fc; 1336 1337 PMD_INIT_FUNC_TRACE(); 1338 1339 if (!(dpaa_intf->fc_conf)) { 1340 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1341 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1342 if (!dpaa_intf->fc_conf) { 1343 DPAA_PMD_ERR("unable to save flow control info"); 1344 return -ENOMEM; 1345 } 1346 } 1347 net_fc = dpaa_intf->fc_conf; 1348 1349 if (fc_conf->high_water < fc_conf->low_water) { 1350 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1351 return -EINVAL; 1352 } 1353 1354 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1355 return 0; 1356 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1357 fc_conf->mode == RTE_ETH_FC_FULL) { 1358 fman_if_set_fc_threshold(dev->process_private, 1359 fc_conf->high_water, 1360 fc_conf->low_water, 1361 dpaa_intf->bp_info->bpid); 1362 if (fc_conf->pause_time) 1363 fman_if_set_fc_quanta(dev->process_private, 1364 fc_conf->pause_time); 1365 } 1366 1367 /* Save the information in dpaa device */ 1368 net_fc->pause_time = fc_conf->pause_time; 1369 net_fc->high_water = fc_conf->high_water; 1370 net_fc->low_water = fc_conf->low_water; 1371 net_fc->send_xon = fc_conf->send_xon; 1372 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1373 net_fc->mode = fc_conf->mode; 1374 net_fc->autoneg = fc_conf->autoneg; 1375 1376 return 0; 1377 } 1378 1379 static int 1380 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1381 struct rte_eth_fc_conf *fc_conf) 1382 { 1383 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1384 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1385 int ret; 1386 1387 PMD_INIT_FUNC_TRACE(); 1388 1389 if (net_fc) { 1390 fc_conf->pause_time = net_fc->pause_time; 1391 fc_conf->high_water = net_fc->high_water; 1392 fc_conf->low_water = net_fc->low_water; 1393 fc_conf->send_xon = net_fc->send_xon; 1394 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1395 fc_conf->mode = net_fc->mode; 1396 fc_conf->autoneg = net_fc->autoneg; 1397 return 0; 1398 } 1399 ret = fman_if_get_fc_threshold(dev->process_private); 1400 if (ret) { 1401 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1402 fc_conf->pause_time = 1403 fman_if_get_fc_quanta(dev->process_private); 1404 } else { 1405 fc_conf->mode = RTE_ETH_FC_NONE; 1406 } 1407 1408 return 0; 1409 } 1410 1411 static int 1412 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1413 struct rte_ether_addr *addr, 1414 uint32_t index, 1415 __rte_unused uint32_t pool) 1416 { 1417 int ret; 1418 1419 PMD_INIT_FUNC_TRACE(); 1420 1421 ret = fman_if_add_mac_addr(dev->process_private, 1422 addr->addr_bytes, index); 1423 1424 if (ret) 1425 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1426 return 0; 1427 } 1428 1429 static void 1430 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1431 uint32_t index) 1432 { 1433 PMD_INIT_FUNC_TRACE(); 1434 1435 fman_if_clear_mac_addr(dev->process_private, index); 1436 } 1437 1438 static int 1439 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1440 struct rte_ether_addr *addr) 1441 { 1442 int ret; 1443 1444 PMD_INIT_FUNC_TRACE(); 1445 1446 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1447 if (ret) 1448 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1449 1450 return ret; 1451 } 1452 1453 static int 1454 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1455 struct rte_eth_rss_conf *rss_conf) 1456 { 1457 struct rte_eth_dev_data *data = dev->data; 1458 struct rte_eth_conf *eth_conf = &data->dev_conf; 1459 1460 PMD_INIT_FUNC_TRACE(); 1461 1462 if (!(default_q || fmc_q)) { 1463 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1464 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1465 return -1; 1466 } 1467 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1468 } else { 1469 DPAA_PMD_ERR("Function not supported\n"); 1470 return -ENOTSUP; 1471 } 1472 return 0; 1473 } 1474 1475 static int 1476 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1477 struct rte_eth_rss_conf *rss_conf) 1478 { 1479 struct rte_eth_dev_data *data = dev->data; 1480 struct rte_eth_conf *eth_conf = &data->dev_conf; 1481 1482 /* dpaa does not support rss_key, so length should be 0*/ 1483 rss_conf->rss_key_len = 0; 1484 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1485 return 0; 1486 } 1487 1488 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1489 uint16_t queue_id) 1490 { 1491 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1492 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1493 1494 if (!rxq->is_static) 1495 return -EINVAL; 1496 1497 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1498 } 1499 1500 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1501 uint16_t queue_id) 1502 { 1503 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1504 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1505 uint32_t temp; 1506 ssize_t temp1; 1507 1508 if (!rxq->is_static) 1509 return -EINVAL; 1510 1511 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1512 1513 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1514 if (temp1 != sizeof(temp)) 1515 DPAA_PMD_DEBUG("read did not return anything"); 1516 1517 qman_fq_portal_thread_irq(rxq->qp); 1518 1519 return 0; 1520 } 1521 1522 static void 1523 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1524 struct rte_eth_rxq_info *qinfo) 1525 { 1526 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1527 struct qman_fq *rxq; 1528 int ret; 1529 1530 rxq = dev->data->rx_queues[queue_id]; 1531 1532 qinfo->mp = dpaa_intf->bp_info->mp; 1533 qinfo->scattered_rx = dev->data->scattered_rx; 1534 qinfo->nb_desc = rxq->nb_desc; 1535 1536 /* Report the HW Rx buffer length to user */ 1537 ret = fman_if_get_maxfrm(dev->process_private); 1538 if (ret > 0) 1539 qinfo->rx_buf_size = ret; 1540 1541 qinfo->conf.rx_free_thresh = 1; 1542 qinfo->conf.rx_drop_en = 1; 1543 qinfo->conf.rx_deferred_start = 0; 1544 qinfo->conf.offloads = rxq->offloads; 1545 } 1546 1547 static void 1548 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1549 struct rte_eth_txq_info *qinfo) 1550 { 1551 struct qman_fq *txq; 1552 1553 txq = dev->data->tx_queues[queue_id]; 1554 1555 qinfo->nb_desc = txq->nb_desc; 1556 qinfo->conf.tx_thresh.pthresh = 0; 1557 qinfo->conf.tx_thresh.hthresh = 0; 1558 qinfo->conf.tx_thresh.wthresh = 0; 1559 1560 qinfo->conf.tx_free_thresh = 0; 1561 qinfo->conf.tx_rs_thresh = 0; 1562 qinfo->conf.offloads = txq->offloads; 1563 qinfo->conf.tx_deferred_start = 0; 1564 } 1565 1566 static struct eth_dev_ops dpaa_devops = { 1567 .dev_configure = dpaa_eth_dev_configure, 1568 .dev_start = dpaa_eth_dev_start, 1569 .dev_stop = dpaa_eth_dev_stop, 1570 .dev_close = dpaa_eth_dev_close, 1571 .dev_infos_get = dpaa_eth_dev_info, 1572 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1573 1574 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1575 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1576 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1577 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1578 .rxq_info_get = dpaa_rxq_info_get, 1579 .txq_info_get = dpaa_txq_info_get, 1580 1581 .flow_ctrl_get = dpaa_flow_ctrl_get, 1582 .flow_ctrl_set = dpaa_flow_ctrl_set, 1583 1584 .link_update = dpaa_eth_link_update, 1585 .stats_get = dpaa_eth_stats_get, 1586 .xstats_get = dpaa_dev_xstats_get, 1587 .xstats_get_by_id = dpaa_xstats_get_by_id, 1588 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1589 .xstats_get_names = dpaa_xstats_get_names, 1590 .xstats_reset = dpaa_eth_stats_reset, 1591 .stats_reset = dpaa_eth_stats_reset, 1592 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1593 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1594 .allmulticast_enable = dpaa_eth_multicast_enable, 1595 .allmulticast_disable = dpaa_eth_multicast_disable, 1596 .mtu_set = dpaa_mtu_set, 1597 .dev_set_link_down = dpaa_link_down, 1598 .dev_set_link_up = dpaa_link_up, 1599 .mac_addr_add = dpaa_dev_add_mac_addr, 1600 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1601 .mac_addr_set = dpaa_dev_set_mac_addr, 1602 1603 .fw_version_get = dpaa_fw_version_get, 1604 1605 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1606 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1607 .rss_hash_update = dpaa_dev_rss_hash_update, 1608 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1609 }; 1610 1611 static bool 1612 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1613 { 1614 if (strcmp(dev->device->driver->name, 1615 drv->driver.name)) 1616 return false; 1617 1618 return true; 1619 } 1620 1621 static bool 1622 is_dpaa_supported(struct rte_eth_dev *dev) 1623 { 1624 return is_device_supported(dev, &rte_dpaa_pmd); 1625 } 1626 1627 int 1628 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1629 { 1630 struct rte_eth_dev *dev; 1631 1632 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1633 1634 dev = &rte_eth_devices[port]; 1635 1636 if (!is_dpaa_supported(dev)) 1637 return -ENOTSUP; 1638 1639 if (on) 1640 fman_if_loopback_enable(dev->process_private); 1641 else 1642 fman_if_loopback_disable(dev->process_private); 1643 1644 return 0; 1645 } 1646 1647 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1648 struct fman_if *fman_intf) 1649 { 1650 struct rte_eth_fc_conf *fc_conf; 1651 int ret; 1652 1653 PMD_INIT_FUNC_TRACE(); 1654 1655 if (!(dpaa_intf->fc_conf)) { 1656 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1657 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1658 if (!dpaa_intf->fc_conf) { 1659 DPAA_PMD_ERR("unable to save flow control info"); 1660 return -ENOMEM; 1661 } 1662 } 1663 fc_conf = dpaa_intf->fc_conf; 1664 ret = fman_if_get_fc_threshold(fman_intf); 1665 if (ret) { 1666 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1667 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1668 } else { 1669 fc_conf->mode = RTE_ETH_FC_NONE; 1670 } 1671 1672 return 0; 1673 } 1674 1675 /* Initialise an Rx FQ */ 1676 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1677 uint32_t fqid) 1678 { 1679 struct qm_mcc_initfq opts = {0}; 1680 int ret; 1681 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1682 struct qm_mcc_initcgr cgr_opts = { 1683 .we_mask = QM_CGR_WE_CS_THRES | 1684 QM_CGR_WE_CSTD_EN | 1685 QM_CGR_WE_MODE, 1686 .cgr = { 1687 .cstd_en = QM_CGR_EN, 1688 .mode = QMAN_CGR_MODE_FRAME 1689 } 1690 }; 1691 1692 if (fmc_q || default_q) { 1693 ret = qman_reserve_fqid(fqid); 1694 if (ret) { 1695 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1696 fqid, ret); 1697 return -EINVAL; 1698 } 1699 } 1700 1701 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1702 ret = qman_create_fq(fqid, flags, fq); 1703 if (ret) { 1704 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1705 fqid, ret); 1706 return ret; 1707 } 1708 fq->is_static = false; 1709 1710 dpaa_poll_queue_default_config(&opts); 1711 1712 if (cgr_rx) { 1713 /* Enable tail drop with cgr on this queue */ 1714 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1715 cgr_rx->cb = NULL; 1716 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1717 &cgr_opts); 1718 if (ret) { 1719 DPAA_PMD_WARN( 1720 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1721 fq->fqid, ret); 1722 goto without_cgr; 1723 } 1724 opts.we_mask |= QM_INITFQ_WE_CGID; 1725 opts.fqd.cgid = cgr_rx->cgrid; 1726 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1727 } 1728 without_cgr: 1729 ret = qman_init_fq(fq, 0, &opts); 1730 if (ret) 1731 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1732 return ret; 1733 } 1734 1735 /* Initialise a Tx FQ */ 1736 static int dpaa_tx_queue_init(struct qman_fq *fq, 1737 struct fman_if *fman_intf, 1738 struct qman_cgr *cgr_tx) 1739 { 1740 struct qm_mcc_initfq opts = {0}; 1741 struct qm_mcc_initcgr cgr_opts = { 1742 .we_mask = QM_CGR_WE_CS_THRES | 1743 QM_CGR_WE_CSTD_EN | 1744 QM_CGR_WE_MODE, 1745 .cgr = { 1746 .cstd_en = QM_CGR_EN, 1747 .mode = QMAN_CGR_MODE_FRAME 1748 } 1749 }; 1750 int ret; 1751 1752 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1753 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1754 if (ret) { 1755 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1756 return ret; 1757 } 1758 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1759 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1760 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1761 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1762 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1763 opts.fqd.context_b = 0; 1764 /* no tx-confirmation */ 1765 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1766 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1767 if (fman_ip_rev >= FMAN_V3) { 1768 /* Set B0V bit in contextA to set ASPID to 0 */ 1769 opts.fqd.context_a.hi |= 0x04000000; 1770 } 1771 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1772 1773 if (cgr_tx) { 1774 /* Enable tail drop with cgr on this queue */ 1775 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1776 td_tx_threshold, 0); 1777 cgr_tx->cb = NULL; 1778 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1779 &cgr_opts); 1780 if (ret) { 1781 DPAA_PMD_WARN( 1782 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1783 fq->fqid, ret); 1784 goto without_cgr; 1785 } 1786 opts.we_mask |= QM_INITFQ_WE_CGID; 1787 opts.fqd.cgid = cgr_tx->cgrid; 1788 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1789 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1790 td_tx_threshold); 1791 } 1792 without_cgr: 1793 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1794 if (ret) 1795 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1796 return ret; 1797 } 1798 1799 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1800 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1801 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1802 { 1803 struct qm_mcc_initfq opts = {0}; 1804 int ret; 1805 1806 PMD_INIT_FUNC_TRACE(); 1807 1808 ret = qman_reserve_fqid(fqid); 1809 if (ret) { 1810 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1811 fqid, ret); 1812 return -EINVAL; 1813 } 1814 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1815 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1816 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1817 if (ret) { 1818 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1819 fqid, ret); 1820 return ret; 1821 } 1822 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1823 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1824 ret = qman_init_fq(fq, 0, &opts); 1825 if (ret) 1826 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1827 fqid, ret); 1828 return ret; 1829 } 1830 #endif 1831 1832 /* Initialise a network interface */ 1833 static int 1834 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1835 { 1836 struct rte_dpaa_device *dpaa_device; 1837 struct fm_eth_port_cfg *cfg; 1838 struct dpaa_if *dpaa_intf; 1839 struct fman_if *fman_intf; 1840 int dev_id; 1841 1842 PMD_INIT_FUNC_TRACE(); 1843 1844 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1845 dev_id = dpaa_device->id.dev_id; 1846 cfg = dpaa_get_eth_port_cfg(dev_id); 1847 fman_intf = cfg->fman_if; 1848 eth_dev->process_private = fman_intf; 1849 1850 /* Plugging of UCODE burst API not supported in Secondary */ 1851 dpaa_intf = eth_dev->data->dev_private; 1852 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1853 if (dpaa_intf->cgr_tx) 1854 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1855 else 1856 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1857 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1858 qman_set_fq_lookup_table( 1859 dpaa_intf->rx_queues->qman_fq_lookup_table); 1860 #endif 1861 1862 return 0; 1863 } 1864 1865 /* Initialise a network interface */ 1866 static int 1867 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1868 { 1869 int num_rx_fqs, fqid; 1870 int loop, ret = 0; 1871 int dev_id; 1872 struct rte_dpaa_device *dpaa_device; 1873 struct dpaa_if *dpaa_intf; 1874 struct fm_eth_port_cfg *cfg; 1875 struct fman_if *fman_intf; 1876 struct fman_if_bpool *bp, *tmp_bp; 1877 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1878 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1879 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1880 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1881 int8_t vsp_id = -1; 1882 1883 PMD_INIT_FUNC_TRACE(); 1884 1885 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1886 dev_id = dpaa_device->id.dev_id; 1887 dpaa_intf = eth_dev->data->dev_private; 1888 cfg = dpaa_get_eth_port_cfg(dev_id); 1889 fman_intf = cfg->fman_if; 1890 1891 dpaa_intf->name = dpaa_device->name; 1892 1893 /* save fman_if & cfg in the interface structure */ 1894 eth_dev->process_private = fman_intf; 1895 dpaa_intf->ifid = dev_id; 1896 dpaa_intf->cfg = cfg; 1897 1898 memset((char *)dev_rx_fqids, 0, 1899 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1900 1901 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1902 1903 /* Initialize Rx FQ's */ 1904 if (default_q) { 1905 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1906 } else if (fmc_q) { 1907 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1908 dev_vspids, 1909 DPAA_MAX_NUM_PCD_QUEUES); 1910 if (num_rx_fqs < 0) { 1911 DPAA_PMD_ERR("%s FMC initializes failed!", 1912 dpaa_intf->name); 1913 goto free_rx; 1914 } 1915 if (!num_rx_fqs) { 1916 DPAA_PMD_WARN("%s is not configured by FMC.", 1917 dpaa_intf->name); 1918 } 1919 } else { 1920 /* FMCLESS mode, load balance to multiple cores.*/ 1921 num_rx_fqs = rte_lcore_count(); 1922 } 1923 1924 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1925 * queues. 1926 */ 1927 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1928 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1929 return -EINVAL; 1930 } 1931 1932 if (num_rx_fqs > 0) { 1933 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1934 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1935 if (!dpaa_intf->rx_queues) { 1936 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1937 return -ENOMEM; 1938 } 1939 } else { 1940 dpaa_intf->rx_queues = NULL; 1941 } 1942 1943 memset(cgrid, 0, sizeof(cgrid)); 1944 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1945 1946 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1947 * Tx tail drop is disabled. 1948 */ 1949 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1950 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1951 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1952 td_tx_threshold); 1953 /* if a very large value is being configured */ 1954 if (td_tx_threshold > UINT16_MAX) 1955 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1956 } 1957 1958 /* If congestion control is enabled globally*/ 1959 if (num_rx_fqs > 0 && td_threshold) { 1960 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1961 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1962 if (!dpaa_intf->cgr_rx) { 1963 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1964 ret = -ENOMEM; 1965 goto free_rx; 1966 } 1967 1968 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1969 if (ret != num_rx_fqs) { 1970 DPAA_PMD_WARN("insufficient CGRIDs available"); 1971 ret = -EINVAL; 1972 goto free_rx; 1973 } 1974 } else { 1975 dpaa_intf->cgr_rx = NULL; 1976 } 1977 1978 if (!fmc_q && !default_q) { 1979 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1980 num_rx_fqs, 0); 1981 if (ret < 0) { 1982 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1983 goto free_rx; 1984 } 1985 } 1986 1987 for (loop = 0; loop < num_rx_fqs; loop++) { 1988 if (default_q) 1989 fqid = cfg->rx_def; 1990 else 1991 fqid = dev_rx_fqids[loop]; 1992 1993 vsp_id = dev_vspids[loop]; 1994 1995 if (dpaa_intf->cgr_rx) 1996 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1997 1998 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1999 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 2000 fqid); 2001 if (ret) 2002 goto free_rx; 2003 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 2004 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 2005 } 2006 dpaa_intf->nb_rx_queues = num_rx_fqs; 2007 2008 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 2009 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 2010 MAX_DPAA_CORES, MAX_CACHELINE); 2011 if (!dpaa_intf->tx_queues) { 2012 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 2013 ret = -ENOMEM; 2014 goto free_rx; 2015 } 2016 2017 /* If congestion control is enabled globally*/ 2018 if (td_tx_threshold) { 2019 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 2020 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 2021 MAX_CACHELINE); 2022 if (!dpaa_intf->cgr_tx) { 2023 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 2024 ret = -ENOMEM; 2025 goto free_rx; 2026 } 2027 2028 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2029 1, 0); 2030 if (ret != MAX_DPAA_CORES) { 2031 DPAA_PMD_WARN("insufficient CGRIDs available"); 2032 ret = -EINVAL; 2033 goto free_rx; 2034 } 2035 } else { 2036 dpaa_intf->cgr_tx = NULL; 2037 } 2038 2039 2040 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2041 if (dpaa_intf->cgr_tx) 2042 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2043 2044 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2045 fman_intf, 2046 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2047 if (ret) 2048 goto free_tx; 2049 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2050 } 2051 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2052 2053 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2054 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2055 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2056 if (ret) { 2057 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2058 goto free_tx; 2059 } 2060 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2061 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2062 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2063 if (ret) { 2064 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2065 goto free_tx; 2066 } 2067 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2068 #endif 2069 2070 DPAA_PMD_DEBUG("All frame queues created"); 2071 2072 /* Get the initial configuration for flow control */ 2073 dpaa_fc_set_default(dpaa_intf, fman_intf); 2074 2075 /* reset bpool list, initialize bpool dynamically */ 2076 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2077 list_del(&bp->node); 2078 rte_free(bp); 2079 } 2080 2081 /* Populate ethdev structure */ 2082 eth_dev->dev_ops = &dpaa_devops; 2083 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2084 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2085 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2086 2087 /* Allocate memory for storing MAC addresses */ 2088 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2089 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2090 if (eth_dev->data->mac_addrs == NULL) { 2091 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2092 "store MAC addresses", 2093 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2094 ret = -ENOMEM; 2095 goto free_tx; 2096 } 2097 2098 /* copy the primary mac address */ 2099 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2100 2101 DPAA_PMD_INFO("net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT, 2102 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2103 2104 if (!fman_intf->is_shared_mac) { 2105 /* Configure error packet handling */ 2106 fman_if_receive_rx_errors(fman_intf, 2107 FM_FD_RX_STATUS_ERR_MASK); 2108 /* Disable RX mode */ 2109 fman_if_disable_rx(fman_intf); 2110 /* Disable promiscuous mode */ 2111 fman_if_promiscuous_disable(fman_intf); 2112 /* Disable multicast */ 2113 fman_if_reset_mcast_filter_table(fman_intf); 2114 /* Reset interface statistics */ 2115 fman_if_stats_reset(fman_intf); 2116 /* Disable SG by default */ 2117 fman_if_set_sg(fman_intf, 0); 2118 fman_if_set_maxfrm(fman_intf, 2119 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2120 } 2121 2122 return 0; 2123 2124 free_tx: 2125 rte_free(dpaa_intf->tx_queues); 2126 dpaa_intf->tx_queues = NULL; 2127 dpaa_intf->nb_tx_queues = 0; 2128 2129 free_rx: 2130 rte_free(dpaa_intf->cgr_rx); 2131 rte_free(dpaa_intf->cgr_tx); 2132 rte_free(dpaa_intf->rx_queues); 2133 dpaa_intf->rx_queues = NULL; 2134 dpaa_intf->nb_rx_queues = 0; 2135 return ret; 2136 } 2137 2138 static int 2139 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2140 struct rte_dpaa_device *dpaa_dev) 2141 { 2142 int diag; 2143 int ret; 2144 struct rte_eth_dev *eth_dev; 2145 2146 PMD_INIT_FUNC_TRACE(); 2147 2148 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2149 RTE_PKTMBUF_HEADROOM) { 2150 DPAA_PMD_ERR( 2151 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2152 RTE_PKTMBUF_HEADROOM, 2153 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2154 2155 return -1; 2156 } 2157 2158 /* In case of secondary process, the device is already configured 2159 * and no further action is required, except portal initialization 2160 * and verifying secondary attachment to port name. 2161 */ 2162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2163 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2164 if (!eth_dev) 2165 return -ENOMEM; 2166 eth_dev->device = &dpaa_dev->device; 2167 eth_dev->dev_ops = &dpaa_devops; 2168 2169 ret = dpaa_dev_init_secondary(eth_dev); 2170 if (ret != 0) { 2171 DPAA_PMD_ERR("secondary dev init failed"); 2172 return ret; 2173 } 2174 2175 rte_eth_dev_probing_finish(eth_dev); 2176 return 0; 2177 } 2178 2179 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2180 if (access("/tmp/fmc.bin", F_OK) == -1) { 2181 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2182 default_q = 1; 2183 } 2184 2185 if (!(default_q || fmc_q)) { 2186 if (dpaa_fm_init()) { 2187 DPAA_PMD_ERR("FM init failed\n"); 2188 return -1; 2189 } 2190 } 2191 2192 /* disabling the default push mode for LS1043 */ 2193 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2194 dpaa_push_mode_max_queue = 0; 2195 2196 /* if push mode queues to be enabled. Currently we are allowing 2197 * only one queue per thread. 2198 */ 2199 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2200 dpaa_push_mode_max_queue = 2201 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2202 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2203 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2204 } 2205 2206 is_global_init = 1; 2207 } 2208 2209 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2210 ret = rte_dpaa_portal_init((void *)1); 2211 if (ret) { 2212 DPAA_PMD_ERR("Unable to initialize portal"); 2213 return ret; 2214 } 2215 } 2216 2217 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2218 if (!eth_dev) 2219 return -ENOMEM; 2220 2221 eth_dev->data->dev_private = 2222 rte_zmalloc("ethdev private structure", 2223 sizeof(struct dpaa_if), 2224 RTE_CACHE_LINE_SIZE); 2225 if (!eth_dev->data->dev_private) { 2226 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2227 rte_eth_dev_release_port(eth_dev); 2228 return -ENOMEM; 2229 } 2230 2231 eth_dev->device = &dpaa_dev->device; 2232 dpaa_dev->eth_dev = eth_dev; 2233 2234 qman_ern_register_cb(dpaa_free_mbuf); 2235 2236 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2237 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2238 2239 /* Invoke PMD device initialization function */ 2240 diag = dpaa_dev_init(eth_dev); 2241 if (diag == 0) { 2242 if (!dpaa_tx_sg_pool) { 2243 dpaa_tx_sg_pool = 2244 rte_pktmbuf_pool_create("dpaa_mbuf_tx_sg_pool", 2245 DPAA_POOL_SIZE, 2246 DPAA_POOL_CACHE_SIZE, 0, 2247 DPAA_MAX_SGS * sizeof(struct qm_sg_entry), 2248 rte_socket_id()); 2249 if (dpaa_tx_sg_pool == NULL) { 2250 DPAA_PMD_ERR("SG pool creation failed\n"); 2251 return -ENOMEM; 2252 } 2253 } 2254 rte_eth_dev_probing_finish(eth_dev); 2255 dpaa_valid_dev++; 2256 return 0; 2257 } 2258 2259 rte_eth_dev_release_port(eth_dev); 2260 return diag; 2261 } 2262 2263 static int 2264 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2265 { 2266 struct rte_eth_dev *eth_dev; 2267 int ret; 2268 2269 PMD_INIT_FUNC_TRACE(); 2270 2271 eth_dev = dpaa_dev->eth_dev; 2272 dpaa_eth_dev_close(eth_dev); 2273 dpaa_valid_dev--; 2274 if (!dpaa_valid_dev) 2275 rte_mempool_free(dpaa_tx_sg_pool); 2276 ret = rte_eth_dev_release_port(eth_dev); 2277 2278 return ret; 2279 } 2280 2281 static void __attribute__((destructor(102))) dpaa_finish(void) 2282 { 2283 /* For secondary, primary will do all the cleanup */ 2284 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2285 return; 2286 2287 if (!(default_q || fmc_q)) { 2288 unsigned int i; 2289 2290 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2291 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2292 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2293 struct dpaa_if *dpaa_intf = 2294 dev->data->dev_private; 2295 struct fman_if *fif = 2296 dev->process_private; 2297 if (dpaa_intf->port_handle) 2298 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2299 DPAA_PMD_WARN("DPAA FM " 2300 "deconfig failed\n"); 2301 if (fif->num_profiles) { 2302 if (dpaa_port_vsp_cleanup(dpaa_intf, 2303 fif)) 2304 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2305 } 2306 } 2307 } 2308 if (is_global_init) 2309 if (dpaa_fm_term()) 2310 DPAA_PMD_WARN("DPAA FM term failed\n"); 2311 2312 is_global_init = 0; 2313 2314 DPAA_PMD_INFO("DPAA fman cleaned up"); 2315 } 2316 } 2317 2318 static struct rte_dpaa_driver rte_dpaa_pmd = { 2319 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2320 .drv_type = FSL_DPAA_ETH, 2321 .probe = rte_dpaa_probe, 2322 .remove = rte_dpaa_remove, 2323 }; 2324 2325 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2326 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2327