1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2019 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <rte_ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <rte_pmd_dpaa.h> 43 44 #include <fsl_usd.h> 45 #include <fsl_qman.h> 46 #include <fsl_bman.h> 47 #include <fsl_fman.h> 48 49 /* Supported Rx offloads */ 50 static uint64_t dev_rx_offloads_sup = 51 DEV_RX_OFFLOAD_JUMBO_FRAME | 52 DEV_RX_OFFLOAD_SCATTER; 53 54 /* Rx offloads which cannot be disabled */ 55 static uint64_t dev_rx_offloads_nodis = 56 DEV_RX_OFFLOAD_IPV4_CKSUM | 57 DEV_RX_OFFLOAD_UDP_CKSUM | 58 DEV_RX_OFFLOAD_TCP_CKSUM | 59 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 60 61 /* Supported Tx offloads */ 62 static uint64_t dev_tx_offloads_sup = 63 DEV_TX_OFFLOAD_MT_LOCKFREE | 64 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 DEV_TX_OFFLOAD_IPV4_CKSUM | 69 DEV_TX_OFFLOAD_UDP_CKSUM | 70 DEV_TX_OFFLOAD_TCP_CKSUM | 71 DEV_TX_OFFLOAD_SCTP_CKSUM | 72 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 73 DEV_TX_OFFLOAD_MULTI_SEGS; 74 75 /* Keep track of whether QMAN and BMAN have been globally initialized */ 76 static int is_global_init; 77 static int default_q; /* use default queue - FMC is not executed*/ 78 /* At present we only allow up to 4 push mode queues as default - as each of 79 * this queue need dedicated portal and we are short of portals. 80 */ 81 #define DPAA_MAX_PUSH_MODE_QUEUE 8 82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 83 84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 86 87 88 /* Per FQ Taildrop in frame count */ 89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 90 91 struct rte_dpaa_xstats_name_off { 92 char name[RTE_ETH_XSTATS_NAME_SIZE]; 93 uint32_t offset; 94 }; 95 96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 97 {"rx_align_err", 98 offsetof(struct dpaa_if_stats, raln)}, 99 {"rx_valid_pause", 100 offsetof(struct dpaa_if_stats, rxpf)}, 101 {"rx_fcs_err", 102 offsetof(struct dpaa_if_stats, rfcs)}, 103 {"rx_vlan_frame", 104 offsetof(struct dpaa_if_stats, rvlan)}, 105 {"rx_frame_err", 106 offsetof(struct dpaa_if_stats, rerr)}, 107 {"rx_drop_err", 108 offsetof(struct dpaa_if_stats, rdrp)}, 109 {"rx_undersized", 110 offsetof(struct dpaa_if_stats, rund)}, 111 {"rx_oversize_err", 112 offsetof(struct dpaa_if_stats, rovr)}, 113 {"rx_fragment_pkt", 114 offsetof(struct dpaa_if_stats, rfrg)}, 115 {"tx_valid_pause", 116 offsetof(struct dpaa_if_stats, txpf)}, 117 {"tx_fcs_err", 118 offsetof(struct dpaa_if_stats, terr)}, 119 {"tx_vlan_frame", 120 offsetof(struct dpaa_if_stats, tvlan)}, 121 {"rx_undersized", 122 offsetof(struct dpaa_if_stats, tund)}, 123 }; 124 125 static struct rte_dpaa_driver rte_dpaa_pmd; 126 127 static int 128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 129 130 static inline void 131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 132 { 133 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 134 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 135 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 136 QM_FQCTRL_PREFERINCACHE; 137 opts->fqd.context_a.stashing.exclusive = 0; 138 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 139 opts->fqd.context_a.stashing.annotation_cl = 140 DPAA_IF_RX_ANNOTATION_STASH; 141 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 142 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 143 } 144 145 static int 146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 147 { 148 struct dpaa_if *dpaa_intf = dev->data->dev_private; 149 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 150 + VLAN_TAG_SIZE; 151 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 152 153 PMD_INIT_FUNC_TRACE(); 154 155 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 156 return -EINVAL; 157 /* 158 * Refuse mtu that requires the support of scattered packets 159 * when this feature has not been enabled before. 160 */ 161 if (dev->data->min_rx_buf_size && 162 !dev->data->scattered_rx && frame_size > buffsz) { 163 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 164 return -EINVAL; 165 } 166 167 /* check <seg size> * <max_seg> >= max_frame */ 168 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 169 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 170 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 171 buffsz * DPAA_SGT_MAX_ENTRIES); 172 return -EINVAL; 173 } 174 175 if (frame_size > RTE_ETHER_MAX_LEN) 176 dev->data->dev_conf.rxmode.offloads &= 177 DEV_RX_OFFLOAD_JUMBO_FRAME; 178 else 179 dev->data->dev_conf.rxmode.offloads &= 180 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 181 182 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 183 184 fman_if_set_maxfrm(dpaa_intf->fif, frame_size); 185 186 return 0; 187 } 188 189 static int 190 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 191 { 192 struct dpaa_if *dpaa_intf = dev->data->dev_private; 193 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 194 uint64_t rx_offloads = eth_conf->rxmode.offloads; 195 uint64_t tx_offloads = eth_conf->txmode.offloads; 196 197 PMD_INIT_FUNC_TRACE(); 198 199 /* Rx offloads which are enabled by default */ 200 if (dev_rx_offloads_nodis & ~rx_offloads) { 201 DPAA_PMD_INFO( 202 "Some of rx offloads enabled by default - requested 0x%" PRIx64 203 " fixed are 0x%" PRIx64, 204 rx_offloads, dev_rx_offloads_nodis); 205 } 206 207 /* Tx offloads which are enabled by default */ 208 if (dev_tx_offloads_nodis & ~tx_offloads) { 209 DPAA_PMD_INFO( 210 "Some of tx offloads enabled by default - requested 0x%" PRIx64 211 " fixed are 0x%" PRIx64, 212 tx_offloads, dev_tx_offloads_nodis); 213 } 214 215 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 216 uint32_t max_len; 217 218 DPAA_PMD_DEBUG("enabling jumbo"); 219 220 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 221 DPAA_MAX_RX_PKT_LEN) 222 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 223 else { 224 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 225 "supported is %d", 226 dev->data->dev_conf.rxmode.max_rx_pkt_len, 227 DPAA_MAX_RX_PKT_LEN); 228 max_len = DPAA_MAX_RX_PKT_LEN; 229 } 230 231 fman_if_set_maxfrm(dpaa_intf->fif, max_len); 232 dev->data->mtu = max_len 233 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE; 234 } 235 236 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 237 DPAA_PMD_DEBUG("enabling scatter mode"); 238 fman_if_set_sg(dpaa_intf->fif, 1); 239 dev->data->scattered_rx = 1; 240 } 241 242 return 0; 243 } 244 245 static const uint32_t * 246 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 247 { 248 static const uint32_t ptypes[] = { 249 RTE_PTYPE_L2_ETHER, 250 RTE_PTYPE_L2_ETHER_VLAN, 251 RTE_PTYPE_L2_ETHER_ARP, 252 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 253 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 254 RTE_PTYPE_L4_ICMP, 255 RTE_PTYPE_L4_TCP, 256 RTE_PTYPE_L4_UDP, 257 RTE_PTYPE_L4_FRAG, 258 RTE_PTYPE_L4_TCP, 259 RTE_PTYPE_L4_UDP, 260 RTE_PTYPE_L4_SCTP 261 }; 262 263 PMD_INIT_FUNC_TRACE(); 264 265 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 266 return ptypes; 267 return NULL; 268 } 269 270 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 271 { 272 struct dpaa_if *dpaa_intf = dev->data->dev_private; 273 274 PMD_INIT_FUNC_TRACE(); 275 276 /* Change tx callback to the real one */ 277 dev->tx_pkt_burst = dpaa_eth_queue_tx; 278 fman_if_enable_rx(dpaa_intf->fif); 279 280 return 0; 281 } 282 283 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 284 { 285 struct dpaa_if *dpaa_intf = dev->data->dev_private; 286 287 PMD_INIT_FUNC_TRACE(); 288 289 fman_if_disable_rx(dpaa_intf->fif); 290 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 291 } 292 293 static void dpaa_eth_dev_close(struct rte_eth_dev *dev) 294 { 295 PMD_INIT_FUNC_TRACE(); 296 297 dpaa_eth_dev_stop(dev); 298 } 299 300 static int 301 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 302 char *fw_version, 303 size_t fw_size) 304 { 305 int ret; 306 FILE *svr_file = NULL; 307 unsigned int svr_ver = 0; 308 309 PMD_INIT_FUNC_TRACE(); 310 311 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 312 if (!svr_file) { 313 DPAA_PMD_ERR("Unable to open SoC device"); 314 return -ENOTSUP; /* Not supported on this infra */ 315 } 316 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 317 dpaa_svr_family = svr_ver & SVR_MASK; 318 else 319 DPAA_PMD_ERR("Unable to read SoC device"); 320 321 fclose(svr_file); 322 323 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 324 svr_ver, fman_ip_rev); 325 ret += 1; /* add the size of '\0' */ 326 327 if (fw_size < (uint32_t)ret) 328 return ret; 329 else 330 return 0; 331 } 332 333 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 334 struct rte_eth_dev_info *dev_info) 335 { 336 struct dpaa_if *dpaa_intf = dev->data->dev_private; 337 338 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 339 340 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 341 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 342 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 343 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 344 dev_info->max_hash_mac_addrs = 0; 345 dev_info->max_vfs = 0; 346 dev_info->max_vmdq_pools = ETH_16_POOLS; 347 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 348 349 if (dpaa_intf->fif->mac_type == fman_mac_1g) { 350 dev_info->speed_capa = ETH_LINK_SPEED_1G; 351 } else if (dpaa_intf->fif->mac_type == fman_mac_10g) { 352 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G); 353 } else { 354 DPAA_PMD_ERR("invalid link_speed: %s, %d", 355 dpaa_intf->name, dpaa_intf->fif->mac_type); 356 return -EINVAL; 357 } 358 359 dev_info->rx_offload_capa = dev_rx_offloads_sup | 360 dev_rx_offloads_nodis; 361 dev_info->tx_offload_capa = dev_tx_offloads_sup | 362 dev_tx_offloads_nodis; 363 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 364 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 365 366 return 0; 367 } 368 369 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 370 int wait_to_complete __rte_unused) 371 { 372 struct dpaa_if *dpaa_intf = dev->data->dev_private; 373 struct rte_eth_link *link = &dev->data->dev_link; 374 375 PMD_INIT_FUNC_TRACE(); 376 377 if (dpaa_intf->fif->mac_type == fman_mac_1g) 378 link->link_speed = ETH_SPEED_NUM_1G; 379 else if (dpaa_intf->fif->mac_type == fman_mac_10g) 380 link->link_speed = ETH_SPEED_NUM_10G; 381 else 382 DPAA_PMD_ERR("invalid link_speed: %s, %d", 383 dpaa_intf->name, dpaa_intf->fif->mac_type); 384 385 link->link_status = dpaa_intf->valid; 386 link->link_duplex = ETH_LINK_FULL_DUPLEX; 387 link->link_autoneg = ETH_LINK_AUTONEG; 388 return 0; 389 } 390 391 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 392 struct rte_eth_stats *stats) 393 { 394 struct dpaa_if *dpaa_intf = dev->data->dev_private; 395 396 PMD_INIT_FUNC_TRACE(); 397 398 fman_if_stats_get(dpaa_intf->fif, stats); 399 return 0; 400 } 401 402 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 403 { 404 struct dpaa_if *dpaa_intf = dev->data->dev_private; 405 406 PMD_INIT_FUNC_TRACE(); 407 408 fman_if_stats_reset(dpaa_intf->fif); 409 410 return 0; 411 } 412 413 static int 414 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 415 unsigned int n) 416 { 417 struct dpaa_if *dpaa_intf = dev->data->dev_private; 418 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 419 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 420 421 if (n < num) 422 return num; 423 424 if (xstats == NULL) 425 return 0; 426 427 fman_if_stats_get_all(dpaa_intf->fif, values, 428 sizeof(struct dpaa_if_stats) / 8); 429 430 for (i = 0; i < num; i++) { 431 xstats[i].id = i; 432 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 433 } 434 return i; 435 } 436 437 static int 438 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 439 struct rte_eth_xstat_name *xstats_names, 440 unsigned int limit) 441 { 442 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 443 444 if (limit < stat_cnt) 445 return stat_cnt; 446 447 if (xstats_names != NULL) 448 for (i = 0; i < stat_cnt; i++) 449 strlcpy(xstats_names[i].name, 450 dpaa_xstats_strings[i].name, 451 sizeof(xstats_names[i].name)); 452 453 return stat_cnt; 454 } 455 456 static int 457 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 458 uint64_t *values, unsigned int n) 459 { 460 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 461 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 462 463 if (!ids) { 464 struct dpaa_if *dpaa_intf = dev->data->dev_private; 465 466 if (n < stat_cnt) 467 return stat_cnt; 468 469 if (!values) 470 return 0; 471 472 fman_if_stats_get_all(dpaa_intf->fif, values_copy, 473 sizeof(struct dpaa_if_stats) / 8); 474 475 for (i = 0; i < stat_cnt; i++) 476 values[i] = 477 values_copy[dpaa_xstats_strings[i].offset / 8]; 478 479 return stat_cnt; 480 } 481 482 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 483 484 for (i = 0; i < n; i++) { 485 if (ids[i] >= stat_cnt) { 486 DPAA_PMD_ERR("id value isn't valid"); 487 return -1; 488 } 489 values[i] = values_copy[ids[i]]; 490 } 491 return n; 492 } 493 494 static int 495 dpaa_xstats_get_names_by_id( 496 struct rte_eth_dev *dev, 497 struct rte_eth_xstat_name *xstats_names, 498 const uint64_t *ids, 499 unsigned int limit) 500 { 501 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 502 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 503 504 if (!ids) 505 return dpaa_xstats_get_names(dev, xstats_names, limit); 506 507 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 508 509 for (i = 0; i < limit; i++) { 510 if (ids[i] >= stat_cnt) { 511 DPAA_PMD_ERR("id value isn't valid"); 512 return -1; 513 } 514 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 515 } 516 return limit; 517 } 518 519 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 520 { 521 struct dpaa_if *dpaa_intf = dev->data->dev_private; 522 523 PMD_INIT_FUNC_TRACE(); 524 525 fman_if_promiscuous_enable(dpaa_intf->fif); 526 527 return 0; 528 } 529 530 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 531 { 532 struct dpaa_if *dpaa_intf = dev->data->dev_private; 533 534 PMD_INIT_FUNC_TRACE(); 535 536 fman_if_promiscuous_disable(dpaa_intf->fif); 537 538 return 0; 539 } 540 541 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 542 { 543 struct dpaa_if *dpaa_intf = dev->data->dev_private; 544 545 PMD_INIT_FUNC_TRACE(); 546 547 fman_if_set_mcast_filter_table(dpaa_intf->fif); 548 549 return 0; 550 } 551 552 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 553 { 554 struct dpaa_if *dpaa_intf = dev->data->dev_private; 555 556 PMD_INIT_FUNC_TRACE(); 557 558 fman_if_reset_mcast_filter_table(dpaa_intf->fif); 559 560 return 0; 561 } 562 563 static 564 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 565 uint16_t nb_desc, 566 unsigned int socket_id __rte_unused, 567 const struct rte_eth_rxconf *rx_conf __rte_unused, 568 struct rte_mempool *mp) 569 { 570 struct dpaa_if *dpaa_intf = dev->data->dev_private; 571 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 572 struct qm_mcc_initfq opts = {0}; 573 u32 flags = 0; 574 int ret; 575 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 576 577 PMD_INIT_FUNC_TRACE(); 578 579 if (queue_idx >= dev->data->nb_rx_queues) { 580 rte_errno = EOVERFLOW; 581 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 582 (void *)dev, queue_idx, dev->data->nb_rx_queues); 583 return -rte_errno; 584 } 585 586 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 587 queue_idx, rxq->fqid); 588 589 /* Max packet can fit in single buffer */ 590 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { 591 ; 592 } else if (dev->data->dev_conf.rxmode.offloads & 593 DEV_RX_OFFLOAD_SCATTER) { 594 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > 595 buffsz * DPAA_SGT_MAX_ENTRIES) { 596 DPAA_PMD_ERR("max RxPkt size %d too big to fit " 597 "MaxSGlist %d", 598 dev->data->dev_conf.rxmode.max_rx_pkt_len, 599 buffsz * DPAA_SGT_MAX_ENTRIES); 600 rte_errno = EOVERFLOW; 601 return -rte_errno; 602 } 603 } else { 604 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 605 " larger than a single mbuf (%u) and scattered" 606 " mode has not been requested", 607 dev->data->dev_conf.rxmode.max_rx_pkt_len, 608 buffsz - RTE_PKTMBUF_HEADROOM); 609 } 610 611 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) { 612 struct fman_if_ic_params icp; 613 uint32_t fd_offset; 614 uint32_t bp_size; 615 616 if (!mp->pool_data) { 617 DPAA_PMD_ERR("Not an offloaded buffer pool!"); 618 return -1; 619 } 620 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 621 622 memset(&icp, 0, sizeof(icp)); 623 /* set ICEOF for to the default value , which is 0*/ 624 icp.iciof = DEFAULT_ICIOF; 625 icp.iceof = DEFAULT_RX_ICEOF; 626 icp.icsz = DEFAULT_ICSZ; 627 fman_if_set_ic_params(dpaa_intf->fif, &icp); 628 629 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 630 fman_if_set_fdoff(dpaa_intf->fif, fd_offset); 631 632 /* Buffer pool size should be equal to Dataroom Size*/ 633 bp_size = rte_pktmbuf_data_room_size(mp); 634 fman_if_set_bp(dpaa_intf->fif, mp->size, 635 dpaa_intf->bp_info->bpid, bp_size); 636 dpaa_intf->valid = 1; 637 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d", 638 dpaa_intf->name, fd_offset, 639 fman_if_get_fdoff(dpaa_intf->fif)); 640 } 641 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 642 fman_if_get_sg_enable(dpaa_intf->fif), 643 dev->data->dev_conf.rxmode.max_rx_pkt_len); 644 /* checking if push mode only, no error check for now */ 645 if (!rxq->is_static && 646 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 647 struct qman_portal *qp; 648 int q_fd; 649 650 dpaa_push_queue_idx++; 651 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 652 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 653 QM_FQCTRL_CTXASTASHING | 654 QM_FQCTRL_PREFERINCACHE; 655 opts.fqd.context_a.stashing.exclusive = 0; 656 /* In muticore scenario stashing becomes a bottleneck on LS1046. 657 * So do not enable stashing in this case 658 */ 659 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 660 opts.fqd.context_a.stashing.annotation_cl = 661 DPAA_IF_RX_ANNOTATION_STASH; 662 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 663 opts.fqd.context_a.stashing.context_cl = 664 DPAA_IF_RX_CONTEXT_STASH; 665 666 /*Create a channel and associate given queue with the channel*/ 667 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 668 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 669 opts.fqd.dest.channel = rxq->ch_id; 670 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 671 flags = QMAN_INITFQ_FLAG_SCHED; 672 673 /* Configure tail drop */ 674 if (dpaa_intf->cgr_rx) { 675 opts.we_mask |= QM_INITFQ_WE_CGID; 676 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 677 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 678 } 679 ret = qman_init_fq(rxq, flags, &opts); 680 if (ret) { 681 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 682 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 683 return ret; 684 } 685 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 686 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 687 } else { 688 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 689 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 690 } 691 692 rxq->is_static = true; 693 694 /* Allocate qman specific portals */ 695 qp = fsl_qman_fq_portal_create(&q_fd); 696 if (!qp) { 697 DPAA_PMD_ERR("Unable to alloc fq portal"); 698 return -1; 699 } 700 rxq->qp = qp; 701 702 /* Set up the device interrupt handler */ 703 if (!dev->intr_handle) { 704 struct rte_dpaa_device *dpaa_dev; 705 struct rte_device *rdev = dev->device; 706 707 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 708 device); 709 dev->intr_handle = &dpaa_dev->intr_handle; 710 dev->intr_handle->intr_vec = rte_zmalloc(NULL, 711 dpaa_push_mode_max_queue, 0); 712 if (!dev->intr_handle->intr_vec) { 713 DPAA_PMD_ERR("intr_vec alloc failed"); 714 return -ENOMEM; 715 } 716 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue; 717 dev->intr_handle->max_intr = dpaa_push_mode_max_queue; 718 } 719 720 dev->intr_handle->type = RTE_INTR_HANDLE_EXT; 721 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1; 722 dev->intr_handle->efds[queue_idx] = q_fd; 723 rxq->q_fd = q_fd; 724 } 725 rxq->bp_array = rte_dpaa_bpid_info; 726 dev->data->rx_queues[queue_idx] = rxq; 727 728 /* configure the CGR size as per the desc size */ 729 if (dpaa_intf->cgr_rx) { 730 struct qm_mcc_initcgr cgr_opts = {0}; 731 732 /* Enable tail drop with cgr on this queue */ 733 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 734 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 735 if (ret) { 736 DPAA_PMD_WARN( 737 "rx taildrop modify fail on fqid %d (ret=%d)", 738 rxq->fqid, ret); 739 } 740 } 741 742 return 0; 743 } 744 745 int 746 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 747 int eth_rx_queue_id, 748 u16 ch_id, 749 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 750 { 751 int ret; 752 u32 flags = 0; 753 struct dpaa_if *dpaa_intf = dev->data->dev_private; 754 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 755 struct qm_mcc_initfq opts = {0}; 756 757 if (dpaa_push_mode_max_queue) 758 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 759 "PUSH mode already enabled for first %d queues.\n" 760 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 761 dpaa_push_mode_max_queue); 762 763 dpaa_poll_queue_default_config(&opts); 764 765 switch (queue_conf->ev.sched_type) { 766 case RTE_SCHED_TYPE_ATOMIC: 767 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 768 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 769 * configuration with HOLD_ACTIVE setting 770 */ 771 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 772 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 773 break; 774 case RTE_SCHED_TYPE_ORDERED: 775 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 776 return -1; 777 default: 778 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 779 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 780 break; 781 } 782 783 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 784 opts.fqd.dest.channel = ch_id; 785 opts.fqd.dest.wq = queue_conf->ev.priority; 786 787 if (dpaa_intf->cgr_rx) { 788 opts.we_mask |= QM_INITFQ_WE_CGID; 789 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 790 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 791 } 792 793 flags = QMAN_INITFQ_FLAG_SCHED; 794 795 ret = qman_init_fq(rxq, flags, &opts); 796 if (ret) { 797 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 798 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 799 return ret; 800 } 801 802 /* copy configuration which needs to be filled during dequeue */ 803 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 804 dev->data->rx_queues[eth_rx_queue_id] = rxq; 805 806 return ret; 807 } 808 809 int 810 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 811 int eth_rx_queue_id) 812 { 813 struct qm_mcc_initfq opts; 814 int ret; 815 u32 flags = 0; 816 struct dpaa_if *dpaa_intf = dev->data->dev_private; 817 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 818 819 dpaa_poll_queue_default_config(&opts); 820 821 if (dpaa_intf->cgr_rx) { 822 opts.we_mask |= QM_INITFQ_WE_CGID; 823 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 824 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 825 } 826 827 ret = qman_init_fq(rxq, flags, &opts); 828 if (ret) { 829 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 830 rxq->fqid, ret); 831 } 832 833 rxq->cb.dqrr_dpdk_cb = NULL; 834 dev->data->rx_queues[eth_rx_queue_id] = NULL; 835 836 return 0; 837 } 838 839 static 840 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 841 { 842 PMD_INIT_FUNC_TRACE(); 843 } 844 845 static 846 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 847 uint16_t nb_desc __rte_unused, 848 unsigned int socket_id __rte_unused, 849 const struct rte_eth_txconf *tx_conf __rte_unused) 850 { 851 struct dpaa_if *dpaa_intf = dev->data->dev_private; 852 853 PMD_INIT_FUNC_TRACE(); 854 855 if (queue_idx >= dev->data->nb_tx_queues) { 856 rte_errno = EOVERFLOW; 857 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 858 (void *)dev, queue_idx, dev->data->nb_tx_queues); 859 return -rte_errno; 860 } 861 862 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 863 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid); 864 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; 865 return 0; 866 } 867 868 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 869 { 870 PMD_INIT_FUNC_TRACE(); 871 } 872 873 static uint32_t 874 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 875 { 876 struct dpaa_if *dpaa_intf = dev->data->dev_private; 877 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 878 u32 frm_cnt = 0; 879 880 PMD_INIT_FUNC_TRACE(); 881 882 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 883 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n", 884 rx_queue_id, frm_cnt); 885 } 886 return frm_cnt; 887 } 888 889 static int dpaa_link_down(struct rte_eth_dev *dev) 890 { 891 PMD_INIT_FUNC_TRACE(); 892 893 dpaa_eth_dev_stop(dev); 894 return 0; 895 } 896 897 static int dpaa_link_up(struct rte_eth_dev *dev) 898 { 899 PMD_INIT_FUNC_TRACE(); 900 901 dpaa_eth_dev_start(dev); 902 return 0; 903 } 904 905 static int 906 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 907 struct rte_eth_fc_conf *fc_conf) 908 { 909 struct dpaa_if *dpaa_intf = dev->data->dev_private; 910 struct rte_eth_fc_conf *net_fc; 911 912 PMD_INIT_FUNC_TRACE(); 913 914 if (!(dpaa_intf->fc_conf)) { 915 dpaa_intf->fc_conf = rte_zmalloc(NULL, 916 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 917 if (!dpaa_intf->fc_conf) { 918 DPAA_PMD_ERR("unable to save flow control info"); 919 return -ENOMEM; 920 } 921 } 922 net_fc = dpaa_intf->fc_conf; 923 924 if (fc_conf->high_water < fc_conf->low_water) { 925 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 926 return -EINVAL; 927 } 928 929 if (fc_conf->mode == RTE_FC_NONE) { 930 return 0; 931 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 932 fc_conf->mode == RTE_FC_FULL) { 933 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water, 934 fc_conf->low_water, 935 dpaa_intf->bp_info->bpid); 936 if (fc_conf->pause_time) 937 fman_if_set_fc_quanta(dpaa_intf->fif, 938 fc_conf->pause_time); 939 } 940 941 /* Save the information in dpaa device */ 942 net_fc->pause_time = fc_conf->pause_time; 943 net_fc->high_water = fc_conf->high_water; 944 net_fc->low_water = fc_conf->low_water; 945 net_fc->send_xon = fc_conf->send_xon; 946 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 947 net_fc->mode = fc_conf->mode; 948 net_fc->autoneg = fc_conf->autoneg; 949 950 return 0; 951 } 952 953 static int 954 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 955 struct rte_eth_fc_conf *fc_conf) 956 { 957 struct dpaa_if *dpaa_intf = dev->data->dev_private; 958 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 959 int ret; 960 961 PMD_INIT_FUNC_TRACE(); 962 963 if (net_fc) { 964 fc_conf->pause_time = net_fc->pause_time; 965 fc_conf->high_water = net_fc->high_water; 966 fc_conf->low_water = net_fc->low_water; 967 fc_conf->send_xon = net_fc->send_xon; 968 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 969 fc_conf->mode = net_fc->mode; 970 fc_conf->autoneg = net_fc->autoneg; 971 return 0; 972 } 973 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 974 if (ret) { 975 fc_conf->mode = RTE_FC_TX_PAUSE; 976 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 977 } else { 978 fc_conf->mode = RTE_FC_NONE; 979 } 980 981 return 0; 982 } 983 984 static int 985 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 986 struct rte_ether_addr *addr, 987 uint32_t index, 988 __rte_unused uint32_t pool) 989 { 990 int ret; 991 struct dpaa_if *dpaa_intf = dev->data->dev_private; 992 993 PMD_INIT_FUNC_TRACE(); 994 995 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index); 996 997 if (ret) 998 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:" 999 " err = %d", ret); 1000 return 0; 1001 } 1002 1003 static void 1004 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1005 uint32_t index) 1006 { 1007 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1008 1009 PMD_INIT_FUNC_TRACE(); 1010 1011 fman_if_clear_mac_addr(dpaa_intf->fif, index); 1012 } 1013 1014 static int 1015 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1016 struct rte_ether_addr *addr) 1017 { 1018 int ret; 1019 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1020 1021 PMD_INIT_FUNC_TRACE(); 1022 1023 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0); 1024 if (ret) 1025 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret); 1026 1027 return ret; 1028 } 1029 1030 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1031 uint16_t queue_id) 1032 { 1033 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1034 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1035 1036 if (!rxq->is_static) 1037 return -EINVAL; 1038 1039 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1040 } 1041 1042 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1043 uint16_t queue_id) 1044 { 1045 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1046 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1047 uint32_t temp; 1048 ssize_t temp1; 1049 1050 if (!rxq->is_static) 1051 return -EINVAL; 1052 1053 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1054 1055 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1056 if (temp1 != sizeof(temp)) 1057 DPAA_EVENTDEV_ERR("irq read error"); 1058 1059 qman_fq_portal_thread_irq(rxq->qp); 1060 1061 return 0; 1062 } 1063 1064 static struct eth_dev_ops dpaa_devops = { 1065 .dev_configure = dpaa_eth_dev_configure, 1066 .dev_start = dpaa_eth_dev_start, 1067 .dev_stop = dpaa_eth_dev_stop, 1068 .dev_close = dpaa_eth_dev_close, 1069 .dev_infos_get = dpaa_eth_dev_info, 1070 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1071 1072 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1073 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1074 .rx_queue_release = dpaa_eth_rx_queue_release, 1075 .tx_queue_release = dpaa_eth_tx_queue_release, 1076 .rx_queue_count = dpaa_dev_rx_queue_count, 1077 1078 .flow_ctrl_get = dpaa_flow_ctrl_get, 1079 .flow_ctrl_set = dpaa_flow_ctrl_set, 1080 1081 .link_update = dpaa_eth_link_update, 1082 .stats_get = dpaa_eth_stats_get, 1083 .xstats_get = dpaa_dev_xstats_get, 1084 .xstats_get_by_id = dpaa_xstats_get_by_id, 1085 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1086 .xstats_get_names = dpaa_xstats_get_names, 1087 .xstats_reset = dpaa_eth_stats_reset, 1088 .stats_reset = dpaa_eth_stats_reset, 1089 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1090 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1091 .allmulticast_enable = dpaa_eth_multicast_enable, 1092 .allmulticast_disable = dpaa_eth_multicast_disable, 1093 .mtu_set = dpaa_mtu_set, 1094 .dev_set_link_down = dpaa_link_down, 1095 .dev_set_link_up = dpaa_link_up, 1096 .mac_addr_add = dpaa_dev_add_mac_addr, 1097 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1098 .mac_addr_set = dpaa_dev_set_mac_addr, 1099 1100 .fw_version_get = dpaa_fw_version_get, 1101 1102 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1103 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1104 }; 1105 1106 static bool 1107 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1108 { 1109 if (strcmp(dev->device->driver->name, 1110 drv->driver.name)) 1111 return false; 1112 1113 return true; 1114 } 1115 1116 static bool 1117 is_dpaa_supported(struct rte_eth_dev *dev) 1118 { 1119 return is_device_supported(dev, &rte_dpaa_pmd); 1120 } 1121 1122 int 1123 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) 1124 { 1125 struct rte_eth_dev *dev; 1126 struct dpaa_if *dpaa_intf; 1127 1128 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1129 1130 dev = &rte_eth_devices[port]; 1131 1132 if (!is_dpaa_supported(dev)) 1133 return -ENOTSUP; 1134 1135 dpaa_intf = dev->data->dev_private; 1136 1137 if (on) 1138 fman_if_loopback_enable(dpaa_intf->fif); 1139 else 1140 fman_if_loopback_disable(dpaa_intf->fif); 1141 1142 return 0; 1143 } 1144 1145 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) 1146 { 1147 struct rte_eth_fc_conf *fc_conf; 1148 int ret; 1149 1150 PMD_INIT_FUNC_TRACE(); 1151 1152 if (!(dpaa_intf->fc_conf)) { 1153 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1154 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1155 if (!dpaa_intf->fc_conf) { 1156 DPAA_PMD_ERR("unable to save flow control info"); 1157 return -ENOMEM; 1158 } 1159 } 1160 fc_conf = dpaa_intf->fc_conf; 1161 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 1162 if (ret) { 1163 fc_conf->mode = RTE_FC_TX_PAUSE; 1164 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 1165 } else { 1166 fc_conf->mode = RTE_FC_NONE; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* Initialise an Rx FQ */ 1173 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1174 uint32_t fqid) 1175 { 1176 struct qm_mcc_initfq opts = {0}; 1177 int ret; 1178 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1179 struct qm_mcc_initcgr cgr_opts = { 1180 .we_mask = QM_CGR_WE_CS_THRES | 1181 QM_CGR_WE_CSTD_EN | 1182 QM_CGR_WE_MODE, 1183 .cgr = { 1184 .cstd_en = QM_CGR_EN, 1185 .mode = QMAN_CGR_MODE_FRAME 1186 } 1187 }; 1188 1189 if (fqid) { 1190 ret = qman_reserve_fqid(fqid); 1191 if (ret) { 1192 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d", 1193 fqid, ret); 1194 return -EINVAL; 1195 } 1196 } else { 1197 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 1198 } 1199 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1200 ret = qman_create_fq(fqid, flags, fq); 1201 if (ret) { 1202 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1203 fqid, ret); 1204 return ret; 1205 } 1206 fq->is_static = false; 1207 1208 dpaa_poll_queue_default_config(&opts); 1209 1210 if (cgr_rx) { 1211 /* Enable tail drop with cgr on this queue */ 1212 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1213 cgr_rx->cb = NULL; 1214 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1215 &cgr_opts); 1216 if (ret) { 1217 DPAA_PMD_WARN( 1218 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1219 fq->fqid, ret); 1220 goto without_cgr; 1221 } 1222 opts.we_mask |= QM_INITFQ_WE_CGID; 1223 opts.fqd.cgid = cgr_rx->cgrid; 1224 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1225 } 1226 without_cgr: 1227 ret = qman_init_fq(fq, 0, &opts); 1228 if (ret) 1229 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1230 return ret; 1231 } 1232 1233 /* Initialise a Tx FQ */ 1234 static int dpaa_tx_queue_init(struct qman_fq *fq, 1235 struct fman_if *fman_intf) 1236 { 1237 struct qm_mcc_initfq opts = {0}; 1238 int ret; 1239 1240 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1241 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1242 if (ret) { 1243 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1244 return ret; 1245 } 1246 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1247 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1248 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1249 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1250 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1251 opts.fqd.context_b = 0; 1252 /* no tx-confirmation */ 1253 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1254 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1255 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1256 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1257 if (ret) 1258 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1259 return ret; 1260 } 1261 1262 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1263 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1264 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1265 { 1266 struct qm_mcc_initfq opts = {0}; 1267 int ret; 1268 1269 PMD_INIT_FUNC_TRACE(); 1270 1271 ret = qman_reserve_fqid(fqid); 1272 if (ret) { 1273 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1274 fqid, ret); 1275 return -EINVAL; 1276 } 1277 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1278 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1279 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1280 if (ret) { 1281 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1282 fqid, ret); 1283 return ret; 1284 } 1285 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1286 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1287 ret = qman_init_fq(fq, 0, &opts); 1288 if (ret) 1289 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1290 fqid, ret); 1291 return ret; 1292 } 1293 #endif 1294 1295 /* Initialise a network interface */ 1296 static int 1297 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1298 { 1299 int num_rx_fqs, fqid; 1300 int loop, ret = 0; 1301 int dev_id; 1302 struct rte_dpaa_device *dpaa_device; 1303 struct dpaa_if *dpaa_intf; 1304 struct fm_eth_port_cfg *cfg; 1305 struct fman_if *fman_intf; 1306 struct fman_if_bpool *bp, *tmp_bp; 1307 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1308 1309 PMD_INIT_FUNC_TRACE(); 1310 1311 dpaa_intf = eth_dev->data->dev_private; 1312 /* For secondary processes, the primary has done all the work */ 1313 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1314 eth_dev->dev_ops = &dpaa_devops; 1315 /* Plugging of UCODE burst API not supported in Secondary */ 1316 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1317 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1318 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1319 qman_set_fq_lookup_table( 1320 dpaa_intf->rx_queues->qman_fq_lookup_table); 1321 #endif 1322 return 0; 1323 } 1324 1325 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1326 dev_id = dpaa_device->id.dev_id; 1327 dpaa_intf = eth_dev->data->dev_private; 1328 cfg = &dpaa_netcfg->port_cfg[dev_id]; 1329 fman_intf = cfg->fman_if; 1330 1331 dpaa_intf->name = dpaa_device->name; 1332 1333 /* save fman_if & cfg in the interface struture */ 1334 dpaa_intf->fif = fman_intf; 1335 dpaa_intf->ifid = dev_id; 1336 dpaa_intf->cfg = cfg; 1337 1338 /* Initialize Rx FQ's */ 1339 if (default_q) { 1340 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1341 } else { 1342 if (getenv("DPAA_NUM_RX_QUEUES")) 1343 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES")); 1344 else 1345 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1346 } 1347 1348 1349 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1350 * queues. 1351 */ 1352 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1353 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1354 return -EINVAL; 1355 } 1356 1357 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1358 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1359 if (!dpaa_intf->rx_queues) { 1360 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1361 return -ENOMEM; 1362 } 1363 1364 /* If congestion control is enabled globally*/ 1365 if (td_threshold) { 1366 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1367 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1368 if (!dpaa_intf->cgr_rx) { 1369 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1370 ret = -ENOMEM; 1371 goto free_rx; 1372 } 1373 1374 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1375 if (ret != num_rx_fqs) { 1376 DPAA_PMD_WARN("insufficient CGRIDs available"); 1377 ret = -EINVAL; 1378 goto free_rx; 1379 } 1380 } else { 1381 dpaa_intf->cgr_rx = NULL; 1382 } 1383 1384 for (loop = 0; loop < num_rx_fqs; loop++) { 1385 if (default_q) 1386 fqid = cfg->rx_def; 1387 else 1388 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx * 1389 DPAA_PCD_FQID_MULTIPLIER + loop; 1390 1391 if (dpaa_intf->cgr_rx) 1392 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1393 1394 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1395 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1396 fqid); 1397 if (ret) 1398 goto free_rx; 1399 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1400 } 1401 dpaa_intf->nb_rx_queues = num_rx_fqs; 1402 1403 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1404 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1405 MAX_DPAA_CORES, MAX_CACHELINE); 1406 if (!dpaa_intf->tx_queues) { 1407 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1408 ret = -ENOMEM; 1409 goto free_rx; 1410 } 1411 1412 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 1413 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1414 fman_intf); 1415 if (ret) 1416 goto free_tx; 1417 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1418 } 1419 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 1420 1421 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1422 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1423 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1424 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1425 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1426 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1427 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1428 #endif 1429 1430 DPAA_PMD_DEBUG("All frame queues created"); 1431 1432 /* Get the initial configuration for flow control */ 1433 dpaa_fc_set_default(dpaa_intf); 1434 1435 /* reset bpool list, initialize bpool dynamically */ 1436 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1437 list_del(&bp->node); 1438 rte_free(bp); 1439 } 1440 1441 /* Populate ethdev structure */ 1442 eth_dev->dev_ops = &dpaa_devops; 1443 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1444 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1445 1446 /* Allocate memory for storing MAC addresses */ 1447 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1448 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1449 if (eth_dev->data->mac_addrs == NULL) { 1450 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1451 "store MAC addresses", 1452 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1453 ret = -ENOMEM; 1454 goto free_tx; 1455 } 1456 1457 /* copy the primary mac address */ 1458 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1459 1460 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1461 dpaa_device->name, 1462 fman_intf->mac_addr.addr_bytes[0], 1463 fman_intf->mac_addr.addr_bytes[1], 1464 fman_intf->mac_addr.addr_bytes[2], 1465 fman_intf->mac_addr.addr_bytes[3], 1466 fman_intf->mac_addr.addr_bytes[4], 1467 fman_intf->mac_addr.addr_bytes[5]); 1468 1469 /* Disable RX mode */ 1470 fman_if_discard_rx_errors(fman_intf); 1471 fman_if_disable_rx(fman_intf); 1472 /* Disable promiscuous mode */ 1473 fman_if_promiscuous_disable(fman_intf); 1474 /* Disable multicast */ 1475 fman_if_reset_mcast_filter_table(fman_intf); 1476 /* Reset interface statistics */ 1477 fman_if_stats_reset(fman_intf); 1478 /* Disable SG by default */ 1479 fman_if_set_sg(fman_intf, 0); 1480 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 1481 1482 return 0; 1483 1484 free_tx: 1485 rte_free(dpaa_intf->tx_queues); 1486 dpaa_intf->tx_queues = NULL; 1487 dpaa_intf->nb_tx_queues = 0; 1488 1489 free_rx: 1490 rte_free(dpaa_intf->cgr_rx); 1491 rte_free(dpaa_intf->rx_queues); 1492 dpaa_intf->rx_queues = NULL; 1493 dpaa_intf->nb_rx_queues = 0; 1494 return ret; 1495 } 1496 1497 static int 1498 dpaa_dev_uninit(struct rte_eth_dev *dev) 1499 { 1500 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1501 int loop; 1502 1503 PMD_INIT_FUNC_TRACE(); 1504 1505 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1506 return -EPERM; 1507 1508 if (!dpaa_intf) { 1509 DPAA_PMD_WARN("Already closed or not started"); 1510 return -1; 1511 } 1512 1513 dpaa_eth_dev_close(dev); 1514 1515 /* release configuration memory */ 1516 if (dpaa_intf->fc_conf) 1517 rte_free(dpaa_intf->fc_conf); 1518 1519 /* Release RX congestion Groups */ 1520 if (dpaa_intf->cgr_rx) { 1521 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 1522 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 1523 1524 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 1525 dpaa_intf->nb_rx_queues); 1526 } 1527 1528 rte_free(dpaa_intf->cgr_rx); 1529 dpaa_intf->cgr_rx = NULL; 1530 1531 rte_free(dpaa_intf->rx_queues); 1532 dpaa_intf->rx_queues = NULL; 1533 1534 rte_free(dpaa_intf->tx_queues); 1535 dpaa_intf->tx_queues = NULL; 1536 1537 dev->dev_ops = NULL; 1538 dev->rx_pkt_burst = NULL; 1539 dev->tx_pkt_burst = NULL; 1540 1541 return 0; 1542 } 1543 1544 static int 1545 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, 1546 struct rte_dpaa_device *dpaa_dev) 1547 { 1548 int diag; 1549 int ret; 1550 struct rte_eth_dev *eth_dev; 1551 1552 PMD_INIT_FUNC_TRACE(); 1553 1554 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 1555 RTE_PKTMBUF_HEADROOM) { 1556 DPAA_PMD_ERR( 1557 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 1558 RTE_PKTMBUF_HEADROOM, 1559 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 1560 1561 return -1; 1562 } 1563 1564 /* In case of secondary process, the device is already configured 1565 * and no further action is required, except portal initialization 1566 * and verifying secondary attachment to port name. 1567 */ 1568 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1569 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1570 if (!eth_dev) 1571 return -ENOMEM; 1572 eth_dev->device = &dpaa_dev->device; 1573 eth_dev->dev_ops = &dpaa_devops; 1574 rte_eth_dev_probing_finish(eth_dev); 1575 return 0; 1576 } 1577 1578 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 1579 /* One time load of Qman/Bman drivers */ 1580 ret = qman_global_init(); 1581 if (ret) { 1582 DPAA_PMD_ERR("QMAN initialization failed: %d", 1583 ret); 1584 return ret; 1585 } 1586 ret = bman_global_init(); 1587 if (ret) { 1588 DPAA_PMD_ERR("BMAN initialization failed: %d", 1589 ret); 1590 return ret; 1591 } 1592 1593 if (access("/tmp/fmc.bin", F_OK) == -1) { 1594 RTE_LOG(INFO, PMD, 1595 "* FMC not configured.Enabling default mode\n"); 1596 default_q = 1; 1597 } 1598 1599 /* disabling the default push mode for LS1043 */ 1600 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 1601 dpaa_push_mode_max_queue = 0; 1602 1603 /* if push mode queues to be enabled. Currenly we are allowing 1604 * only one queue per thread. 1605 */ 1606 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 1607 dpaa_push_mode_max_queue = 1608 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 1609 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 1610 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 1611 } 1612 1613 is_global_init = 1; 1614 } 1615 1616 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 1617 ret = rte_dpaa_portal_init((void *)1); 1618 if (ret) { 1619 DPAA_PMD_ERR("Unable to initialize portal"); 1620 return ret; 1621 } 1622 } 1623 1624 /* In case of secondary process, the device is already configured 1625 * and no further action is required, except portal initialization 1626 * and verifying secondary attachment to port name. 1627 */ 1628 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1629 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1630 if (!eth_dev) 1631 return -ENOMEM; 1632 } else { 1633 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 1634 if (eth_dev == NULL) 1635 return -ENOMEM; 1636 1637 eth_dev->data->dev_private = rte_zmalloc( 1638 "ethdev private structure", 1639 sizeof(struct dpaa_if), 1640 RTE_CACHE_LINE_SIZE); 1641 if (!eth_dev->data->dev_private) { 1642 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 1643 rte_eth_dev_release_port(eth_dev); 1644 return -ENOMEM; 1645 } 1646 } 1647 eth_dev->device = &dpaa_dev->device; 1648 dpaa_dev->eth_dev = eth_dev; 1649 1650 /* Invoke PMD device initialization function */ 1651 diag = dpaa_dev_init(eth_dev); 1652 if (diag == 0) { 1653 rte_eth_dev_probing_finish(eth_dev); 1654 return 0; 1655 } 1656 1657 rte_eth_dev_release_port(eth_dev); 1658 return diag; 1659 } 1660 1661 static int 1662 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 1663 { 1664 struct rte_eth_dev *eth_dev; 1665 1666 PMD_INIT_FUNC_TRACE(); 1667 1668 eth_dev = dpaa_dev->eth_dev; 1669 dpaa_dev_uninit(eth_dev); 1670 1671 rte_eth_dev_release_port(eth_dev); 1672 1673 return 0; 1674 } 1675 1676 static struct rte_dpaa_driver rte_dpaa_pmd = { 1677 .drv_type = FSL_DPAA_ETH, 1678 .probe = rte_dpaa_probe, 1679 .remove = rte_dpaa_remove, 1680 }; 1681 1682 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 1683