xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.c (revision 8f1d23ece06adff5eae9f1b4365bdbbd3abee2b2)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4  *   Copyright 2017-2020 NXP
5  *
6  */
7 /* System headers */
8 #include <stdio.h>
9 #include <inttypes.h>
10 #include <unistd.h>
11 #include <limits.h>
12 #include <sched.h>
13 #include <signal.h>
14 #include <pthread.h>
15 #include <sys/types.h>
16 #include <sys/syscall.h>
17 
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
22 #include <rte_log.h>
23 #include <rte_debug.h>
24 #include <rte_pci.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
29 #include <rte_eal.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <ethdev_driver.h>
33 #include <rte_malloc.h>
34 #include <rte_ring.h>
35 
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
39 
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <dpaa_flow.h>
43 #include <rte_pmd_dpaa.h>
44 
45 #include <fsl_usd.h>
46 #include <fsl_qman.h>
47 #include <fsl_bman.h>
48 #include <fsl_fman.h>
49 #include <process.h>
50 #include <fmlib/fm_ext.h>
51 
52 #define CHECK_INTERVAL         100  /* 100ms */
53 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
54 
55 /* Supported Rx offloads */
56 static uint64_t dev_rx_offloads_sup =
57 		RTE_ETH_RX_OFFLOAD_SCATTER;
58 
59 /* Rx offloads which cannot be disabled */
60 static uint64_t dev_rx_offloads_nodis =
61 		RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
62 		RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
63 		RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
64 		RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
65 		RTE_ETH_RX_OFFLOAD_RSS_HASH;
66 
67 /* Supported Tx offloads */
68 static uint64_t dev_tx_offloads_sup =
69 		RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
70 		RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
71 
72 /* Tx offloads which cannot be disabled */
73 static uint64_t dev_tx_offloads_nodis =
74 		RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
75 		RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
76 		RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
77 		RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
78 		RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
79 		RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
80 
81 /* Keep track of whether QMAN and BMAN have been globally initialized */
82 static int is_global_init;
83 static int fmc_q = 1;	/* Indicates the use of static fmc for distribution */
84 static int default_q;	/* use default queue - FMC is not executed*/
85 /* At present we only allow up to 4 push mode queues as default - as each of
86  * this queue need dedicated portal and we are short of portals.
87  */
88 #define DPAA_MAX_PUSH_MODE_QUEUE       8
89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
90 
91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
93 
94 
95 /* Per RX FQ Taildrop in frame count */
96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
97 
98 /* Per TX FQ Taildrop in frame count, disabled by default */
99 static unsigned int td_tx_threshold;
100 
101 struct rte_dpaa_xstats_name_off {
102 	char name[RTE_ETH_XSTATS_NAME_SIZE];
103 	uint32_t offset;
104 };
105 
106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
107 	{"rx_align_err",
108 		offsetof(struct dpaa_if_stats, raln)},
109 	{"rx_valid_pause",
110 		offsetof(struct dpaa_if_stats, rxpf)},
111 	{"rx_fcs_err",
112 		offsetof(struct dpaa_if_stats, rfcs)},
113 	{"rx_vlan_frame",
114 		offsetof(struct dpaa_if_stats, rvlan)},
115 	{"rx_frame_err",
116 		offsetof(struct dpaa_if_stats, rerr)},
117 	{"rx_drop_err",
118 		offsetof(struct dpaa_if_stats, rdrp)},
119 	{"rx_undersized",
120 		offsetof(struct dpaa_if_stats, rund)},
121 	{"rx_oversize_err",
122 		offsetof(struct dpaa_if_stats, rovr)},
123 	{"rx_fragment_pkt",
124 		offsetof(struct dpaa_if_stats, rfrg)},
125 	{"tx_valid_pause",
126 		offsetof(struct dpaa_if_stats, txpf)},
127 	{"tx_fcs_err",
128 		offsetof(struct dpaa_if_stats, terr)},
129 	{"tx_vlan_frame",
130 		offsetof(struct dpaa_if_stats, tvlan)},
131 	{"rx_undersized",
132 		offsetof(struct dpaa_if_stats, tund)},
133 };
134 
135 static struct rte_dpaa_driver rte_dpaa_pmd;
136 
137 static int
138 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
139 
140 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
141 				int wait_to_complete __rte_unused);
142 
143 static void dpaa_interrupt_handler(void *param);
144 
145 static inline void
146 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
147 {
148 	memset(opts, 0, sizeof(struct qm_mcc_initfq));
149 	opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
150 	opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
151 			   QM_FQCTRL_PREFERINCACHE;
152 	opts->fqd.context_a.stashing.exclusive = 0;
153 	if (dpaa_svr_family != SVR_LS1046A_FAMILY)
154 		opts->fqd.context_a.stashing.annotation_cl =
155 						DPAA_IF_RX_ANNOTATION_STASH;
156 	opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
157 	opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
158 }
159 
160 static int
161 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
162 {
163 	uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
164 				+ VLAN_TAG_SIZE;
165 	uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
166 
167 	PMD_INIT_FUNC_TRACE();
168 
169 	/*
170 	 * Refuse mtu that requires the support of scattered packets
171 	 * when this feature has not been enabled before.
172 	 */
173 	if (dev->data->min_rx_buf_size &&
174 		!dev->data->scattered_rx && frame_size > buffsz) {
175 		DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
176 		return -EINVAL;
177 	}
178 
179 	/* check <seg size> * <max_seg>  >= max_frame */
180 	if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
181 		(frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
182 		DPAA_PMD_ERR("Too big to fit for Max SG list %d",
183 				buffsz * DPAA_SGT_MAX_ENTRIES);
184 		return -EINVAL;
185 	}
186 
187 	fman_if_set_maxfrm(dev->process_private, frame_size);
188 
189 	return 0;
190 }
191 
192 static int
193 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
194 {
195 	struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
196 	uint64_t rx_offloads = eth_conf->rxmode.offloads;
197 	uint64_t tx_offloads = eth_conf->txmode.offloads;
198 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
199 	struct rte_device *rdev = dev->device;
200 	struct rte_eth_link *link = &dev->data->dev_link;
201 	struct rte_dpaa_device *dpaa_dev;
202 	struct fman_if *fif = dev->process_private;
203 	struct __fman_if *__fif;
204 	struct rte_intr_handle *intr_handle;
205 	uint32_t max_rx_pktlen;
206 	int speed, duplex;
207 	int ret, rx_status;
208 
209 	PMD_INIT_FUNC_TRACE();
210 
211 	dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
212 	intr_handle = dpaa_dev->intr_handle;
213 	__fif = container_of(fif, struct __fman_if, __if);
214 
215 	/* Check if interface is enabled in case of shared MAC */
216 	if (fif->is_shared_mac) {
217 		rx_status = fman_if_get_rx_status(fif);
218 		if (!rx_status) {
219 			DPAA_PMD_ERR("%s Interface not enabled in kernel!",
220 				     dpaa_intf->name);
221 			return -EHOSTDOWN;
222 		}
223 	}
224 
225 	/* Rx offloads which are enabled by default */
226 	if (dev_rx_offloads_nodis & ~rx_offloads) {
227 		DPAA_PMD_INFO(
228 		"Some of rx offloads enabled by default - requested 0x%" PRIx64
229 		" fixed are 0x%" PRIx64,
230 		rx_offloads, dev_rx_offloads_nodis);
231 	}
232 
233 	/* Tx offloads which are enabled by default */
234 	if (dev_tx_offloads_nodis & ~tx_offloads) {
235 		DPAA_PMD_INFO(
236 		"Some of tx offloads enabled by default - requested 0x%" PRIx64
237 		" fixed are 0x%" PRIx64,
238 		tx_offloads, dev_tx_offloads_nodis);
239 	}
240 
241 	max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
242 			RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
243 	if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) {
244 		DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
245 			"supported is %d",
246 			max_rx_pktlen, DPAA_MAX_RX_PKT_LEN);
247 		max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
248 	}
249 
250 	fman_if_set_maxfrm(dev->process_private, max_rx_pktlen);
251 
252 	if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {
253 		DPAA_PMD_DEBUG("enabling scatter mode");
254 		fman_if_set_sg(dev->process_private, 1);
255 		dev->data->scattered_rx = 1;
256 	}
257 
258 	if (!(default_q || fmc_q)) {
259 		if (dpaa_fm_config(dev,
260 			eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
261 			dpaa_write_fm_config_to_file();
262 			DPAA_PMD_ERR("FM port configuration: Failed\n");
263 			return -1;
264 		}
265 		dpaa_write_fm_config_to_file();
266 	}
267 
268 	/* if the interrupts were configured on this devices*/
269 	if (intr_handle && rte_intr_fd_get(intr_handle)) {
270 		if (dev->data->dev_conf.intr_conf.lsc != 0)
271 			rte_intr_callback_register(intr_handle,
272 					   dpaa_interrupt_handler,
273 					   (void *)dev);
274 
275 		ret = dpaa_intr_enable(__fif->node_name,
276 				       rte_intr_fd_get(intr_handle));
277 		if (ret) {
278 			if (dev->data->dev_conf.intr_conf.lsc != 0) {
279 				rte_intr_callback_unregister(intr_handle,
280 					dpaa_interrupt_handler,
281 					(void *)dev);
282 				if (ret == EINVAL)
283 					printf("Failed to enable interrupt: Not Supported\n");
284 				else
285 					printf("Failed to enable interrupt\n");
286 			}
287 			dev->data->dev_conf.intr_conf.lsc = 0;
288 			dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
289 		}
290 	}
291 
292 	/* Wait for link status to get updated */
293 	if (!link->link_status)
294 		sleep(1);
295 
296 	/* Configure link only if link is UP*/
297 	if (link->link_status) {
298 		if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
299 			/* Start autoneg only if link is not in autoneg mode */
300 			if (!link->link_autoneg)
301 				dpaa_restart_link_autoneg(__fif->node_name);
302 		} else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
303 			switch (eth_conf->link_speeds &  RTE_ETH_LINK_SPEED_FIXED) {
304 			case RTE_ETH_LINK_SPEED_10M_HD:
305 				speed = RTE_ETH_SPEED_NUM_10M;
306 				duplex = RTE_ETH_LINK_HALF_DUPLEX;
307 				break;
308 			case RTE_ETH_LINK_SPEED_10M:
309 				speed = RTE_ETH_SPEED_NUM_10M;
310 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
311 				break;
312 			case RTE_ETH_LINK_SPEED_100M_HD:
313 				speed = RTE_ETH_SPEED_NUM_100M;
314 				duplex = RTE_ETH_LINK_HALF_DUPLEX;
315 				break;
316 			case RTE_ETH_LINK_SPEED_100M:
317 				speed = RTE_ETH_SPEED_NUM_100M;
318 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
319 				break;
320 			case RTE_ETH_LINK_SPEED_1G:
321 				speed = RTE_ETH_SPEED_NUM_1G;
322 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
323 				break;
324 			case RTE_ETH_LINK_SPEED_2_5G:
325 				speed = RTE_ETH_SPEED_NUM_2_5G;
326 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
327 				break;
328 			case RTE_ETH_LINK_SPEED_10G:
329 				speed = RTE_ETH_SPEED_NUM_10G;
330 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
331 				break;
332 			default:
333 				speed = RTE_ETH_SPEED_NUM_NONE;
334 				duplex = RTE_ETH_LINK_FULL_DUPLEX;
335 				break;
336 			}
337 			/* Set link speed */
338 			dpaa_update_link_speed(__fif->node_name, speed, duplex);
339 		} else {
340 			/* Manual autoneg - custom advertisement speed. */
341 			printf("Custom Advertisement speeds not supported\n");
342 		}
343 	}
344 
345 	return 0;
346 }
347 
348 static const uint32_t *
349 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
350 {
351 	static const uint32_t ptypes[] = {
352 		RTE_PTYPE_L2_ETHER,
353 		RTE_PTYPE_L2_ETHER_VLAN,
354 		RTE_PTYPE_L2_ETHER_ARP,
355 		RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
356 		RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
357 		RTE_PTYPE_L4_ICMP,
358 		RTE_PTYPE_L4_TCP,
359 		RTE_PTYPE_L4_UDP,
360 		RTE_PTYPE_L4_FRAG,
361 		RTE_PTYPE_L4_TCP,
362 		RTE_PTYPE_L4_UDP,
363 		RTE_PTYPE_L4_SCTP
364 	};
365 
366 	PMD_INIT_FUNC_TRACE();
367 
368 	if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
369 		return ptypes;
370 	return NULL;
371 }
372 
373 static void dpaa_interrupt_handler(void *param)
374 {
375 	struct rte_eth_dev *dev = param;
376 	struct rte_device *rdev = dev->device;
377 	struct rte_dpaa_device *dpaa_dev;
378 	struct rte_intr_handle *intr_handle;
379 	uint64_t buf;
380 	int bytes_read;
381 
382 	dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
383 	intr_handle = dpaa_dev->intr_handle;
384 
385 	if (rte_intr_fd_get(intr_handle) < 0)
386 		return;
387 
388 	bytes_read = read(rte_intr_fd_get(intr_handle), &buf,
389 			  sizeof(uint64_t));
390 	if (bytes_read < 0)
391 		DPAA_PMD_ERR("Error reading eventfd\n");
392 	dpaa_eth_link_update(dev, 0);
393 	rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
394 }
395 
396 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
397 {
398 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
399 
400 	PMD_INIT_FUNC_TRACE();
401 
402 	if (!(default_q || fmc_q))
403 		dpaa_write_fm_config_to_file();
404 
405 	/* Change tx callback to the real one */
406 	if (dpaa_intf->cgr_tx)
407 		dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
408 	else
409 		dev->tx_pkt_burst = dpaa_eth_queue_tx;
410 
411 	fman_if_enable_rx(dev->process_private);
412 
413 	return 0;
414 }
415 
416 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev)
417 {
418 	struct fman_if *fif = dev->process_private;
419 
420 	PMD_INIT_FUNC_TRACE();
421 	dev->data->dev_started = 0;
422 
423 	if (!fif->is_shared_mac)
424 		fman_if_disable_rx(fif);
425 	dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
426 
427 	return 0;
428 }
429 
430 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
431 {
432 	struct fman_if *fif = dev->process_private;
433 	struct __fman_if *__fif;
434 	struct rte_device *rdev = dev->device;
435 	struct rte_dpaa_device *dpaa_dev;
436 	struct rte_intr_handle *intr_handle;
437 	struct rte_eth_link *link = &dev->data->dev_link;
438 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
439 	int loop;
440 	int ret;
441 
442 	PMD_INIT_FUNC_TRACE();
443 
444 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
445 		return 0;
446 
447 	if (!dpaa_intf) {
448 		DPAA_PMD_WARN("Already closed or not started");
449 		return -1;
450 	}
451 
452 	/* DPAA FM deconfig */
453 	if (!(default_q || fmc_q)) {
454 		if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
455 			DPAA_PMD_WARN("DPAA FM deconfig failed\n");
456 	}
457 
458 	dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
459 	intr_handle = dpaa_dev->intr_handle;
460 	__fif = container_of(fif, struct __fman_if, __if);
461 
462 	ret = dpaa_eth_dev_stop(dev);
463 
464 	/* Reset link to autoneg */
465 	if (link->link_status && !link->link_autoneg)
466 		dpaa_restart_link_autoneg(__fif->node_name);
467 
468 	if (intr_handle && rte_intr_fd_get(intr_handle) &&
469 	    dev->data->dev_conf.intr_conf.lsc != 0) {
470 		dpaa_intr_disable(__fif->node_name);
471 		rte_intr_callback_unregister(intr_handle,
472 					     dpaa_interrupt_handler,
473 					     (void *)dev);
474 	}
475 
476 	/* release configuration memory */
477 	rte_free(dpaa_intf->fc_conf);
478 
479 	/* Release RX congestion Groups */
480 	if (dpaa_intf->cgr_rx) {
481 		for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
482 			qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
483 	}
484 
485 	rte_free(dpaa_intf->cgr_rx);
486 	dpaa_intf->cgr_rx = NULL;
487 	/* Release TX congestion Groups */
488 	if (dpaa_intf->cgr_tx) {
489 		for (loop = 0; loop < MAX_DPAA_CORES; loop++)
490 			qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
491 		rte_free(dpaa_intf->cgr_tx);
492 		dpaa_intf->cgr_tx = NULL;
493 	}
494 
495 	rte_free(dpaa_intf->rx_queues);
496 	dpaa_intf->rx_queues = NULL;
497 
498 	rte_free(dpaa_intf->tx_queues);
499 	dpaa_intf->tx_queues = NULL;
500 
501 	return ret;
502 }
503 
504 static int
505 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
506 		     char *fw_version,
507 		     size_t fw_size)
508 {
509 	int ret;
510 	FILE *svr_file = NULL;
511 	unsigned int svr_ver = 0;
512 
513 	PMD_INIT_FUNC_TRACE();
514 
515 	svr_file = fopen(DPAA_SOC_ID_FILE, "r");
516 	if (!svr_file) {
517 		DPAA_PMD_ERR("Unable to open SoC device");
518 		return -ENOTSUP; /* Not supported on this infra */
519 	}
520 	if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
521 		dpaa_svr_family = svr_ver & SVR_MASK;
522 	else
523 		DPAA_PMD_ERR("Unable to read SoC device");
524 
525 	fclose(svr_file);
526 
527 	ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
528 		       svr_ver, fman_ip_rev);
529 	if (ret < 0)
530 		return -EINVAL;
531 
532 	ret += 1; /* add the size of '\0' */
533 	if (fw_size < (size_t)ret)
534 		return ret;
535 	else
536 		return 0;
537 }
538 
539 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
540 			     struct rte_eth_dev_info *dev_info)
541 {
542 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
543 	struct fman_if *fif = dev->process_private;
544 
545 	DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
546 
547 	dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
548 	dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
549 	dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
550 	dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
551 	dev_info->max_hash_mac_addrs = 0;
552 	dev_info->max_vfs = 0;
553 	dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
554 	dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
555 
556 	if (fif->mac_type == fman_mac_1g) {
557 		dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
558 					| RTE_ETH_LINK_SPEED_10M
559 					| RTE_ETH_LINK_SPEED_100M_HD
560 					| RTE_ETH_LINK_SPEED_100M
561 					| RTE_ETH_LINK_SPEED_1G;
562 	} else if (fif->mac_type == fman_mac_2_5g) {
563 		dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
564 					| RTE_ETH_LINK_SPEED_10M
565 					| RTE_ETH_LINK_SPEED_100M_HD
566 					| RTE_ETH_LINK_SPEED_100M
567 					| RTE_ETH_LINK_SPEED_1G
568 					| RTE_ETH_LINK_SPEED_2_5G;
569 	} else if (fif->mac_type == fman_mac_10g) {
570 		dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
571 					| RTE_ETH_LINK_SPEED_10M
572 					| RTE_ETH_LINK_SPEED_100M_HD
573 					| RTE_ETH_LINK_SPEED_100M
574 					| RTE_ETH_LINK_SPEED_1G
575 					| RTE_ETH_LINK_SPEED_2_5G
576 					| RTE_ETH_LINK_SPEED_10G;
577 	} else {
578 		DPAA_PMD_ERR("invalid link_speed: %s, %d",
579 			     dpaa_intf->name, fif->mac_type);
580 		return -EINVAL;
581 	}
582 
583 	dev_info->rx_offload_capa = dev_rx_offloads_sup |
584 					dev_rx_offloads_nodis;
585 	dev_info->tx_offload_capa = dev_tx_offloads_sup |
586 					dev_tx_offloads_nodis;
587 	dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
588 	dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
589 	dev_info->default_rxportconf.nb_queues = 1;
590 	dev_info->default_txportconf.nb_queues = 1;
591 	dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
592 	dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
593 
594 	return 0;
595 }
596 
597 static int
598 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
599 			__rte_unused uint16_t queue_id,
600 			struct rte_eth_burst_mode *mode)
601 {
602 	struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
603 	int ret = -EINVAL;
604 	unsigned int i;
605 	const struct burst_info {
606 		uint64_t flags;
607 		const char *output;
608 	} rx_offload_map[] = {
609 			{RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"},
610 			{RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
611 			{RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
612 			{RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
613 			{RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
614 			{RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}
615 	};
616 
617 	/* Update Rx offload info */
618 	for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
619 		if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
620 			snprintf(mode->info, sizeof(mode->info), "%s",
621 				rx_offload_map[i].output);
622 			ret = 0;
623 			break;
624 		}
625 	}
626 	return ret;
627 }
628 
629 static int
630 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
631 			__rte_unused uint16_t queue_id,
632 			struct rte_eth_burst_mode *mode)
633 {
634 	struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
635 	int ret = -EINVAL;
636 	unsigned int i;
637 	const struct burst_info {
638 		uint64_t flags;
639 		const char *output;
640 	} tx_offload_map[] = {
641 			{RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
642 			{RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
643 			{RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
644 			{RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
645 			{RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
646 			{RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
647 			{RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
648 			{RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
649 	};
650 
651 	/* Update Tx offload info */
652 	for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
653 		if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
654 			snprintf(mode->info, sizeof(mode->info), "%s",
655 				tx_offload_map[i].output);
656 			ret = 0;
657 			break;
658 		}
659 	}
660 	return ret;
661 }
662 
663 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
664 				int wait_to_complete)
665 {
666 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
667 	struct rte_eth_link *link = &dev->data->dev_link;
668 	struct fman_if *fif = dev->process_private;
669 	struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
670 	int ret, ioctl_version;
671 	uint8_t count;
672 
673 	PMD_INIT_FUNC_TRACE();
674 
675 	ioctl_version = dpaa_get_ioctl_version_number();
676 
677 	if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
678 		for (count = 0; count <= MAX_REPEAT_TIME; count++) {
679 			ret = dpaa_get_link_status(__fif->node_name, link);
680 			if (ret)
681 				return ret;
682 			if (link->link_status == RTE_ETH_LINK_DOWN &&
683 			    wait_to_complete)
684 				rte_delay_ms(CHECK_INTERVAL);
685 			else
686 				break;
687 		}
688 	} else {
689 		link->link_status = dpaa_intf->valid;
690 	}
691 
692 	if (ioctl_version < 2) {
693 		link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
694 		link->link_autoneg = RTE_ETH_LINK_AUTONEG;
695 
696 		if (fif->mac_type == fman_mac_1g)
697 			link->link_speed = RTE_ETH_SPEED_NUM_1G;
698 		else if (fif->mac_type == fman_mac_2_5g)
699 			link->link_speed = RTE_ETH_SPEED_NUM_2_5G;
700 		else if (fif->mac_type == fman_mac_10g)
701 			link->link_speed = RTE_ETH_SPEED_NUM_10G;
702 		else
703 			DPAA_PMD_ERR("invalid link_speed: %s, %d",
704 				     dpaa_intf->name, fif->mac_type);
705 	}
706 
707 	DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
708 		      link->link_status ? "Up" : "Down");
709 	return 0;
710 }
711 
712 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
713 			       struct rte_eth_stats *stats)
714 {
715 	PMD_INIT_FUNC_TRACE();
716 
717 	fman_if_stats_get(dev->process_private, stats);
718 	return 0;
719 }
720 
721 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
722 {
723 	PMD_INIT_FUNC_TRACE();
724 
725 	fman_if_stats_reset(dev->process_private);
726 
727 	return 0;
728 }
729 
730 static int
731 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
732 		    unsigned int n)
733 {
734 	unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
735 	uint64_t values[sizeof(struct dpaa_if_stats) / 8];
736 
737 	if (n < num)
738 		return num;
739 
740 	if (xstats == NULL)
741 		return 0;
742 
743 	fman_if_stats_get_all(dev->process_private, values,
744 			      sizeof(struct dpaa_if_stats) / 8);
745 
746 	for (i = 0; i < num; i++) {
747 		xstats[i].id = i;
748 		xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
749 	}
750 	return i;
751 }
752 
753 static int
754 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
755 		      struct rte_eth_xstat_name *xstats_names,
756 		      unsigned int limit)
757 {
758 	unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
759 
760 	if (limit < stat_cnt)
761 		return stat_cnt;
762 
763 	if (xstats_names != NULL)
764 		for (i = 0; i < stat_cnt; i++)
765 			strlcpy(xstats_names[i].name,
766 				dpaa_xstats_strings[i].name,
767 				sizeof(xstats_names[i].name));
768 
769 	return stat_cnt;
770 }
771 
772 static int
773 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
774 		      uint64_t *values, unsigned int n)
775 {
776 	unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
777 	uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
778 
779 	if (!ids) {
780 		if (n < stat_cnt)
781 			return stat_cnt;
782 
783 		if (!values)
784 			return 0;
785 
786 		fman_if_stats_get_all(dev->process_private, values_copy,
787 				      sizeof(struct dpaa_if_stats) / 8);
788 
789 		for (i = 0; i < stat_cnt; i++)
790 			values[i] =
791 				values_copy[dpaa_xstats_strings[i].offset / 8];
792 
793 		return stat_cnt;
794 	}
795 
796 	dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
797 
798 	for (i = 0; i < n; i++) {
799 		if (ids[i] >= stat_cnt) {
800 			DPAA_PMD_ERR("id value isn't valid");
801 			return -1;
802 		}
803 		values[i] = values_copy[ids[i]];
804 	}
805 	return n;
806 }
807 
808 static int
809 dpaa_xstats_get_names_by_id(
810 	struct rte_eth_dev *dev,
811 	const uint64_t *ids,
812 	struct rte_eth_xstat_name *xstats_names,
813 	unsigned int limit)
814 {
815 	unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
816 	struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
817 
818 	if (!ids)
819 		return dpaa_xstats_get_names(dev, xstats_names, limit);
820 
821 	dpaa_xstats_get_names(dev, xstats_names_copy, limit);
822 
823 	for (i = 0; i < limit; i++) {
824 		if (ids[i] >= stat_cnt) {
825 			DPAA_PMD_ERR("id value isn't valid");
826 			return -1;
827 		}
828 		strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
829 	}
830 	return limit;
831 }
832 
833 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
834 {
835 	PMD_INIT_FUNC_TRACE();
836 
837 	fman_if_promiscuous_enable(dev->process_private);
838 
839 	return 0;
840 }
841 
842 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
843 {
844 	PMD_INIT_FUNC_TRACE();
845 
846 	fman_if_promiscuous_disable(dev->process_private);
847 
848 	return 0;
849 }
850 
851 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
852 {
853 	PMD_INIT_FUNC_TRACE();
854 
855 	fman_if_set_mcast_filter_table(dev->process_private);
856 
857 	return 0;
858 }
859 
860 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
861 {
862 	PMD_INIT_FUNC_TRACE();
863 
864 	fman_if_reset_mcast_filter_table(dev->process_private);
865 
866 	return 0;
867 }
868 
869 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
870 {
871 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
872 	struct fman_if_ic_params icp;
873 	uint32_t fd_offset;
874 	uint32_t bp_size;
875 
876 	memset(&icp, 0, sizeof(icp));
877 	/* set ICEOF for to the default value , which is 0*/
878 	icp.iciof = DEFAULT_ICIOF;
879 	icp.iceof = DEFAULT_RX_ICEOF;
880 	icp.icsz = DEFAULT_ICSZ;
881 	fman_if_set_ic_params(dev->process_private, &icp);
882 
883 	fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
884 	fman_if_set_fdoff(dev->process_private, fd_offset);
885 
886 	/* Buffer pool size should be equal to Dataroom Size*/
887 	bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
888 
889 	fman_if_set_bp(dev->process_private,
890 		       dpaa_intf->bp_info->mp->size,
891 		       dpaa_intf->bp_info->bpid, bp_size);
892 }
893 
894 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
895 					     int8_t vsp_id, uint32_t bpid)
896 {
897 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
898 	struct fman_if *fif = dev->process_private;
899 
900 	if (fif->num_profiles) {
901 		if (vsp_id < 0)
902 			vsp_id = fif->base_profile_id;
903 	} else {
904 		if (vsp_id < 0)
905 			vsp_id = 0;
906 	}
907 
908 	if (dpaa_intf->vsp_bpid[vsp_id] &&
909 		bpid != dpaa_intf->vsp_bpid[vsp_id]) {
910 		DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
911 
912 		return -1;
913 	}
914 
915 	return 0;
916 }
917 
918 static
919 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
920 			    uint16_t nb_desc,
921 			    unsigned int socket_id __rte_unused,
922 			    const struct rte_eth_rxconf *rx_conf,
923 			    struct rte_mempool *mp)
924 {
925 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
926 	struct fman_if *fif = dev->process_private;
927 	struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
928 	struct qm_mcc_initfq opts = {0};
929 	u32 flags = 0;
930 	int ret;
931 	u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
932 	uint32_t max_rx_pktlen;
933 
934 	PMD_INIT_FUNC_TRACE();
935 
936 	if (queue_idx >= dev->data->nb_rx_queues) {
937 		rte_errno = EOVERFLOW;
938 		DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
939 		      (void *)dev, queue_idx, dev->data->nb_rx_queues);
940 		return -rte_errno;
941 	}
942 
943 	/* Rx deferred start is not supported */
944 	if (rx_conf->rx_deferred_start) {
945 		DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
946 		return -EINVAL;
947 	}
948 	rxq->nb_desc = UINT16_MAX;
949 	rxq->offloads = rx_conf->offloads;
950 
951 	DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
952 			queue_idx, rxq->fqid);
953 
954 	if (!fif->num_profiles) {
955 		if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
956 			dpaa_intf->bp_info->mp != mp) {
957 			DPAA_PMD_WARN("Multiple pools on same interface not"
958 				      " supported");
959 			return -EINVAL;
960 		}
961 	} else {
962 		if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
963 			DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
964 			return -EINVAL;
965 		}
966 	}
967 
968 	if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
969 	    dpaa_intf->bp_info->mp != mp) {
970 		DPAA_PMD_WARN("Multiple pools on same interface not supported");
971 		return -EINVAL;
972 	}
973 
974 	max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
975 		VLAN_TAG_SIZE;
976 	/* Max packet can fit in single buffer */
977 	if (max_rx_pktlen <= buffsz) {
978 		;
979 	} else if (dev->data->dev_conf.rxmode.offloads &
980 			RTE_ETH_RX_OFFLOAD_SCATTER) {
981 		if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) {
982 			DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit "
983 				"MaxSGlist %d",
984 				max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES);
985 			rte_errno = EOVERFLOW;
986 			return -rte_errno;
987 		}
988 	} else {
989 		DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
990 		     " larger than a single mbuf (%u) and scattered"
991 		     " mode has not been requested",
992 		     max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM);
993 	}
994 
995 	dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
996 
997 	/* For shared interface, it's done in kernel, skip.*/
998 	if (!fif->is_shared_mac)
999 		dpaa_fman_if_pool_setup(dev);
1000 
1001 	if (fif->num_profiles) {
1002 		int8_t vsp_id = rxq->vsp_id;
1003 
1004 		if (vsp_id >= 0) {
1005 			ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
1006 					DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
1007 					fif);
1008 			if (ret) {
1009 				DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1010 				return ret;
1011 			}
1012 		} else {
1013 			DPAA_PMD_INFO("Base profile is associated to"
1014 				" RXQ fqid:%d\r\n", rxq->fqid);
1015 			if (fif->is_shared_mac) {
1016 				DPAA_PMD_ERR("Fatal: Base profile is associated"
1017 					     " to shared interface on DPDK.");
1018 				return -EINVAL;
1019 			}
1020 			dpaa_intf->vsp_bpid[fif->base_profile_id] =
1021 				DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1022 		}
1023 	} else {
1024 		dpaa_intf->vsp_bpid[0] =
1025 			DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1026 	}
1027 
1028 	dpaa_intf->valid = 1;
1029 	DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1030 		fman_if_get_sg_enable(fif), max_rx_pktlen);
1031 	/* checking if push mode only, no error check for now */
1032 	if (!rxq->is_static &&
1033 	    dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1034 		struct qman_portal *qp;
1035 		int q_fd;
1036 
1037 		dpaa_push_queue_idx++;
1038 		opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1039 		opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1040 				   QM_FQCTRL_CTXASTASHING |
1041 				   QM_FQCTRL_PREFERINCACHE;
1042 		opts.fqd.context_a.stashing.exclusive = 0;
1043 		/* In multicore scenario stashing becomes a bottleneck on LS1046.
1044 		 * So do not enable stashing in this case
1045 		 */
1046 		if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1047 			opts.fqd.context_a.stashing.annotation_cl =
1048 						DPAA_IF_RX_ANNOTATION_STASH;
1049 		opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1050 		opts.fqd.context_a.stashing.context_cl =
1051 						DPAA_IF_RX_CONTEXT_STASH;
1052 
1053 		/*Create a channel and associate given queue with the channel*/
1054 		qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1055 		opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1056 		opts.fqd.dest.channel = rxq->ch_id;
1057 		opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1058 		flags = QMAN_INITFQ_FLAG_SCHED;
1059 
1060 		/* Configure tail drop */
1061 		if (dpaa_intf->cgr_rx) {
1062 			opts.we_mask |= QM_INITFQ_WE_CGID;
1063 			opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1064 			opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1065 		}
1066 		ret = qman_init_fq(rxq, flags, &opts);
1067 		if (ret) {
1068 			DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1069 				"ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1070 			return ret;
1071 		}
1072 		if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1073 			rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1074 		} else {
1075 			rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1076 			rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1077 		}
1078 
1079 		rxq->is_static = true;
1080 
1081 		/* Allocate qman specific portals */
1082 		qp = fsl_qman_fq_portal_create(&q_fd);
1083 		if (!qp) {
1084 			DPAA_PMD_ERR("Unable to alloc fq portal");
1085 			return -1;
1086 		}
1087 		rxq->qp = qp;
1088 
1089 		/* Set up the device interrupt handler */
1090 		if (dev->intr_handle == NULL) {
1091 			struct rte_dpaa_device *dpaa_dev;
1092 			struct rte_device *rdev = dev->device;
1093 
1094 			dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1095 						device);
1096 			dev->intr_handle = dpaa_dev->intr_handle;
1097 			if (rte_intr_vec_list_alloc(dev->intr_handle,
1098 					NULL, dpaa_push_mode_max_queue)) {
1099 				DPAA_PMD_ERR("intr_vec alloc failed");
1100 				return -ENOMEM;
1101 			}
1102 			if (rte_intr_nb_efd_set(dev->intr_handle,
1103 					dpaa_push_mode_max_queue))
1104 				return -rte_errno;
1105 
1106 			if (rte_intr_max_intr_set(dev->intr_handle,
1107 					dpaa_push_mode_max_queue))
1108 				return -rte_errno;
1109 		}
1110 
1111 		if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT))
1112 			return -rte_errno;
1113 
1114 		if (rte_intr_vec_list_index_set(dev->intr_handle,
1115 						queue_idx, queue_idx + 1))
1116 			return -rte_errno;
1117 
1118 		if (rte_intr_efds_index_set(dev->intr_handle, queue_idx,
1119 						   q_fd))
1120 			return -rte_errno;
1121 
1122 		rxq->q_fd = q_fd;
1123 	}
1124 	rxq->bp_array = rte_dpaa_bpid_info;
1125 	dev->data->rx_queues[queue_idx] = rxq;
1126 
1127 	/* configure the CGR size as per the desc size */
1128 	if (dpaa_intf->cgr_rx) {
1129 		struct qm_mcc_initcgr cgr_opts = {0};
1130 
1131 		rxq->nb_desc = nb_desc;
1132 		/* Enable tail drop with cgr on this queue */
1133 		qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1134 		ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1135 		if (ret) {
1136 			DPAA_PMD_WARN(
1137 				"rx taildrop modify fail on fqid %d (ret=%d)",
1138 				rxq->fqid, ret);
1139 		}
1140 	}
1141 	/* Enable main queue to receive error packets also by default */
1142 	fman_if_set_err_fqid(fif, rxq->fqid);
1143 	return 0;
1144 }
1145 
1146 int
1147 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1148 		int eth_rx_queue_id,
1149 		u16 ch_id,
1150 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1151 {
1152 	int ret;
1153 	u32 flags = 0;
1154 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1155 	struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1156 	struct qm_mcc_initfq opts = {0};
1157 
1158 	if (dpaa_push_mode_max_queue)
1159 		DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1160 			      "PUSH mode already enabled for first %d queues.\n"
1161 			      "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1162 			      dpaa_push_mode_max_queue);
1163 
1164 	dpaa_poll_queue_default_config(&opts);
1165 
1166 	switch (queue_conf->ev.sched_type) {
1167 	case RTE_SCHED_TYPE_ATOMIC:
1168 		opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1169 		/* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1170 		 * configuration with HOLD_ACTIVE setting
1171 		 */
1172 		opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1173 		rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1174 		break;
1175 	case RTE_SCHED_TYPE_ORDERED:
1176 		DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1177 		return -1;
1178 	default:
1179 		opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1180 		rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1181 		break;
1182 	}
1183 
1184 	opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1185 	opts.fqd.dest.channel = ch_id;
1186 	opts.fqd.dest.wq = queue_conf->ev.priority;
1187 
1188 	if (dpaa_intf->cgr_rx) {
1189 		opts.we_mask |= QM_INITFQ_WE_CGID;
1190 		opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1191 		opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1192 	}
1193 
1194 	flags = QMAN_INITFQ_FLAG_SCHED;
1195 
1196 	ret = qman_init_fq(rxq, flags, &opts);
1197 	if (ret) {
1198 		DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1199 				"ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1200 		return ret;
1201 	}
1202 
1203 	/* copy configuration which needs to be filled during dequeue */
1204 	memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1205 	dev->data->rx_queues[eth_rx_queue_id] = rxq;
1206 
1207 	return ret;
1208 }
1209 
1210 int
1211 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1212 		int eth_rx_queue_id)
1213 {
1214 	struct qm_mcc_initfq opts = {0};
1215 	int ret;
1216 	u32 flags = 0;
1217 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1218 	struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1219 
1220 	qman_retire_fq(rxq, NULL);
1221 	qman_oos_fq(rxq);
1222 	ret = qman_init_fq(rxq, flags, &opts);
1223 	if (ret) {
1224 		DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d",
1225 			     rxq->fqid, ret);
1226 	}
1227 
1228 	rxq->cb.dqrr_dpdk_cb = NULL;
1229 	dev->data->rx_queues[eth_rx_queue_id] = NULL;
1230 
1231 	return 0;
1232 }
1233 
1234 static
1235 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1236 			    uint16_t nb_desc __rte_unused,
1237 		unsigned int socket_id __rte_unused,
1238 		const struct rte_eth_txconf *tx_conf)
1239 {
1240 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1241 	struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1242 
1243 	PMD_INIT_FUNC_TRACE();
1244 
1245 	/* Tx deferred start is not supported */
1246 	if (tx_conf->tx_deferred_start) {
1247 		DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1248 		return -EINVAL;
1249 	}
1250 	txq->nb_desc = UINT16_MAX;
1251 	txq->offloads = tx_conf->offloads;
1252 
1253 	if (queue_idx >= dev->data->nb_tx_queues) {
1254 		rte_errno = EOVERFLOW;
1255 		DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1256 		      (void *)dev, queue_idx, dev->data->nb_tx_queues);
1257 		return -rte_errno;
1258 	}
1259 
1260 	DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1261 			queue_idx, txq->fqid);
1262 	dev->data->tx_queues[queue_idx] = txq;
1263 
1264 	return 0;
1265 }
1266 
1267 static uint32_t
1268 dpaa_dev_rx_queue_count(void *rx_queue)
1269 {
1270 	struct qman_fq *rxq = rx_queue;
1271 	u32 frm_cnt = 0;
1272 
1273 	PMD_INIT_FUNC_TRACE();
1274 
1275 	if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1276 		DPAA_PMD_DEBUG("RX frame count for q(%p) is %u",
1277 			       rx_queue, frm_cnt);
1278 	}
1279 	return frm_cnt;
1280 }
1281 
1282 static int dpaa_link_down(struct rte_eth_dev *dev)
1283 {
1284 	struct fman_if *fif = dev->process_private;
1285 	struct __fman_if *__fif;
1286 
1287 	PMD_INIT_FUNC_TRACE();
1288 
1289 	__fif = container_of(fif, struct __fman_if, __if);
1290 
1291 	if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1292 		dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN);
1293 	else
1294 		return dpaa_eth_dev_stop(dev);
1295 	return 0;
1296 }
1297 
1298 static int dpaa_link_up(struct rte_eth_dev *dev)
1299 {
1300 	struct fman_if *fif = dev->process_private;
1301 	struct __fman_if *__fif;
1302 
1303 	PMD_INIT_FUNC_TRACE();
1304 
1305 	__fif = container_of(fif, struct __fman_if, __if);
1306 
1307 	if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1308 		dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP);
1309 	else
1310 		dpaa_eth_dev_start(dev);
1311 	return 0;
1312 }
1313 
1314 static int
1315 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1316 		   struct rte_eth_fc_conf *fc_conf)
1317 {
1318 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1319 	struct rte_eth_fc_conf *net_fc;
1320 
1321 	PMD_INIT_FUNC_TRACE();
1322 
1323 	if (!(dpaa_intf->fc_conf)) {
1324 		dpaa_intf->fc_conf = rte_zmalloc(NULL,
1325 			sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1326 		if (!dpaa_intf->fc_conf) {
1327 			DPAA_PMD_ERR("unable to save flow control info");
1328 			return -ENOMEM;
1329 		}
1330 	}
1331 	net_fc = dpaa_intf->fc_conf;
1332 
1333 	if (fc_conf->high_water < fc_conf->low_water) {
1334 		DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1335 		return -EINVAL;
1336 	}
1337 
1338 	if (fc_conf->mode == RTE_ETH_FC_NONE) {
1339 		return 0;
1340 	} else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE ||
1341 		 fc_conf->mode == RTE_ETH_FC_FULL) {
1342 		fman_if_set_fc_threshold(dev->process_private,
1343 					 fc_conf->high_water,
1344 					 fc_conf->low_water,
1345 					 dpaa_intf->bp_info->bpid);
1346 		if (fc_conf->pause_time)
1347 			fman_if_set_fc_quanta(dev->process_private,
1348 					      fc_conf->pause_time);
1349 	}
1350 
1351 	/* Save the information in dpaa device */
1352 	net_fc->pause_time = fc_conf->pause_time;
1353 	net_fc->high_water = fc_conf->high_water;
1354 	net_fc->low_water = fc_conf->low_water;
1355 	net_fc->send_xon = fc_conf->send_xon;
1356 	net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1357 	net_fc->mode = fc_conf->mode;
1358 	net_fc->autoneg = fc_conf->autoneg;
1359 
1360 	return 0;
1361 }
1362 
1363 static int
1364 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1365 		   struct rte_eth_fc_conf *fc_conf)
1366 {
1367 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1368 	struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1369 	int ret;
1370 
1371 	PMD_INIT_FUNC_TRACE();
1372 
1373 	if (net_fc) {
1374 		fc_conf->pause_time = net_fc->pause_time;
1375 		fc_conf->high_water = net_fc->high_water;
1376 		fc_conf->low_water = net_fc->low_water;
1377 		fc_conf->send_xon = net_fc->send_xon;
1378 		fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1379 		fc_conf->mode = net_fc->mode;
1380 		fc_conf->autoneg = net_fc->autoneg;
1381 		return 0;
1382 	}
1383 	ret = fman_if_get_fc_threshold(dev->process_private);
1384 	if (ret) {
1385 		fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1386 		fc_conf->pause_time =
1387 			fman_if_get_fc_quanta(dev->process_private);
1388 	} else {
1389 		fc_conf->mode = RTE_ETH_FC_NONE;
1390 	}
1391 
1392 	return 0;
1393 }
1394 
1395 static int
1396 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1397 			     struct rte_ether_addr *addr,
1398 			     uint32_t index,
1399 			     __rte_unused uint32_t pool)
1400 {
1401 	int ret;
1402 
1403 	PMD_INIT_FUNC_TRACE();
1404 
1405 	ret = fman_if_add_mac_addr(dev->process_private,
1406 				   addr->addr_bytes, index);
1407 
1408 	if (ret)
1409 		DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1410 	return 0;
1411 }
1412 
1413 static void
1414 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1415 			  uint32_t index)
1416 {
1417 	PMD_INIT_FUNC_TRACE();
1418 
1419 	fman_if_clear_mac_addr(dev->process_private, index);
1420 }
1421 
1422 static int
1423 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1424 		       struct rte_ether_addr *addr)
1425 {
1426 	int ret;
1427 
1428 	PMD_INIT_FUNC_TRACE();
1429 
1430 	ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1431 	if (ret)
1432 		DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1433 
1434 	return ret;
1435 }
1436 
1437 static int
1438 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1439 			 struct rte_eth_rss_conf *rss_conf)
1440 {
1441 	struct rte_eth_dev_data *data = dev->data;
1442 	struct rte_eth_conf *eth_conf = &data->dev_conf;
1443 
1444 	PMD_INIT_FUNC_TRACE();
1445 
1446 	if (!(default_q || fmc_q)) {
1447 		if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1448 			DPAA_PMD_ERR("FM port configuration: Failed\n");
1449 			return -1;
1450 		}
1451 		eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1452 	} else {
1453 		DPAA_PMD_ERR("Function not supported\n");
1454 		return -ENOTSUP;
1455 	}
1456 	return 0;
1457 }
1458 
1459 static int
1460 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1461 			   struct rte_eth_rss_conf *rss_conf)
1462 {
1463 	struct rte_eth_dev_data *data = dev->data;
1464 	struct rte_eth_conf *eth_conf = &data->dev_conf;
1465 
1466 	/* dpaa does not support rss_key, so length should be 0*/
1467 	rss_conf->rss_key_len = 0;
1468 	rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1469 	return 0;
1470 }
1471 
1472 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1473 				      uint16_t queue_id)
1474 {
1475 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1476 	struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1477 
1478 	if (!rxq->is_static)
1479 		return -EINVAL;
1480 
1481 	return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1482 }
1483 
1484 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1485 				       uint16_t queue_id)
1486 {
1487 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1488 	struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1489 	uint32_t temp;
1490 	ssize_t temp1;
1491 
1492 	if (!rxq->is_static)
1493 		return -EINVAL;
1494 
1495 	qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1496 
1497 	temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1498 	if (temp1 != sizeof(temp))
1499 		DPAA_PMD_ERR("irq read error");
1500 
1501 	qman_fq_portal_thread_irq(rxq->qp);
1502 
1503 	return 0;
1504 }
1505 
1506 static void
1507 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1508 	struct rte_eth_rxq_info *qinfo)
1509 {
1510 	struct dpaa_if *dpaa_intf = dev->data->dev_private;
1511 	struct qman_fq *rxq;
1512 	int ret;
1513 
1514 	rxq = dev->data->rx_queues[queue_id];
1515 
1516 	qinfo->mp = dpaa_intf->bp_info->mp;
1517 	qinfo->scattered_rx = dev->data->scattered_rx;
1518 	qinfo->nb_desc = rxq->nb_desc;
1519 
1520 	/* Report the HW Rx buffer length to user */
1521 	ret = fman_if_get_maxfrm(dev->process_private);
1522 	if (ret > 0)
1523 		qinfo->rx_buf_size = ret;
1524 
1525 	qinfo->conf.rx_free_thresh = 1;
1526 	qinfo->conf.rx_drop_en = 1;
1527 	qinfo->conf.rx_deferred_start = 0;
1528 	qinfo->conf.offloads = rxq->offloads;
1529 }
1530 
1531 static void
1532 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1533 	struct rte_eth_txq_info *qinfo)
1534 {
1535 	struct qman_fq *txq;
1536 
1537 	txq = dev->data->tx_queues[queue_id];
1538 
1539 	qinfo->nb_desc = txq->nb_desc;
1540 	qinfo->conf.tx_thresh.pthresh = 0;
1541 	qinfo->conf.tx_thresh.hthresh = 0;
1542 	qinfo->conf.tx_thresh.wthresh = 0;
1543 
1544 	qinfo->conf.tx_free_thresh = 0;
1545 	qinfo->conf.tx_rs_thresh = 0;
1546 	qinfo->conf.offloads = txq->offloads;
1547 	qinfo->conf.tx_deferred_start = 0;
1548 }
1549 
1550 static struct eth_dev_ops dpaa_devops = {
1551 	.dev_configure		  = dpaa_eth_dev_configure,
1552 	.dev_start		  = dpaa_eth_dev_start,
1553 	.dev_stop		  = dpaa_eth_dev_stop,
1554 	.dev_close		  = dpaa_eth_dev_close,
1555 	.dev_infos_get		  = dpaa_eth_dev_info,
1556 	.dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1557 
1558 	.rx_queue_setup		  = dpaa_eth_rx_queue_setup,
1559 	.tx_queue_setup		  = dpaa_eth_tx_queue_setup,
1560 	.rx_burst_mode_get	  = dpaa_dev_rx_burst_mode_get,
1561 	.tx_burst_mode_get	  = dpaa_dev_tx_burst_mode_get,
1562 	.rxq_info_get		  = dpaa_rxq_info_get,
1563 	.txq_info_get		  = dpaa_txq_info_get,
1564 
1565 	.flow_ctrl_get		  = dpaa_flow_ctrl_get,
1566 	.flow_ctrl_set		  = dpaa_flow_ctrl_set,
1567 
1568 	.link_update		  = dpaa_eth_link_update,
1569 	.stats_get		  = dpaa_eth_stats_get,
1570 	.xstats_get		  = dpaa_dev_xstats_get,
1571 	.xstats_get_by_id	  = dpaa_xstats_get_by_id,
1572 	.xstats_get_names_by_id	  = dpaa_xstats_get_names_by_id,
1573 	.xstats_get_names	  = dpaa_xstats_get_names,
1574 	.xstats_reset		  = dpaa_eth_stats_reset,
1575 	.stats_reset		  = dpaa_eth_stats_reset,
1576 	.promiscuous_enable	  = dpaa_eth_promiscuous_enable,
1577 	.promiscuous_disable	  = dpaa_eth_promiscuous_disable,
1578 	.allmulticast_enable	  = dpaa_eth_multicast_enable,
1579 	.allmulticast_disable	  = dpaa_eth_multicast_disable,
1580 	.mtu_set		  = dpaa_mtu_set,
1581 	.dev_set_link_down	  = dpaa_link_down,
1582 	.dev_set_link_up	  = dpaa_link_up,
1583 	.mac_addr_add		  = dpaa_dev_add_mac_addr,
1584 	.mac_addr_remove	  = dpaa_dev_remove_mac_addr,
1585 	.mac_addr_set		  = dpaa_dev_set_mac_addr,
1586 
1587 	.fw_version_get		  = dpaa_fw_version_get,
1588 
1589 	.rx_queue_intr_enable	  = dpaa_dev_queue_intr_enable,
1590 	.rx_queue_intr_disable	  = dpaa_dev_queue_intr_disable,
1591 	.rss_hash_update	  = dpaa_dev_rss_hash_update,
1592 	.rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1593 };
1594 
1595 static bool
1596 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1597 {
1598 	if (strcmp(dev->device->driver->name,
1599 		   drv->driver.name))
1600 		return false;
1601 
1602 	return true;
1603 }
1604 
1605 static bool
1606 is_dpaa_supported(struct rte_eth_dev *dev)
1607 {
1608 	return is_device_supported(dev, &rte_dpaa_pmd);
1609 }
1610 
1611 int
1612 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1613 {
1614 	struct rte_eth_dev *dev;
1615 
1616 	RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1617 
1618 	dev = &rte_eth_devices[port];
1619 
1620 	if (!is_dpaa_supported(dev))
1621 		return -ENOTSUP;
1622 
1623 	if (on)
1624 		fman_if_loopback_enable(dev->process_private);
1625 	else
1626 		fman_if_loopback_disable(dev->process_private);
1627 
1628 	return 0;
1629 }
1630 
1631 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1632 			       struct fman_if *fman_intf)
1633 {
1634 	struct rte_eth_fc_conf *fc_conf;
1635 	int ret;
1636 
1637 	PMD_INIT_FUNC_TRACE();
1638 
1639 	if (!(dpaa_intf->fc_conf)) {
1640 		dpaa_intf->fc_conf = rte_zmalloc(NULL,
1641 			sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1642 		if (!dpaa_intf->fc_conf) {
1643 			DPAA_PMD_ERR("unable to save flow control info");
1644 			return -ENOMEM;
1645 		}
1646 	}
1647 	fc_conf = dpaa_intf->fc_conf;
1648 	ret = fman_if_get_fc_threshold(fman_intf);
1649 	if (ret) {
1650 		fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1651 		fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1652 	} else {
1653 		fc_conf->mode = RTE_ETH_FC_NONE;
1654 	}
1655 
1656 	return 0;
1657 }
1658 
1659 /* Initialise an Rx FQ */
1660 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1661 			      uint32_t fqid)
1662 {
1663 	struct qm_mcc_initfq opts = {0};
1664 	int ret;
1665 	u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1666 	struct qm_mcc_initcgr cgr_opts = {
1667 		.we_mask = QM_CGR_WE_CS_THRES |
1668 				QM_CGR_WE_CSTD_EN |
1669 				QM_CGR_WE_MODE,
1670 		.cgr = {
1671 			.cstd_en = QM_CGR_EN,
1672 			.mode = QMAN_CGR_MODE_FRAME
1673 		}
1674 	};
1675 
1676 	if (fmc_q || default_q) {
1677 		ret = qman_reserve_fqid(fqid);
1678 		if (ret) {
1679 			DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1680 				     fqid, ret);
1681 			return -EINVAL;
1682 		}
1683 	}
1684 
1685 	DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1686 	ret = qman_create_fq(fqid, flags, fq);
1687 	if (ret) {
1688 		DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1689 			fqid, ret);
1690 		return ret;
1691 	}
1692 	fq->is_static = false;
1693 
1694 	dpaa_poll_queue_default_config(&opts);
1695 
1696 	if (cgr_rx) {
1697 		/* Enable tail drop with cgr on this queue */
1698 		qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1699 		cgr_rx->cb = NULL;
1700 		ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1701 				      &cgr_opts);
1702 		if (ret) {
1703 			DPAA_PMD_WARN(
1704 				"rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1705 				fq->fqid, ret);
1706 			goto without_cgr;
1707 		}
1708 		opts.we_mask |= QM_INITFQ_WE_CGID;
1709 		opts.fqd.cgid = cgr_rx->cgrid;
1710 		opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1711 	}
1712 without_cgr:
1713 	ret = qman_init_fq(fq, 0, &opts);
1714 	if (ret)
1715 		DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1716 	return ret;
1717 }
1718 
1719 /* Initialise a Tx FQ */
1720 static int dpaa_tx_queue_init(struct qman_fq *fq,
1721 			      struct fman_if *fman_intf,
1722 			      struct qman_cgr *cgr_tx)
1723 {
1724 	struct qm_mcc_initfq opts = {0};
1725 	struct qm_mcc_initcgr cgr_opts = {
1726 		.we_mask = QM_CGR_WE_CS_THRES |
1727 				QM_CGR_WE_CSTD_EN |
1728 				QM_CGR_WE_MODE,
1729 		.cgr = {
1730 			.cstd_en = QM_CGR_EN,
1731 			.mode = QMAN_CGR_MODE_FRAME
1732 		}
1733 	};
1734 	int ret;
1735 
1736 	ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1737 			     QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1738 	if (ret) {
1739 		DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1740 		return ret;
1741 	}
1742 	opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1743 		       QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1744 	opts.fqd.dest.channel = fman_intf->tx_channel_id;
1745 	opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1746 	opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1747 	opts.fqd.context_b = 0;
1748 	/* no tx-confirmation */
1749 	opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1750 	opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1751 	if (fman_ip_rev >= FMAN_V3) {
1752 		/* Set B0V bit in contextA to set ASPID to 0 */
1753 		opts.fqd.context_a.hi |= 0x04000000;
1754 	}
1755 	DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1756 
1757 	if (cgr_tx) {
1758 		/* Enable tail drop with cgr on this queue */
1759 		qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1760 				      td_tx_threshold, 0);
1761 		cgr_tx->cb = NULL;
1762 		ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1763 				      &cgr_opts);
1764 		if (ret) {
1765 			DPAA_PMD_WARN(
1766 				"rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1767 				fq->fqid, ret);
1768 			goto without_cgr;
1769 		}
1770 		opts.we_mask |= QM_INITFQ_WE_CGID;
1771 		opts.fqd.cgid = cgr_tx->cgrid;
1772 		opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1773 		DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1774 				td_tx_threshold);
1775 	}
1776 without_cgr:
1777 	ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1778 	if (ret)
1779 		DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1780 	return ret;
1781 }
1782 
1783 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1784 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1785 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1786 {
1787 	struct qm_mcc_initfq opts = {0};
1788 	int ret;
1789 
1790 	PMD_INIT_FUNC_TRACE();
1791 
1792 	ret = qman_reserve_fqid(fqid);
1793 	if (ret) {
1794 		DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1795 			fqid, ret);
1796 		return -EINVAL;
1797 	}
1798 	/* "map" this Rx FQ to one of the interfaces Tx FQID */
1799 	DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1800 	ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1801 	if (ret) {
1802 		DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1803 			fqid, ret);
1804 		return ret;
1805 	}
1806 	opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1807 	opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1808 	ret = qman_init_fq(fq, 0, &opts);
1809 	if (ret)
1810 		DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1811 			    fqid, ret);
1812 	return ret;
1813 }
1814 #endif
1815 
1816 /* Initialise a network interface */
1817 static int
1818 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1819 {
1820 	struct rte_dpaa_device *dpaa_device;
1821 	struct fm_eth_port_cfg *cfg;
1822 	struct dpaa_if *dpaa_intf;
1823 	struct fman_if *fman_intf;
1824 	int dev_id;
1825 
1826 	PMD_INIT_FUNC_TRACE();
1827 
1828 	dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1829 	dev_id = dpaa_device->id.dev_id;
1830 	cfg = dpaa_get_eth_port_cfg(dev_id);
1831 	fman_intf = cfg->fman_if;
1832 	eth_dev->process_private = fman_intf;
1833 
1834 	/* Plugging of UCODE burst API not supported in Secondary */
1835 	dpaa_intf = eth_dev->data->dev_private;
1836 	eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1837 	if (dpaa_intf->cgr_tx)
1838 		eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1839 	else
1840 		eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1841 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1842 	qman_set_fq_lookup_table(
1843 		dpaa_intf->rx_queues->qman_fq_lookup_table);
1844 #endif
1845 
1846 	return 0;
1847 }
1848 
1849 /* Initialise a network interface */
1850 static int
1851 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1852 {
1853 	int num_rx_fqs, fqid;
1854 	int loop, ret = 0;
1855 	int dev_id;
1856 	struct rte_dpaa_device *dpaa_device;
1857 	struct dpaa_if *dpaa_intf;
1858 	struct fm_eth_port_cfg *cfg;
1859 	struct fman_if *fman_intf;
1860 	struct fman_if_bpool *bp, *tmp_bp;
1861 	uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1862 	uint32_t cgrid_tx[MAX_DPAA_CORES];
1863 	uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1864 	int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1865 	int8_t vsp_id = -1;
1866 
1867 	PMD_INIT_FUNC_TRACE();
1868 
1869 	dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1870 	dev_id = dpaa_device->id.dev_id;
1871 	dpaa_intf = eth_dev->data->dev_private;
1872 	cfg = dpaa_get_eth_port_cfg(dev_id);
1873 	fman_intf = cfg->fman_if;
1874 
1875 	dpaa_intf->name = dpaa_device->name;
1876 
1877 	/* save fman_if & cfg in the interface structure */
1878 	eth_dev->process_private = fman_intf;
1879 	dpaa_intf->ifid = dev_id;
1880 	dpaa_intf->cfg = cfg;
1881 
1882 	memset((char *)dev_rx_fqids, 0,
1883 		sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1884 
1885 	memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1886 
1887 	/* Initialize Rx FQ's */
1888 	if (default_q) {
1889 		num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1890 	} else if (fmc_q) {
1891 		num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1892 						dev_vspids,
1893 						DPAA_MAX_NUM_PCD_QUEUES);
1894 		if (num_rx_fqs < 0) {
1895 			DPAA_PMD_ERR("%s FMC initializes failed!",
1896 				dpaa_intf->name);
1897 			goto free_rx;
1898 		}
1899 		if (!num_rx_fqs) {
1900 			DPAA_PMD_WARN("%s is not configured by FMC.",
1901 				dpaa_intf->name);
1902 		}
1903 	} else {
1904 		/* FMCLESS mode, load balance to multiple cores.*/
1905 		num_rx_fqs = rte_lcore_count();
1906 	}
1907 
1908 	/* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1909 	 * queues.
1910 	 */
1911 	if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1912 		DPAA_PMD_ERR("Invalid number of RX queues\n");
1913 		return -EINVAL;
1914 	}
1915 
1916 	if (num_rx_fqs > 0) {
1917 		dpaa_intf->rx_queues = rte_zmalloc(NULL,
1918 			sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1919 		if (!dpaa_intf->rx_queues) {
1920 			DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1921 			return -ENOMEM;
1922 		}
1923 	} else {
1924 		dpaa_intf->rx_queues = NULL;
1925 	}
1926 
1927 	memset(cgrid, 0, sizeof(cgrid));
1928 	memset(cgrid_tx, 0, sizeof(cgrid_tx));
1929 
1930 	/* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1931 	 * Tx tail drop is disabled.
1932 	 */
1933 	if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1934 		td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1935 		DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1936 			       td_tx_threshold);
1937 		/* if a very large value is being configured */
1938 		if (td_tx_threshold > UINT16_MAX)
1939 			td_tx_threshold = CGR_RX_PERFQ_THRESH;
1940 	}
1941 
1942 	/* If congestion control is enabled globally*/
1943 	if (num_rx_fqs > 0 && td_threshold) {
1944 		dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1945 			sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1946 		if (!dpaa_intf->cgr_rx) {
1947 			DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1948 			ret = -ENOMEM;
1949 			goto free_rx;
1950 		}
1951 
1952 		ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1953 		if (ret != num_rx_fqs) {
1954 			DPAA_PMD_WARN("insufficient CGRIDs available");
1955 			ret = -EINVAL;
1956 			goto free_rx;
1957 		}
1958 	} else {
1959 		dpaa_intf->cgr_rx = NULL;
1960 	}
1961 
1962 	if (!fmc_q && !default_q) {
1963 		ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1964 					    num_rx_fqs, 0);
1965 		if (ret < 0) {
1966 			DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1967 			goto free_rx;
1968 		}
1969 	}
1970 
1971 	for (loop = 0; loop < num_rx_fqs; loop++) {
1972 		if (default_q)
1973 			fqid = cfg->rx_def;
1974 		else
1975 			fqid = dev_rx_fqids[loop];
1976 
1977 		vsp_id = dev_vspids[loop];
1978 
1979 		if (dpaa_intf->cgr_rx)
1980 			dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1981 
1982 		ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1983 			dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1984 			fqid);
1985 		if (ret)
1986 			goto free_rx;
1987 		dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1988 		dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1989 	}
1990 	dpaa_intf->nb_rx_queues = num_rx_fqs;
1991 
1992 	/* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1993 	dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1994 		MAX_DPAA_CORES, MAX_CACHELINE);
1995 	if (!dpaa_intf->tx_queues) {
1996 		DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1997 		ret = -ENOMEM;
1998 		goto free_rx;
1999 	}
2000 
2001 	/* If congestion control is enabled globally*/
2002 	if (td_tx_threshold) {
2003 		dpaa_intf->cgr_tx = rte_zmalloc(NULL,
2004 			sizeof(struct qman_cgr) * MAX_DPAA_CORES,
2005 			MAX_CACHELINE);
2006 		if (!dpaa_intf->cgr_tx) {
2007 			DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
2008 			ret = -ENOMEM;
2009 			goto free_rx;
2010 		}
2011 
2012 		ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2013 					     1, 0);
2014 		if (ret != MAX_DPAA_CORES) {
2015 			DPAA_PMD_WARN("insufficient CGRIDs available");
2016 			ret = -EINVAL;
2017 			goto free_rx;
2018 		}
2019 	} else {
2020 		dpaa_intf->cgr_tx = NULL;
2021 	}
2022 
2023 
2024 	for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2025 		if (dpaa_intf->cgr_tx)
2026 			dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2027 
2028 		ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2029 			fman_intf,
2030 			dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2031 		if (ret)
2032 			goto free_tx;
2033 		dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2034 	}
2035 	dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2036 
2037 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2038 	ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2039 			[DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2040 	if (ret) {
2041 		DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2042 		goto free_tx;
2043 	}
2044 	dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2045 	ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2046 			[DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2047 	if (ret) {
2048 		DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2049 		goto free_tx;
2050 	}
2051 	dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2052 #endif
2053 
2054 	DPAA_PMD_DEBUG("All frame queues created");
2055 
2056 	/* Get the initial configuration for flow control */
2057 	dpaa_fc_set_default(dpaa_intf, fman_intf);
2058 
2059 	/* reset bpool list, initialize bpool dynamically */
2060 	list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2061 		list_del(&bp->node);
2062 		rte_free(bp);
2063 	}
2064 
2065 	/* Populate ethdev structure */
2066 	eth_dev->dev_ops = &dpaa_devops;
2067 	eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2068 	eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2069 	eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2070 
2071 	/* Allocate memory for storing MAC addresses */
2072 	eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2073 		RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2074 	if (eth_dev->data->mac_addrs == NULL) {
2075 		DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2076 						"store MAC addresses",
2077 				RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2078 		ret = -ENOMEM;
2079 		goto free_tx;
2080 	}
2081 
2082 	/* copy the primary mac address */
2083 	rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2084 
2085 	RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n",
2086 		dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr));
2087 
2088 	if (!fman_intf->is_shared_mac) {
2089 		/* Configure error packet handling */
2090 		fman_if_receive_rx_errors(fman_intf,
2091 			FM_FD_RX_STATUS_ERR_MASK);
2092 		/* Disable RX mode */
2093 		fman_if_disable_rx(fman_intf);
2094 		/* Disable promiscuous mode */
2095 		fman_if_promiscuous_disable(fman_intf);
2096 		/* Disable multicast */
2097 		fman_if_reset_mcast_filter_table(fman_intf);
2098 		/* Reset interface statistics */
2099 		fman_if_stats_reset(fman_intf);
2100 		/* Disable SG by default */
2101 		fman_if_set_sg(fman_intf, 0);
2102 		fman_if_set_maxfrm(fman_intf,
2103 				   RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2104 	}
2105 
2106 	return 0;
2107 
2108 free_tx:
2109 	rte_free(dpaa_intf->tx_queues);
2110 	dpaa_intf->tx_queues = NULL;
2111 	dpaa_intf->nb_tx_queues = 0;
2112 
2113 free_rx:
2114 	rte_free(dpaa_intf->cgr_rx);
2115 	rte_free(dpaa_intf->cgr_tx);
2116 	rte_free(dpaa_intf->rx_queues);
2117 	dpaa_intf->rx_queues = NULL;
2118 	dpaa_intf->nb_rx_queues = 0;
2119 	return ret;
2120 }
2121 
2122 static int
2123 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2124 	       struct rte_dpaa_device *dpaa_dev)
2125 {
2126 	int diag;
2127 	int ret;
2128 	struct rte_eth_dev *eth_dev;
2129 
2130 	PMD_INIT_FUNC_TRACE();
2131 
2132 	if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2133 		RTE_PKTMBUF_HEADROOM) {
2134 		DPAA_PMD_ERR(
2135 		"RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2136 		RTE_PKTMBUF_HEADROOM,
2137 		DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2138 
2139 		return -1;
2140 	}
2141 
2142 	/* In case of secondary process, the device is already configured
2143 	 * and no further action is required, except portal initialization
2144 	 * and verifying secondary attachment to port name.
2145 	 */
2146 	if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2147 		eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2148 		if (!eth_dev)
2149 			return -ENOMEM;
2150 		eth_dev->device = &dpaa_dev->device;
2151 		eth_dev->dev_ops = &dpaa_devops;
2152 
2153 		ret = dpaa_dev_init_secondary(eth_dev);
2154 		if (ret != 0) {
2155 			RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2156 			return ret;
2157 		}
2158 
2159 		rte_eth_dev_probing_finish(eth_dev);
2160 		return 0;
2161 	}
2162 
2163 	if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2164 		if (access("/tmp/fmc.bin", F_OK) == -1) {
2165 			DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2166 			default_q = 1;
2167 		}
2168 
2169 		if (!(default_q || fmc_q)) {
2170 			if (dpaa_fm_init()) {
2171 				DPAA_PMD_ERR("FM init failed\n");
2172 				return -1;
2173 			}
2174 		}
2175 
2176 		/* disabling the default push mode for LS1043 */
2177 		if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2178 			dpaa_push_mode_max_queue = 0;
2179 
2180 		/* if push mode queues to be enabled. Currently we are allowing
2181 		 * only one queue per thread.
2182 		 */
2183 		if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2184 			dpaa_push_mode_max_queue =
2185 					atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2186 			if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2187 			    dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2188 		}
2189 
2190 		is_global_init = 1;
2191 	}
2192 
2193 	if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2194 		ret = rte_dpaa_portal_init((void *)1);
2195 		if (ret) {
2196 			DPAA_PMD_ERR("Unable to initialize portal");
2197 			return ret;
2198 		}
2199 	}
2200 
2201 	eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2202 	if (!eth_dev)
2203 		return -ENOMEM;
2204 
2205 	eth_dev->data->dev_private =
2206 			rte_zmalloc("ethdev private structure",
2207 					sizeof(struct dpaa_if),
2208 					RTE_CACHE_LINE_SIZE);
2209 	if (!eth_dev->data->dev_private) {
2210 		DPAA_PMD_ERR("Cannot allocate memzone for port data");
2211 		rte_eth_dev_release_port(eth_dev);
2212 		return -ENOMEM;
2213 	}
2214 
2215 	eth_dev->device = &dpaa_dev->device;
2216 	dpaa_dev->eth_dev = eth_dev;
2217 
2218 	qman_ern_register_cb(dpaa_free_mbuf);
2219 
2220 	if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2221 		eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2222 
2223 	/* Invoke PMD device initialization function */
2224 	diag = dpaa_dev_init(eth_dev);
2225 	if (diag == 0) {
2226 		rte_eth_dev_probing_finish(eth_dev);
2227 		return 0;
2228 	}
2229 
2230 	rte_eth_dev_release_port(eth_dev);
2231 	return diag;
2232 }
2233 
2234 static int
2235 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2236 {
2237 	struct rte_eth_dev *eth_dev;
2238 	int ret;
2239 
2240 	PMD_INIT_FUNC_TRACE();
2241 
2242 	eth_dev = dpaa_dev->eth_dev;
2243 	dpaa_eth_dev_close(eth_dev);
2244 	ret = rte_eth_dev_release_port(eth_dev);
2245 
2246 	return ret;
2247 }
2248 
2249 static void __attribute__((destructor(102))) dpaa_finish(void)
2250 {
2251 	/* For secondary, primary will do all the cleanup */
2252 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2253 		return;
2254 
2255 	if (!(default_q || fmc_q)) {
2256 		unsigned int i;
2257 
2258 		for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2259 			if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2260 				struct rte_eth_dev *dev = &rte_eth_devices[i];
2261 				struct dpaa_if *dpaa_intf =
2262 					dev->data->dev_private;
2263 				struct fman_if *fif =
2264 					dev->process_private;
2265 				if (dpaa_intf->port_handle)
2266 					if (dpaa_fm_deconfig(dpaa_intf, fif))
2267 						DPAA_PMD_WARN("DPAA FM "
2268 							"deconfig failed\n");
2269 				if (fif->num_profiles) {
2270 					if (dpaa_port_vsp_cleanup(dpaa_intf,
2271 								  fif))
2272 						DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2273 				}
2274 			}
2275 		}
2276 		if (is_global_init)
2277 			if (dpaa_fm_term())
2278 				DPAA_PMD_WARN("DPAA FM term failed\n");
2279 
2280 		is_global_init = 0;
2281 
2282 		DPAA_PMD_INFO("DPAA fman cleaned up");
2283 	}
2284 }
2285 
2286 static struct rte_dpaa_driver rte_dpaa_pmd = {
2287 	.drv_flags = RTE_DPAA_DRV_INTR_LSC,
2288 	.drv_type = FSL_DPAA_ETH,
2289 	.probe = rte_dpaa_probe,
2290 	.remove = rte_dpaa_remove,
2291 };
2292 
2293 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2294 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);
2295