1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 RTE_ETH_RX_OFFLOAD_SCATTER; 58 59 /* Rx offloads which cannot be disabled */ 60 static uint64_t dev_rx_offloads_nodis = 61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_RSS_HASH; 66 67 /* Supported Tx offloads */ 68 static uint64_t dev_tx_offloads_sup = 69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 71 72 /* Tx offloads which cannot be disabled */ 73 static uint64_t dev_tx_offloads_nodis = 74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 80 81 /* Keep track of whether QMAN and BMAN have been globally initialized */ 82 static int is_global_init; 83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 84 static int default_q; /* use default queue - FMC is not executed*/ 85 /* At present we only allow up to 4 push mode queues as default - as each of 86 * this queue need dedicated portal and we are short of portals. 87 */ 88 #define DPAA_MAX_PUSH_MODE_QUEUE 8 89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 90 91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 93 94 95 /* Per RX FQ Taildrop in frame count */ 96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 97 98 /* Per TX FQ Taildrop in frame count, disabled by default */ 99 static unsigned int td_tx_threshold; 100 101 struct rte_dpaa_xstats_name_off { 102 char name[RTE_ETH_XSTATS_NAME_SIZE]; 103 uint32_t offset; 104 }; 105 106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 107 {"rx_align_err", 108 offsetof(struct dpaa_if_stats, raln)}, 109 {"rx_valid_pause", 110 offsetof(struct dpaa_if_stats, rxpf)}, 111 {"rx_fcs_err", 112 offsetof(struct dpaa_if_stats, rfcs)}, 113 {"rx_vlan_frame", 114 offsetof(struct dpaa_if_stats, rvlan)}, 115 {"rx_frame_err", 116 offsetof(struct dpaa_if_stats, rerr)}, 117 {"rx_drop_err", 118 offsetof(struct dpaa_if_stats, rdrp)}, 119 {"rx_undersized", 120 offsetof(struct dpaa_if_stats, rund)}, 121 {"rx_oversize_err", 122 offsetof(struct dpaa_if_stats, rovr)}, 123 {"rx_fragment_pkt", 124 offsetof(struct dpaa_if_stats, rfrg)}, 125 {"tx_valid_pause", 126 offsetof(struct dpaa_if_stats, txpf)}, 127 {"tx_fcs_err", 128 offsetof(struct dpaa_if_stats, terr)}, 129 {"tx_vlan_frame", 130 offsetof(struct dpaa_if_stats, tvlan)}, 131 {"rx_undersized", 132 offsetof(struct dpaa_if_stats, tund)}, 133 }; 134 135 static struct rte_dpaa_driver rte_dpaa_pmd; 136 137 static int 138 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 139 140 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 141 int wait_to_complete __rte_unused); 142 143 static void dpaa_interrupt_handler(void *param); 144 145 static inline void 146 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 147 { 148 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 149 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 150 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 151 QM_FQCTRL_PREFERINCACHE; 152 opts->fqd.context_a.stashing.exclusive = 0; 153 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 154 opts->fqd.context_a.stashing.annotation_cl = 155 DPAA_IF_RX_ANNOTATION_STASH; 156 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 157 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 158 } 159 160 static int 161 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 162 { 163 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 164 + VLAN_TAG_SIZE; 165 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 166 167 PMD_INIT_FUNC_TRACE(); 168 169 /* 170 * Refuse mtu that requires the support of scattered packets 171 * when this feature has not been enabled before. 172 */ 173 if (dev->data->min_rx_buf_size && 174 !dev->data->scattered_rx && frame_size > buffsz) { 175 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 176 return -EINVAL; 177 } 178 179 /* check <seg size> * <max_seg> >= max_frame */ 180 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 181 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 182 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 183 buffsz * DPAA_SGT_MAX_ENTRIES); 184 return -EINVAL; 185 } 186 187 fman_if_set_maxfrm(dev->process_private, frame_size); 188 189 return 0; 190 } 191 192 static int 193 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 194 { 195 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 196 uint64_t rx_offloads = eth_conf->rxmode.offloads; 197 uint64_t tx_offloads = eth_conf->txmode.offloads; 198 struct rte_device *rdev = dev->device; 199 struct rte_eth_link *link = &dev->data->dev_link; 200 struct rte_dpaa_device *dpaa_dev; 201 struct fman_if *fif = dev->process_private; 202 struct __fman_if *__fif; 203 struct rte_intr_handle *intr_handle; 204 uint32_t max_rx_pktlen; 205 int speed, duplex; 206 int ret; 207 208 PMD_INIT_FUNC_TRACE(); 209 210 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 211 intr_handle = dpaa_dev->intr_handle; 212 __fif = container_of(fif, struct __fman_if, __if); 213 214 /* Rx offloads which are enabled by default */ 215 if (dev_rx_offloads_nodis & ~rx_offloads) { 216 DPAA_PMD_INFO( 217 "Some of rx offloads enabled by default - requested 0x%" PRIx64 218 " fixed are 0x%" PRIx64, 219 rx_offloads, dev_rx_offloads_nodis); 220 } 221 222 /* Tx offloads which are enabled by default */ 223 if (dev_tx_offloads_nodis & ~tx_offloads) { 224 DPAA_PMD_INFO( 225 "Some of tx offloads enabled by default - requested 0x%" PRIx64 226 " fixed are 0x%" PRIx64, 227 tx_offloads, dev_tx_offloads_nodis); 228 } 229 230 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 231 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 232 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 233 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 234 "supported is %d", 235 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 236 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 237 } 238 239 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 240 241 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 242 DPAA_PMD_DEBUG("enabling scatter mode"); 243 fman_if_set_sg(dev->process_private, 1); 244 dev->data->scattered_rx = 1; 245 } 246 247 if (!(default_q || fmc_q)) { 248 if (dpaa_fm_config(dev, 249 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 250 dpaa_write_fm_config_to_file(); 251 DPAA_PMD_ERR("FM port configuration: Failed\n"); 252 return -1; 253 } 254 dpaa_write_fm_config_to_file(); 255 } 256 257 /* if the interrupts were configured on this devices*/ 258 if (intr_handle && rte_intr_fd_get(intr_handle)) { 259 if (dev->data->dev_conf.intr_conf.lsc != 0) 260 rte_intr_callback_register(intr_handle, 261 dpaa_interrupt_handler, 262 (void *)dev); 263 264 ret = dpaa_intr_enable(__fif->node_name, 265 rte_intr_fd_get(intr_handle)); 266 if (ret) { 267 if (dev->data->dev_conf.intr_conf.lsc != 0) { 268 rte_intr_callback_unregister(intr_handle, 269 dpaa_interrupt_handler, 270 (void *)dev); 271 if (ret == EINVAL) 272 printf("Failed to enable interrupt: Not Supported\n"); 273 else 274 printf("Failed to enable interrupt\n"); 275 } 276 dev->data->dev_conf.intr_conf.lsc = 0; 277 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 278 } 279 } 280 281 /* Wait for link status to get updated */ 282 if (!link->link_status) 283 sleep(1); 284 285 /* Configure link only if link is UP*/ 286 if (link->link_status) { 287 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 288 /* Start autoneg only if link is not in autoneg mode */ 289 if (!link->link_autoneg) 290 dpaa_restart_link_autoneg(__fif->node_name); 291 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 292 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 293 case RTE_ETH_LINK_SPEED_10M_HD: 294 speed = RTE_ETH_SPEED_NUM_10M; 295 duplex = RTE_ETH_LINK_HALF_DUPLEX; 296 break; 297 case RTE_ETH_LINK_SPEED_10M: 298 speed = RTE_ETH_SPEED_NUM_10M; 299 duplex = RTE_ETH_LINK_FULL_DUPLEX; 300 break; 301 case RTE_ETH_LINK_SPEED_100M_HD: 302 speed = RTE_ETH_SPEED_NUM_100M; 303 duplex = RTE_ETH_LINK_HALF_DUPLEX; 304 break; 305 case RTE_ETH_LINK_SPEED_100M: 306 speed = RTE_ETH_SPEED_NUM_100M; 307 duplex = RTE_ETH_LINK_FULL_DUPLEX; 308 break; 309 case RTE_ETH_LINK_SPEED_1G: 310 speed = RTE_ETH_SPEED_NUM_1G; 311 duplex = RTE_ETH_LINK_FULL_DUPLEX; 312 break; 313 case RTE_ETH_LINK_SPEED_2_5G: 314 speed = RTE_ETH_SPEED_NUM_2_5G; 315 duplex = RTE_ETH_LINK_FULL_DUPLEX; 316 break; 317 case RTE_ETH_LINK_SPEED_10G: 318 speed = RTE_ETH_SPEED_NUM_10G; 319 duplex = RTE_ETH_LINK_FULL_DUPLEX; 320 break; 321 default: 322 speed = RTE_ETH_SPEED_NUM_NONE; 323 duplex = RTE_ETH_LINK_FULL_DUPLEX; 324 break; 325 } 326 /* Set link speed */ 327 dpaa_update_link_speed(__fif->node_name, speed, duplex); 328 } else { 329 /* Manual autoneg - custom advertisement speed. */ 330 printf("Custom Advertisement speeds not supported\n"); 331 } 332 } 333 334 return 0; 335 } 336 337 static const uint32_t * 338 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 339 { 340 static const uint32_t ptypes[] = { 341 RTE_PTYPE_L2_ETHER, 342 RTE_PTYPE_L2_ETHER_VLAN, 343 RTE_PTYPE_L2_ETHER_ARP, 344 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 345 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 346 RTE_PTYPE_L4_ICMP, 347 RTE_PTYPE_L4_TCP, 348 RTE_PTYPE_L4_UDP, 349 RTE_PTYPE_L4_FRAG, 350 RTE_PTYPE_L4_TCP, 351 RTE_PTYPE_L4_UDP, 352 RTE_PTYPE_L4_SCTP 353 }; 354 355 PMD_INIT_FUNC_TRACE(); 356 357 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 358 return ptypes; 359 return NULL; 360 } 361 362 static void dpaa_interrupt_handler(void *param) 363 { 364 struct rte_eth_dev *dev = param; 365 struct rte_device *rdev = dev->device; 366 struct rte_dpaa_device *dpaa_dev; 367 struct rte_intr_handle *intr_handle; 368 uint64_t buf; 369 int bytes_read; 370 371 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 372 intr_handle = dpaa_dev->intr_handle; 373 374 if (rte_intr_fd_get(intr_handle) < 0) 375 return; 376 377 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 378 sizeof(uint64_t)); 379 if (bytes_read < 0) 380 DPAA_PMD_ERR("Error reading eventfd\n"); 381 dpaa_eth_link_update(dev, 0); 382 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 383 } 384 385 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 386 { 387 struct dpaa_if *dpaa_intf = dev->data->dev_private; 388 389 PMD_INIT_FUNC_TRACE(); 390 391 if (!(default_q || fmc_q)) 392 dpaa_write_fm_config_to_file(); 393 394 /* Change tx callback to the real one */ 395 if (dpaa_intf->cgr_tx) 396 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 397 else 398 dev->tx_pkt_burst = dpaa_eth_queue_tx; 399 400 fman_if_enable_rx(dev->process_private); 401 402 return 0; 403 } 404 405 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 406 { 407 struct fman_if *fif = dev->process_private; 408 409 PMD_INIT_FUNC_TRACE(); 410 dev->data->dev_started = 0; 411 412 if (!fif->is_shared_mac) 413 fman_if_disable_rx(fif); 414 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 415 416 return 0; 417 } 418 419 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 420 { 421 struct fman_if *fif = dev->process_private; 422 struct __fman_if *__fif; 423 struct rte_device *rdev = dev->device; 424 struct rte_dpaa_device *dpaa_dev; 425 struct rte_intr_handle *intr_handle; 426 struct rte_eth_link *link = &dev->data->dev_link; 427 struct dpaa_if *dpaa_intf = dev->data->dev_private; 428 int loop; 429 int ret; 430 431 PMD_INIT_FUNC_TRACE(); 432 433 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 434 return 0; 435 436 if (!dpaa_intf) { 437 DPAA_PMD_WARN("Already closed or not started"); 438 return -1; 439 } 440 441 /* DPAA FM deconfig */ 442 if (!(default_q || fmc_q)) { 443 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 444 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 445 } 446 447 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 448 intr_handle = dpaa_dev->intr_handle; 449 __fif = container_of(fif, struct __fman_if, __if); 450 451 ret = dpaa_eth_dev_stop(dev); 452 453 /* Reset link to autoneg */ 454 if (link->link_status && !link->link_autoneg) 455 dpaa_restart_link_autoneg(__fif->node_name); 456 457 if (intr_handle && rte_intr_fd_get(intr_handle) && 458 dev->data->dev_conf.intr_conf.lsc != 0) { 459 dpaa_intr_disable(__fif->node_name); 460 rte_intr_callback_unregister(intr_handle, 461 dpaa_interrupt_handler, 462 (void *)dev); 463 } 464 465 /* release configuration memory */ 466 if (dpaa_intf->fc_conf) 467 rte_free(dpaa_intf->fc_conf); 468 469 /* Release RX congestion Groups */ 470 if (dpaa_intf->cgr_rx) { 471 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 472 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 473 } 474 475 rte_free(dpaa_intf->cgr_rx); 476 dpaa_intf->cgr_rx = NULL; 477 /* Release TX congestion Groups */ 478 if (dpaa_intf->cgr_tx) { 479 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 480 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 481 rte_free(dpaa_intf->cgr_tx); 482 dpaa_intf->cgr_tx = NULL; 483 } 484 485 rte_free(dpaa_intf->rx_queues); 486 dpaa_intf->rx_queues = NULL; 487 488 rte_free(dpaa_intf->tx_queues); 489 dpaa_intf->tx_queues = NULL; 490 491 return ret; 492 } 493 494 static int 495 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 496 char *fw_version, 497 size_t fw_size) 498 { 499 int ret; 500 FILE *svr_file = NULL; 501 unsigned int svr_ver = 0; 502 503 PMD_INIT_FUNC_TRACE(); 504 505 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 506 if (!svr_file) { 507 DPAA_PMD_ERR("Unable to open SoC device"); 508 return -ENOTSUP; /* Not supported on this infra */ 509 } 510 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 511 dpaa_svr_family = svr_ver & SVR_MASK; 512 else 513 DPAA_PMD_ERR("Unable to read SoC device"); 514 515 fclose(svr_file); 516 517 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 518 svr_ver, fman_ip_rev); 519 if (ret < 0) 520 return -EINVAL; 521 522 ret += 1; /* add the size of '\0' */ 523 if (fw_size < (size_t)ret) 524 return ret; 525 else 526 return 0; 527 } 528 529 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 530 struct rte_eth_dev_info *dev_info) 531 { 532 struct dpaa_if *dpaa_intf = dev->data->dev_private; 533 struct fman_if *fif = dev->process_private; 534 535 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 536 537 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 538 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 539 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 540 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 541 dev_info->max_hash_mac_addrs = 0; 542 dev_info->max_vfs = 0; 543 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 544 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 545 546 if (fif->mac_type == fman_mac_1g) { 547 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 548 | RTE_ETH_LINK_SPEED_10M 549 | RTE_ETH_LINK_SPEED_100M_HD 550 | RTE_ETH_LINK_SPEED_100M 551 | RTE_ETH_LINK_SPEED_1G; 552 } else if (fif->mac_type == fman_mac_2_5g) { 553 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 554 | RTE_ETH_LINK_SPEED_10M 555 | RTE_ETH_LINK_SPEED_100M_HD 556 | RTE_ETH_LINK_SPEED_100M 557 | RTE_ETH_LINK_SPEED_1G 558 | RTE_ETH_LINK_SPEED_2_5G; 559 } else if (fif->mac_type == fman_mac_10g) { 560 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 561 | RTE_ETH_LINK_SPEED_10M 562 | RTE_ETH_LINK_SPEED_100M_HD 563 | RTE_ETH_LINK_SPEED_100M 564 | RTE_ETH_LINK_SPEED_1G 565 | RTE_ETH_LINK_SPEED_2_5G 566 | RTE_ETH_LINK_SPEED_10G; 567 } else { 568 DPAA_PMD_ERR("invalid link_speed: %s, %d", 569 dpaa_intf->name, fif->mac_type); 570 return -EINVAL; 571 } 572 573 dev_info->rx_offload_capa = dev_rx_offloads_sup | 574 dev_rx_offloads_nodis; 575 dev_info->tx_offload_capa = dev_tx_offloads_sup | 576 dev_tx_offloads_nodis; 577 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 578 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 579 dev_info->default_rxportconf.nb_queues = 1; 580 dev_info->default_txportconf.nb_queues = 1; 581 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 582 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 583 584 return 0; 585 } 586 587 static int 588 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 589 __rte_unused uint16_t queue_id, 590 struct rte_eth_burst_mode *mode) 591 { 592 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 593 int ret = -EINVAL; 594 unsigned int i; 595 const struct burst_info { 596 uint64_t flags; 597 const char *output; 598 } rx_offload_map[] = { 599 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 600 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 601 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 602 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 603 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 604 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 605 }; 606 607 /* Update Rx offload info */ 608 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 609 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 610 snprintf(mode->info, sizeof(mode->info), "%s", 611 rx_offload_map[i].output); 612 ret = 0; 613 break; 614 } 615 } 616 return ret; 617 } 618 619 static int 620 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 621 __rte_unused uint16_t queue_id, 622 struct rte_eth_burst_mode *mode) 623 { 624 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 625 int ret = -EINVAL; 626 unsigned int i; 627 const struct burst_info { 628 uint64_t flags; 629 const char *output; 630 } tx_offload_map[] = { 631 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 632 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 633 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 634 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 635 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 636 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 637 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 638 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 639 }; 640 641 /* Update Tx offload info */ 642 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 643 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 644 snprintf(mode->info, sizeof(mode->info), "%s", 645 tx_offload_map[i].output); 646 ret = 0; 647 break; 648 } 649 } 650 return ret; 651 } 652 653 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 654 int wait_to_complete) 655 { 656 struct dpaa_if *dpaa_intf = dev->data->dev_private; 657 struct rte_eth_link *link = &dev->data->dev_link; 658 struct fman_if *fif = dev->process_private; 659 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 660 int ret, ioctl_version; 661 uint8_t count; 662 663 PMD_INIT_FUNC_TRACE(); 664 665 ioctl_version = dpaa_get_ioctl_version_number(); 666 667 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 668 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 669 ret = dpaa_get_link_status(__fif->node_name, link); 670 if (ret) 671 return ret; 672 if (link->link_status == RTE_ETH_LINK_DOWN && 673 wait_to_complete) 674 rte_delay_ms(CHECK_INTERVAL); 675 else 676 break; 677 } 678 } else { 679 link->link_status = dpaa_intf->valid; 680 } 681 682 if (ioctl_version < 2) { 683 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 684 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 685 686 if (fif->mac_type == fman_mac_1g) 687 link->link_speed = RTE_ETH_SPEED_NUM_1G; 688 else if (fif->mac_type == fman_mac_2_5g) 689 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 690 else if (fif->mac_type == fman_mac_10g) 691 link->link_speed = RTE_ETH_SPEED_NUM_10G; 692 else 693 DPAA_PMD_ERR("invalid link_speed: %s, %d", 694 dpaa_intf->name, fif->mac_type); 695 } 696 697 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 698 link->link_status ? "Up" : "Down"); 699 return 0; 700 } 701 702 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 703 struct rte_eth_stats *stats) 704 { 705 PMD_INIT_FUNC_TRACE(); 706 707 fman_if_stats_get(dev->process_private, stats); 708 return 0; 709 } 710 711 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 712 { 713 PMD_INIT_FUNC_TRACE(); 714 715 fman_if_stats_reset(dev->process_private); 716 717 return 0; 718 } 719 720 static int 721 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 722 unsigned int n) 723 { 724 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 725 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 726 727 if (n < num) 728 return num; 729 730 if (xstats == NULL) 731 return 0; 732 733 fman_if_stats_get_all(dev->process_private, values, 734 sizeof(struct dpaa_if_stats) / 8); 735 736 for (i = 0; i < num; i++) { 737 xstats[i].id = i; 738 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 739 } 740 return i; 741 } 742 743 static int 744 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 745 struct rte_eth_xstat_name *xstats_names, 746 unsigned int limit) 747 { 748 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 749 750 if (limit < stat_cnt) 751 return stat_cnt; 752 753 if (xstats_names != NULL) 754 for (i = 0; i < stat_cnt; i++) 755 strlcpy(xstats_names[i].name, 756 dpaa_xstats_strings[i].name, 757 sizeof(xstats_names[i].name)); 758 759 return stat_cnt; 760 } 761 762 static int 763 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 764 uint64_t *values, unsigned int n) 765 { 766 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 767 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 768 769 if (!ids) { 770 if (n < stat_cnt) 771 return stat_cnt; 772 773 if (!values) 774 return 0; 775 776 fman_if_stats_get_all(dev->process_private, values_copy, 777 sizeof(struct dpaa_if_stats) / 8); 778 779 for (i = 0; i < stat_cnt; i++) 780 values[i] = 781 values_copy[dpaa_xstats_strings[i].offset / 8]; 782 783 return stat_cnt; 784 } 785 786 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 787 788 for (i = 0; i < n; i++) { 789 if (ids[i] >= stat_cnt) { 790 DPAA_PMD_ERR("id value isn't valid"); 791 return -1; 792 } 793 values[i] = values_copy[ids[i]]; 794 } 795 return n; 796 } 797 798 static int 799 dpaa_xstats_get_names_by_id( 800 struct rte_eth_dev *dev, 801 const uint64_t *ids, 802 struct rte_eth_xstat_name *xstats_names, 803 unsigned int limit) 804 { 805 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 806 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 807 808 if (!ids) 809 return dpaa_xstats_get_names(dev, xstats_names, limit); 810 811 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 812 813 for (i = 0; i < limit; i++) { 814 if (ids[i] >= stat_cnt) { 815 DPAA_PMD_ERR("id value isn't valid"); 816 return -1; 817 } 818 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 819 } 820 return limit; 821 } 822 823 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 824 { 825 PMD_INIT_FUNC_TRACE(); 826 827 fman_if_promiscuous_enable(dev->process_private); 828 829 return 0; 830 } 831 832 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 833 { 834 PMD_INIT_FUNC_TRACE(); 835 836 fman_if_promiscuous_disable(dev->process_private); 837 838 return 0; 839 } 840 841 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 842 { 843 PMD_INIT_FUNC_TRACE(); 844 845 fman_if_set_mcast_filter_table(dev->process_private); 846 847 return 0; 848 } 849 850 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 851 { 852 PMD_INIT_FUNC_TRACE(); 853 854 fman_if_reset_mcast_filter_table(dev->process_private); 855 856 return 0; 857 } 858 859 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 860 { 861 struct dpaa_if *dpaa_intf = dev->data->dev_private; 862 struct fman_if_ic_params icp; 863 uint32_t fd_offset; 864 uint32_t bp_size; 865 866 memset(&icp, 0, sizeof(icp)); 867 /* set ICEOF for to the default value , which is 0*/ 868 icp.iciof = DEFAULT_ICIOF; 869 icp.iceof = DEFAULT_RX_ICEOF; 870 icp.icsz = DEFAULT_ICSZ; 871 fman_if_set_ic_params(dev->process_private, &icp); 872 873 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 874 fman_if_set_fdoff(dev->process_private, fd_offset); 875 876 /* Buffer pool size should be equal to Dataroom Size*/ 877 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 878 879 fman_if_set_bp(dev->process_private, 880 dpaa_intf->bp_info->mp->size, 881 dpaa_intf->bp_info->bpid, bp_size); 882 } 883 884 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 885 int8_t vsp_id, uint32_t bpid) 886 { 887 struct dpaa_if *dpaa_intf = dev->data->dev_private; 888 struct fman_if *fif = dev->process_private; 889 890 if (fif->num_profiles) { 891 if (vsp_id < 0) 892 vsp_id = fif->base_profile_id; 893 } else { 894 if (vsp_id < 0) 895 vsp_id = 0; 896 } 897 898 if (dpaa_intf->vsp_bpid[vsp_id] && 899 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 900 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 901 902 return -1; 903 } 904 905 return 0; 906 } 907 908 static 909 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 910 uint16_t nb_desc, 911 unsigned int socket_id __rte_unused, 912 const struct rte_eth_rxconf *rx_conf, 913 struct rte_mempool *mp) 914 { 915 struct dpaa_if *dpaa_intf = dev->data->dev_private; 916 struct fman_if *fif = dev->process_private; 917 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 918 struct qm_mcc_initfq opts = {0}; 919 u32 flags = 0; 920 int ret; 921 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 922 uint32_t max_rx_pktlen; 923 924 PMD_INIT_FUNC_TRACE(); 925 926 if (queue_idx >= dev->data->nb_rx_queues) { 927 rte_errno = EOVERFLOW; 928 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 929 (void *)dev, queue_idx, dev->data->nb_rx_queues); 930 return -rte_errno; 931 } 932 933 /* Rx deferred start is not supported */ 934 if (rx_conf->rx_deferred_start) { 935 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 936 return -EINVAL; 937 } 938 rxq->nb_desc = UINT16_MAX; 939 rxq->offloads = rx_conf->offloads; 940 941 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 942 queue_idx, rxq->fqid); 943 944 if (!fif->num_profiles) { 945 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 946 dpaa_intf->bp_info->mp != mp) { 947 DPAA_PMD_WARN("Multiple pools on same interface not" 948 " supported"); 949 return -EINVAL; 950 } 951 } else { 952 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 953 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 954 return -EINVAL; 955 } 956 } 957 958 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 959 dpaa_intf->bp_info->mp != mp) { 960 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 961 return -EINVAL; 962 } 963 964 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 965 VLAN_TAG_SIZE; 966 /* Max packet can fit in single buffer */ 967 if (max_rx_pktlen <= buffsz) { 968 ; 969 } else if (dev->data->dev_conf.rxmode.offloads & 970 RTE_ETH_RX_OFFLOAD_SCATTER) { 971 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 972 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 973 "MaxSGlist %d", 974 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 975 rte_errno = EOVERFLOW; 976 return -rte_errno; 977 } 978 } else { 979 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 980 " larger than a single mbuf (%u) and scattered" 981 " mode has not been requested", 982 max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM); 983 } 984 985 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 986 987 /* For shared interface, it's done in kernel, skip.*/ 988 if (!fif->is_shared_mac) 989 dpaa_fman_if_pool_setup(dev); 990 991 if (fif->num_profiles) { 992 int8_t vsp_id = rxq->vsp_id; 993 994 if (vsp_id >= 0) { 995 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 996 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 997 fif); 998 if (ret) { 999 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1000 return ret; 1001 } 1002 } else { 1003 DPAA_PMD_INFO("Base profile is associated to" 1004 " RXQ fqid:%d\r\n", rxq->fqid); 1005 if (fif->is_shared_mac) { 1006 DPAA_PMD_ERR("Fatal: Base profile is associated" 1007 " to shared interface on DPDK."); 1008 return -EINVAL; 1009 } 1010 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1011 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1012 } 1013 } else { 1014 dpaa_intf->vsp_bpid[0] = 1015 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1016 } 1017 1018 dpaa_intf->valid = 1; 1019 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1020 fman_if_get_sg_enable(fif), max_rx_pktlen); 1021 /* checking if push mode only, no error check for now */ 1022 if (!rxq->is_static && 1023 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1024 struct qman_portal *qp; 1025 int q_fd; 1026 1027 dpaa_push_queue_idx++; 1028 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1029 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1030 QM_FQCTRL_CTXASTASHING | 1031 QM_FQCTRL_PREFERINCACHE; 1032 opts.fqd.context_a.stashing.exclusive = 0; 1033 /* In muticore scenario stashing becomes a bottleneck on LS1046. 1034 * So do not enable stashing in this case 1035 */ 1036 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1037 opts.fqd.context_a.stashing.annotation_cl = 1038 DPAA_IF_RX_ANNOTATION_STASH; 1039 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1040 opts.fqd.context_a.stashing.context_cl = 1041 DPAA_IF_RX_CONTEXT_STASH; 1042 1043 /*Create a channel and associate given queue with the channel*/ 1044 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1045 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1046 opts.fqd.dest.channel = rxq->ch_id; 1047 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1048 flags = QMAN_INITFQ_FLAG_SCHED; 1049 1050 /* Configure tail drop */ 1051 if (dpaa_intf->cgr_rx) { 1052 opts.we_mask |= QM_INITFQ_WE_CGID; 1053 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1054 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1055 } 1056 ret = qman_init_fq(rxq, flags, &opts); 1057 if (ret) { 1058 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1059 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1060 return ret; 1061 } 1062 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1063 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1064 } else { 1065 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1066 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1067 } 1068 1069 rxq->is_static = true; 1070 1071 /* Allocate qman specific portals */ 1072 qp = fsl_qman_fq_portal_create(&q_fd); 1073 if (!qp) { 1074 DPAA_PMD_ERR("Unable to alloc fq portal"); 1075 return -1; 1076 } 1077 rxq->qp = qp; 1078 1079 /* Set up the device interrupt handler */ 1080 if (dev->intr_handle == NULL) { 1081 struct rte_dpaa_device *dpaa_dev; 1082 struct rte_device *rdev = dev->device; 1083 1084 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1085 device); 1086 dev->intr_handle = dpaa_dev->intr_handle; 1087 if (rte_intr_vec_list_alloc(dev->intr_handle, 1088 NULL, dpaa_push_mode_max_queue)) { 1089 DPAA_PMD_ERR("intr_vec alloc failed"); 1090 return -ENOMEM; 1091 } 1092 if (rte_intr_nb_efd_set(dev->intr_handle, 1093 dpaa_push_mode_max_queue)) 1094 return -rte_errno; 1095 1096 if (rte_intr_max_intr_set(dev->intr_handle, 1097 dpaa_push_mode_max_queue)) 1098 return -rte_errno; 1099 } 1100 1101 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1102 return -rte_errno; 1103 1104 if (rte_intr_vec_list_index_set(dev->intr_handle, 1105 queue_idx, queue_idx + 1)) 1106 return -rte_errno; 1107 1108 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1109 q_fd)) 1110 return -rte_errno; 1111 1112 rxq->q_fd = q_fd; 1113 } 1114 rxq->bp_array = rte_dpaa_bpid_info; 1115 dev->data->rx_queues[queue_idx] = rxq; 1116 1117 /* configure the CGR size as per the desc size */ 1118 if (dpaa_intf->cgr_rx) { 1119 struct qm_mcc_initcgr cgr_opts = {0}; 1120 1121 rxq->nb_desc = nb_desc; 1122 /* Enable tail drop with cgr on this queue */ 1123 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1124 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1125 if (ret) { 1126 DPAA_PMD_WARN( 1127 "rx taildrop modify fail on fqid %d (ret=%d)", 1128 rxq->fqid, ret); 1129 } 1130 } 1131 /* Enable main queue to receive error packets also by default */ 1132 fman_if_set_err_fqid(fif, rxq->fqid); 1133 return 0; 1134 } 1135 1136 int 1137 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1138 int eth_rx_queue_id, 1139 u16 ch_id, 1140 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1141 { 1142 int ret; 1143 u32 flags = 0; 1144 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1145 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1146 struct qm_mcc_initfq opts = {0}; 1147 1148 if (dpaa_push_mode_max_queue) 1149 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1150 "PUSH mode already enabled for first %d queues.\n" 1151 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1152 dpaa_push_mode_max_queue); 1153 1154 dpaa_poll_queue_default_config(&opts); 1155 1156 switch (queue_conf->ev.sched_type) { 1157 case RTE_SCHED_TYPE_ATOMIC: 1158 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1159 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1160 * configuration with HOLD_ACTIVE setting 1161 */ 1162 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1163 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1164 break; 1165 case RTE_SCHED_TYPE_ORDERED: 1166 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1167 return -1; 1168 default: 1169 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1170 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1171 break; 1172 } 1173 1174 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1175 opts.fqd.dest.channel = ch_id; 1176 opts.fqd.dest.wq = queue_conf->ev.priority; 1177 1178 if (dpaa_intf->cgr_rx) { 1179 opts.we_mask |= QM_INITFQ_WE_CGID; 1180 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1181 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1182 } 1183 1184 flags = QMAN_INITFQ_FLAG_SCHED; 1185 1186 ret = qman_init_fq(rxq, flags, &opts); 1187 if (ret) { 1188 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1189 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1190 return ret; 1191 } 1192 1193 /* copy configuration which needs to be filled during dequeue */ 1194 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1195 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1196 1197 return ret; 1198 } 1199 1200 int 1201 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1202 int eth_rx_queue_id) 1203 { 1204 struct qm_mcc_initfq opts; 1205 int ret; 1206 u32 flags = 0; 1207 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1208 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1209 1210 dpaa_poll_queue_default_config(&opts); 1211 1212 if (dpaa_intf->cgr_rx) { 1213 opts.we_mask |= QM_INITFQ_WE_CGID; 1214 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1215 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1216 } 1217 1218 ret = qman_init_fq(rxq, flags, &opts); 1219 if (ret) { 1220 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 1221 rxq->fqid, ret); 1222 } 1223 1224 rxq->cb.dqrr_dpdk_cb = NULL; 1225 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1226 1227 return 0; 1228 } 1229 1230 static 1231 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1232 uint16_t nb_desc __rte_unused, 1233 unsigned int socket_id __rte_unused, 1234 const struct rte_eth_txconf *tx_conf) 1235 { 1236 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1237 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1238 1239 PMD_INIT_FUNC_TRACE(); 1240 1241 /* Tx deferred start is not supported */ 1242 if (tx_conf->tx_deferred_start) { 1243 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1244 return -EINVAL; 1245 } 1246 txq->nb_desc = UINT16_MAX; 1247 txq->offloads = tx_conf->offloads; 1248 1249 if (queue_idx >= dev->data->nb_tx_queues) { 1250 rte_errno = EOVERFLOW; 1251 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1252 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1253 return -rte_errno; 1254 } 1255 1256 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1257 queue_idx, txq->fqid); 1258 dev->data->tx_queues[queue_idx] = txq; 1259 1260 return 0; 1261 } 1262 1263 static uint32_t 1264 dpaa_dev_rx_queue_count(void *rx_queue) 1265 { 1266 struct qman_fq *rxq = rx_queue; 1267 u32 frm_cnt = 0; 1268 1269 PMD_INIT_FUNC_TRACE(); 1270 1271 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1272 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1273 rx_queue, frm_cnt); 1274 } 1275 return frm_cnt; 1276 } 1277 1278 static int dpaa_link_down(struct rte_eth_dev *dev) 1279 { 1280 struct fman_if *fif = dev->process_private; 1281 struct __fman_if *__fif; 1282 1283 PMD_INIT_FUNC_TRACE(); 1284 1285 __fif = container_of(fif, struct __fman_if, __if); 1286 1287 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1288 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1289 else 1290 return dpaa_eth_dev_stop(dev); 1291 return 0; 1292 } 1293 1294 static int dpaa_link_up(struct rte_eth_dev *dev) 1295 { 1296 struct fman_if *fif = dev->process_private; 1297 struct __fman_if *__fif; 1298 1299 PMD_INIT_FUNC_TRACE(); 1300 1301 __fif = container_of(fif, struct __fman_if, __if); 1302 1303 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1304 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1305 else 1306 dpaa_eth_dev_start(dev); 1307 return 0; 1308 } 1309 1310 static int 1311 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1312 struct rte_eth_fc_conf *fc_conf) 1313 { 1314 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1315 struct rte_eth_fc_conf *net_fc; 1316 1317 PMD_INIT_FUNC_TRACE(); 1318 1319 if (!(dpaa_intf->fc_conf)) { 1320 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1321 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1322 if (!dpaa_intf->fc_conf) { 1323 DPAA_PMD_ERR("unable to save flow control info"); 1324 return -ENOMEM; 1325 } 1326 } 1327 net_fc = dpaa_intf->fc_conf; 1328 1329 if (fc_conf->high_water < fc_conf->low_water) { 1330 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1331 return -EINVAL; 1332 } 1333 1334 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1335 return 0; 1336 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1337 fc_conf->mode == RTE_ETH_FC_FULL) { 1338 fman_if_set_fc_threshold(dev->process_private, 1339 fc_conf->high_water, 1340 fc_conf->low_water, 1341 dpaa_intf->bp_info->bpid); 1342 if (fc_conf->pause_time) 1343 fman_if_set_fc_quanta(dev->process_private, 1344 fc_conf->pause_time); 1345 } 1346 1347 /* Save the information in dpaa device */ 1348 net_fc->pause_time = fc_conf->pause_time; 1349 net_fc->high_water = fc_conf->high_water; 1350 net_fc->low_water = fc_conf->low_water; 1351 net_fc->send_xon = fc_conf->send_xon; 1352 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1353 net_fc->mode = fc_conf->mode; 1354 net_fc->autoneg = fc_conf->autoneg; 1355 1356 return 0; 1357 } 1358 1359 static int 1360 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1361 struct rte_eth_fc_conf *fc_conf) 1362 { 1363 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1364 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1365 int ret; 1366 1367 PMD_INIT_FUNC_TRACE(); 1368 1369 if (net_fc) { 1370 fc_conf->pause_time = net_fc->pause_time; 1371 fc_conf->high_water = net_fc->high_water; 1372 fc_conf->low_water = net_fc->low_water; 1373 fc_conf->send_xon = net_fc->send_xon; 1374 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1375 fc_conf->mode = net_fc->mode; 1376 fc_conf->autoneg = net_fc->autoneg; 1377 return 0; 1378 } 1379 ret = fman_if_get_fc_threshold(dev->process_private); 1380 if (ret) { 1381 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1382 fc_conf->pause_time = 1383 fman_if_get_fc_quanta(dev->process_private); 1384 } else { 1385 fc_conf->mode = RTE_ETH_FC_NONE; 1386 } 1387 1388 return 0; 1389 } 1390 1391 static int 1392 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1393 struct rte_ether_addr *addr, 1394 uint32_t index, 1395 __rte_unused uint32_t pool) 1396 { 1397 int ret; 1398 1399 PMD_INIT_FUNC_TRACE(); 1400 1401 ret = fman_if_add_mac_addr(dev->process_private, 1402 addr->addr_bytes, index); 1403 1404 if (ret) 1405 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1406 return 0; 1407 } 1408 1409 static void 1410 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1411 uint32_t index) 1412 { 1413 PMD_INIT_FUNC_TRACE(); 1414 1415 fman_if_clear_mac_addr(dev->process_private, index); 1416 } 1417 1418 static int 1419 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1420 struct rte_ether_addr *addr) 1421 { 1422 int ret; 1423 1424 PMD_INIT_FUNC_TRACE(); 1425 1426 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1427 if (ret) 1428 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1429 1430 return ret; 1431 } 1432 1433 static int 1434 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1435 struct rte_eth_rss_conf *rss_conf) 1436 { 1437 struct rte_eth_dev_data *data = dev->data; 1438 struct rte_eth_conf *eth_conf = &data->dev_conf; 1439 1440 PMD_INIT_FUNC_TRACE(); 1441 1442 if (!(default_q || fmc_q)) { 1443 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1444 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1445 return -1; 1446 } 1447 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1448 } else { 1449 DPAA_PMD_ERR("Function not supported\n"); 1450 return -ENOTSUP; 1451 } 1452 return 0; 1453 } 1454 1455 static int 1456 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1457 struct rte_eth_rss_conf *rss_conf) 1458 { 1459 struct rte_eth_dev_data *data = dev->data; 1460 struct rte_eth_conf *eth_conf = &data->dev_conf; 1461 1462 /* dpaa does not support rss_key, so length should be 0*/ 1463 rss_conf->rss_key_len = 0; 1464 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1465 return 0; 1466 } 1467 1468 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1469 uint16_t queue_id) 1470 { 1471 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1472 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1473 1474 if (!rxq->is_static) 1475 return -EINVAL; 1476 1477 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1478 } 1479 1480 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1481 uint16_t queue_id) 1482 { 1483 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1484 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1485 uint32_t temp; 1486 ssize_t temp1; 1487 1488 if (!rxq->is_static) 1489 return -EINVAL; 1490 1491 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1492 1493 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1494 if (temp1 != sizeof(temp)) 1495 DPAA_PMD_ERR("irq read error"); 1496 1497 qman_fq_portal_thread_irq(rxq->qp); 1498 1499 return 0; 1500 } 1501 1502 static void 1503 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1504 struct rte_eth_rxq_info *qinfo) 1505 { 1506 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1507 struct qman_fq *rxq; 1508 int ret; 1509 1510 rxq = dev->data->rx_queues[queue_id]; 1511 1512 qinfo->mp = dpaa_intf->bp_info->mp; 1513 qinfo->scattered_rx = dev->data->scattered_rx; 1514 qinfo->nb_desc = rxq->nb_desc; 1515 1516 /* Report the HW Rx buffer length to user */ 1517 ret = fman_if_get_maxfrm(dev->process_private); 1518 if (ret > 0) 1519 qinfo->rx_buf_size = ret; 1520 1521 qinfo->conf.rx_free_thresh = 1; 1522 qinfo->conf.rx_drop_en = 1; 1523 qinfo->conf.rx_deferred_start = 0; 1524 qinfo->conf.offloads = rxq->offloads; 1525 } 1526 1527 static void 1528 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1529 struct rte_eth_txq_info *qinfo) 1530 { 1531 struct qman_fq *txq; 1532 1533 txq = dev->data->tx_queues[queue_id]; 1534 1535 qinfo->nb_desc = txq->nb_desc; 1536 qinfo->conf.tx_thresh.pthresh = 0; 1537 qinfo->conf.tx_thresh.hthresh = 0; 1538 qinfo->conf.tx_thresh.wthresh = 0; 1539 1540 qinfo->conf.tx_free_thresh = 0; 1541 qinfo->conf.tx_rs_thresh = 0; 1542 qinfo->conf.offloads = txq->offloads; 1543 qinfo->conf.tx_deferred_start = 0; 1544 } 1545 1546 static struct eth_dev_ops dpaa_devops = { 1547 .dev_configure = dpaa_eth_dev_configure, 1548 .dev_start = dpaa_eth_dev_start, 1549 .dev_stop = dpaa_eth_dev_stop, 1550 .dev_close = dpaa_eth_dev_close, 1551 .dev_infos_get = dpaa_eth_dev_info, 1552 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1553 1554 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1555 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1556 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1557 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1558 .rxq_info_get = dpaa_rxq_info_get, 1559 .txq_info_get = dpaa_txq_info_get, 1560 1561 .flow_ctrl_get = dpaa_flow_ctrl_get, 1562 .flow_ctrl_set = dpaa_flow_ctrl_set, 1563 1564 .link_update = dpaa_eth_link_update, 1565 .stats_get = dpaa_eth_stats_get, 1566 .xstats_get = dpaa_dev_xstats_get, 1567 .xstats_get_by_id = dpaa_xstats_get_by_id, 1568 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1569 .xstats_get_names = dpaa_xstats_get_names, 1570 .xstats_reset = dpaa_eth_stats_reset, 1571 .stats_reset = dpaa_eth_stats_reset, 1572 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1573 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1574 .allmulticast_enable = dpaa_eth_multicast_enable, 1575 .allmulticast_disable = dpaa_eth_multicast_disable, 1576 .mtu_set = dpaa_mtu_set, 1577 .dev_set_link_down = dpaa_link_down, 1578 .dev_set_link_up = dpaa_link_up, 1579 .mac_addr_add = dpaa_dev_add_mac_addr, 1580 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1581 .mac_addr_set = dpaa_dev_set_mac_addr, 1582 1583 .fw_version_get = dpaa_fw_version_get, 1584 1585 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1586 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1587 .rss_hash_update = dpaa_dev_rss_hash_update, 1588 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1589 }; 1590 1591 static bool 1592 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1593 { 1594 if (strcmp(dev->device->driver->name, 1595 drv->driver.name)) 1596 return false; 1597 1598 return true; 1599 } 1600 1601 static bool 1602 is_dpaa_supported(struct rte_eth_dev *dev) 1603 { 1604 return is_device_supported(dev, &rte_dpaa_pmd); 1605 } 1606 1607 int 1608 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1609 { 1610 struct rte_eth_dev *dev; 1611 1612 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1613 1614 dev = &rte_eth_devices[port]; 1615 1616 if (!is_dpaa_supported(dev)) 1617 return -ENOTSUP; 1618 1619 if (on) 1620 fman_if_loopback_enable(dev->process_private); 1621 else 1622 fman_if_loopback_disable(dev->process_private); 1623 1624 return 0; 1625 } 1626 1627 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1628 struct fman_if *fman_intf) 1629 { 1630 struct rte_eth_fc_conf *fc_conf; 1631 int ret; 1632 1633 PMD_INIT_FUNC_TRACE(); 1634 1635 if (!(dpaa_intf->fc_conf)) { 1636 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1637 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1638 if (!dpaa_intf->fc_conf) { 1639 DPAA_PMD_ERR("unable to save flow control info"); 1640 return -ENOMEM; 1641 } 1642 } 1643 fc_conf = dpaa_intf->fc_conf; 1644 ret = fman_if_get_fc_threshold(fman_intf); 1645 if (ret) { 1646 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1647 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1648 } else { 1649 fc_conf->mode = RTE_ETH_FC_NONE; 1650 } 1651 1652 return 0; 1653 } 1654 1655 /* Initialise an Rx FQ */ 1656 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1657 uint32_t fqid) 1658 { 1659 struct qm_mcc_initfq opts = {0}; 1660 int ret; 1661 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1662 struct qm_mcc_initcgr cgr_opts = { 1663 .we_mask = QM_CGR_WE_CS_THRES | 1664 QM_CGR_WE_CSTD_EN | 1665 QM_CGR_WE_MODE, 1666 .cgr = { 1667 .cstd_en = QM_CGR_EN, 1668 .mode = QMAN_CGR_MODE_FRAME 1669 } 1670 }; 1671 1672 if (fmc_q || default_q) { 1673 ret = qman_reserve_fqid(fqid); 1674 if (ret) { 1675 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1676 fqid, ret); 1677 return -EINVAL; 1678 } 1679 } 1680 1681 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1682 ret = qman_create_fq(fqid, flags, fq); 1683 if (ret) { 1684 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1685 fqid, ret); 1686 return ret; 1687 } 1688 fq->is_static = false; 1689 1690 dpaa_poll_queue_default_config(&opts); 1691 1692 if (cgr_rx) { 1693 /* Enable tail drop with cgr on this queue */ 1694 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1695 cgr_rx->cb = NULL; 1696 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1697 &cgr_opts); 1698 if (ret) { 1699 DPAA_PMD_WARN( 1700 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1701 fq->fqid, ret); 1702 goto without_cgr; 1703 } 1704 opts.we_mask |= QM_INITFQ_WE_CGID; 1705 opts.fqd.cgid = cgr_rx->cgrid; 1706 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1707 } 1708 without_cgr: 1709 ret = qman_init_fq(fq, 0, &opts); 1710 if (ret) 1711 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1712 return ret; 1713 } 1714 1715 /* Initialise a Tx FQ */ 1716 static int dpaa_tx_queue_init(struct qman_fq *fq, 1717 struct fman_if *fman_intf, 1718 struct qman_cgr *cgr_tx) 1719 { 1720 struct qm_mcc_initfq opts = {0}; 1721 struct qm_mcc_initcgr cgr_opts = { 1722 .we_mask = QM_CGR_WE_CS_THRES | 1723 QM_CGR_WE_CSTD_EN | 1724 QM_CGR_WE_MODE, 1725 .cgr = { 1726 .cstd_en = QM_CGR_EN, 1727 .mode = QMAN_CGR_MODE_FRAME 1728 } 1729 }; 1730 int ret; 1731 1732 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1733 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1734 if (ret) { 1735 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1736 return ret; 1737 } 1738 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1739 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1740 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1741 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1742 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1743 opts.fqd.context_b = 0; 1744 /* no tx-confirmation */ 1745 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1746 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1747 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1748 1749 if (cgr_tx) { 1750 /* Enable tail drop with cgr on this queue */ 1751 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1752 td_tx_threshold, 0); 1753 cgr_tx->cb = NULL; 1754 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1755 &cgr_opts); 1756 if (ret) { 1757 DPAA_PMD_WARN( 1758 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1759 fq->fqid, ret); 1760 goto without_cgr; 1761 } 1762 opts.we_mask |= QM_INITFQ_WE_CGID; 1763 opts.fqd.cgid = cgr_tx->cgrid; 1764 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1765 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1766 td_tx_threshold); 1767 } 1768 without_cgr: 1769 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1770 if (ret) 1771 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1772 return ret; 1773 } 1774 1775 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1776 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1777 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1778 { 1779 struct qm_mcc_initfq opts = {0}; 1780 int ret; 1781 1782 PMD_INIT_FUNC_TRACE(); 1783 1784 ret = qman_reserve_fqid(fqid); 1785 if (ret) { 1786 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1787 fqid, ret); 1788 return -EINVAL; 1789 } 1790 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1791 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1792 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1793 if (ret) { 1794 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1795 fqid, ret); 1796 return ret; 1797 } 1798 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1799 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1800 ret = qman_init_fq(fq, 0, &opts); 1801 if (ret) 1802 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1803 fqid, ret); 1804 return ret; 1805 } 1806 #endif 1807 1808 /* Initialise a network interface */ 1809 static int 1810 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1811 { 1812 struct rte_dpaa_device *dpaa_device; 1813 struct fm_eth_port_cfg *cfg; 1814 struct dpaa_if *dpaa_intf; 1815 struct fman_if *fman_intf; 1816 int dev_id; 1817 1818 PMD_INIT_FUNC_TRACE(); 1819 1820 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1821 dev_id = dpaa_device->id.dev_id; 1822 cfg = dpaa_get_eth_port_cfg(dev_id); 1823 fman_intf = cfg->fman_if; 1824 eth_dev->process_private = fman_intf; 1825 1826 /* Plugging of UCODE burst API not supported in Secondary */ 1827 dpaa_intf = eth_dev->data->dev_private; 1828 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1829 if (dpaa_intf->cgr_tx) 1830 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1831 else 1832 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1833 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1834 qman_set_fq_lookup_table( 1835 dpaa_intf->rx_queues->qman_fq_lookup_table); 1836 #endif 1837 1838 return 0; 1839 } 1840 1841 /* Initialise a network interface */ 1842 static int 1843 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1844 { 1845 int num_rx_fqs, fqid; 1846 int loop, ret = 0; 1847 int dev_id; 1848 struct rte_dpaa_device *dpaa_device; 1849 struct dpaa_if *dpaa_intf; 1850 struct fm_eth_port_cfg *cfg; 1851 struct fman_if *fman_intf; 1852 struct fman_if_bpool *bp, *tmp_bp; 1853 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1854 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1855 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1856 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1857 int8_t vsp_id = -1; 1858 1859 PMD_INIT_FUNC_TRACE(); 1860 1861 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1862 dev_id = dpaa_device->id.dev_id; 1863 dpaa_intf = eth_dev->data->dev_private; 1864 cfg = dpaa_get_eth_port_cfg(dev_id); 1865 fman_intf = cfg->fman_if; 1866 1867 dpaa_intf->name = dpaa_device->name; 1868 1869 /* save fman_if & cfg in the interface struture */ 1870 eth_dev->process_private = fman_intf; 1871 dpaa_intf->ifid = dev_id; 1872 dpaa_intf->cfg = cfg; 1873 1874 memset((char *)dev_rx_fqids, 0, 1875 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1876 1877 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1878 1879 /* Initialize Rx FQ's */ 1880 if (default_q) { 1881 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1882 } else if (fmc_q) { 1883 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1884 dev_vspids, 1885 DPAA_MAX_NUM_PCD_QUEUES); 1886 if (num_rx_fqs < 0) { 1887 DPAA_PMD_ERR("%s FMC initializes failed!", 1888 dpaa_intf->name); 1889 goto free_rx; 1890 } 1891 if (!num_rx_fqs) { 1892 DPAA_PMD_WARN("%s is not configured by FMC.", 1893 dpaa_intf->name); 1894 } 1895 } else { 1896 /* FMCLESS mode, load balance to multiple cores.*/ 1897 num_rx_fqs = rte_lcore_count(); 1898 } 1899 1900 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1901 * queues. 1902 */ 1903 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1904 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1905 return -EINVAL; 1906 } 1907 1908 if (num_rx_fqs > 0) { 1909 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1910 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1911 if (!dpaa_intf->rx_queues) { 1912 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1913 return -ENOMEM; 1914 } 1915 } else { 1916 dpaa_intf->rx_queues = NULL; 1917 } 1918 1919 memset(cgrid, 0, sizeof(cgrid)); 1920 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1921 1922 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1923 * Tx tail drop is disabled. 1924 */ 1925 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1926 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1927 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1928 td_tx_threshold); 1929 /* if a very large value is being configured */ 1930 if (td_tx_threshold > UINT16_MAX) 1931 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1932 } 1933 1934 /* If congestion control is enabled globally*/ 1935 if (num_rx_fqs > 0 && td_threshold) { 1936 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1937 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1938 if (!dpaa_intf->cgr_rx) { 1939 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1940 ret = -ENOMEM; 1941 goto free_rx; 1942 } 1943 1944 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1945 if (ret != num_rx_fqs) { 1946 DPAA_PMD_WARN("insufficient CGRIDs available"); 1947 ret = -EINVAL; 1948 goto free_rx; 1949 } 1950 } else { 1951 dpaa_intf->cgr_rx = NULL; 1952 } 1953 1954 if (!fmc_q && !default_q) { 1955 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1956 num_rx_fqs, 0); 1957 if (ret < 0) { 1958 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1959 goto free_rx; 1960 } 1961 } 1962 1963 for (loop = 0; loop < num_rx_fqs; loop++) { 1964 if (default_q) 1965 fqid = cfg->rx_def; 1966 else 1967 fqid = dev_rx_fqids[loop]; 1968 1969 vsp_id = dev_vspids[loop]; 1970 1971 if (dpaa_intf->cgr_rx) 1972 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1973 1974 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1975 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1976 fqid); 1977 if (ret) 1978 goto free_rx; 1979 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 1980 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1981 } 1982 dpaa_intf->nb_rx_queues = num_rx_fqs; 1983 1984 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1985 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1986 MAX_DPAA_CORES, MAX_CACHELINE); 1987 if (!dpaa_intf->tx_queues) { 1988 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1989 ret = -ENOMEM; 1990 goto free_rx; 1991 } 1992 1993 /* If congestion control is enabled globally*/ 1994 if (td_tx_threshold) { 1995 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 1996 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 1997 MAX_CACHELINE); 1998 if (!dpaa_intf->cgr_tx) { 1999 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 2000 ret = -ENOMEM; 2001 goto free_rx; 2002 } 2003 2004 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2005 1, 0); 2006 if (ret != MAX_DPAA_CORES) { 2007 DPAA_PMD_WARN("insufficient CGRIDs available"); 2008 ret = -EINVAL; 2009 goto free_rx; 2010 } 2011 } else { 2012 dpaa_intf->cgr_tx = NULL; 2013 } 2014 2015 2016 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2017 if (dpaa_intf->cgr_tx) 2018 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2019 2020 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2021 fman_intf, 2022 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2023 if (ret) 2024 goto free_tx; 2025 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2026 } 2027 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2028 2029 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2030 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2031 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2032 if (ret) { 2033 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2034 goto free_tx; 2035 } 2036 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2037 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2038 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2039 if (ret) { 2040 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2041 goto free_tx; 2042 } 2043 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2044 #endif 2045 2046 DPAA_PMD_DEBUG("All frame queues created"); 2047 2048 /* Get the initial configuration for flow control */ 2049 dpaa_fc_set_default(dpaa_intf, fman_intf); 2050 2051 /* reset bpool list, initialize bpool dynamically */ 2052 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2053 list_del(&bp->node); 2054 rte_free(bp); 2055 } 2056 2057 /* Populate ethdev structure */ 2058 eth_dev->dev_ops = &dpaa_devops; 2059 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2060 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2061 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2062 2063 /* Allocate memory for storing MAC addresses */ 2064 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2065 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2066 if (eth_dev->data->mac_addrs == NULL) { 2067 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2068 "store MAC addresses", 2069 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2070 ret = -ENOMEM; 2071 goto free_tx; 2072 } 2073 2074 /* copy the primary mac address */ 2075 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2076 2077 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n", 2078 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2079 2080 if (!fman_intf->is_shared_mac) { 2081 /* Configure error packet handling */ 2082 fman_if_receive_rx_errors(fman_intf, 2083 FM_FD_RX_STATUS_ERR_MASK); 2084 /* Disable RX mode */ 2085 fman_if_disable_rx(fman_intf); 2086 /* Disable promiscuous mode */ 2087 fman_if_promiscuous_disable(fman_intf); 2088 /* Disable multicast */ 2089 fman_if_reset_mcast_filter_table(fman_intf); 2090 /* Reset interface statistics */ 2091 fman_if_stats_reset(fman_intf); 2092 /* Disable SG by default */ 2093 fman_if_set_sg(fman_intf, 0); 2094 fman_if_set_maxfrm(fman_intf, 2095 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2096 } 2097 2098 return 0; 2099 2100 free_tx: 2101 rte_free(dpaa_intf->tx_queues); 2102 dpaa_intf->tx_queues = NULL; 2103 dpaa_intf->nb_tx_queues = 0; 2104 2105 free_rx: 2106 rte_free(dpaa_intf->cgr_rx); 2107 rte_free(dpaa_intf->cgr_tx); 2108 rte_free(dpaa_intf->rx_queues); 2109 dpaa_intf->rx_queues = NULL; 2110 dpaa_intf->nb_rx_queues = 0; 2111 return ret; 2112 } 2113 2114 static int 2115 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2116 struct rte_dpaa_device *dpaa_dev) 2117 { 2118 int diag; 2119 int ret; 2120 struct rte_eth_dev *eth_dev; 2121 2122 PMD_INIT_FUNC_TRACE(); 2123 2124 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2125 RTE_PKTMBUF_HEADROOM) { 2126 DPAA_PMD_ERR( 2127 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2128 RTE_PKTMBUF_HEADROOM, 2129 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2130 2131 return -1; 2132 } 2133 2134 /* In case of secondary process, the device is already configured 2135 * and no further action is required, except portal initialization 2136 * and verifying secondary attachment to port name. 2137 */ 2138 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2139 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2140 if (!eth_dev) 2141 return -ENOMEM; 2142 eth_dev->device = &dpaa_dev->device; 2143 eth_dev->dev_ops = &dpaa_devops; 2144 2145 ret = dpaa_dev_init_secondary(eth_dev); 2146 if (ret != 0) { 2147 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 2148 return ret; 2149 } 2150 2151 rte_eth_dev_probing_finish(eth_dev); 2152 return 0; 2153 } 2154 2155 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2156 if (access("/tmp/fmc.bin", F_OK) == -1) { 2157 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2158 default_q = 1; 2159 } 2160 2161 if (!(default_q || fmc_q)) { 2162 if (dpaa_fm_init()) { 2163 DPAA_PMD_ERR("FM init failed\n"); 2164 return -1; 2165 } 2166 } 2167 2168 /* disabling the default push mode for LS1043 */ 2169 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2170 dpaa_push_mode_max_queue = 0; 2171 2172 /* if push mode queues to be enabled. Currenly we are allowing 2173 * only one queue per thread. 2174 */ 2175 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2176 dpaa_push_mode_max_queue = 2177 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2178 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2179 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2180 } 2181 2182 is_global_init = 1; 2183 } 2184 2185 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2186 ret = rte_dpaa_portal_init((void *)1); 2187 if (ret) { 2188 DPAA_PMD_ERR("Unable to initialize portal"); 2189 return ret; 2190 } 2191 } 2192 2193 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2194 if (!eth_dev) 2195 return -ENOMEM; 2196 2197 eth_dev->data->dev_private = 2198 rte_zmalloc("ethdev private structure", 2199 sizeof(struct dpaa_if), 2200 RTE_CACHE_LINE_SIZE); 2201 if (!eth_dev->data->dev_private) { 2202 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2203 rte_eth_dev_release_port(eth_dev); 2204 return -ENOMEM; 2205 } 2206 2207 eth_dev->device = &dpaa_dev->device; 2208 dpaa_dev->eth_dev = eth_dev; 2209 2210 qman_ern_register_cb(dpaa_free_mbuf); 2211 2212 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2213 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2214 2215 /* Invoke PMD device initialization function */ 2216 diag = dpaa_dev_init(eth_dev); 2217 if (diag == 0) { 2218 rte_eth_dev_probing_finish(eth_dev); 2219 return 0; 2220 } 2221 2222 rte_eth_dev_release_port(eth_dev); 2223 return diag; 2224 } 2225 2226 static int 2227 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2228 { 2229 struct rte_eth_dev *eth_dev; 2230 int ret; 2231 2232 PMD_INIT_FUNC_TRACE(); 2233 2234 eth_dev = dpaa_dev->eth_dev; 2235 dpaa_eth_dev_close(eth_dev); 2236 ret = rte_eth_dev_release_port(eth_dev); 2237 2238 return ret; 2239 } 2240 2241 static void __attribute__((destructor(102))) dpaa_finish(void) 2242 { 2243 /* For secondary, primary will do all the cleanup */ 2244 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2245 return; 2246 2247 if (!(default_q || fmc_q)) { 2248 unsigned int i; 2249 2250 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2251 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2252 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2253 struct dpaa_if *dpaa_intf = 2254 dev->data->dev_private; 2255 struct fman_if *fif = 2256 dev->process_private; 2257 if (dpaa_intf->port_handle) 2258 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2259 DPAA_PMD_WARN("DPAA FM " 2260 "deconfig failed\n"); 2261 if (fif->num_profiles) { 2262 if (dpaa_port_vsp_cleanup(dpaa_intf, 2263 fif)) 2264 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2265 } 2266 } 2267 } 2268 if (is_global_init) 2269 if (dpaa_fm_term()) 2270 DPAA_PMD_WARN("DPAA FM term failed\n"); 2271 2272 is_global_init = 0; 2273 2274 DPAA_PMD_INFO("DPAA fman cleaned up"); 2275 } 2276 } 2277 2278 static struct rte_dpaa_driver rte_dpaa_pmd = { 2279 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2280 .drv_type = FSL_DPAA_ETH, 2281 .probe = rte_dpaa_probe, 2282 .remove = rte_dpaa_remove, 2283 }; 2284 2285 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2286 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2287