1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_byteorder.h> 19 #include <rte_common.h> 20 #include <rte_interrupts.h> 21 #include <rte_log.h> 22 #include <rte_debug.h> 23 #include <rte_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_malloc.h> 33 #include <rte_ring.h> 34 35 #include <rte_dpaa_bus.h> 36 #include <rte_dpaa_logs.h> 37 #include <dpaa_mempool.h> 38 39 #include <dpaa_ethdev.h> 40 #include <dpaa_rxtx.h> 41 #include <rte_pmd_dpaa.h> 42 43 #include <fsl_usd.h> 44 #include <fsl_qman.h> 45 #include <fsl_bman.h> 46 #include <fsl_fman.h> 47 48 /* Supported Rx offloads */ 49 static uint64_t dev_rx_offloads_sup = 50 DEV_RX_OFFLOAD_JUMBO_FRAME | 51 DEV_RX_OFFLOAD_SCATTER; 52 53 /* Rx offloads which cannot be disabled */ 54 static uint64_t dev_rx_offloads_nodis = 55 DEV_RX_OFFLOAD_IPV4_CKSUM | 56 DEV_RX_OFFLOAD_UDP_CKSUM | 57 DEV_RX_OFFLOAD_TCP_CKSUM | 58 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 59 60 /* Supported Tx offloads */ 61 static uint64_t dev_tx_offloads_sup; 62 63 /* Tx offloads which cannot be disabled */ 64 static uint64_t dev_tx_offloads_nodis = 65 DEV_TX_OFFLOAD_IPV4_CKSUM | 66 DEV_TX_OFFLOAD_UDP_CKSUM | 67 DEV_TX_OFFLOAD_TCP_CKSUM | 68 DEV_TX_OFFLOAD_SCTP_CKSUM | 69 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 70 DEV_TX_OFFLOAD_MULTI_SEGS | 71 DEV_TX_OFFLOAD_MT_LOCKFREE | 72 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 73 74 /* Keep track of whether QMAN and BMAN have been globally initialized */ 75 static int is_global_init; 76 static int default_q; /* use default queue - FMC is not executed*/ 77 /* At present we only allow up to 4 push mode queues as default - as each of 78 * this queue need dedicated portal and we are short of portals. 79 */ 80 #define DPAA_MAX_PUSH_MODE_QUEUE 8 81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 82 83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 85 86 87 /* Per FQ Taildrop in frame count */ 88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 89 90 struct rte_dpaa_xstats_name_off { 91 char name[RTE_ETH_XSTATS_NAME_SIZE]; 92 uint32_t offset; 93 }; 94 95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 96 {"rx_align_err", 97 offsetof(struct dpaa_if_stats, raln)}, 98 {"rx_valid_pause", 99 offsetof(struct dpaa_if_stats, rxpf)}, 100 {"rx_fcs_err", 101 offsetof(struct dpaa_if_stats, rfcs)}, 102 {"rx_vlan_frame", 103 offsetof(struct dpaa_if_stats, rvlan)}, 104 {"rx_frame_err", 105 offsetof(struct dpaa_if_stats, rerr)}, 106 {"rx_drop_err", 107 offsetof(struct dpaa_if_stats, rdrp)}, 108 {"rx_undersized", 109 offsetof(struct dpaa_if_stats, rund)}, 110 {"rx_oversize_err", 111 offsetof(struct dpaa_if_stats, rovr)}, 112 {"rx_fragment_pkt", 113 offsetof(struct dpaa_if_stats, rfrg)}, 114 {"tx_valid_pause", 115 offsetof(struct dpaa_if_stats, txpf)}, 116 {"tx_fcs_err", 117 offsetof(struct dpaa_if_stats, terr)}, 118 {"tx_vlan_frame", 119 offsetof(struct dpaa_if_stats, tvlan)}, 120 {"rx_undersized", 121 offsetof(struct dpaa_if_stats, tund)}, 122 }; 123 124 static struct rte_dpaa_driver rte_dpaa_pmd; 125 126 static void 127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 128 129 static inline void 130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 131 { 132 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 135 QM_FQCTRL_PREFERINCACHE; 136 opts->fqd.context_a.stashing.exclusive = 0; 137 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 138 opts->fqd.context_a.stashing.annotation_cl = 139 DPAA_IF_RX_ANNOTATION_STASH; 140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 142 } 143 144 static int 145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 146 { 147 struct dpaa_if *dpaa_intf = dev->data->dev_private; 148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 149 + VLAN_TAG_SIZE; 150 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 151 152 PMD_INIT_FUNC_TRACE(); 153 154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 155 return -EINVAL; 156 /* 157 * Refuse mtu that requires the support of scattered packets 158 * when this feature has not been enabled before. 159 */ 160 if (dev->data->min_rx_buf_size && 161 !dev->data->scattered_rx && frame_size > buffsz) { 162 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 163 return -EINVAL; 164 } 165 166 /* check <seg size> * <max_seg> >= max_frame */ 167 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 168 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 169 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 170 buffsz * DPAA_SGT_MAX_ENTRIES); 171 return -EINVAL; 172 } 173 174 if (frame_size > ETHER_MAX_LEN) 175 dev->data->dev_conf.rxmode.offloads &= 176 DEV_RX_OFFLOAD_JUMBO_FRAME; 177 else 178 dev->data->dev_conf.rxmode.offloads &= 179 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 180 181 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 182 183 fman_if_set_maxfrm(dpaa_intf->fif, frame_size); 184 185 return 0; 186 } 187 188 static int 189 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 190 { 191 struct dpaa_if *dpaa_intf = dev->data->dev_private; 192 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 193 uint64_t rx_offloads = eth_conf->rxmode.offloads; 194 uint64_t tx_offloads = eth_conf->txmode.offloads; 195 196 PMD_INIT_FUNC_TRACE(); 197 198 /* Rx offloads validation */ 199 if (dev_rx_offloads_nodis & ~rx_offloads) { 200 DPAA_PMD_WARN( 201 "Rx offloads non configurable - requested 0x%" PRIx64 202 " ignored 0x%" PRIx64, 203 rx_offloads, dev_rx_offloads_nodis); 204 } 205 206 /* Tx offloads validation */ 207 if (dev_tx_offloads_nodis & ~tx_offloads) { 208 DPAA_PMD_WARN( 209 "Tx offloads non configurable - requested 0x%" PRIx64 210 " ignored 0x%" PRIx64, 211 tx_offloads, dev_tx_offloads_nodis); 212 } 213 214 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 215 uint32_t max_len; 216 217 DPAA_PMD_DEBUG("enabling jumbo"); 218 219 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 220 DPAA_MAX_RX_PKT_LEN) 221 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 222 else { 223 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 224 "supported is %d", 225 dev->data->dev_conf.rxmode.max_rx_pkt_len, 226 DPAA_MAX_RX_PKT_LEN); 227 max_len = DPAA_MAX_RX_PKT_LEN; 228 } 229 230 fman_if_set_maxfrm(dpaa_intf->fif, max_len); 231 dev->data->mtu = max_len 232 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE; 233 } 234 235 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 236 DPAA_PMD_DEBUG("enabling scatter mode"); 237 fman_if_set_sg(dpaa_intf->fif, 1); 238 dev->data->scattered_rx = 1; 239 } 240 241 return 0; 242 } 243 244 static const uint32_t * 245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 246 { 247 static const uint32_t ptypes[] = { 248 RTE_PTYPE_L2_ETHER, 249 RTE_PTYPE_L2_ETHER_VLAN, 250 RTE_PTYPE_L2_ETHER_ARP, 251 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 252 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 253 RTE_PTYPE_L4_ICMP, 254 RTE_PTYPE_L4_TCP, 255 RTE_PTYPE_L4_UDP, 256 RTE_PTYPE_L4_FRAG, 257 RTE_PTYPE_L4_TCP, 258 RTE_PTYPE_L4_UDP, 259 RTE_PTYPE_L4_SCTP 260 }; 261 262 PMD_INIT_FUNC_TRACE(); 263 264 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 265 return ptypes; 266 return NULL; 267 } 268 269 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 270 { 271 struct dpaa_if *dpaa_intf = dev->data->dev_private; 272 273 PMD_INIT_FUNC_TRACE(); 274 275 /* Change tx callback to the real one */ 276 dev->tx_pkt_burst = dpaa_eth_queue_tx; 277 fman_if_enable_rx(dpaa_intf->fif); 278 279 return 0; 280 } 281 282 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 283 { 284 struct dpaa_if *dpaa_intf = dev->data->dev_private; 285 286 PMD_INIT_FUNC_TRACE(); 287 288 fman_if_disable_rx(dpaa_intf->fif); 289 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 290 } 291 292 static void dpaa_eth_dev_close(struct rte_eth_dev *dev) 293 { 294 PMD_INIT_FUNC_TRACE(); 295 296 dpaa_eth_dev_stop(dev); 297 } 298 299 static int 300 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 301 char *fw_version, 302 size_t fw_size) 303 { 304 int ret; 305 FILE *svr_file = NULL; 306 unsigned int svr_ver = 0; 307 308 PMD_INIT_FUNC_TRACE(); 309 310 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 311 if (!svr_file) { 312 DPAA_PMD_ERR("Unable to open SoC device"); 313 return -ENOTSUP; /* Not supported on this infra */ 314 } 315 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 316 dpaa_svr_family = svr_ver & SVR_MASK; 317 else 318 DPAA_PMD_ERR("Unable to read SoC device"); 319 320 fclose(svr_file); 321 322 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 323 svr_ver, fman_ip_rev); 324 ret += 1; /* add the size of '\0' */ 325 326 if (fw_size < (uint32_t)ret) 327 return ret; 328 else 329 return 0; 330 } 331 332 static void dpaa_eth_dev_info(struct rte_eth_dev *dev, 333 struct rte_eth_dev_info *dev_info) 334 { 335 struct dpaa_if *dpaa_intf = dev->data->dev_private; 336 337 PMD_INIT_FUNC_TRACE(); 338 339 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 340 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 341 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 342 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 343 dev_info->max_hash_mac_addrs = 0; 344 dev_info->max_vfs = 0; 345 dev_info->max_vmdq_pools = ETH_16_POOLS; 346 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 347 348 if (dpaa_intf->fif->mac_type == fman_mac_1g) 349 dev_info->speed_capa = ETH_LINK_SPEED_1G; 350 else if (dpaa_intf->fif->mac_type == fman_mac_10g) 351 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G); 352 else 353 DPAA_PMD_ERR("invalid link_speed: %s, %d", 354 dpaa_intf->name, dpaa_intf->fif->mac_type); 355 356 dev_info->rx_offload_capa = dev_rx_offloads_sup | 357 dev_rx_offloads_nodis; 358 dev_info->tx_offload_capa = dev_tx_offloads_sup | 359 dev_tx_offloads_nodis; 360 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 361 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 362 } 363 364 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 365 int wait_to_complete __rte_unused) 366 { 367 struct dpaa_if *dpaa_intf = dev->data->dev_private; 368 struct rte_eth_link *link = &dev->data->dev_link; 369 370 PMD_INIT_FUNC_TRACE(); 371 372 if (dpaa_intf->fif->mac_type == fman_mac_1g) 373 link->link_speed = ETH_SPEED_NUM_1G; 374 else if (dpaa_intf->fif->mac_type == fman_mac_10g) 375 link->link_speed = ETH_SPEED_NUM_10G; 376 else 377 DPAA_PMD_ERR("invalid link_speed: %s, %d", 378 dpaa_intf->name, dpaa_intf->fif->mac_type); 379 380 link->link_status = dpaa_intf->valid; 381 link->link_duplex = ETH_LINK_FULL_DUPLEX; 382 link->link_autoneg = ETH_LINK_AUTONEG; 383 return 0; 384 } 385 386 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 387 struct rte_eth_stats *stats) 388 { 389 struct dpaa_if *dpaa_intf = dev->data->dev_private; 390 391 PMD_INIT_FUNC_TRACE(); 392 393 fman_if_stats_get(dpaa_intf->fif, stats); 394 return 0; 395 } 396 397 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev) 398 { 399 struct dpaa_if *dpaa_intf = dev->data->dev_private; 400 401 PMD_INIT_FUNC_TRACE(); 402 403 fman_if_stats_reset(dpaa_intf->fif); 404 } 405 406 static int 407 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 408 unsigned int n) 409 { 410 struct dpaa_if *dpaa_intf = dev->data->dev_private; 411 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 412 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 413 414 if (n < num) 415 return num; 416 417 if (xstats == NULL) 418 return 0; 419 420 fman_if_stats_get_all(dpaa_intf->fif, values, 421 sizeof(struct dpaa_if_stats) / 8); 422 423 for (i = 0; i < num; i++) { 424 xstats[i].id = i; 425 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 426 } 427 return i; 428 } 429 430 static int 431 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 432 struct rte_eth_xstat_name *xstats_names, 433 unsigned int limit) 434 { 435 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 436 437 if (limit < stat_cnt) 438 return stat_cnt; 439 440 if (xstats_names != NULL) 441 for (i = 0; i < stat_cnt; i++) 442 snprintf(xstats_names[i].name, 443 sizeof(xstats_names[i].name), 444 "%s", 445 dpaa_xstats_strings[i].name); 446 447 return stat_cnt; 448 } 449 450 static int 451 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 452 uint64_t *values, unsigned int n) 453 { 454 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 455 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 456 457 if (!ids) { 458 struct dpaa_if *dpaa_intf = dev->data->dev_private; 459 460 if (n < stat_cnt) 461 return stat_cnt; 462 463 if (!values) 464 return 0; 465 466 fman_if_stats_get_all(dpaa_intf->fif, values_copy, 467 sizeof(struct dpaa_if_stats) / 8); 468 469 for (i = 0; i < stat_cnt; i++) 470 values[i] = 471 values_copy[dpaa_xstats_strings[i].offset / 8]; 472 473 return stat_cnt; 474 } 475 476 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 477 478 for (i = 0; i < n; i++) { 479 if (ids[i] >= stat_cnt) { 480 DPAA_PMD_ERR("id value isn't valid"); 481 return -1; 482 } 483 values[i] = values_copy[ids[i]]; 484 } 485 return n; 486 } 487 488 static int 489 dpaa_xstats_get_names_by_id( 490 struct rte_eth_dev *dev, 491 struct rte_eth_xstat_name *xstats_names, 492 const uint64_t *ids, 493 unsigned int limit) 494 { 495 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 496 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 497 498 if (!ids) 499 return dpaa_xstats_get_names(dev, xstats_names, limit); 500 501 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 502 503 for (i = 0; i < limit; i++) { 504 if (ids[i] >= stat_cnt) { 505 DPAA_PMD_ERR("id value isn't valid"); 506 return -1; 507 } 508 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 509 } 510 return limit; 511 } 512 513 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 514 { 515 struct dpaa_if *dpaa_intf = dev->data->dev_private; 516 517 PMD_INIT_FUNC_TRACE(); 518 519 fman_if_promiscuous_enable(dpaa_intf->fif); 520 } 521 522 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 523 { 524 struct dpaa_if *dpaa_intf = dev->data->dev_private; 525 526 PMD_INIT_FUNC_TRACE(); 527 528 fman_if_promiscuous_disable(dpaa_intf->fif); 529 } 530 531 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 532 { 533 struct dpaa_if *dpaa_intf = dev->data->dev_private; 534 535 PMD_INIT_FUNC_TRACE(); 536 537 fman_if_set_mcast_filter_table(dpaa_intf->fif); 538 } 539 540 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 541 { 542 struct dpaa_if *dpaa_intf = dev->data->dev_private; 543 544 PMD_INIT_FUNC_TRACE(); 545 546 fman_if_reset_mcast_filter_table(dpaa_intf->fif); 547 } 548 549 static 550 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 551 uint16_t nb_desc, 552 unsigned int socket_id __rte_unused, 553 const struct rte_eth_rxconf *rx_conf __rte_unused, 554 struct rte_mempool *mp) 555 { 556 struct dpaa_if *dpaa_intf = dev->data->dev_private; 557 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 558 struct qm_mcc_initfq opts = {0}; 559 u32 flags = 0; 560 int ret; 561 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 562 563 PMD_INIT_FUNC_TRACE(); 564 565 if (queue_idx >= dev->data->nb_rx_queues) { 566 rte_errno = EOVERFLOW; 567 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 568 (void *)dev, queue_idx, dev->data->nb_rx_queues); 569 return -rte_errno; 570 } 571 572 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 573 queue_idx, rxq->fqid); 574 575 /* Max packet can fit in single buffer */ 576 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { 577 ; 578 } else if (dev->data->dev_conf.rxmode.offloads & 579 DEV_RX_OFFLOAD_SCATTER) { 580 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > 581 buffsz * DPAA_SGT_MAX_ENTRIES) { 582 DPAA_PMD_ERR("max RxPkt size %d too big to fit " 583 "MaxSGlist %d", 584 dev->data->dev_conf.rxmode.max_rx_pkt_len, 585 buffsz * DPAA_SGT_MAX_ENTRIES); 586 rte_errno = EOVERFLOW; 587 return -rte_errno; 588 } 589 } else { 590 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 591 " larger than a single mbuf (%u) and scattered" 592 " mode has not been requested", 593 dev->data->dev_conf.rxmode.max_rx_pkt_len, 594 buffsz - RTE_PKTMBUF_HEADROOM); 595 } 596 597 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) { 598 struct fman_if_ic_params icp; 599 uint32_t fd_offset; 600 uint32_t bp_size; 601 602 if (!mp->pool_data) { 603 DPAA_PMD_ERR("Not an offloaded buffer pool!"); 604 return -1; 605 } 606 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 607 608 memset(&icp, 0, sizeof(icp)); 609 /* set ICEOF for to the default value , which is 0*/ 610 icp.iciof = DEFAULT_ICIOF; 611 icp.iceof = DEFAULT_RX_ICEOF; 612 icp.icsz = DEFAULT_ICSZ; 613 fman_if_set_ic_params(dpaa_intf->fif, &icp); 614 615 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 616 fman_if_set_fdoff(dpaa_intf->fif, fd_offset); 617 618 /* Buffer pool size should be equal to Dataroom Size*/ 619 bp_size = rte_pktmbuf_data_room_size(mp); 620 fman_if_set_bp(dpaa_intf->fif, mp->size, 621 dpaa_intf->bp_info->bpid, bp_size); 622 dpaa_intf->valid = 1; 623 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d", 624 dpaa_intf->name, fd_offset, 625 fman_if_get_fdoff(dpaa_intf->fif)); 626 } 627 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 628 fman_if_get_sg_enable(dpaa_intf->fif), 629 dev->data->dev_conf.rxmode.max_rx_pkt_len); 630 /* checking if push mode only, no error check for now */ 631 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 632 dpaa_push_queue_idx++; 633 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 634 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 635 QM_FQCTRL_CTXASTASHING | 636 QM_FQCTRL_PREFERINCACHE; 637 opts.fqd.context_a.stashing.exclusive = 0; 638 /* In muticore scenario stashing becomes a bottleneck on LS1046. 639 * So do not enable stashing in this case 640 */ 641 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 642 opts.fqd.context_a.stashing.annotation_cl = 643 DPAA_IF_RX_ANNOTATION_STASH; 644 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 645 opts.fqd.context_a.stashing.context_cl = 646 DPAA_IF_RX_CONTEXT_STASH; 647 648 /*Create a channel and associate given queue with the channel*/ 649 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 650 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 651 opts.fqd.dest.channel = rxq->ch_id; 652 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 653 flags = QMAN_INITFQ_FLAG_SCHED; 654 655 /* Configure tail drop */ 656 if (dpaa_intf->cgr_rx) { 657 opts.we_mask |= QM_INITFQ_WE_CGID; 658 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 659 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 660 } 661 ret = qman_init_fq(rxq, flags, &opts); 662 if (ret) { 663 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 664 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 665 return ret; 666 } 667 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 668 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 669 } else { 670 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 671 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 672 } 673 674 rxq->is_static = true; 675 } 676 rxq->bp_array = rte_dpaa_bpid_info; 677 dev->data->rx_queues[queue_idx] = rxq; 678 679 /* configure the CGR size as per the desc size */ 680 if (dpaa_intf->cgr_rx) { 681 struct qm_mcc_initcgr cgr_opts = {0}; 682 683 /* Enable tail drop with cgr on this queue */ 684 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 685 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 686 if (ret) { 687 DPAA_PMD_WARN( 688 "rx taildrop modify fail on fqid %d (ret=%d)", 689 rxq->fqid, ret); 690 } 691 } 692 693 return 0; 694 } 695 696 int 697 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 698 int eth_rx_queue_id, 699 u16 ch_id, 700 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 701 { 702 int ret; 703 u32 flags = 0; 704 struct dpaa_if *dpaa_intf = dev->data->dev_private; 705 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 706 struct qm_mcc_initfq opts = {0}; 707 708 if (dpaa_push_mode_max_queue) 709 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 710 "PUSH mode already enabled for first %d queues.\n" 711 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 712 dpaa_push_mode_max_queue); 713 714 dpaa_poll_queue_default_config(&opts); 715 716 switch (queue_conf->ev.sched_type) { 717 case RTE_SCHED_TYPE_ATOMIC: 718 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 719 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 720 * configuration with HOLD_ACTIVE setting 721 */ 722 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 723 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 724 break; 725 case RTE_SCHED_TYPE_ORDERED: 726 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 727 return -1; 728 default: 729 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 730 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 731 break; 732 } 733 734 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 735 opts.fqd.dest.channel = ch_id; 736 opts.fqd.dest.wq = queue_conf->ev.priority; 737 738 if (dpaa_intf->cgr_rx) { 739 opts.we_mask |= QM_INITFQ_WE_CGID; 740 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 741 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 742 } 743 744 flags = QMAN_INITFQ_FLAG_SCHED; 745 746 ret = qman_init_fq(rxq, flags, &opts); 747 if (ret) { 748 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 749 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 750 return ret; 751 } 752 753 /* copy configuration which needs to be filled during dequeue */ 754 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 755 dev->data->rx_queues[eth_rx_queue_id] = rxq; 756 757 return ret; 758 } 759 760 int 761 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 762 int eth_rx_queue_id) 763 { 764 struct qm_mcc_initfq opts; 765 int ret; 766 u32 flags = 0; 767 struct dpaa_if *dpaa_intf = dev->data->dev_private; 768 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 769 770 dpaa_poll_queue_default_config(&opts); 771 772 if (dpaa_intf->cgr_rx) { 773 opts.we_mask |= QM_INITFQ_WE_CGID; 774 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 775 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 776 } 777 778 ret = qman_init_fq(rxq, flags, &opts); 779 if (ret) { 780 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 781 rxq->fqid, ret); 782 } 783 784 rxq->cb.dqrr_dpdk_cb = NULL; 785 dev->data->rx_queues[eth_rx_queue_id] = NULL; 786 787 return 0; 788 } 789 790 static 791 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 792 { 793 PMD_INIT_FUNC_TRACE(); 794 } 795 796 static 797 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 798 uint16_t nb_desc __rte_unused, 799 unsigned int socket_id __rte_unused, 800 const struct rte_eth_txconf *tx_conf __rte_unused) 801 { 802 struct dpaa_if *dpaa_intf = dev->data->dev_private; 803 804 PMD_INIT_FUNC_TRACE(); 805 806 if (queue_idx >= dev->data->nb_tx_queues) { 807 rte_errno = EOVERFLOW; 808 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 809 (void *)dev, queue_idx, dev->data->nb_tx_queues); 810 return -rte_errno; 811 } 812 813 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 814 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid); 815 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; 816 return 0; 817 } 818 819 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 820 { 821 PMD_INIT_FUNC_TRACE(); 822 } 823 824 static uint32_t 825 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 826 { 827 struct dpaa_if *dpaa_intf = dev->data->dev_private; 828 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 829 u32 frm_cnt = 0; 830 831 PMD_INIT_FUNC_TRACE(); 832 833 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 834 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n", 835 rx_queue_id, frm_cnt); 836 } 837 return frm_cnt; 838 } 839 840 static int dpaa_link_down(struct rte_eth_dev *dev) 841 { 842 PMD_INIT_FUNC_TRACE(); 843 844 dpaa_eth_dev_stop(dev); 845 return 0; 846 } 847 848 static int dpaa_link_up(struct rte_eth_dev *dev) 849 { 850 PMD_INIT_FUNC_TRACE(); 851 852 dpaa_eth_dev_start(dev); 853 return 0; 854 } 855 856 static int 857 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 858 struct rte_eth_fc_conf *fc_conf) 859 { 860 struct dpaa_if *dpaa_intf = dev->data->dev_private; 861 struct rte_eth_fc_conf *net_fc; 862 863 PMD_INIT_FUNC_TRACE(); 864 865 if (!(dpaa_intf->fc_conf)) { 866 dpaa_intf->fc_conf = rte_zmalloc(NULL, 867 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 868 if (!dpaa_intf->fc_conf) { 869 DPAA_PMD_ERR("unable to save flow control info"); 870 return -ENOMEM; 871 } 872 } 873 net_fc = dpaa_intf->fc_conf; 874 875 if (fc_conf->high_water < fc_conf->low_water) { 876 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 877 return -EINVAL; 878 } 879 880 if (fc_conf->mode == RTE_FC_NONE) { 881 return 0; 882 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 883 fc_conf->mode == RTE_FC_FULL) { 884 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water, 885 fc_conf->low_water, 886 dpaa_intf->bp_info->bpid); 887 if (fc_conf->pause_time) 888 fman_if_set_fc_quanta(dpaa_intf->fif, 889 fc_conf->pause_time); 890 } 891 892 /* Save the information in dpaa device */ 893 net_fc->pause_time = fc_conf->pause_time; 894 net_fc->high_water = fc_conf->high_water; 895 net_fc->low_water = fc_conf->low_water; 896 net_fc->send_xon = fc_conf->send_xon; 897 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 898 net_fc->mode = fc_conf->mode; 899 net_fc->autoneg = fc_conf->autoneg; 900 901 return 0; 902 } 903 904 static int 905 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 906 struct rte_eth_fc_conf *fc_conf) 907 { 908 struct dpaa_if *dpaa_intf = dev->data->dev_private; 909 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 910 int ret; 911 912 PMD_INIT_FUNC_TRACE(); 913 914 if (net_fc) { 915 fc_conf->pause_time = net_fc->pause_time; 916 fc_conf->high_water = net_fc->high_water; 917 fc_conf->low_water = net_fc->low_water; 918 fc_conf->send_xon = net_fc->send_xon; 919 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 920 fc_conf->mode = net_fc->mode; 921 fc_conf->autoneg = net_fc->autoneg; 922 return 0; 923 } 924 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 925 if (ret) { 926 fc_conf->mode = RTE_FC_TX_PAUSE; 927 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 928 } else { 929 fc_conf->mode = RTE_FC_NONE; 930 } 931 932 return 0; 933 } 934 935 static int 936 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 937 struct ether_addr *addr, 938 uint32_t index, 939 __rte_unused uint32_t pool) 940 { 941 int ret; 942 struct dpaa_if *dpaa_intf = dev->data->dev_private; 943 944 PMD_INIT_FUNC_TRACE(); 945 946 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index); 947 948 if (ret) 949 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:" 950 " err = %d", ret); 951 return 0; 952 } 953 954 static void 955 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 956 uint32_t index) 957 { 958 struct dpaa_if *dpaa_intf = dev->data->dev_private; 959 960 PMD_INIT_FUNC_TRACE(); 961 962 fman_if_clear_mac_addr(dpaa_intf->fif, index); 963 } 964 965 static int 966 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 967 struct ether_addr *addr) 968 { 969 int ret; 970 struct dpaa_if *dpaa_intf = dev->data->dev_private; 971 972 PMD_INIT_FUNC_TRACE(); 973 974 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0); 975 if (ret) 976 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret); 977 978 return ret; 979 } 980 981 static struct eth_dev_ops dpaa_devops = { 982 .dev_configure = dpaa_eth_dev_configure, 983 .dev_start = dpaa_eth_dev_start, 984 .dev_stop = dpaa_eth_dev_stop, 985 .dev_close = dpaa_eth_dev_close, 986 .dev_infos_get = dpaa_eth_dev_info, 987 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 988 989 .rx_queue_setup = dpaa_eth_rx_queue_setup, 990 .tx_queue_setup = dpaa_eth_tx_queue_setup, 991 .rx_queue_release = dpaa_eth_rx_queue_release, 992 .tx_queue_release = dpaa_eth_tx_queue_release, 993 .rx_queue_count = dpaa_dev_rx_queue_count, 994 995 .flow_ctrl_get = dpaa_flow_ctrl_get, 996 .flow_ctrl_set = dpaa_flow_ctrl_set, 997 998 .link_update = dpaa_eth_link_update, 999 .stats_get = dpaa_eth_stats_get, 1000 .xstats_get = dpaa_dev_xstats_get, 1001 .xstats_get_by_id = dpaa_xstats_get_by_id, 1002 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1003 .xstats_get_names = dpaa_xstats_get_names, 1004 .xstats_reset = dpaa_eth_stats_reset, 1005 .stats_reset = dpaa_eth_stats_reset, 1006 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1007 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1008 .allmulticast_enable = dpaa_eth_multicast_enable, 1009 .allmulticast_disable = dpaa_eth_multicast_disable, 1010 .mtu_set = dpaa_mtu_set, 1011 .dev_set_link_down = dpaa_link_down, 1012 .dev_set_link_up = dpaa_link_up, 1013 .mac_addr_add = dpaa_dev_add_mac_addr, 1014 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1015 .mac_addr_set = dpaa_dev_set_mac_addr, 1016 1017 .fw_version_get = dpaa_fw_version_get, 1018 }; 1019 1020 static bool 1021 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1022 { 1023 if (strcmp(dev->device->driver->name, 1024 drv->driver.name)) 1025 return false; 1026 1027 return true; 1028 } 1029 1030 static bool 1031 is_dpaa_supported(struct rte_eth_dev *dev) 1032 { 1033 return is_device_supported(dev, &rte_dpaa_pmd); 1034 } 1035 1036 int 1037 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) 1038 { 1039 struct rte_eth_dev *dev; 1040 struct dpaa_if *dpaa_intf; 1041 1042 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1043 1044 dev = &rte_eth_devices[port]; 1045 1046 if (!is_dpaa_supported(dev)) 1047 return -ENOTSUP; 1048 1049 dpaa_intf = dev->data->dev_private; 1050 1051 if (on) 1052 fman_if_loopback_enable(dpaa_intf->fif); 1053 else 1054 fman_if_loopback_disable(dpaa_intf->fif); 1055 1056 return 0; 1057 } 1058 1059 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) 1060 { 1061 struct rte_eth_fc_conf *fc_conf; 1062 int ret; 1063 1064 PMD_INIT_FUNC_TRACE(); 1065 1066 if (!(dpaa_intf->fc_conf)) { 1067 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1068 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1069 if (!dpaa_intf->fc_conf) { 1070 DPAA_PMD_ERR("unable to save flow control info"); 1071 return -ENOMEM; 1072 } 1073 } 1074 fc_conf = dpaa_intf->fc_conf; 1075 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 1076 if (ret) { 1077 fc_conf->mode = RTE_FC_TX_PAUSE; 1078 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 1079 } else { 1080 fc_conf->mode = RTE_FC_NONE; 1081 } 1082 1083 return 0; 1084 } 1085 1086 /* Initialise an Rx FQ */ 1087 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1088 uint32_t fqid) 1089 { 1090 struct qm_mcc_initfq opts = {0}; 1091 int ret; 1092 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1093 struct qm_mcc_initcgr cgr_opts = { 1094 .we_mask = QM_CGR_WE_CS_THRES | 1095 QM_CGR_WE_CSTD_EN | 1096 QM_CGR_WE_MODE, 1097 .cgr = { 1098 .cstd_en = QM_CGR_EN, 1099 .mode = QMAN_CGR_MODE_FRAME 1100 } 1101 }; 1102 1103 PMD_INIT_FUNC_TRACE(); 1104 1105 if (fqid) { 1106 ret = qman_reserve_fqid(fqid); 1107 if (ret) { 1108 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d", 1109 fqid, ret); 1110 return -EINVAL; 1111 } 1112 } else { 1113 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 1114 } 1115 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1116 ret = qman_create_fq(fqid, flags, fq); 1117 if (ret) { 1118 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1119 fqid, ret); 1120 return ret; 1121 } 1122 fq->is_static = false; 1123 1124 dpaa_poll_queue_default_config(&opts); 1125 1126 if (cgr_rx) { 1127 /* Enable tail drop with cgr on this queue */ 1128 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1129 cgr_rx->cb = NULL; 1130 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1131 &cgr_opts); 1132 if (ret) { 1133 DPAA_PMD_WARN( 1134 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1135 fq->fqid, ret); 1136 goto without_cgr; 1137 } 1138 opts.we_mask |= QM_INITFQ_WE_CGID; 1139 opts.fqd.cgid = cgr_rx->cgrid; 1140 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1141 } 1142 without_cgr: 1143 ret = qman_init_fq(fq, 0, &opts); 1144 if (ret) 1145 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1146 return ret; 1147 } 1148 1149 /* Initialise a Tx FQ */ 1150 static int dpaa_tx_queue_init(struct qman_fq *fq, 1151 struct fman_if *fman_intf) 1152 { 1153 struct qm_mcc_initfq opts = {0}; 1154 int ret; 1155 1156 PMD_INIT_FUNC_TRACE(); 1157 1158 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1159 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1160 if (ret) { 1161 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1162 return ret; 1163 } 1164 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1165 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1166 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1167 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1168 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1169 opts.fqd.context_b = 0; 1170 /* no tx-confirmation */ 1171 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1172 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1173 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1174 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1175 if (ret) 1176 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1177 return ret; 1178 } 1179 1180 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1181 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1182 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1183 { 1184 struct qm_mcc_initfq opts = {0}; 1185 int ret; 1186 1187 PMD_INIT_FUNC_TRACE(); 1188 1189 ret = qman_reserve_fqid(fqid); 1190 if (ret) { 1191 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1192 fqid, ret); 1193 return -EINVAL; 1194 } 1195 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1196 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1197 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1198 if (ret) { 1199 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1200 fqid, ret); 1201 return ret; 1202 } 1203 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1204 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1205 ret = qman_init_fq(fq, 0, &opts); 1206 if (ret) 1207 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1208 fqid, ret); 1209 return ret; 1210 } 1211 #endif 1212 1213 /* Initialise a network interface */ 1214 static int 1215 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1216 { 1217 int num_cores, num_rx_fqs, fqid; 1218 int loop, ret = 0; 1219 int dev_id; 1220 struct rte_dpaa_device *dpaa_device; 1221 struct dpaa_if *dpaa_intf; 1222 struct fm_eth_port_cfg *cfg; 1223 struct fman_if *fman_intf; 1224 struct fman_if_bpool *bp, *tmp_bp; 1225 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1226 1227 PMD_INIT_FUNC_TRACE(); 1228 1229 dpaa_intf = eth_dev->data->dev_private; 1230 /* For secondary processes, the primary has done all the work */ 1231 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1232 eth_dev->dev_ops = &dpaa_devops; 1233 /* Plugging of UCODE burst API not supported in Secondary */ 1234 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1235 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1236 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1237 qman_set_fq_lookup_table( 1238 dpaa_intf->rx_queues->qman_fq_lookup_table); 1239 #endif 1240 return 0; 1241 } 1242 1243 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1244 dev_id = dpaa_device->id.dev_id; 1245 dpaa_intf = eth_dev->data->dev_private; 1246 cfg = &dpaa_netcfg->port_cfg[dev_id]; 1247 fman_intf = cfg->fman_if; 1248 1249 dpaa_intf->name = dpaa_device->name; 1250 1251 /* save fman_if & cfg in the interface struture */ 1252 dpaa_intf->fif = fman_intf; 1253 dpaa_intf->ifid = dev_id; 1254 dpaa_intf->cfg = cfg; 1255 1256 /* Initialize Rx FQ's */ 1257 if (default_q) { 1258 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1259 } else { 1260 if (getenv("DPAA_NUM_RX_QUEUES")) 1261 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES")); 1262 else 1263 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1264 } 1265 1266 1267 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1268 * queues. 1269 */ 1270 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1271 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1272 return -EINVAL; 1273 } 1274 1275 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1276 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1277 if (!dpaa_intf->rx_queues) { 1278 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1279 return -ENOMEM; 1280 } 1281 1282 /* If congestion control is enabled globally*/ 1283 if (td_threshold) { 1284 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1285 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1286 if (!dpaa_intf->cgr_rx) { 1287 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1288 ret = -ENOMEM; 1289 goto free_rx; 1290 } 1291 1292 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1293 if (ret != num_rx_fqs) { 1294 DPAA_PMD_WARN("insufficient CGRIDs available"); 1295 ret = -EINVAL; 1296 goto free_rx; 1297 } 1298 } else { 1299 dpaa_intf->cgr_rx = NULL; 1300 } 1301 1302 for (loop = 0; loop < num_rx_fqs; loop++) { 1303 if (default_q) 1304 fqid = cfg->rx_def; 1305 else 1306 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx * 1307 DPAA_PCD_FQID_MULTIPLIER + loop; 1308 1309 if (dpaa_intf->cgr_rx) 1310 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1311 1312 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1313 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1314 fqid); 1315 if (ret) 1316 goto free_rx; 1317 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1318 } 1319 dpaa_intf->nb_rx_queues = num_rx_fqs; 1320 1321 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1322 num_cores = rte_lcore_count(); 1323 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1324 num_cores, MAX_CACHELINE); 1325 if (!dpaa_intf->tx_queues) { 1326 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1327 ret = -ENOMEM; 1328 goto free_rx; 1329 } 1330 1331 for (loop = 0; loop < num_cores; loop++) { 1332 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1333 fman_intf); 1334 if (ret) 1335 goto free_tx; 1336 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1337 } 1338 dpaa_intf->nb_tx_queues = num_cores; 1339 1340 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1341 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1342 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1343 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1344 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1345 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1346 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1347 #endif 1348 1349 DPAA_PMD_DEBUG("All frame queues created"); 1350 1351 /* Get the initial configuration for flow control */ 1352 dpaa_fc_set_default(dpaa_intf); 1353 1354 /* reset bpool list, initialize bpool dynamically */ 1355 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1356 list_del(&bp->node); 1357 rte_free(bp); 1358 } 1359 1360 /* Populate ethdev structure */ 1361 eth_dev->dev_ops = &dpaa_devops; 1362 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1363 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1364 1365 /* Allocate memory for storing MAC addresses */ 1366 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1367 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1368 if (eth_dev->data->mac_addrs == NULL) { 1369 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1370 "store MAC addresses", 1371 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1372 ret = -ENOMEM; 1373 goto free_tx; 1374 } 1375 1376 /* copy the primary mac address */ 1377 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1378 1379 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1380 dpaa_device->name, 1381 fman_intf->mac_addr.addr_bytes[0], 1382 fman_intf->mac_addr.addr_bytes[1], 1383 fman_intf->mac_addr.addr_bytes[2], 1384 fman_intf->mac_addr.addr_bytes[3], 1385 fman_intf->mac_addr.addr_bytes[4], 1386 fman_intf->mac_addr.addr_bytes[5]); 1387 1388 /* Disable RX mode */ 1389 fman_if_discard_rx_errors(fman_intf); 1390 fman_if_disable_rx(fman_intf); 1391 /* Disable promiscuous mode */ 1392 fman_if_promiscuous_disable(fman_intf); 1393 /* Disable multicast */ 1394 fman_if_reset_mcast_filter_table(fman_intf); 1395 /* Reset interface statistics */ 1396 fman_if_stats_reset(fman_intf); 1397 /* Disable SG by default */ 1398 fman_if_set_sg(fman_intf, 0); 1399 fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE); 1400 1401 return 0; 1402 1403 free_tx: 1404 rte_free(dpaa_intf->tx_queues); 1405 dpaa_intf->tx_queues = NULL; 1406 dpaa_intf->nb_tx_queues = 0; 1407 1408 free_rx: 1409 rte_free(dpaa_intf->cgr_rx); 1410 rte_free(dpaa_intf->rx_queues); 1411 dpaa_intf->rx_queues = NULL; 1412 dpaa_intf->nb_rx_queues = 0; 1413 return ret; 1414 } 1415 1416 static int 1417 dpaa_dev_uninit(struct rte_eth_dev *dev) 1418 { 1419 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1420 int loop; 1421 1422 PMD_INIT_FUNC_TRACE(); 1423 1424 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1425 return -EPERM; 1426 1427 if (!dpaa_intf) { 1428 DPAA_PMD_WARN("Already closed or not started"); 1429 return -1; 1430 } 1431 1432 dpaa_eth_dev_close(dev); 1433 1434 /* release configuration memory */ 1435 if (dpaa_intf->fc_conf) 1436 rte_free(dpaa_intf->fc_conf); 1437 1438 /* Release RX congestion Groups */ 1439 if (dpaa_intf->cgr_rx) { 1440 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 1441 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 1442 1443 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 1444 dpaa_intf->nb_rx_queues); 1445 } 1446 1447 rte_free(dpaa_intf->cgr_rx); 1448 dpaa_intf->cgr_rx = NULL; 1449 1450 rte_free(dpaa_intf->rx_queues); 1451 dpaa_intf->rx_queues = NULL; 1452 1453 rte_free(dpaa_intf->tx_queues); 1454 dpaa_intf->tx_queues = NULL; 1455 1456 dev->dev_ops = NULL; 1457 dev->rx_pkt_burst = NULL; 1458 dev->tx_pkt_burst = NULL; 1459 1460 return 0; 1461 } 1462 1463 static int 1464 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, 1465 struct rte_dpaa_device *dpaa_dev) 1466 { 1467 int diag; 1468 int ret; 1469 struct rte_eth_dev *eth_dev; 1470 1471 PMD_INIT_FUNC_TRACE(); 1472 1473 /* In case of secondary process, the device is already configured 1474 * and no further action is required, except portal initialization 1475 * and verifying secondary attachment to port name. 1476 */ 1477 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1478 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1479 if (!eth_dev) 1480 return -ENOMEM; 1481 eth_dev->device = &dpaa_dev->device; 1482 eth_dev->dev_ops = &dpaa_devops; 1483 rte_eth_dev_probing_finish(eth_dev); 1484 return 0; 1485 } 1486 1487 if (!is_global_init) { 1488 /* One time load of Qman/Bman drivers */ 1489 ret = qman_global_init(); 1490 if (ret) { 1491 DPAA_PMD_ERR("QMAN initialization failed: %d", 1492 ret); 1493 return ret; 1494 } 1495 ret = bman_global_init(); 1496 if (ret) { 1497 DPAA_PMD_ERR("BMAN initialization failed: %d", 1498 ret); 1499 return ret; 1500 } 1501 1502 if (access("/tmp/fmc.bin", F_OK) == -1) { 1503 RTE_LOG(INFO, PMD, 1504 "* FMC not configured.Enabling default mode\n"); 1505 default_q = 1; 1506 } 1507 1508 /* disabling the default push mode for LS1043 */ 1509 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 1510 dpaa_push_mode_max_queue = 0; 1511 1512 /* if push mode queues to be enabled. Currenly we are allowing 1513 * only one queue per thread. 1514 */ 1515 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 1516 dpaa_push_mode_max_queue = 1517 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 1518 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 1519 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 1520 } 1521 1522 is_global_init = 1; 1523 } 1524 1525 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 1526 ret = rte_dpaa_portal_init((void *)1); 1527 if (ret) { 1528 DPAA_PMD_ERR("Unable to initialize portal"); 1529 return ret; 1530 } 1531 } 1532 1533 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 1534 if (eth_dev == NULL) 1535 return -ENOMEM; 1536 1537 eth_dev->data->dev_private = rte_zmalloc( 1538 "ethdev private structure", 1539 sizeof(struct dpaa_if), 1540 RTE_CACHE_LINE_SIZE); 1541 if (!eth_dev->data->dev_private) { 1542 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 1543 rte_eth_dev_release_port(eth_dev); 1544 return -ENOMEM; 1545 } 1546 1547 eth_dev->device = &dpaa_dev->device; 1548 dpaa_dev->eth_dev = eth_dev; 1549 1550 /* Invoke PMD device initialization function */ 1551 diag = dpaa_dev_init(eth_dev); 1552 if (diag == 0) { 1553 rte_eth_dev_probing_finish(eth_dev); 1554 return 0; 1555 } 1556 1557 rte_eth_dev_release_port(eth_dev); 1558 return diag; 1559 } 1560 1561 static int 1562 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 1563 { 1564 struct rte_eth_dev *eth_dev; 1565 1566 PMD_INIT_FUNC_TRACE(); 1567 1568 eth_dev = dpaa_dev->eth_dev; 1569 dpaa_dev_uninit(eth_dev); 1570 1571 rte_eth_dev_release_port(eth_dev); 1572 1573 return 0; 1574 } 1575 1576 static struct rte_dpaa_driver rte_dpaa_pmd = { 1577 .drv_type = FSL_DPAA_ETH, 1578 .probe = rte_dpaa_probe, 1579 .remove = rte_dpaa_remove, 1580 }; 1581 1582 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 1583