1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_byteorder.h> 19 #include <rte_common.h> 20 #include <rte_interrupts.h> 21 #include <rte_log.h> 22 #include <rte_debug.h> 23 #include <rte_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_malloc.h> 33 #include <rte_ring.h> 34 35 #include <rte_dpaa_bus.h> 36 #include <rte_dpaa_logs.h> 37 #include <dpaa_mempool.h> 38 39 #include <dpaa_ethdev.h> 40 #include <dpaa_rxtx.h> 41 #include <rte_pmd_dpaa.h> 42 43 #include <fsl_usd.h> 44 #include <fsl_qman.h> 45 #include <fsl_bman.h> 46 #include <fsl_fman.h> 47 48 /* Supported Rx offloads */ 49 static uint64_t dev_rx_offloads_sup = 50 DEV_RX_OFFLOAD_JUMBO_FRAME; 51 52 /* Rx offloads which cannot be disabled */ 53 static uint64_t dev_rx_offloads_nodis = 54 DEV_RX_OFFLOAD_IPV4_CKSUM | 55 DEV_RX_OFFLOAD_UDP_CKSUM | 56 DEV_RX_OFFLOAD_TCP_CKSUM | 57 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 58 DEV_RX_OFFLOAD_CRC_STRIP | 59 DEV_RX_OFFLOAD_SCATTER; 60 61 /* Supported Tx offloads */ 62 static uint64_t dev_tx_offloads_sup; 63 64 /* Tx offloads which cannot be disabled */ 65 static uint64_t dev_tx_offloads_nodis = 66 DEV_TX_OFFLOAD_IPV4_CKSUM | 67 DEV_TX_OFFLOAD_UDP_CKSUM | 68 DEV_TX_OFFLOAD_TCP_CKSUM | 69 DEV_TX_OFFLOAD_SCTP_CKSUM | 70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 71 DEV_TX_OFFLOAD_MULTI_SEGS | 72 DEV_TX_OFFLOAD_MT_LOCKFREE | 73 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 74 75 /* Keep track of whether QMAN and BMAN have been globally initialized */ 76 static int is_global_init; 77 /* At present we only allow up to 4 push mode queues as default - as each of 78 * this queue need dedicated portal and we are short of portals. 79 */ 80 #define DPAA_MAX_PUSH_MODE_QUEUE 8 81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 82 83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 85 86 87 /* Per FQ Taildrop in frame count */ 88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 89 90 struct rte_dpaa_xstats_name_off { 91 char name[RTE_ETH_XSTATS_NAME_SIZE]; 92 uint32_t offset; 93 }; 94 95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 96 {"rx_align_err", 97 offsetof(struct dpaa_if_stats, raln)}, 98 {"rx_valid_pause", 99 offsetof(struct dpaa_if_stats, rxpf)}, 100 {"rx_fcs_err", 101 offsetof(struct dpaa_if_stats, rfcs)}, 102 {"rx_vlan_frame", 103 offsetof(struct dpaa_if_stats, rvlan)}, 104 {"rx_frame_err", 105 offsetof(struct dpaa_if_stats, rerr)}, 106 {"rx_drop_err", 107 offsetof(struct dpaa_if_stats, rdrp)}, 108 {"rx_undersized", 109 offsetof(struct dpaa_if_stats, rund)}, 110 {"rx_oversize_err", 111 offsetof(struct dpaa_if_stats, rovr)}, 112 {"rx_fragment_pkt", 113 offsetof(struct dpaa_if_stats, rfrg)}, 114 {"tx_valid_pause", 115 offsetof(struct dpaa_if_stats, txpf)}, 116 {"tx_fcs_err", 117 offsetof(struct dpaa_if_stats, terr)}, 118 {"tx_vlan_frame", 119 offsetof(struct dpaa_if_stats, tvlan)}, 120 {"rx_undersized", 121 offsetof(struct dpaa_if_stats, tund)}, 122 }; 123 124 static struct rte_dpaa_driver rte_dpaa_pmd; 125 126 static void 127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 128 129 static inline void 130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 131 { 132 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 135 QM_FQCTRL_PREFERINCACHE; 136 opts->fqd.context_a.stashing.exclusive = 0; 137 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 138 opts->fqd.context_a.stashing.annotation_cl = 139 DPAA_IF_RX_ANNOTATION_STASH; 140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 142 } 143 144 static int 145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 146 { 147 struct dpaa_if *dpaa_intf = dev->data->dev_private; 148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 149 + VLAN_TAG_SIZE; 150 151 PMD_INIT_FUNC_TRACE(); 152 153 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 154 return -EINVAL; 155 if (frame_size > ETHER_MAX_LEN) 156 dev->data->dev_conf.rxmode.offloads &= 157 DEV_RX_OFFLOAD_JUMBO_FRAME; 158 else 159 dev->data->dev_conf.rxmode.offloads &= 160 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 161 162 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 163 164 fman_if_set_maxfrm(dpaa_intf->fif, frame_size); 165 166 return 0; 167 } 168 169 static int 170 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 171 { 172 struct dpaa_if *dpaa_intf = dev->data->dev_private; 173 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 174 uint64_t rx_offloads = eth_conf->rxmode.offloads; 175 uint64_t tx_offloads = eth_conf->txmode.offloads; 176 177 PMD_INIT_FUNC_TRACE(); 178 179 /* Rx offloads validation */ 180 if (dev_rx_offloads_nodis & ~rx_offloads) { 181 DPAA_PMD_WARN( 182 "Rx offloads non configurable - requested 0x%" PRIx64 183 " ignored 0x%" PRIx64, 184 rx_offloads, dev_rx_offloads_nodis); 185 } 186 187 /* Tx offloads validation */ 188 if (dev_tx_offloads_nodis & ~tx_offloads) { 189 DPAA_PMD_WARN( 190 "Tx offloads non configurable - requested 0x%" PRIx64 191 " ignored 0x%" PRIx64, 192 tx_offloads, dev_tx_offloads_nodis); 193 } 194 195 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 196 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 197 DPAA_MAX_RX_PKT_LEN) { 198 fman_if_set_maxfrm(dpaa_intf->fif, 199 dev->data->dev_conf.rxmode.max_rx_pkt_len); 200 return 0; 201 } else { 202 return -1; 203 } 204 } 205 return 0; 206 } 207 208 static const uint32_t * 209 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 210 { 211 static const uint32_t ptypes[] = { 212 /*todo -= add more types */ 213 RTE_PTYPE_L2_ETHER, 214 RTE_PTYPE_L3_IPV4, 215 RTE_PTYPE_L3_IPV4_EXT, 216 RTE_PTYPE_L3_IPV6, 217 RTE_PTYPE_L3_IPV6_EXT, 218 RTE_PTYPE_L4_TCP, 219 RTE_PTYPE_L4_UDP, 220 RTE_PTYPE_L4_SCTP 221 }; 222 223 PMD_INIT_FUNC_TRACE(); 224 225 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 226 return ptypes; 227 return NULL; 228 } 229 230 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 231 { 232 struct dpaa_if *dpaa_intf = dev->data->dev_private; 233 234 PMD_INIT_FUNC_TRACE(); 235 236 /* Change tx callback to the real one */ 237 dev->tx_pkt_burst = dpaa_eth_queue_tx; 238 fman_if_enable_rx(dpaa_intf->fif); 239 240 return 0; 241 } 242 243 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 244 { 245 struct dpaa_if *dpaa_intf = dev->data->dev_private; 246 247 PMD_INIT_FUNC_TRACE(); 248 249 fman_if_disable_rx(dpaa_intf->fif); 250 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 251 } 252 253 static void dpaa_eth_dev_close(struct rte_eth_dev *dev) 254 { 255 PMD_INIT_FUNC_TRACE(); 256 257 dpaa_eth_dev_stop(dev); 258 } 259 260 static int 261 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 262 char *fw_version, 263 size_t fw_size) 264 { 265 int ret; 266 FILE *svr_file = NULL; 267 unsigned int svr_ver = 0; 268 269 PMD_INIT_FUNC_TRACE(); 270 271 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 272 if (!svr_file) { 273 DPAA_PMD_ERR("Unable to open SoC device"); 274 return -ENOTSUP; /* Not supported on this infra */ 275 } 276 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 277 dpaa_svr_family = svr_ver & SVR_MASK; 278 else 279 DPAA_PMD_ERR("Unable to read SoC device"); 280 281 fclose(svr_file); 282 283 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 284 svr_ver, fman_ip_rev); 285 ret += 1; /* add the size of '\0' */ 286 287 if (fw_size < (uint32_t)ret) 288 return ret; 289 else 290 return 0; 291 } 292 293 static void dpaa_eth_dev_info(struct rte_eth_dev *dev, 294 struct rte_eth_dev_info *dev_info) 295 { 296 struct dpaa_if *dpaa_intf = dev->data->dev_private; 297 298 PMD_INIT_FUNC_TRACE(); 299 300 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 301 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 302 dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE; 303 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 304 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 305 dev_info->max_hash_mac_addrs = 0; 306 dev_info->max_vfs = 0; 307 dev_info->max_vmdq_pools = ETH_16_POOLS; 308 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 309 dev_info->speed_capa = (ETH_LINK_SPEED_1G | 310 ETH_LINK_SPEED_10G); 311 dev_info->rx_offload_capa = dev_rx_offloads_sup | 312 dev_rx_offloads_nodis; 313 dev_info->tx_offload_capa = dev_tx_offloads_sup | 314 dev_tx_offloads_nodis; 315 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 316 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 317 } 318 319 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 320 int wait_to_complete __rte_unused) 321 { 322 struct dpaa_if *dpaa_intf = dev->data->dev_private; 323 struct rte_eth_link *link = &dev->data->dev_link; 324 325 PMD_INIT_FUNC_TRACE(); 326 327 if (dpaa_intf->fif->mac_type == fman_mac_1g) 328 link->link_speed = ETH_SPEED_NUM_1G; 329 else if (dpaa_intf->fif->mac_type == fman_mac_10g) 330 link->link_speed = ETH_SPEED_NUM_10G; 331 else 332 DPAA_PMD_ERR("invalid link_speed: %s, %d", 333 dpaa_intf->name, dpaa_intf->fif->mac_type); 334 335 link->link_status = dpaa_intf->valid; 336 link->link_duplex = ETH_LINK_FULL_DUPLEX; 337 link->link_autoneg = ETH_LINK_AUTONEG; 338 return 0; 339 } 340 341 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 342 struct rte_eth_stats *stats) 343 { 344 struct dpaa_if *dpaa_intf = dev->data->dev_private; 345 346 PMD_INIT_FUNC_TRACE(); 347 348 fman_if_stats_get(dpaa_intf->fif, stats); 349 return 0; 350 } 351 352 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev) 353 { 354 struct dpaa_if *dpaa_intf = dev->data->dev_private; 355 356 PMD_INIT_FUNC_TRACE(); 357 358 fman_if_stats_reset(dpaa_intf->fif); 359 } 360 361 static int 362 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 363 unsigned int n) 364 { 365 struct dpaa_if *dpaa_intf = dev->data->dev_private; 366 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 367 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 368 369 if (n < num) 370 return num; 371 372 if (xstats == NULL) 373 return 0; 374 375 fman_if_stats_get_all(dpaa_intf->fif, values, 376 sizeof(struct dpaa_if_stats) / 8); 377 378 for (i = 0; i < num; i++) { 379 xstats[i].id = i; 380 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 381 } 382 return i; 383 } 384 385 static int 386 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 387 struct rte_eth_xstat_name *xstats_names, 388 unsigned int limit) 389 { 390 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 391 392 if (limit < stat_cnt) 393 return stat_cnt; 394 395 if (xstats_names != NULL) 396 for (i = 0; i < stat_cnt; i++) 397 snprintf(xstats_names[i].name, 398 sizeof(xstats_names[i].name), 399 "%s", 400 dpaa_xstats_strings[i].name); 401 402 return stat_cnt; 403 } 404 405 static int 406 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 407 uint64_t *values, unsigned int n) 408 { 409 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 410 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 411 412 if (!ids) { 413 struct dpaa_if *dpaa_intf = dev->data->dev_private; 414 415 if (n < stat_cnt) 416 return stat_cnt; 417 418 if (!values) 419 return 0; 420 421 fman_if_stats_get_all(dpaa_intf->fif, values_copy, 422 sizeof(struct dpaa_if_stats) / 8); 423 424 for (i = 0; i < stat_cnt; i++) 425 values[i] = 426 values_copy[dpaa_xstats_strings[i].offset / 8]; 427 428 return stat_cnt; 429 } 430 431 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 432 433 for (i = 0; i < n; i++) { 434 if (ids[i] >= stat_cnt) { 435 DPAA_PMD_ERR("id value isn't valid"); 436 return -1; 437 } 438 values[i] = values_copy[ids[i]]; 439 } 440 return n; 441 } 442 443 static int 444 dpaa_xstats_get_names_by_id( 445 struct rte_eth_dev *dev, 446 struct rte_eth_xstat_name *xstats_names, 447 const uint64_t *ids, 448 unsigned int limit) 449 { 450 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 451 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 452 453 if (!ids) 454 return dpaa_xstats_get_names(dev, xstats_names, limit); 455 456 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 457 458 for (i = 0; i < limit; i++) { 459 if (ids[i] >= stat_cnt) { 460 DPAA_PMD_ERR("id value isn't valid"); 461 return -1; 462 } 463 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 464 } 465 return limit; 466 } 467 468 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 469 { 470 struct dpaa_if *dpaa_intf = dev->data->dev_private; 471 472 PMD_INIT_FUNC_TRACE(); 473 474 fman_if_promiscuous_enable(dpaa_intf->fif); 475 } 476 477 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 478 { 479 struct dpaa_if *dpaa_intf = dev->data->dev_private; 480 481 PMD_INIT_FUNC_TRACE(); 482 483 fman_if_promiscuous_disable(dpaa_intf->fif); 484 } 485 486 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 487 { 488 struct dpaa_if *dpaa_intf = dev->data->dev_private; 489 490 PMD_INIT_FUNC_TRACE(); 491 492 fman_if_set_mcast_filter_table(dpaa_intf->fif); 493 } 494 495 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 496 { 497 struct dpaa_if *dpaa_intf = dev->data->dev_private; 498 499 PMD_INIT_FUNC_TRACE(); 500 501 fman_if_reset_mcast_filter_table(dpaa_intf->fif); 502 } 503 504 static 505 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 506 uint16_t nb_desc, 507 unsigned int socket_id __rte_unused, 508 const struct rte_eth_rxconf *rx_conf __rte_unused, 509 struct rte_mempool *mp) 510 { 511 struct dpaa_if *dpaa_intf = dev->data->dev_private; 512 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 513 struct qm_mcc_initfq opts = {0}; 514 u32 flags = 0; 515 int ret; 516 517 PMD_INIT_FUNC_TRACE(); 518 519 DPAA_PMD_INFO("Rx queue setup for queue index: %d", queue_idx); 520 521 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) { 522 struct fman_if_ic_params icp; 523 uint32_t fd_offset; 524 uint32_t bp_size; 525 526 if (!mp->pool_data) { 527 DPAA_PMD_ERR("Not an offloaded buffer pool!"); 528 return -1; 529 } 530 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 531 532 memset(&icp, 0, sizeof(icp)); 533 /* set ICEOF for to the default value , which is 0*/ 534 icp.iciof = DEFAULT_ICIOF; 535 icp.iceof = DEFAULT_RX_ICEOF; 536 icp.icsz = DEFAULT_ICSZ; 537 fman_if_set_ic_params(dpaa_intf->fif, &icp); 538 539 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 540 fman_if_set_fdoff(dpaa_intf->fif, fd_offset); 541 542 /* Buffer pool size should be equal to Dataroom Size*/ 543 bp_size = rte_pktmbuf_data_room_size(mp); 544 fman_if_set_bp(dpaa_intf->fif, mp->size, 545 dpaa_intf->bp_info->bpid, bp_size); 546 dpaa_intf->valid = 1; 547 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d", 548 dpaa_intf->name, fd_offset, 549 fman_if_get_fdoff(dpaa_intf->fif)); 550 } 551 /* checking if push mode only, no error check for now */ 552 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 553 dpaa_push_queue_idx++; 554 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 555 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 556 QM_FQCTRL_CTXASTASHING | 557 QM_FQCTRL_PREFERINCACHE; 558 opts.fqd.context_a.stashing.exclusive = 0; 559 /* In muticore scenario stashing becomes a bottleneck on LS1046. 560 * So do not enable stashing in this case 561 */ 562 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 563 opts.fqd.context_a.stashing.annotation_cl = 564 DPAA_IF_RX_ANNOTATION_STASH; 565 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 566 opts.fqd.context_a.stashing.context_cl = 567 DPAA_IF_RX_CONTEXT_STASH; 568 569 /*Create a channel and associate given queue with the channel*/ 570 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 571 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 572 opts.fqd.dest.channel = rxq->ch_id; 573 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 574 flags = QMAN_INITFQ_FLAG_SCHED; 575 576 /* Configure tail drop */ 577 if (dpaa_intf->cgr_rx) { 578 opts.we_mask |= QM_INITFQ_WE_CGID; 579 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 580 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 581 } 582 ret = qman_init_fq(rxq, flags, &opts); 583 if (ret) 584 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d" 585 " ret: %d", rxq->fqid, ret); 586 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 587 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 588 rxq->is_static = true; 589 } 590 dev->data->rx_queues[queue_idx] = rxq; 591 592 /* configure the CGR size as per the desc size */ 593 if (dpaa_intf->cgr_rx) { 594 struct qm_mcc_initcgr cgr_opts = {0}; 595 596 /* Enable tail drop with cgr on this queue */ 597 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 598 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 599 if (ret) { 600 DPAA_PMD_WARN( 601 "rx taildrop modify fail on fqid %d (ret=%d)", 602 rxq->fqid, ret); 603 } 604 } 605 606 return 0; 607 } 608 609 int __rte_experimental 610 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 611 int eth_rx_queue_id, 612 u16 ch_id, 613 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 614 { 615 int ret; 616 u32 flags = 0; 617 struct dpaa_if *dpaa_intf = dev->data->dev_private; 618 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 619 struct qm_mcc_initfq opts = {0}; 620 621 if (dpaa_push_mode_max_queue) 622 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n" 623 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 624 dpaa_push_mode_max_queue); 625 626 dpaa_poll_queue_default_config(&opts); 627 628 switch (queue_conf->ev.sched_type) { 629 case RTE_SCHED_TYPE_ATOMIC: 630 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 631 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 632 * configuration with HOLD_ACTIVE setting 633 */ 634 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 635 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 636 break; 637 case RTE_SCHED_TYPE_ORDERED: 638 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 639 return -1; 640 default: 641 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 642 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 643 break; 644 } 645 646 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 647 opts.fqd.dest.channel = ch_id; 648 opts.fqd.dest.wq = queue_conf->ev.priority; 649 650 if (dpaa_intf->cgr_rx) { 651 opts.we_mask |= QM_INITFQ_WE_CGID; 652 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 653 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 654 } 655 656 flags = QMAN_INITFQ_FLAG_SCHED; 657 658 ret = qman_init_fq(rxq, flags, &opts); 659 if (ret) { 660 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d ret:%d", 661 rxq->fqid, ret); 662 return ret; 663 } 664 665 /* copy configuration which needs to be filled during dequeue */ 666 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 667 dev->data->rx_queues[eth_rx_queue_id] = rxq; 668 669 return ret; 670 } 671 672 int __rte_experimental 673 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 674 int eth_rx_queue_id) 675 { 676 struct qm_mcc_initfq opts; 677 int ret; 678 u32 flags = 0; 679 struct dpaa_if *dpaa_intf = dev->data->dev_private; 680 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 681 682 dpaa_poll_queue_default_config(&opts); 683 684 if (dpaa_intf->cgr_rx) { 685 opts.we_mask |= QM_INITFQ_WE_CGID; 686 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 687 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 688 } 689 690 ret = qman_init_fq(rxq, flags, &opts); 691 if (ret) { 692 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 693 rxq->fqid, ret); 694 } 695 696 rxq->cb.dqrr_dpdk_cb = NULL; 697 dev->data->rx_queues[eth_rx_queue_id] = NULL; 698 699 return 0; 700 } 701 702 static 703 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 704 { 705 PMD_INIT_FUNC_TRACE(); 706 } 707 708 static 709 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 710 uint16_t nb_desc __rte_unused, 711 unsigned int socket_id __rte_unused, 712 const struct rte_eth_txconf *tx_conf __rte_unused) 713 { 714 struct dpaa_if *dpaa_intf = dev->data->dev_private; 715 716 PMD_INIT_FUNC_TRACE(); 717 718 DPAA_PMD_INFO("Tx queue setup for queue index: %d", queue_idx); 719 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; 720 return 0; 721 } 722 723 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 724 { 725 PMD_INIT_FUNC_TRACE(); 726 } 727 728 static uint32_t 729 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 730 { 731 struct dpaa_if *dpaa_intf = dev->data->dev_private; 732 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 733 u32 frm_cnt = 0; 734 735 PMD_INIT_FUNC_TRACE(); 736 737 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 738 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n", 739 rx_queue_id, frm_cnt); 740 } 741 return frm_cnt; 742 } 743 744 static int dpaa_link_down(struct rte_eth_dev *dev) 745 { 746 PMD_INIT_FUNC_TRACE(); 747 748 dpaa_eth_dev_stop(dev); 749 return 0; 750 } 751 752 static int dpaa_link_up(struct rte_eth_dev *dev) 753 { 754 PMD_INIT_FUNC_TRACE(); 755 756 dpaa_eth_dev_start(dev); 757 return 0; 758 } 759 760 static int 761 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 762 struct rte_eth_fc_conf *fc_conf) 763 { 764 struct dpaa_if *dpaa_intf = dev->data->dev_private; 765 struct rte_eth_fc_conf *net_fc; 766 767 PMD_INIT_FUNC_TRACE(); 768 769 if (!(dpaa_intf->fc_conf)) { 770 dpaa_intf->fc_conf = rte_zmalloc(NULL, 771 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 772 if (!dpaa_intf->fc_conf) { 773 DPAA_PMD_ERR("unable to save flow control info"); 774 return -ENOMEM; 775 } 776 } 777 net_fc = dpaa_intf->fc_conf; 778 779 if (fc_conf->high_water < fc_conf->low_water) { 780 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 781 return -EINVAL; 782 } 783 784 if (fc_conf->mode == RTE_FC_NONE) { 785 return 0; 786 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 787 fc_conf->mode == RTE_FC_FULL) { 788 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water, 789 fc_conf->low_water, 790 dpaa_intf->bp_info->bpid); 791 if (fc_conf->pause_time) 792 fman_if_set_fc_quanta(dpaa_intf->fif, 793 fc_conf->pause_time); 794 } 795 796 /* Save the information in dpaa device */ 797 net_fc->pause_time = fc_conf->pause_time; 798 net_fc->high_water = fc_conf->high_water; 799 net_fc->low_water = fc_conf->low_water; 800 net_fc->send_xon = fc_conf->send_xon; 801 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 802 net_fc->mode = fc_conf->mode; 803 net_fc->autoneg = fc_conf->autoneg; 804 805 return 0; 806 } 807 808 static int 809 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 810 struct rte_eth_fc_conf *fc_conf) 811 { 812 struct dpaa_if *dpaa_intf = dev->data->dev_private; 813 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 814 int ret; 815 816 PMD_INIT_FUNC_TRACE(); 817 818 if (net_fc) { 819 fc_conf->pause_time = net_fc->pause_time; 820 fc_conf->high_water = net_fc->high_water; 821 fc_conf->low_water = net_fc->low_water; 822 fc_conf->send_xon = net_fc->send_xon; 823 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 824 fc_conf->mode = net_fc->mode; 825 fc_conf->autoneg = net_fc->autoneg; 826 return 0; 827 } 828 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 829 if (ret) { 830 fc_conf->mode = RTE_FC_TX_PAUSE; 831 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 832 } else { 833 fc_conf->mode = RTE_FC_NONE; 834 } 835 836 return 0; 837 } 838 839 static int 840 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 841 struct ether_addr *addr, 842 uint32_t index, 843 __rte_unused uint32_t pool) 844 { 845 int ret; 846 struct dpaa_if *dpaa_intf = dev->data->dev_private; 847 848 PMD_INIT_FUNC_TRACE(); 849 850 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index); 851 852 if (ret) 853 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:" 854 " err = %d", ret); 855 return 0; 856 } 857 858 static void 859 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 860 uint32_t index) 861 { 862 struct dpaa_if *dpaa_intf = dev->data->dev_private; 863 864 PMD_INIT_FUNC_TRACE(); 865 866 fman_if_clear_mac_addr(dpaa_intf->fif, index); 867 } 868 869 static int 870 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 871 struct ether_addr *addr) 872 { 873 int ret; 874 struct dpaa_if *dpaa_intf = dev->data->dev_private; 875 876 PMD_INIT_FUNC_TRACE(); 877 878 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0); 879 if (ret) 880 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret); 881 882 return ret; 883 } 884 885 static struct eth_dev_ops dpaa_devops = { 886 .dev_configure = dpaa_eth_dev_configure, 887 .dev_start = dpaa_eth_dev_start, 888 .dev_stop = dpaa_eth_dev_stop, 889 .dev_close = dpaa_eth_dev_close, 890 .dev_infos_get = dpaa_eth_dev_info, 891 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 892 893 .rx_queue_setup = dpaa_eth_rx_queue_setup, 894 .tx_queue_setup = dpaa_eth_tx_queue_setup, 895 .rx_queue_release = dpaa_eth_rx_queue_release, 896 .tx_queue_release = dpaa_eth_tx_queue_release, 897 .rx_queue_count = dpaa_dev_rx_queue_count, 898 899 .flow_ctrl_get = dpaa_flow_ctrl_get, 900 .flow_ctrl_set = dpaa_flow_ctrl_set, 901 902 .link_update = dpaa_eth_link_update, 903 .stats_get = dpaa_eth_stats_get, 904 .xstats_get = dpaa_dev_xstats_get, 905 .xstats_get_by_id = dpaa_xstats_get_by_id, 906 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 907 .xstats_get_names = dpaa_xstats_get_names, 908 .xstats_reset = dpaa_eth_stats_reset, 909 .stats_reset = dpaa_eth_stats_reset, 910 .promiscuous_enable = dpaa_eth_promiscuous_enable, 911 .promiscuous_disable = dpaa_eth_promiscuous_disable, 912 .allmulticast_enable = dpaa_eth_multicast_enable, 913 .allmulticast_disable = dpaa_eth_multicast_disable, 914 .mtu_set = dpaa_mtu_set, 915 .dev_set_link_down = dpaa_link_down, 916 .dev_set_link_up = dpaa_link_up, 917 .mac_addr_add = dpaa_dev_add_mac_addr, 918 .mac_addr_remove = dpaa_dev_remove_mac_addr, 919 .mac_addr_set = dpaa_dev_set_mac_addr, 920 921 .fw_version_get = dpaa_fw_version_get, 922 }; 923 924 static bool 925 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 926 { 927 if (strcmp(dev->device->driver->name, 928 drv->driver.name)) 929 return false; 930 931 return true; 932 } 933 934 static bool 935 is_dpaa_supported(struct rte_eth_dev *dev) 936 { 937 return is_device_supported(dev, &rte_dpaa_pmd); 938 } 939 940 int __rte_experimental 941 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) 942 { 943 struct rte_eth_dev *dev; 944 struct dpaa_if *dpaa_intf; 945 946 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 947 948 dev = &rte_eth_devices[port]; 949 950 if (!is_dpaa_supported(dev)) 951 return -ENOTSUP; 952 953 dpaa_intf = dev->data->dev_private; 954 955 if (on) 956 fman_if_loopback_enable(dpaa_intf->fif); 957 else 958 fman_if_loopback_disable(dpaa_intf->fif); 959 960 return 0; 961 } 962 963 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) 964 { 965 struct rte_eth_fc_conf *fc_conf; 966 int ret; 967 968 PMD_INIT_FUNC_TRACE(); 969 970 if (!(dpaa_intf->fc_conf)) { 971 dpaa_intf->fc_conf = rte_zmalloc(NULL, 972 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 973 if (!dpaa_intf->fc_conf) { 974 DPAA_PMD_ERR("unable to save flow control info"); 975 return -ENOMEM; 976 } 977 } 978 fc_conf = dpaa_intf->fc_conf; 979 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 980 if (ret) { 981 fc_conf->mode = RTE_FC_TX_PAUSE; 982 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 983 } else { 984 fc_conf->mode = RTE_FC_NONE; 985 } 986 987 return 0; 988 } 989 990 /* Initialise an Rx FQ */ 991 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 992 uint32_t fqid) 993 { 994 struct qm_mcc_initfq opts = {0}; 995 int ret; 996 u32 flags = 0; 997 struct qm_mcc_initcgr cgr_opts = { 998 .we_mask = QM_CGR_WE_CS_THRES | 999 QM_CGR_WE_CSTD_EN | 1000 QM_CGR_WE_MODE, 1001 .cgr = { 1002 .cstd_en = QM_CGR_EN, 1003 .mode = QMAN_CGR_MODE_FRAME 1004 } 1005 }; 1006 1007 PMD_INIT_FUNC_TRACE(); 1008 1009 ret = qman_reserve_fqid(fqid); 1010 if (ret) { 1011 DPAA_PMD_ERR("reserve rx fqid %d failed with ret: %d", 1012 fqid, ret); 1013 return -EINVAL; 1014 } 1015 1016 DPAA_PMD_DEBUG("creating rx fq %p, fqid %d", fq, fqid); 1017 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1018 if (ret) { 1019 DPAA_PMD_ERR("create rx fqid %d failed with ret: %d", 1020 fqid, ret); 1021 return ret; 1022 } 1023 fq->is_static = false; 1024 1025 dpaa_poll_queue_default_config(&opts); 1026 1027 if (cgr_rx) { 1028 /* Enable tail drop with cgr on this queue */ 1029 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1030 cgr_rx->cb = NULL; 1031 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1032 &cgr_opts); 1033 if (ret) { 1034 DPAA_PMD_WARN( 1035 "rx taildrop init fail on rx fqid %d (ret=%d)", 1036 fqid, ret); 1037 goto without_cgr; 1038 } 1039 opts.we_mask |= QM_INITFQ_WE_CGID; 1040 opts.fqd.cgid = cgr_rx->cgrid; 1041 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1042 } 1043 without_cgr: 1044 ret = qman_init_fq(fq, flags, &opts); 1045 if (ret) 1046 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", fqid, ret); 1047 return ret; 1048 } 1049 1050 /* Initialise a Tx FQ */ 1051 static int dpaa_tx_queue_init(struct qman_fq *fq, 1052 struct fman_if *fman_intf) 1053 { 1054 struct qm_mcc_initfq opts = {0}; 1055 int ret; 1056 1057 PMD_INIT_FUNC_TRACE(); 1058 1059 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1060 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1061 if (ret) { 1062 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1063 return ret; 1064 } 1065 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1066 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1067 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1068 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1069 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1070 opts.fqd.context_b = 0; 1071 /* no tx-confirmation */ 1072 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1073 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1074 DPAA_PMD_DEBUG("init tx fq %p, fqid %d", fq, fq->fqid); 1075 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1076 if (ret) 1077 DPAA_PMD_ERR("init tx fqid %d failed %d", fq->fqid, ret); 1078 return ret; 1079 } 1080 1081 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1082 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1083 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1084 { 1085 struct qm_mcc_initfq opts = {0}; 1086 int ret; 1087 1088 PMD_INIT_FUNC_TRACE(); 1089 1090 ret = qman_reserve_fqid(fqid); 1091 if (ret) { 1092 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1093 fqid, ret); 1094 return -EINVAL; 1095 } 1096 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1097 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1098 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1099 if (ret) { 1100 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1101 fqid, ret); 1102 return ret; 1103 } 1104 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1105 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1106 ret = qman_init_fq(fq, 0, &opts); 1107 if (ret) 1108 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1109 fqid, ret); 1110 return ret; 1111 } 1112 #endif 1113 1114 /* Initialise a network interface */ 1115 static int 1116 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1117 { 1118 int num_cores, num_rx_fqs, fqid; 1119 int loop, ret = 0; 1120 int dev_id; 1121 struct rte_dpaa_device *dpaa_device; 1122 struct dpaa_if *dpaa_intf; 1123 struct fm_eth_port_cfg *cfg; 1124 struct fman_if *fman_intf; 1125 struct fman_if_bpool *bp, *tmp_bp; 1126 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1127 1128 PMD_INIT_FUNC_TRACE(); 1129 1130 /* For secondary processes, the primary has done all the work */ 1131 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1132 return 0; 1133 1134 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1135 dev_id = dpaa_device->id.dev_id; 1136 dpaa_intf = eth_dev->data->dev_private; 1137 cfg = &dpaa_netcfg->port_cfg[dev_id]; 1138 fman_intf = cfg->fman_if; 1139 1140 dpaa_intf->name = dpaa_device->name; 1141 1142 /* save fman_if & cfg in the interface struture */ 1143 dpaa_intf->fif = fman_intf; 1144 dpaa_intf->ifid = dev_id; 1145 dpaa_intf->cfg = cfg; 1146 1147 /* Initialize Rx FQ's */ 1148 if (getenv("DPAA_NUM_RX_QUEUES")) 1149 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES")); 1150 else 1151 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1152 1153 /* if push mode queues to be enabled. Currenly we are allowing only 1154 * one queue per thread. 1155 */ 1156 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 1157 dpaa_push_mode_max_queue = 1158 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 1159 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 1160 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 1161 } 1162 1163 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1164 * queues. 1165 */ 1166 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1167 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1168 return -EINVAL; 1169 } 1170 1171 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1172 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1173 if (!dpaa_intf->rx_queues) { 1174 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1175 return -ENOMEM; 1176 } 1177 1178 /* If congestion control is enabled globally*/ 1179 if (td_threshold) { 1180 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1181 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1182 if (!dpaa_intf->cgr_rx) { 1183 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1184 ret = -ENOMEM; 1185 goto free_rx; 1186 } 1187 1188 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1189 if (ret != num_rx_fqs) { 1190 DPAA_PMD_WARN("insufficient CGRIDs available"); 1191 ret = -EINVAL; 1192 goto free_rx; 1193 } 1194 } else { 1195 dpaa_intf->cgr_rx = NULL; 1196 } 1197 1198 for (loop = 0; loop < num_rx_fqs; loop++) { 1199 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid * 1200 DPAA_PCD_FQID_MULTIPLIER + loop; 1201 1202 if (dpaa_intf->cgr_rx) 1203 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1204 1205 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1206 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1207 fqid); 1208 if (ret) 1209 goto free_rx; 1210 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1211 } 1212 dpaa_intf->nb_rx_queues = num_rx_fqs; 1213 1214 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1215 num_cores = rte_lcore_count(); 1216 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1217 num_cores, MAX_CACHELINE); 1218 if (!dpaa_intf->tx_queues) { 1219 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1220 ret = -ENOMEM; 1221 goto free_rx; 1222 } 1223 1224 for (loop = 0; loop < num_cores; loop++) { 1225 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1226 fman_intf); 1227 if (ret) 1228 goto free_tx; 1229 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1230 } 1231 dpaa_intf->nb_tx_queues = num_cores; 1232 1233 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1234 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1235 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1236 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1237 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1238 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1239 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1240 #endif 1241 1242 DPAA_PMD_DEBUG("All frame queues created"); 1243 1244 /* Get the initial configuration for flow control */ 1245 dpaa_fc_set_default(dpaa_intf); 1246 1247 /* reset bpool list, initialize bpool dynamically */ 1248 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1249 list_del(&bp->node); 1250 free(bp); 1251 } 1252 1253 /* Populate ethdev structure */ 1254 eth_dev->dev_ops = &dpaa_devops; 1255 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1256 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1257 1258 /* Allocate memory for storing MAC addresses */ 1259 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1260 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1261 if (eth_dev->data->mac_addrs == NULL) { 1262 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1263 "store MAC addresses", 1264 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1265 ret = -ENOMEM; 1266 goto free_tx; 1267 } 1268 1269 /* copy the primary mac address */ 1270 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1271 1272 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1273 dpaa_device->name, 1274 fman_intf->mac_addr.addr_bytes[0], 1275 fman_intf->mac_addr.addr_bytes[1], 1276 fman_intf->mac_addr.addr_bytes[2], 1277 fman_intf->mac_addr.addr_bytes[3], 1278 fman_intf->mac_addr.addr_bytes[4], 1279 fman_intf->mac_addr.addr_bytes[5]); 1280 1281 /* Disable RX mode */ 1282 fman_if_discard_rx_errors(fman_intf); 1283 fman_if_disable_rx(fman_intf); 1284 /* Disable promiscuous mode */ 1285 fman_if_promiscuous_disable(fman_intf); 1286 /* Disable multicast */ 1287 fman_if_reset_mcast_filter_table(fman_intf); 1288 /* Reset interface statistics */ 1289 fman_if_stats_reset(fman_intf); 1290 1291 return 0; 1292 1293 free_tx: 1294 rte_free(dpaa_intf->tx_queues); 1295 dpaa_intf->tx_queues = NULL; 1296 dpaa_intf->nb_tx_queues = 0; 1297 1298 free_rx: 1299 rte_free(dpaa_intf->cgr_rx); 1300 rte_free(dpaa_intf->rx_queues); 1301 dpaa_intf->rx_queues = NULL; 1302 dpaa_intf->nb_rx_queues = 0; 1303 return ret; 1304 } 1305 1306 static int 1307 dpaa_dev_uninit(struct rte_eth_dev *dev) 1308 { 1309 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1310 int loop; 1311 1312 PMD_INIT_FUNC_TRACE(); 1313 1314 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1315 return -EPERM; 1316 1317 if (!dpaa_intf) { 1318 DPAA_PMD_WARN("Already closed or not started"); 1319 return -1; 1320 } 1321 1322 dpaa_eth_dev_close(dev); 1323 1324 /* release configuration memory */ 1325 if (dpaa_intf->fc_conf) 1326 rte_free(dpaa_intf->fc_conf); 1327 1328 /* Release RX congestion Groups */ 1329 if (dpaa_intf->cgr_rx) { 1330 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 1331 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 1332 1333 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 1334 dpaa_intf->nb_rx_queues); 1335 } 1336 1337 rte_free(dpaa_intf->cgr_rx); 1338 dpaa_intf->cgr_rx = NULL; 1339 1340 rte_free(dpaa_intf->rx_queues); 1341 dpaa_intf->rx_queues = NULL; 1342 1343 rte_free(dpaa_intf->tx_queues); 1344 dpaa_intf->tx_queues = NULL; 1345 1346 /* free memory for storing MAC addresses */ 1347 rte_free(dev->data->mac_addrs); 1348 dev->data->mac_addrs = NULL; 1349 1350 dev->dev_ops = NULL; 1351 dev->rx_pkt_burst = NULL; 1352 dev->tx_pkt_burst = NULL; 1353 1354 return 0; 1355 } 1356 1357 static int 1358 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 1359 struct rte_dpaa_device *dpaa_dev) 1360 { 1361 int diag; 1362 int ret; 1363 struct rte_eth_dev *eth_dev; 1364 1365 PMD_INIT_FUNC_TRACE(); 1366 1367 /* In case of secondary process, the device is already configured 1368 * and no further action is required, except portal initialization 1369 * and verifying secondary attachment to port name. 1370 */ 1371 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1372 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1373 if (!eth_dev) 1374 return -ENOMEM; 1375 rte_eth_dev_probing_finish(eth_dev); 1376 return 0; 1377 } 1378 1379 if (!is_global_init) { 1380 /* One time load of Qman/Bman drivers */ 1381 ret = qman_global_init(); 1382 if (ret) { 1383 DPAA_PMD_ERR("QMAN initialization failed: %d", 1384 ret); 1385 return ret; 1386 } 1387 ret = bman_global_init(); 1388 if (ret) { 1389 DPAA_PMD_ERR("BMAN initialization failed: %d", 1390 ret); 1391 return ret; 1392 } 1393 1394 is_global_init = 1; 1395 } 1396 1397 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 1398 ret = rte_dpaa_portal_init((void *)1); 1399 if (ret) { 1400 DPAA_PMD_ERR("Unable to initialize portal"); 1401 return ret; 1402 } 1403 } 1404 1405 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 1406 if (eth_dev == NULL) 1407 return -ENOMEM; 1408 1409 eth_dev->data->dev_private = rte_zmalloc( 1410 "ethdev private structure", 1411 sizeof(struct dpaa_if), 1412 RTE_CACHE_LINE_SIZE); 1413 if (!eth_dev->data->dev_private) { 1414 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 1415 rte_eth_dev_release_port(eth_dev); 1416 return -ENOMEM; 1417 } 1418 1419 eth_dev->device = &dpaa_dev->device; 1420 eth_dev->device->driver = &dpaa_drv->driver; 1421 dpaa_dev->eth_dev = eth_dev; 1422 1423 /* Invoke PMD device initialization function */ 1424 diag = dpaa_dev_init(eth_dev); 1425 if (diag == 0) { 1426 rte_eth_dev_probing_finish(eth_dev); 1427 return 0; 1428 } 1429 1430 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1431 rte_free(eth_dev->data->dev_private); 1432 1433 rte_eth_dev_release_port(eth_dev); 1434 return diag; 1435 } 1436 1437 static int 1438 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 1439 { 1440 struct rte_eth_dev *eth_dev; 1441 1442 PMD_INIT_FUNC_TRACE(); 1443 1444 eth_dev = dpaa_dev->eth_dev; 1445 dpaa_dev_uninit(eth_dev); 1446 1447 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1448 rte_free(eth_dev->data->dev_private); 1449 1450 rte_eth_dev_release_port(eth_dev); 1451 1452 return 0; 1453 } 1454 1455 static struct rte_dpaa_driver rte_dpaa_pmd = { 1456 .drv_type = FSL_DPAA_ETH, 1457 .probe = rte_dpaa_probe, 1458 .remove = rte_dpaa_remove, 1459 }; 1460 1461 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 1462