1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <rte_ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <rte_pmd_dpaa.h> 43 44 #include <fsl_usd.h> 45 #include <fsl_qman.h> 46 #include <fsl_bman.h> 47 #include <fsl_fman.h> 48 #include <process.h> 49 50 /* Supported Rx offloads */ 51 static uint64_t dev_rx_offloads_sup = 52 DEV_RX_OFFLOAD_JUMBO_FRAME | 53 DEV_RX_OFFLOAD_SCATTER; 54 55 /* Rx offloads which cannot be disabled */ 56 static uint64_t dev_rx_offloads_nodis = 57 DEV_RX_OFFLOAD_IPV4_CKSUM | 58 DEV_RX_OFFLOAD_UDP_CKSUM | 59 DEV_RX_OFFLOAD_TCP_CKSUM | 60 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 61 DEV_RX_OFFLOAD_RSS_HASH; 62 63 /* Supported Tx offloads */ 64 static uint64_t dev_tx_offloads_sup = 65 DEV_TX_OFFLOAD_MT_LOCKFREE | 66 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 67 68 /* Tx offloads which cannot be disabled */ 69 static uint64_t dev_tx_offloads_nodis = 70 DEV_TX_OFFLOAD_IPV4_CKSUM | 71 DEV_TX_OFFLOAD_UDP_CKSUM | 72 DEV_TX_OFFLOAD_TCP_CKSUM | 73 DEV_TX_OFFLOAD_SCTP_CKSUM | 74 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 75 DEV_TX_OFFLOAD_MULTI_SEGS; 76 77 /* Keep track of whether QMAN and BMAN have been globally initialized */ 78 static int is_global_init; 79 static int default_q; /* use default queue - FMC is not executed*/ 80 /* At present we only allow up to 4 push mode queues as default - as each of 81 * this queue need dedicated portal and we are short of portals. 82 */ 83 #define DPAA_MAX_PUSH_MODE_QUEUE 8 84 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 85 86 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 87 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 88 89 90 /* Per RX FQ Taildrop in frame count */ 91 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 92 93 /* Per TX FQ Taildrop in frame count, disabled by default */ 94 static unsigned int td_tx_threshold; 95 96 struct rte_dpaa_xstats_name_off { 97 char name[RTE_ETH_XSTATS_NAME_SIZE]; 98 uint32_t offset; 99 }; 100 101 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 102 {"rx_align_err", 103 offsetof(struct dpaa_if_stats, raln)}, 104 {"rx_valid_pause", 105 offsetof(struct dpaa_if_stats, rxpf)}, 106 {"rx_fcs_err", 107 offsetof(struct dpaa_if_stats, rfcs)}, 108 {"rx_vlan_frame", 109 offsetof(struct dpaa_if_stats, rvlan)}, 110 {"rx_frame_err", 111 offsetof(struct dpaa_if_stats, rerr)}, 112 {"rx_drop_err", 113 offsetof(struct dpaa_if_stats, rdrp)}, 114 {"rx_undersized", 115 offsetof(struct dpaa_if_stats, rund)}, 116 {"rx_oversize_err", 117 offsetof(struct dpaa_if_stats, rovr)}, 118 {"rx_fragment_pkt", 119 offsetof(struct dpaa_if_stats, rfrg)}, 120 {"tx_valid_pause", 121 offsetof(struct dpaa_if_stats, txpf)}, 122 {"tx_fcs_err", 123 offsetof(struct dpaa_if_stats, terr)}, 124 {"tx_vlan_frame", 125 offsetof(struct dpaa_if_stats, tvlan)}, 126 {"rx_undersized", 127 offsetof(struct dpaa_if_stats, tund)}, 128 }; 129 130 static struct rte_dpaa_driver rte_dpaa_pmd; 131 132 static int 133 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 134 135 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 136 int wait_to_complete __rte_unused); 137 138 static void dpaa_interrupt_handler(void *param); 139 140 static inline void 141 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 142 { 143 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 144 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 145 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 146 QM_FQCTRL_PREFERINCACHE; 147 opts->fqd.context_a.stashing.exclusive = 0; 148 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 149 opts->fqd.context_a.stashing.annotation_cl = 150 DPAA_IF_RX_ANNOTATION_STASH; 151 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 152 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 153 } 154 155 static int 156 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 157 { 158 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 159 + VLAN_TAG_SIZE; 160 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 161 162 PMD_INIT_FUNC_TRACE(); 163 164 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 165 return -EINVAL; 166 /* 167 * Refuse mtu that requires the support of scattered packets 168 * when this feature has not been enabled before. 169 */ 170 if (dev->data->min_rx_buf_size && 171 !dev->data->scattered_rx && frame_size > buffsz) { 172 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 173 return -EINVAL; 174 } 175 176 /* check <seg size> * <max_seg> >= max_frame */ 177 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 178 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 179 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 180 buffsz * DPAA_SGT_MAX_ENTRIES); 181 return -EINVAL; 182 } 183 184 if (frame_size > RTE_ETHER_MAX_LEN) 185 dev->data->dev_conf.rxmode.offloads |= 186 DEV_RX_OFFLOAD_JUMBO_FRAME; 187 else 188 dev->data->dev_conf.rxmode.offloads &= 189 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 190 191 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 192 193 fman_if_set_maxfrm(dev->process_private, frame_size); 194 195 return 0; 196 } 197 198 static int 199 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 200 { 201 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 202 uint64_t rx_offloads = eth_conf->rxmode.offloads; 203 uint64_t tx_offloads = eth_conf->txmode.offloads; 204 struct rte_device *rdev = dev->device; 205 struct rte_dpaa_device *dpaa_dev; 206 struct fman_if *fif = dev->process_private; 207 struct __fman_if *__fif; 208 struct rte_intr_handle *intr_handle; 209 int ret; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 214 intr_handle = &dpaa_dev->intr_handle; 215 __fif = container_of(fif, struct __fman_if, __if); 216 217 /* Rx offloads which are enabled by default */ 218 if (dev_rx_offloads_nodis & ~rx_offloads) { 219 DPAA_PMD_INFO( 220 "Some of rx offloads enabled by default - requested 0x%" PRIx64 221 " fixed are 0x%" PRIx64, 222 rx_offloads, dev_rx_offloads_nodis); 223 } 224 225 /* Tx offloads which are enabled by default */ 226 if (dev_tx_offloads_nodis & ~tx_offloads) { 227 DPAA_PMD_INFO( 228 "Some of tx offloads enabled by default - requested 0x%" PRIx64 229 " fixed are 0x%" PRIx64, 230 tx_offloads, dev_tx_offloads_nodis); 231 } 232 233 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 234 uint32_t max_len; 235 236 DPAA_PMD_DEBUG("enabling jumbo"); 237 238 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 239 DPAA_MAX_RX_PKT_LEN) 240 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 241 else { 242 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 243 "supported is %d", 244 dev->data->dev_conf.rxmode.max_rx_pkt_len, 245 DPAA_MAX_RX_PKT_LEN); 246 max_len = DPAA_MAX_RX_PKT_LEN; 247 } 248 249 fman_if_set_maxfrm(dev->process_private, max_len); 250 dev->data->mtu = max_len 251 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE; 252 } 253 254 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 255 DPAA_PMD_DEBUG("enabling scatter mode"); 256 fman_if_set_sg(dev->process_private, 1); 257 dev->data->scattered_rx = 1; 258 } 259 260 /* if the interrupts were configured on this devices*/ 261 if (intr_handle && intr_handle->fd) { 262 if (dev->data->dev_conf.intr_conf.lsc != 0) 263 rte_intr_callback_register(intr_handle, 264 dpaa_interrupt_handler, 265 (void *)dev); 266 267 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd); 268 if (ret) { 269 if (dev->data->dev_conf.intr_conf.lsc != 0) { 270 rte_intr_callback_unregister(intr_handle, 271 dpaa_interrupt_handler, 272 (void *)dev); 273 if (ret == EINVAL) 274 printf("Failed to enable interrupt: Not Supported\n"); 275 else 276 printf("Failed to enable interrupt\n"); 277 } 278 dev->data->dev_conf.intr_conf.lsc = 0; 279 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 280 } 281 } 282 return 0; 283 } 284 285 static const uint32_t * 286 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 287 { 288 static const uint32_t ptypes[] = { 289 RTE_PTYPE_L2_ETHER, 290 RTE_PTYPE_L2_ETHER_VLAN, 291 RTE_PTYPE_L2_ETHER_ARP, 292 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 293 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 294 RTE_PTYPE_L4_ICMP, 295 RTE_PTYPE_L4_TCP, 296 RTE_PTYPE_L4_UDP, 297 RTE_PTYPE_L4_FRAG, 298 RTE_PTYPE_L4_TCP, 299 RTE_PTYPE_L4_UDP, 300 RTE_PTYPE_L4_SCTP 301 }; 302 303 PMD_INIT_FUNC_TRACE(); 304 305 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 306 return ptypes; 307 return NULL; 308 } 309 310 static void dpaa_interrupt_handler(void *param) 311 { 312 struct rte_eth_dev *dev = param; 313 struct rte_device *rdev = dev->device; 314 struct rte_dpaa_device *dpaa_dev; 315 struct rte_intr_handle *intr_handle; 316 uint64_t buf; 317 int bytes_read; 318 319 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 320 intr_handle = &dpaa_dev->intr_handle; 321 322 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t)); 323 if (bytes_read < 0) 324 DPAA_PMD_ERR("Error reading eventfd\n"); 325 dpaa_eth_link_update(dev, 0); 326 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 327 } 328 329 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 330 { 331 struct dpaa_if *dpaa_intf = dev->data->dev_private; 332 333 PMD_INIT_FUNC_TRACE(); 334 335 /* Change tx callback to the real one */ 336 if (dpaa_intf->cgr_tx) 337 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 338 else 339 dev->tx_pkt_burst = dpaa_eth_queue_tx; 340 341 fman_if_enable_rx(dev->process_private); 342 343 return 0; 344 } 345 346 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 347 { 348 struct fman_if *fif = dev->process_private; 349 350 PMD_INIT_FUNC_TRACE(); 351 352 fman_if_disable_rx(fif); 353 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 354 } 355 356 static void dpaa_eth_dev_close(struct rte_eth_dev *dev) 357 { 358 struct fman_if *fif = dev->process_private; 359 struct __fman_if *__fif; 360 struct rte_device *rdev = dev->device; 361 struct rte_dpaa_device *dpaa_dev; 362 struct rte_intr_handle *intr_handle; 363 364 PMD_INIT_FUNC_TRACE(); 365 366 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 367 intr_handle = &dpaa_dev->intr_handle; 368 __fif = container_of(fif, struct __fman_if, __if); 369 370 dpaa_eth_dev_stop(dev); 371 372 if (intr_handle && intr_handle->fd && 373 dev->data->dev_conf.intr_conf.lsc != 0) { 374 dpaa_intr_disable(__fif->node_name); 375 rte_intr_callback_unregister(intr_handle, 376 dpaa_interrupt_handler, 377 (void *)dev); 378 } 379 } 380 381 static int 382 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 383 char *fw_version, 384 size_t fw_size) 385 { 386 int ret; 387 FILE *svr_file = NULL; 388 unsigned int svr_ver = 0; 389 390 PMD_INIT_FUNC_TRACE(); 391 392 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 393 if (!svr_file) { 394 DPAA_PMD_ERR("Unable to open SoC device"); 395 return -ENOTSUP; /* Not supported on this infra */ 396 } 397 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 398 dpaa_svr_family = svr_ver & SVR_MASK; 399 else 400 DPAA_PMD_ERR("Unable to read SoC device"); 401 402 fclose(svr_file); 403 404 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 405 svr_ver, fman_ip_rev); 406 ret += 1; /* add the size of '\0' */ 407 408 if (fw_size < (uint32_t)ret) 409 return ret; 410 else 411 return 0; 412 } 413 414 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 415 struct rte_eth_dev_info *dev_info) 416 { 417 struct dpaa_if *dpaa_intf = dev->data->dev_private; 418 struct fman_if *fif = dev->process_private; 419 420 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 421 422 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 423 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 424 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 425 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 426 dev_info->max_hash_mac_addrs = 0; 427 dev_info->max_vfs = 0; 428 dev_info->max_vmdq_pools = ETH_16_POOLS; 429 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 430 431 if (fif->mac_type == fman_mac_1g) { 432 dev_info->speed_capa = ETH_LINK_SPEED_1G; 433 } else if (fif->mac_type == fman_mac_2_5g) { 434 dev_info->speed_capa = ETH_LINK_SPEED_1G 435 | ETH_LINK_SPEED_2_5G; 436 } else if (fif->mac_type == fman_mac_10g) { 437 dev_info->speed_capa = ETH_LINK_SPEED_1G 438 | ETH_LINK_SPEED_2_5G 439 | ETH_LINK_SPEED_10G; 440 } else { 441 DPAA_PMD_ERR("invalid link_speed: %s, %d", 442 dpaa_intf->name, fif->mac_type); 443 return -EINVAL; 444 } 445 446 dev_info->rx_offload_capa = dev_rx_offloads_sup | 447 dev_rx_offloads_nodis; 448 dev_info->tx_offload_capa = dev_tx_offloads_sup | 449 dev_tx_offloads_nodis; 450 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 451 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 452 dev_info->default_rxportconf.nb_queues = 1; 453 dev_info->default_txportconf.nb_queues = 1; 454 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 455 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 456 457 return 0; 458 } 459 460 static int 461 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 462 __rte_unused uint16_t queue_id, 463 struct rte_eth_burst_mode *mode) 464 { 465 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 466 int ret = -EINVAL; 467 unsigned int i; 468 const struct burst_info { 469 uint64_t flags; 470 const char *output; 471 } rx_offload_map[] = { 472 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 473 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}, 474 {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 475 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 476 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 477 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 478 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"} 479 }; 480 481 /* Update Rx offload info */ 482 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 483 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 484 snprintf(mode->info, sizeof(mode->info), "%s", 485 rx_offload_map[i].output); 486 ret = 0; 487 break; 488 } 489 } 490 return ret; 491 } 492 493 static int 494 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 495 __rte_unused uint16_t queue_id, 496 struct rte_eth_burst_mode *mode) 497 { 498 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 499 int ret = -EINVAL; 500 unsigned int i; 501 const struct burst_info { 502 uint64_t flags; 503 const char *output; 504 } tx_offload_map[] = { 505 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 506 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 507 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 508 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 509 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 510 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 511 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 512 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 513 }; 514 515 /* Update Tx offload info */ 516 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 517 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 518 snprintf(mode->info, sizeof(mode->info), "%s", 519 tx_offload_map[i].output); 520 ret = 0; 521 break; 522 } 523 } 524 return ret; 525 } 526 527 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 528 int wait_to_complete __rte_unused) 529 { 530 struct dpaa_if *dpaa_intf = dev->data->dev_private; 531 struct rte_eth_link *link = &dev->data->dev_link; 532 struct fman_if *fif = dev->process_private; 533 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 534 int ret; 535 536 PMD_INIT_FUNC_TRACE(); 537 538 if (fif->mac_type == fman_mac_1g) 539 link->link_speed = ETH_SPEED_NUM_1G; 540 else if (fif->mac_type == fman_mac_2_5g) 541 link->link_speed = ETH_SPEED_NUM_2_5G; 542 else if (fif->mac_type == fman_mac_10g) 543 link->link_speed = ETH_SPEED_NUM_10G; 544 else 545 DPAA_PMD_ERR("invalid link_speed: %s, %d", 546 dpaa_intf->name, fif->mac_type); 547 548 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 549 ret = dpaa_get_link_status(__fif->node_name); 550 if (ret < 0) 551 return ret; 552 link->link_status = ret; 553 } else { 554 link->link_status = dpaa_intf->valid; 555 } 556 557 link->link_duplex = ETH_LINK_FULL_DUPLEX; 558 link->link_autoneg = ETH_LINK_AUTONEG; 559 560 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 561 link->link_status ? "Up" : "Down"); 562 return 0; 563 } 564 565 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 566 struct rte_eth_stats *stats) 567 { 568 PMD_INIT_FUNC_TRACE(); 569 570 fman_if_stats_get(dev->process_private, stats); 571 return 0; 572 } 573 574 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 575 { 576 PMD_INIT_FUNC_TRACE(); 577 578 fman_if_stats_reset(dev->process_private); 579 580 return 0; 581 } 582 583 static int 584 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 585 unsigned int n) 586 { 587 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 588 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 589 590 if (n < num) 591 return num; 592 593 if (xstats == NULL) 594 return 0; 595 596 fman_if_stats_get_all(dev->process_private, values, 597 sizeof(struct dpaa_if_stats) / 8); 598 599 for (i = 0; i < num; i++) { 600 xstats[i].id = i; 601 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 602 } 603 return i; 604 } 605 606 static int 607 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 608 struct rte_eth_xstat_name *xstats_names, 609 unsigned int limit) 610 { 611 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 612 613 if (limit < stat_cnt) 614 return stat_cnt; 615 616 if (xstats_names != NULL) 617 for (i = 0; i < stat_cnt; i++) 618 strlcpy(xstats_names[i].name, 619 dpaa_xstats_strings[i].name, 620 sizeof(xstats_names[i].name)); 621 622 return stat_cnt; 623 } 624 625 static int 626 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 627 uint64_t *values, unsigned int n) 628 { 629 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 630 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 631 632 if (!ids) { 633 if (n < stat_cnt) 634 return stat_cnt; 635 636 if (!values) 637 return 0; 638 639 fman_if_stats_get_all(dev->process_private, values_copy, 640 sizeof(struct dpaa_if_stats) / 8); 641 642 for (i = 0; i < stat_cnt; i++) 643 values[i] = 644 values_copy[dpaa_xstats_strings[i].offset / 8]; 645 646 return stat_cnt; 647 } 648 649 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 650 651 for (i = 0; i < n; i++) { 652 if (ids[i] >= stat_cnt) { 653 DPAA_PMD_ERR("id value isn't valid"); 654 return -1; 655 } 656 values[i] = values_copy[ids[i]]; 657 } 658 return n; 659 } 660 661 static int 662 dpaa_xstats_get_names_by_id( 663 struct rte_eth_dev *dev, 664 struct rte_eth_xstat_name *xstats_names, 665 const uint64_t *ids, 666 unsigned int limit) 667 { 668 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 669 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 670 671 if (!ids) 672 return dpaa_xstats_get_names(dev, xstats_names, limit); 673 674 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 675 676 for (i = 0; i < limit; i++) { 677 if (ids[i] >= stat_cnt) { 678 DPAA_PMD_ERR("id value isn't valid"); 679 return -1; 680 } 681 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 682 } 683 return limit; 684 } 685 686 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 687 { 688 PMD_INIT_FUNC_TRACE(); 689 690 fman_if_promiscuous_enable(dev->process_private); 691 692 return 0; 693 } 694 695 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 696 { 697 PMD_INIT_FUNC_TRACE(); 698 699 fman_if_promiscuous_disable(dev->process_private); 700 701 return 0; 702 } 703 704 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 705 { 706 PMD_INIT_FUNC_TRACE(); 707 708 fman_if_set_mcast_filter_table(dev->process_private); 709 710 return 0; 711 } 712 713 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 714 { 715 PMD_INIT_FUNC_TRACE(); 716 717 fman_if_reset_mcast_filter_table(dev->process_private); 718 719 return 0; 720 } 721 722 static 723 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 724 uint16_t nb_desc, 725 unsigned int socket_id __rte_unused, 726 const struct rte_eth_rxconf *rx_conf, 727 struct rte_mempool *mp) 728 { 729 struct dpaa_if *dpaa_intf = dev->data->dev_private; 730 struct fman_if *fif = dev->process_private; 731 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 732 struct qm_mcc_initfq opts = {0}; 733 u32 flags = 0; 734 int ret; 735 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 736 737 PMD_INIT_FUNC_TRACE(); 738 739 if (queue_idx >= dev->data->nb_rx_queues) { 740 rte_errno = EOVERFLOW; 741 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 742 (void *)dev, queue_idx, dev->data->nb_rx_queues); 743 return -rte_errno; 744 } 745 746 /* Rx deferred start is not supported */ 747 if (rx_conf->rx_deferred_start) { 748 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 749 return -EINVAL; 750 } 751 rxq->nb_desc = UINT16_MAX; 752 rxq->offloads = rx_conf->offloads; 753 754 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 755 queue_idx, rxq->fqid); 756 757 /* Max packet can fit in single buffer */ 758 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { 759 ; 760 } else if (dev->data->dev_conf.rxmode.offloads & 761 DEV_RX_OFFLOAD_SCATTER) { 762 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > 763 buffsz * DPAA_SGT_MAX_ENTRIES) { 764 DPAA_PMD_ERR("max RxPkt size %d too big to fit " 765 "MaxSGlist %d", 766 dev->data->dev_conf.rxmode.max_rx_pkt_len, 767 buffsz * DPAA_SGT_MAX_ENTRIES); 768 rte_errno = EOVERFLOW; 769 return -rte_errno; 770 } 771 } else { 772 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 773 " larger than a single mbuf (%u) and scattered" 774 " mode has not been requested", 775 dev->data->dev_conf.rxmode.max_rx_pkt_len, 776 buffsz - RTE_PKTMBUF_HEADROOM); 777 } 778 779 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) { 780 struct fman_if_ic_params icp; 781 uint32_t fd_offset; 782 uint32_t bp_size; 783 784 if (!mp->pool_data) { 785 DPAA_PMD_ERR("Not an offloaded buffer pool!"); 786 return -1; 787 } 788 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 789 790 memset(&icp, 0, sizeof(icp)); 791 /* set ICEOF for to the default value , which is 0*/ 792 icp.iciof = DEFAULT_ICIOF; 793 icp.iceof = DEFAULT_RX_ICEOF; 794 icp.icsz = DEFAULT_ICSZ; 795 fman_if_set_ic_params(fif, &icp); 796 797 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 798 fman_if_set_fdoff(fif, fd_offset); 799 800 /* Buffer pool size should be equal to Dataroom Size*/ 801 bp_size = rte_pktmbuf_data_room_size(mp); 802 fman_if_set_bp(fif, mp->size, 803 dpaa_intf->bp_info->bpid, bp_size); 804 dpaa_intf->valid = 1; 805 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d", 806 dpaa_intf->name, fd_offset, 807 fman_if_get_fdoff(fif)); 808 } 809 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 810 fman_if_get_sg_enable(fif), 811 dev->data->dev_conf.rxmode.max_rx_pkt_len); 812 /* checking if push mode only, no error check for now */ 813 if (!rxq->is_static && 814 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 815 struct qman_portal *qp; 816 int q_fd; 817 818 dpaa_push_queue_idx++; 819 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 820 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 821 QM_FQCTRL_CTXASTASHING | 822 QM_FQCTRL_PREFERINCACHE; 823 opts.fqd.context_a.stashing.exclusive = 0; 824 /* In muticore scenario stashing becomes a bottleneck on LS1046. 825 * So do not enable stashing in this case 826 */ 827 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 828 opts.fqd.context_a.stashing.annotation_cl = 829 DPAA_IF_RX_ANNOTATION_STASH; 830 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 831 opts.fqd.context_a.stashing.context_cl = 832 DPAA_IF_RX_CONTEXT_STASH; 833 834 /*Create a channel and associate given queue with the channel*/ 835 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 836 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 837 opts.fqd.dest.channel = rxq->ch_id; 838 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 839 flags = QMAN_INITFQ_FLAG_SCHED; 840 841 /* Configure tail drop */ 842 if (dpaa_intf->cgr_rx) { 843 opts.we_mask |= QM_INITFQ_WE_CGID; 844 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 845 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 846 } 847 ret = qman_init_fq(rxq, flags, &opts); 848 if (ret) { 849 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 850 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 851 return ret; 852 } 853 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 854 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 855 } else { 856 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 857 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 858 } 859 860 rxq->is_static = true; 861 862 /* Allocate qman specific portals */ 863 qp = fsl_qman_fq_portal_create(&q_fd); 864 if (!qp) { 865 DPAA_PMD_ERR("Unable to alloc fq portal"); 866 return -1; 867 } 868 rxq->qp = qp; 869 870 /* Set up the device interrupt handler */ 871 if (!dev->intr_handle) { 872 struct rte_dpaa_device *dpaa_dev; 873 struct rte_device *rdev = dev->device; 874 875 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 876 device); 877 dev->intr_handle = &dpaa_dev->intr_handle; 878 dev->intr_handle->intr_vec = rte_zmalloc(NULL, 879 dpaa_push_mode_max_queue, 0); 880 if (!dev->intr_handle->intr_vec) { 881 DPAA_PMD_ERR("intr_vec alloc failed"); 882 return -ENOMEM; 883 } 884 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue; 885 dev->intr_handle->max_intr = dpaa_push_mode_max_queue; 886 } 887 888 dev->intr_handle->type = RTE_INTR_HANDLE_EXT; 889 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1; 890 dev->intr_handle->efds[queue_idx] = q_fd; 891 rxq->q_fd = q_fd; 892 } 893 rxq->bp_array = rte_dpaa_bpid_info; 894 dev->data->rx_queues[queue_idx] = rxq; 895 896 /* configure the CGR size as per the desc size */ 897 if (dpaa_intf->cgr_rx) { 898 struct qm_mcc_initcgr cgr_opts = {0}; 899 900 rxq->nb_desc = nb_desc; 901 /* Enable tail drop with cgr on this queue */ 902 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 903 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 904 if (ret) { 905 DPAA_PMD_WARN( 906 "rx taildrop modify fail on fqid %d (ret=%d)", 907 rxq->fqid, ret); 908 } 909 } 910 911 return 0; 912 } 913 914 int 915 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 916 int eth_rx_queue_id, 917 u16 ch_id, 918 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 919 { 920 int ret; 921 u32 flags = 0; 922 struct dpaa_if *dpaa_intf = dev->data->dev_private; 923 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 924 struct qm_mcc_initfq opts = {0}; 925 926 if (dpaa_push_mode_max_queue) 927 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 928 "PUSH mode already enabled for first %d queues.\n" 929 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 930 dpaa_push_mode_max_queue); 931 932 dpaa_poll_queue_default_config(&opts); 933 934 switch (queue_conf->ev.sched_type) { 935 case RTE_SCHED_TYPE_ATOMIC: 936 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 937 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 938 * configuration with HOLD_ACTIVE setting 939 */ 940 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 941 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 942 break; 943 case RTE_SCHED_TYPE_ORDERED: 944 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 945 return -1; 946 default: 947 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 948 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 949 break; 950 } 951 952 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 953 opts.fqd.dest.channel = ch_id; 954 opts.fqd.dest.wq = queue_conf->ev.priority; 955 956 if (dpaa_intf->cgr_rx) { 957 opts.we_mask |= QM_INITFQ_WE_CGID; 958 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 959 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 960 } 961 962 flags = QMAN_INITFQ_FLAG_SCHED; 963 964 ret = qman_init_fq(rxq, flags, &opts); 965 if (ret) { 966 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 967 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 968 return ret; 969 } 970 971 /* copy configuration which needs to be filled during dequeue */ 972 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 973 dev->data->rx_queues[eth_rx_queue_id] = rxq; 974 975 return ret; 976 } 977 978 int 979 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 980 int eth_rx_queue_id) 981 { 982 struct qm_mcc_initfq opts; 983 int ret; 984 u32 flags = 0; 985 struct dpaa_if *dpaa_intf = dev->data->dev_private; 986 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 987 988 dpaa_poll_queue_default_config(&opts); 989 990 if (dpaa_intf->cgr_rx) { 991 opts.we_mask |= QM_INITFQ_WE_CGID; 992 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 993 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 994 } 995 996 ret = qman_init_fq(rxq, flags, &opts); 997 if (ret) { 998 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 999 rxq->fqid, ret); 1000 } 1001 1002 rxq->cb.dqrr_dpdk_cb = NULL; 1003 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1004 1005 return 0; 1006 } 1007 1008 static 1009 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 1010 { 1011 PMD_INIT_FUNC_TRACE(); 1012 } 1013 1014 static 1015 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1016 uint16_t nb_desc __rte_unused, 1017 unsigned int socket_id __rte_unused, 1018 const struct rte_eth_txconf *tx_conf) 1019 { 1020 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1021 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1022 1023 PMD_INIT_FUNC_TRACE(); 1024 1025 /* Tx deferred start is not supported */ 1026 if (tx_conf->tx_deferred_start) { 1027 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1028 return -EINVAL; 1029 } 1030 txq->nb_desc = UINT16_MAX; 1031 txq->offloads = tx_conf->offloads; 1032 1033 if (queue_idx >= dev->data->nb_tx_queues) { 1034 rte_errno = EOVERFLOW; 1035 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1036 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1037 return -rte_errno; 1038 } 1039 1040 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1041 queue_idx, txq->fqid); 1042 dev->data->tx_queues[queue_idx] = txq; 1043 1044 return 0; 1045 } 1046 1047 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 1048 { 1049 PMD_INIT_FUNC_TRACE(); 1050 } 1051 1052 static uint32_t 1053 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1054 { 1055 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1056 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 1057 u32 frm_cnt = 0; 1058 1059 PMD_INIT_FUNC_TRACE(); 1060 1061 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1062 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u", 1063 rx_queue_id, frm_cnt); 1064 } 1065 return frm_cnt; 1066 } 1067 1068 static int dpaa_link_down(struct rte_eth_dev *dev) 1069 { 1070 struct fman_if *fif = dev->process_private; 1071 struct __fman_if *__fif; 1072 1073 PMD_INIT_FUNC_TRACE(); 1074 1075 __fif = container_of(fif, struct __fman_if, __if); 1076 1077 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1078 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN); 1079 else 1080 dpaa_eth_dev_stop(dev); 1081 return 0; 1082 } 1083 1084 static int dpaa_link_up(struct rte_eth_dev *dev) 1085 { 1086 struct fman_if *fif = dev->process_private; 1087 struct __fman_if *__fif; 1088 1089 PMD_INIT_FUNC_TRACE(); 1090 1091 __fif = container_of(fif, struct __fman_if, __if); 1092 1093 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1094 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP); 1095 else 1096 dpaa_eth_dev_start(dev); 1097 return 0; 1098 } 1099 1100 static int 1101 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1102 struct rte_eth_fc_conf *fc_conf) 1103 { 1104 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1105 struct rte_eth_fc_conf *net_fc; 1106 1107 PMD_INIT_FUNC_TRACE(); 1108 1109 if (!(dpaa_intf->fc_conf)) { 1110 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1111 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1112 if (!dpaa_intf->fc_conf) { 1113 DPAA_PMD_ERR("unable to save flow control info"); 1114 return -ENOMEM; 1115 } 1116 } 1117 net_fc = dpaa_intf->fc_conf; 1118 1119 if (fc_conf->high_water < fc_conf->low_water) { 1120 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1121 return -EINVAL; 1122 } 1123 1124 if (fc_conf->mode == RTE_FC_NONE) { 1125 return 0; 1126 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 1127 fc_conf->mode == RTE_FC_FULL) { 1128 fman_if_set_fc_threshold(dev->process_private, 1129 fc_conf->high_water, 1130 fc_conf->low_water, 1131 dpaa_intf->bp_info->bpid); 1132 if (fc_conf->pause_time) 1133 fman_if_set_fc_quanta(dev->process_private, 1134 fc_conf->pause_time); 1135 } 1136 1137 /* Save the information in dpaa device */ 1138 net_fc->pause_time = fc_conf->pause_time; 1139 net_fc->high_water = fc_conf->high_water; 1140 net_fc->low_water = fc_conf->low_water; 1141 net_fc->send_xon = fc_conf->send_xon; 1142 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1143 net_fc->mode = fc_conf->mode; 1144 net_fc->autoneg = fc_conf->autoneg; 1145 1146 return 0; 1147 } 1148 1149 static int 1150 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1151 struct rte_eth_fc_conf *fc_conf) 1152 { 1153 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1154 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1155 int ret; 1156 1157 PMD_INIT_FUNC_TRACE(); 1158 1159 if (net_fc) { 1160 fc_conf->pause_time = net_fc->pause_time; 1161 fc_conf->high_water = net_fc->high_water; 1162 fc_conf->low_water = net_fc->low_water; 1163 fc_conf->send_xon = net_fc->send_xon; 1164 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1165 fc_conf->mode = net_fc->mode; 1166 fc_conf->autoneg = net_fc->autoneg; 1167 return 0; 1168 } 1169 ret = fman_if_get_fc_threshold(dev->process_private); 1170 if (ret) { 1171 fc_conf->mode = RTE_FC_TX_PAUSE; 1172 fc_conf->pause_time = 1173 fman_if_get_fc_quanta(dev->process_private); 1174 } else { 1175 fc_conf->mode = RTE_FC_NONE; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int 1182 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1183 struct rte_ether_addr *addr, 1184 uint32_t index, 1185 __rte_unused uint32_t pool) 1186 { 1187 int ret; 1188 1189 PMD_INIT_FUNC_TRACE(); 1190 1191 ret = fman_if_add_mac_addr(dev->process_private, 1192 addr->addr_bytes, index); 1193 1194 if (ret) 1195 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1196 return 0; 1197 } 1198 1199 static void 1200 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1201 uint32_t index) 1202 { 1203 PMD_INIT_FUNC_TRACE(); 1204 1205 fman_if_clear_mac_addr(dev->process_private, index); 1206 } 1207 1208 static int 1209 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1210 struct rte_ether_addr *addr) 1211 { 1212 int ret; 1213 1214 PMD_INIT_FUNC_TRACE(); 1215 1216 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1217 if (ret) 1218 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1219 1220 return ret; 1221 } 1222 1223 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1224 uint16_t queue_id) 1225 { 1226 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1227 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1228 1229 if (!rxq->is_static) 1230 return -EINVAL; 1231 1232 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1233 } 1234 1235 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1236 uint16_t queue_id) 1237 { 1238 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1239 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1240 uint32_t temp; 1241 ssize_t temp1; 1242 1243 if (!rxq->is_static) 1244 return -EINVAL; 1245 1246 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1247 1248 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1249 if (temp1 != sizeof(temp)) 1250 DPAA_PMD_ERR("irq read error"); 1251 1252 qman_fq_portal_thread_irq(rxq->qp); 1253 1254 return 0; 1255 } 1256 1257 static void 1258 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1259 struct rte_eth_rxq_info *qinfo) 1260 { 1261 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1262 struct qman_fq *rxq; 1263 1264 rxq = dev->data->rx_queues[queue_id]; 1265 1266 qinfo->mp = dpaa_intf->bp_info->mp; 1267 qinfo->scattered_rx = dev->data->scattered_rx; 1268 qinfo->nb_desc = rxq->nb_desc; 1269 qinfo->conf.rx_free_thresh = 1; 1270 qinfo->conf.rx_drop_en = 1; 1271 qinfo->conf.rx_deferred_start = 0; 1272 qinfo->conf.offloads = rxq->offloads; 1273 } 1274 1275 static void 1276 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1277 struct rte_eth_txq_info *qinfo) 1278 { 1279 struct qman_fq *txq; 1280 1281 txq = dev->data->tx_queues[queue_id]; 1282 1283 qinfo->nb_desc = txq->nb_desc; 1284 qinfo->conf.tx_thresh.pthresh = 0; 1285 qinfo->conf.tx_thresh.hthresh = 0; 1286 qinfo->conf.tx_thresh.wthresh = 0; 1287 1288 qinfo->conf.tx_free_thresh = 0; 1289 qinfo->conf.tx_rs_thresh = 0; 1290 qinfo->conf.offloads = txq->offloads; 1291 qinfo->conf.tx_deferred_start = 0; 1292 } 1293 1294 static struct eth_dev_ops dpaa_devops = { 1295 .dev_configure = dpaa_eth_dev_configure, 1296 .dev_start = dpaa_eth_dev_start, 1297 .dev_stop = dpaa_eth_dev_stop, 1298 .dev_close = dpaa_eth_dev_close, 1299 .dev_infos_get = dpaa_eth_dev_info, 1300 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1301 1302 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1303 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1304 .rx_queue_release = dpaa_eth_rx_queue_release, 1305 .tx_queue_release = dpaa_eth_tx_queue_release, 1306 .rx_queue_count = dpaa_dev_rx_queue_count, 1307 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1308 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1309 .rxq_info_get = dpaa_rxq_info_get, 1310 .txq_info_get = dpaa_txq_info_get, 1311 1312 .flow_ctrl_get = dpaa_flow_ctrl_get, 1313 .flow_ctrl_set = dpaa_flow_ctrl_set, 1314 1315 .link_update = dpaa_eth_link_update, 1316 .stats_get = dpaa_eth_stats_get, 1317 .xstats_get = dpaa_dev_xstats_get, 1318 .xstats_get_by_id = dpaa_xstats_get_by_id, 1319 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1320 .xstats_get_names = dpaa_xstats_get_names, 1321 .xstats_reset = dpaa_eth_stats_reset, 1322 .stats_reset = dpaa_eth_stats_reset, 1323 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1324 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1325 .allmulticast_enable = dpaa_eth_multicast_enable, 1326 .allmulticast_disable = dpaa_eth_multicast_disable, 1327 .mtu_set = dpaa_mtu_set, 1328 .dev_set_link_down = dpaa_link_down, 1329 .dev_set_link_up = dpaa_link_up, 1330 .mac_addr_add = dpaa_dev_add_mac_addr, 1331 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1332 .mac_addr_set = dpaa_dev_set_mac_addr, 1333 1334 .fw_version_get = dpaa_fw_version_get, 1335 1336 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1337 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1338 }; 1339 1340 static bool 1341 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1342 { 1343 if (strcmp(dev->device->driver->name, 1344 drv->driver.name)) 1345 return false; 1346 1347 return true; 1348 } 1349 1350 static bool 1351 is_dpaa_supported(struct rte_eth_dev *dev) 1352 { 1353 return is_device_supported(dev, &rte_dpaa_pmd); 1354 } 1355 1356 int 1357 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) 1358 { 1359 struct rte_eth_dev *dev; 1360 1361 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1362 1363 dev = &rte_eth_devices[port]; 1364 1365 if (!is_dpaa_supported(dev)) 1366 return -ENOTSUP; 1367 1368 if (on) 1369 fman_if_loopback_enable(dev->process_private); 1370 else 1371 fman_if_loopback_disable(dev->process_private); 1372 1373 return 0; 1374 } 1375 1376 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1377 struct fman_if *fman_intf) 1378 { 1379 struct rte_eth_fc_conf *fc_conf; 1380 int ret; 1381 1382 PMD_INIT_FUNC_TRACE(); 1383 1384 if (!(dpaa_intf->fc_conf)) { 1385 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1386 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1387 if (!dpaa_intf->fc_conf) { 1388 DPAA_PMD_ERR("unable to save flow control info"); 1389 return -ENOMEM; 1390 } 1391 } 1392 fc_conf = dpaa_intf->fc_conf; 1393 ret = fman_if_get_fc_threshold(fman_intf); 1394 if (ret) { 1395 fc_conf->mode = RTE_FC_TX_PAUSE; 1396 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1397 } else { 1398 fc_conf->mode = RTE_FC_NONE; 1399 } 1400 1401 return 0; 1402 } 1403 1404 /* Initialise an Rx FQ */ 1405 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1406 uint32_t fqid) 1407 { 1408 struct qm_mcc_initfq opts = {0}; 1409 int ret; 1410 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1411 struct qm_mcc_initcgr cgr_opts = { 1412 .we_mask = QM_CGR_WE_CS_THRES | 1413 QM_CGR_WE_CSTD_EN | 1414 QM_CGR_WE_MODE, 1415 .cgr = { 1416 .cstd_en = QM_CGR_EN, 1417 .mode = QMAN_CGR_MODE_FRAME 1418 } 1419 }; 1420 1421 if (fqid) { 1422 ret = qman_reserve_fqid(fqid); 1423 if (ret) { 1424 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d", 1425 fqid, ret); 1426 return -EINVAL; 1427 } 1428 } else { 1429 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 1430 } 1431 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1432 ret = qman_create_fq(fqid, flags, fq); 1433 if (ret) { 1434 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1435 fqid, ret); 1436 return ret; 1437 } 1438 fq->is_static = false; 1439 1440 dpaa_poll_queue_default_config(&opts); 1441 1442 if (cgr_rx) { 1443 /* Enable tail drop with cgr on this queue */ 1444 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1445 cgr_rx->cb = NULL; 1446 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1447 &cgr_opts); 1448 if (ret) { 1449 DPAA_PMD_WARN( 1450 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1451 fq->fqid, ret); 1452 goto without_cgr; 1453 } 1454 opts.we_mask |= QM_INITFQ_WE_CGID; 1455 opts.fqd.cgid = cgr_rx->cgrid; 1456 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1457 } 1458 without_cgr: 1459 ret = qman_init_fq(fq, 0, &opts); 1460 if (ret) 1461 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1462 return ret; 1463 } 1464 1465 /* Initialise a Tx FQ */ 1466 static int dpaa_tx_queue_init(struct qman_fq *fq, 1467 struct fman_if *fman_intf, 1468 struct qman_cgr *cgr_tx) 1469 { 1470 struct qm_mcc_initfq opts = {0}; 1471 struct qm_mcc_initcgr cgr_opts = { 1472 .we_mask = QM_CGR_WE_CS_THRES | 1473 QM_CGR_WE_CSTD_EN | 1474 QM_CGR_WE_MODE, 1475 .cgr = { 1476 .cstd_en = QM_CGR_EN, 1477 .mode = QMAN_CGR_MODE_FRAME 1478 } 1479 }; 1480 int ret; 1481 1482 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1483 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1484 if (ret) { 1485 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1486 return ret; 1487 } 1488 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1489 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1490 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1491 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1492 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1493 opts.fqd.context_b = 0; 1494 /* no tx-confirmation */ 1495 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1496 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1497 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1498 1499 if (cgr_tx) { 1500 /* Enable tail drop with cgr on this queue */ 1501 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1502 td_tx_threshold, 0); 1503 cgr_tx->cb = NULL; 1504 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1505 &cgr_opts); 1506 if (ret) { 1507 DPAA_PMD_WARN( 1508 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1509 fq->fqid, ret); 1510 goto without_cgr; 1511 } 1512 opts.we_mask |= QM_INITFQ_WE_CGID; 1513 opts.fqd.cgid = cgr_tx->cgrid; 1514 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1515 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1516 td_tx_threshold); 1517 } 1518 without_cgr: 1519 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1520 if (ret) 1521 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1522 return ret; 1523 } 1524 1525 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1526 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1527 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1528 { 1529 struct qm_mcc_initfq opts = {0}; 1530 int ret; 1531 1532 PMD_INIT_FUNC_TRACE(); 1533 1534 ret = qman_reserve_fqid(fqid); 1535 if (ret) { 1536 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1537 fqid, ret); 1538 return -EINVAL; 1539 } 1540 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1541 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1542 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1543 if (ret) { 1544 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1545 fqid, ret); 1546 return ret; 1547 } 1548 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1549 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1550 ret = qman_init_fq(fq, 0, &opts); 1551 if (ret) 1552 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1553 fqid, ret); 1554 return ret; 1555 } 1556 #endif 1557 1558 /* Initialise a network interface */ 1559 static int 1560 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1561 { 1562 struct rte_dpaa_device *dpaa_device; 1563 struct fm_eth_port_cfg *cfg; 1564 struct dpaa_if *dpaa_intf; 1565 struct fman_if *fman_intf; 1566 int dev_id; 1567 1568 PMD_INIT_FUNC_TRACE(); 1569 1570 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1571 dev_id = dpaa_device->id.dev_id; 1572 cfg = dpaa_get_eth_port_cfg(dev_id); 1573 fman_intf = cfg->fman_if; 1574 eth_dev->process_private = fman_intf; 1575 1576 /* Plugging of UCODE burst API not supported in Secondary */ 1577 dpaa_intf = eth_dev->data->dev_private; 1578 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1579 if (dpaa_intf->cgr_tx) 1580 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1581 else 1582 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1583 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1584 qman_set_fq_lookup_table( 1585 dpaa_intf->rx_queues->qman_fq_lookup_table); 1586 #endif 1587 1588 return 0; 1589 } 1590 1591 /* Initialise a network interface */ 1592 static int 1593 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1594 { 1595 int num_rx_fqs, fqid; 1596 int loop, ret = 0; 1597 int dev_id; 1598 struct rte_dpaa_device *dpaa_device; 1599 struct dpaa_if *dpaa_intf; 1600 struct fm_eth_port_cfg *cfg; 1601 struct fman_if *fman_intf; 1602 struct fman_if_bpool *bp, *tmp_bp; 1603 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1604 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1605 char eth_buf[RTE_ETHER_ADDR_FMT_SIZE]; 1606 1607 PMD_INIT_FUNC_TRACE(); 1608 1609 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1610 dev_id = dpaa_device->id.dev_id; 1611 dpaa_intf = eth_dev->data->dev_private; 1612 cfg = dpaa_get_eth_port_cfg(dev_id); 1613 fman_intf = cfg->fman_if; 1614 1615 dpaa_intf->name = dpaa_device->name; 1616 1617 /* save fman_if & cfg in the interface struture */ 1618 eth_dev->process_private = fman_intf; 1619 dpaa_intf->ifid = dev_id; 1620 dpaa_intf->cfg = cfg; 1621 1622 /* Initialize Rx FQ's */ 1623 if (default_q) { 1624 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1625 } else { 1626 if (getenv("DPAA_NUM_RX_QUEUES")) 1627 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES")); 1628 else 1629 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1630 } 1631 1632 1633 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1634 * queues. 1635 */ 1636 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1637 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1638 return -EINVAL; 1639 } 1640 1641 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1642 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1643 if (!dpaa_intf->rx_queues) { 1644 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1645 return -ENOMEM; 1646 } 1647 1648 memset(cgrid, 0, sizeof(cgrid)); 1649 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1650 1651 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1652 * Tx tail drop is disabled. 1653 */ 1654 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1655 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1656 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1657 td_tx_threshold); 1658 /* if a very large value is being configured */ 1659 if (td_tx_threshold > UINT16_MAX) 1660 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1661 } 1662 1663 /* If congestion control is enabled globally*/ 1664 if (td_threshold) { 1665 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1666 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1667 if (!dpaa_intf->cgr_rx) { 1668 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1669 ret = -ENOMEM; 1670 goto free_rx; 1671 } 1672 1673 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1674 if (ret != num_rx_fqs) { 1675 DPAA_PMD_WARN("insufficient CGRIDs available"); 1676 ret = -EINVAL; 1677 goto free_rx; 1678 } 1679 } else { 1680 dpaa_intf->cgr_rx = NULL; 1681 } 1682 1683 for (loop = 0; loop < num_rx_fqs; loop++) { 1684 if (default_q) 1685 fqid = cfg->rx_def; 1686 else 1687 fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx * 1688 DPAA_PCD_FQID_MULTIPLIER + loop; 1689 1690 if (dpaa_intf->cgr_rx) 1691 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1692 1693 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1694 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1695 fqid); 1696 if (ret) 1697 goto free_rx; 1698 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1699 } 1700 dpaa_intf->nb_rx_queues = num_rx_fqs; 1701 1702 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1703 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1704 MAX_DPAA_CORES, MAX_CACHELINE); 1705 if (!dpaa_intf->tx_queues) { 1706 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1707 ret = -ENOMEM; 1708 goto free_rx; 1709 } 1710 1711 /* If congestion control is enabled globally*/ 1712 if (td_tx_threshold) { 1713 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 1714 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 1715 MAX_CACHELINE); 1716 if (!dpaa_intf->cgr_tx) { 1717 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 1718 ret = -ENOMEM; 1719 goto free_rx; 1720 } 1721 1722 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 1723 1, 0); 1724 if (ret != MAX_DPAA_CORES) { 1725 DPAA_PMD_WARN("insufficient CGRIDs available"); 1726 ret = -EINVAL; 1727 goto free_rx; 1728 } 1729 } else { 1730 dpaa_intf->cgr_tx = NULL; 1731 } 1732 1733 1734 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 1735 if (dpaa_intf->cgr_tx) 1736 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 1737 1738 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1739 fman_intf, 1740 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 1741 if (ret) 1742 goto free_tx; 1743 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1744 } 1745 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 1746 1747 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1748 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1749 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1750 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1751 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1752 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1753 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1754 #endif 1755 1756 DPAA_PMD_DEBUG("All frame queues created"); 1757 1758 /* Get the initial configuration for flow control */ 1759 dpaa_fc_set_default(dpaa_intf, fman_intf); 1760 1761 /* reset bpool list, initialize bpool dynamically */ 1762 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1763 list_del(&bp->node); 1764 rte_free(bp); 1765 } 1766 1767 /* Populate ethdev structure */ 1768 eth_dev->dev_ops = &dpaa_devops; 1769 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1770 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1771 1772 /* Allocate memory for storing MAC addresses */ 1773 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1774 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1775 if (eth_dev->data->mac_addrs == NULL) { 1776 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1777 "store MAC addresses", 1778 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1779 ret = -ENOMEM; 1780 goto free_tx; 1781 } 1782 1783 /* copy the primary mac address */ 1784 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1785 rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr); 1786 1787 DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf); 1788 1789 /* Disable RX mode */ 1790 fman_if_discard_rx_errors(fman_intf); 1791 fman_if_disable_rx(fman_intf); 1792 /* Disable promiscuous mode */ 1793 fman_if_promiscuous_disable(fman_intf); 1794 /* Disable multicast */ 1795 fman_if_reset_mcast_filter_table(fman_intf); 1796 /* Reset interface statistics */ 1797 fman_if_stats_reset(fman_intf); 1798 /* Disable SG by default */ 1799 fman_if_set_sg(fman_intf, 0); 1800 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 1801 1802 return 0; 1803 1804 free_tx: 1805 rte_free(dpaa_intf->tx_queues); 1806 dpaa_intf->tx_queues = NULL; 1807 dpaa_intf->nb_tx_queues = 0; 1808 1809 free_rx: 1810 rte_free(dpaa_intf->cgr_rx); 1811 rte_free(dpaa_intf->cgr_tx); 1812 rte_free(dpaa_intf->rx_queues); 1813 dpaa_intf->rx_queues = NULL; 1814 dpaa_intf->nb_rx_queues = 0; 1815 return ret; 1816 } 1817 1818 static int 1819 dpaa_dev_uninit(struct rte_eth_dev *dev) 1820 { 1821 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1822 int loop; 1823 1824 PMD_INIT_FUNC_TRACE(); 1825 1826 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1827 return -EPERM; 1828 1829 if (!dpaa_intf) { 1830 DPAA_PMD_WARN("Already closed or not started"); 1831 return -1; 1832 } 1833 1834 dpaa_eth_dev_close(dev); 1835 1836 /* release configuration memory */ 1837 if (dpaa_intf->fc_conf) 1838 rte_free(dpaa_intf->fc_conf); 1839 1840 /* Release RX congestion Groups */ 1841 if (dpaa_intf->cgr_rx) { 1842 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 1843 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 1844 1845 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 1846 dpaa_intf->nb_rx_queues); 1847 } 1848 1849 rte_free(dpaa_intf->cgr_rx); 1850 dpaa_intf->cgr_rx = NULL; 1851 1852 /* Release TX congestion Groups */ 1853 if (dpaa_intf->cgr_tx) { 1854 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 1855 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 1856 1857 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid, 1858 MAX_DPAA_CORES); 1859 rte_free(dpaa_intf->cgr_tx); 1860 dpaa_intf->cgr_tx = NULL; 1861 } 1862 1863 rte_free(dpaa_intf->rx_queues); 1864 dpaa_intf->rx_queues = NULL; 1865 1866 rte_free(dpaa_intf->tx_queues); 1867 dpaa_intf->tx_queues = NULL; 1868 1869 dev->dev_ops = NULL; 1870 dev->rx_pkt_burst = NULL; 1871 dev->tx_pkt_burst = NULL; 1872 1873 return 0; 1874 } 1875 1876 static int 1877 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, 1878 struct rte_dpaa_device *dpaa_dev) 1879 { 1880 int diag; 1881 int ret; 1882 struct rte_eth_dev *eth_dev; 1883 1884 PMD_INIT_FUNC_TRACE(); 1885 1886 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 1887 RTE_PKTMBUF_HEADROOM) { 1888 DPAA_PMD_ERR( 1889 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 1890 RTE_PKTMBUF_HEADROOM, 1891 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 1892 1893 return -1; 1894 } 1895 1896 /* In case of secondary process, the device is already configured 1897 * and no further action is required, except portal initialization 1898 * and verifying secondary attachment to port name. 1899 */ 1900 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1901 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1902 if (!eth_dev) 1903 return -ENOMEM; 1904 eth_dev->device = &dpaa_dev->device; 1905 eth_dev->dev_ops = &dpaa_devops; 1906 1907 ret = dpaa_dev_init_secondary(eth_dev); 1908 if (ret != 0) { 1909 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 1910 return ret; 1911 } 1912 1913 rte_eth_dev_probing_finish(eth_dev); 1914 return 0; 1915 } 1916 1917 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 1918 if (access("/tmp/fmc.bin", F_OK) == -1) { 1919 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 1920 default_q = 1; 1921 } 1922 1923 /* disabling the default push mode for LS1043 */ 1924 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 1925 dpaa_push_mode_max_queue = 0; 1926 1927 /* if push mode queues to be enabled. Currenly we are allowing 1928 * only one queue per thread. 1929 */ 1930 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 1931 dpaa_push_mode_max_queue = 1932 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 1933 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 1934 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 1935 } 1936 1937 is_global_init = 1; 1938 } 1939 1940 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 1941 ret = rte_dpaa_portal_init((void *)1); 1942 if (ret) { 1943 DPAA_PMD_ERR("Unable to initialize portal"); 1944 return ret; 1945 } 1946 } 1947 1948 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 1949 if (!eth_dev) 1950 return -ENOMEM; 1951 1952 eth_dev->data->dev_private = 1953 rte_zmalloc("ethdev private structure", 1954 sizeof(struct dpaa_if), 1955 RTE_CACHE_LINE_SIZE); 1956 if (!eth_dev->data->dev_private) { 1957 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 1958 rte_eth_dev_release_port(eth_dev); 1959 return -ENOMEM; 1960 } 1961 1962 eth_dev->device = &dpaa_dev->device; 1963 dpaa_dev->eth_dev = eth_dev; 1964 1965 qman_ern_register_cb(dpaa_free_mbuf); 1966 1967 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 1968 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 1969 1970 /* Invoke PMD device initialization function */ 1971 diag = dpaa_dev_init(eth_dev); 1972 if (diag == 0) { 1973 rte_eth_dev_probing_finish(eth_dev); 1974 return 0; 1975 } 1976 1977 rte_eth_dev_release_port(eth_dev); 1978 return diag; 1979 } 1980 1981 static int 1982 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 1983 { 1984 struct rte_eth_dev *eth_dev; 1985 1986 PMD_INIT_FUNC_TRACE(); 1987 1988 eth_dev = dpaa_dev->eth_dev; 1989 dpaa_dev_uninit(eth_dev); 1990 1991 rte_eth_dev_release_port(eth_dev); 1992 1993 return 0; 1994 } 1995 1996 static struct rte_dpaa_driver rte_dpaa_pmd = { 1997 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 1998 .drv_type = FSL_DPAA_ETH, 1999 .probe = rte_dpaa_probe, 2000 .remove = rte_dpaa_remove, 2001 }; 2002 2003 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2004 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE); 2005