1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_atomic.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_random.h> 33 #include <rte_dev.h> 34 #include <rte_kvargs.h> 35 36 #include "base/common.h" 37 #include "base/t4_regs.h" 38 #include "base/t4_msg.h" 39 #include "cxgbe.h" 40 #include "cxgbe_pfvf.h" 41 #include "clip_tbl.h" 42 #include "l2t.h" 43 #include "mps_tcam.h" 44 45 /** 46 * Allocate a chunk of memory. The allocated memory is cleared. 47 */ 48 void *t4_alloc_mem(size_t size) 49 { 50 return rte_zmalloc(NULL, size, 0); 51 } 52 53 /** 54 * Free memory allocated through t4_alloc_mem(). 55 */ 56 void t4_free_mem(void *addr) 57 { 58 rte_free(addr); 59 } 60 61 /* 62 * Response queue handler for the FW event queue. 63 */ 64 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 65 __rte_unused const struct pkt_gl *gl) 66 { 67 u8 opcode = ((const struct rss_header *)rsp)->opcode; 68 69 rsp++; /* skip RSS header */ 70 71 /* 72 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 73 */ 74 if (unlikely(opcode == CPL_FW4_MSG && 75 ((const struct cpl_fw4_msg *)rsp)->type == 76 FW_TYPE_RSSCPL)) { 77 rsp++; 78 opcode = ((const struct rss_header *)rsp)->opcode; 79 rsp++; 80 if (opcode != CPL_SGE_EGR_UPDATE) { 81 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 82 opcode); 83 goto out; 84 } 85 } 86 87 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 88 /* do nothing */ 89 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 90 const struct cpl_fw6_msg *msg = (const void *)rsp; 91 92 t4_handle_fw_rpl(q->adapter, msg->data); 93 } else if (opcode == CPL_ABORT_RPL_RSS) { 94 const struct cpl_abort_rpl_rss *p = (const void *)rsp; 95 96 cxgbe_hash_del_filter_rpl(q->adapter, p); 97 } else if (opcode == CPL_SET_TCB_RPL) { 98 const struct cpl_set_tcb_rpl *p = (const void *)rsp; 99 100 cxgbe_filter_rpl(q->adapter, p); 101 } else if (opcode == CPL_ACT_OPEN_RPL) { 102 const struct cpl_act_open_rpl *p = (const void *)rsp; 103 104 cxgbe_hash_filter_rpl(q->adapter, p); 105 } else if (opcode == CPL_L2T_WRITE_RPL) { 106 const struct cpl_l2t_write_rpl *p = (const void *)rsp; 107 108 cxgbe_do_l2t_write_rpl(q->adapter, p); 109 } else { 110 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 111 opcode); 112 } 113 out: 114 return 0; 115 } 116 117 /** 118 * Setup sge control queues to pass control information. 119 */ 120 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter) 121 { 122 struct sge *s = &adapter->sge; 123 int err = 0, i = 0; 124 125 for_each_port(adapter, i) { 126 struct port_info *pi = adap2pinfo(adapter, i); 127 char name[RTE_ETH_NAME_MAX_LEN]; 128 struct sge_ctrl_txq *q = &s->ctrlq[i]; 129 130 q->q.size = 1024; 131 err = t4_sge_alloc_ctrl_txq(adapter, q, 132 adapter->eth_dev, i, 133 s->fw_evtq.cntxt_id, 134 rte_socket_id()); 135 if (err) { 136 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d", 137 err); 138 goto out; 139 } 140 snprintf(name, sizeof(name), "%s_ctrl_pool_%d", 141 pi->eth_dev->device->driver->name, 142 pi->eth_dev->data->port_id); 143 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size, 144 RTE_CACHE_LINE_SIZE, 145 RTE_MBUF_PRIV_ALIGN, 146 RTE_MBUF_DEFAULT_BUF_SIZE, 147 SOCKET_ID_ANY); 148 if (!q->mb_pool) { 149 err = -rte_errno; 150 dev_err(adapter, 151 "Can't create ctrl pool for port %d. Err: %d\n", 152 pi->eth_dev->data->port_id, err); 153 goto out; 154 } 155 } 156 return 0; 157 out: 158 t4_free_sge_resources(adapter); 159 return err; 160 } 161 162 /** 163 * cxgbe_poll_for_completion: Poll rxq for completion 164 * @q: rxq to poll 165 * @ms: milliseconds to delay 166 * @cnt: number of times to poll 167 * @c: completion to check for 'done' status 168 * 169 * Polls the rxq for reples until completion is done or the count 170 * expires. 171 */ 172 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms, 173 unsigned int cnt, struct t4_completion *c) 174 { 175 unsigned int i; 176 unsigned int work_done, budget = 32; 177 178 if (!c) 179 return -EINVAL; 180 181 for (i = 0; i < cnt; i++) { 182 cxgbe_poll(q, NULL, budget, &work_done); 183 t4_os_lock(&c->lock); 184 if (c->done) { 185 t4_os_unlock(&c->lock); 186 return 0; 187 } 188 t4_os_unlock(&c->lock); 189 rte_delay_ms(ms); 190 } 191 return -ETIMEDOUT; 192 } 193 194 int cxgbe_setup_sge_fwevtq(struct adapter *adapter) 195 { 196 struct sge *s = &adapter->sge; 197 int err = 0; 198 int msi_idx = 0; 199 200 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 201 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 202 rte_socket_id()); 203 return err; 204 } 205 206 static int closest_timer(const struct sge *s, int time) 207 { 208 unsigned int i, match = 0; 209 int delta, min_delta = INT_MAX; 210 211 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 212 delta = time - s->timer_val[i]; 213 if (delta < 0) 214 delta = -delta; 215 if (delta < min_delta) { 216 min_delta = delta; 217 match = i; 218 } 219 } 220 return match; 221 } 222 223 static int closest_thres(const struct sge *s, int thres) 224 { 225 unsigned int i, match = 0; 226 int delta, min_delta = INT_MAX; 227 228 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 229 delta = thres - s->counter_val[i]; 230 if (delta < 0) 231 delta = -delta; 232 if (delta < min_delta) { 233 min_delta = delta; 234 match = i; 235 } 236 } 237 return match; 238 } 239 240 /** 241 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 242 * @q: the Rx queue 243 * @us: the hold-off time in us, or 0 to disable timer 244 * @cnt: the hold-off packet count, or 0 to disable counter 245 * 246 * Sets an Rx queue's interrupt hold-off time and packet count. At least 247 * one of the two needs to be enabled for the queue to generate interrupts. 248 */ 249 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 250 unsigned int cnt) 251 { 252 struct adapter *adap = q->adapter; 253 unsigned int timer_val; 254 255 if (cnt) { 256 int err; 257 u32 v, new_idx; 258 259 new_idx = closest_thres(&adap->sge, cnt); 260 if (q->desc && q->pktcnt_idx != new_idx) { 261 /* the queue has already been created, update it */ 262 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 263 V_FW_PARAMS_PARAM_X( 264 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 265 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 266 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 267 &v, &new_idx); 268 if (err) 269 return err; 270 } 271 q->pktcnt_idx = new_idx; 272 } 273 274 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 275 closest_timer(&adap->sge, us); 276 277 if ((us | cnt) == 0) 278 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 279 else 280 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 281 V_QINTR_CNT_EN(cnt > 0); 282 return 0; 283 } 284 285 /** 286 * Allocate an active-open TID and set it to the supplied value. 287 */ 288 int cxgbe_alloc_atid(struct tid_info *t, void *data) 289 { 290 int atid = -1; 291 292 t4_os_lock(&t->atid_lock); 293 if (t->afree) { 294 union aopen_entry *p = t->afree; 295 296 atid = p - t->atid_tab; 297 t->afree = p->next; 298 p->data = data; 299 t->atids_in_use++; 300 } 301 t4_os_unlock(&t->atid_lock); 302 return atid; 303 } 304 305 /** 306 * Release an active-open TID. 307 */ 308 void cxgbe_free_atid(struct tid_info *t, unsigned int atid) 309 { 310 union aopen_entry *p = &t->atid_tab[atid]; 311 312 t4_os_lock(&t->atid_lock); 313 p->next = t->afree; 314 t->afree = p; 315 t->atids_in_use--; 316 t4_os_unlock(&t->atid_lock); 317 } 318 319 /** 320 * Populate a TID_RELEASE WR. Caller must properly size the skb. 321 */ 322 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid) 323 { 324 struct cpl_tid_release *req; 325 326 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *); 327 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 328 } 329 330 /** 331 * Release a TID and inform HW. If we are unable to allocate the release 332 * message we defer to a work queue. 333 */ 334 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 335 unsigned short family) 336 { 337 struct rte_mbuf *mbuf; 338 struct adapter *adap = container_of(t, struct adapter, tids); 339 340 WARN_ON(tid >= t->ntids); 341 342 if (t->tid_tab[tid]) { 343 t->tid_tab[tid] = NULL; 344 rte_atomic32_dec(&t->conns_in_use); 345 if (t->hash_base && tid >= t->hash_base) { 346 if (family == FILTER_TYPE_IPV4) 347 rte_atomic32_dec(&t->hash_tids_in_use); 348 } else { 349 if (family == FILTER_TYPE_IPV4) 350 rte_atomic32_dec(&t->tids_in_use); 351 } 352 } 353 354 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool); 355 if (mbuf) { 356 mbuf->data_len = sizeof(struct cpl_tid_release); 357 mbuf->pkt_len = mbuf->data_len; 358 mk_tid_release(mbuf, tid); 359 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf); 360 } 361 } 362 363 /** 364 * Insert a TID. 365 */ 366 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, 367 unsigned short family) 368 { 369 t->tid_tab[tid] = data; 370 if (t->hash_base && tid >= t->hash_base) { 371 if (family == FILTER_TYPE_IPV4) 372 rte_atomic32_inc(&t->hash_tids_in_use); 373 } else { 374 if (family == FILTER_TYPE_IPV4) 375 rte_atomic32_inc(&t->tids_in_use); 376 } 377 378 rte_atomic32_inc(&t->conns_in_use); 379 } 380 381 /** 382 * Free TID tables. 383 */ 384 static void tid_free(struct tid_info *t) 385 { 386 if (t->tid_tab) { 387 if (t->ftid_bmap) 388 rte_bitmap_free(t->ftid_bmap); 389 390 if (t->ftid_bmap_array) 391 t4_os_free(t->ftid_bmap_array); 392 393 t4_os_free(t->tid_tab); 394 } 395 396 memset(t, 0, sizeof(struct tid_info)); 397 } 398 399 /** 400 * Allocate and initialize the TID tables. Returns 0 on success. 401 */ 402 static int tid_init(struct tid_info *t) 403 { 404 size_t size; 405 unsigned int ftid_bmap_size; 406 unsigned int natids = t->natids; 407 unsigned int max_ftids = t->nftids; 408 409 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids); 410 size = t->ntids * sizeof(*t->tid_tab) + 411 max_ftids * sizeof(*t->ftid_tab) + 412 natids * sizeof(*t->atid_tab); 413 414 t->tid_tab = t4_os_alloc(size); 415 if (!t->tid_tab) 416 return -ENOMEM; 417 418 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 419 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids]; 420 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size); 421 if (!t->ftid_bmap_array) { 422 tid_free(t); 423 return -ENOMEM; 424 } 425 426 t4_os_lock_init(&t->atid_lock); 427 t4_os_lock_init(&t->ftid_lock); 428 429 t->afree = NULL; 430 t->atids_in_use = 0; 431 rte_atomic32_init(&t->tids_in_use); 432 rte_atomic32_set(&t->tids_in_use, 0); 433 rte_atomic32_init(&t->conns_in_use); 434 rte_atomic32_set(&t->conns_in_use, 0); 435 436 /* Setup the free list for atid_tab and clear the stid bitmap. */ 437 if (natids) { 438 while (--natids) 439 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 440 t->afree = t->atid_tab; 441 } 442 443 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array, 444 ftid_bmap_size); 445 if (!t->ftid_bmap) { 446 tid_free(t); 447 return -ENOMEM; 448 } 449 450 return 0; 451 } 452 453 static inline bool is_x_1g_port(const struct link_config *lc) 454 { 455 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0; 456 } 457 458 static inline bool is_x_10g_port(const struct link_config *lc) 459 { 460 unsigned int speeds, high_speeds; 461 462 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps)); 463 high_speeds = speeds & 464 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 465 466 return high_speeds != 0; 467 } 468 469 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 470 unsigned int us, unsigned int cnt, 471 unsigned int size, unsigned int iqe_size) 472 { 473 q->adapter = adap; 474 cxgb4_set_rspq_intr_params(q, us, cnt); 475 q->iqe_len = iqe_size; 476 q->size = size; 477 } 478 479 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev) 480 { 481 struct port_info *pi = eth_dev->data->dev_private; 482 struct adapter *adap = pi->adapter; 483 struct sge *s = &adap->sge; 484 unsigned int max_queues = s->max_ethqsets / adap->params.nports; 485 486 if ((eth_dev->data->nb_rx_queues < 1) || 487 (eth_dev->data->nb_tx_queues < 1)) 488 return -EINVAL; 489 490 if ((eth_dev->data->nb_rx_queues > max_queues) || 491 (eth_dev->data->nb_tx_queues > max_queues)) 492 return -EINVAL; 493 494 if (eth_dev->data->nb_rx_queues > pi->rss_size) 495 return -EINVAL; 496 497 /* We must configure RSS, since config has changed*/ 498 pi->flags &= ~PORT_RSS_DONE; 499 500 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 501 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 502 503 return 0; 504 } 505 506 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev) 507 { 508 struct port_info *pi = eth_dev->data->dev_private; 509 struct adapter *adap = pi->adapter; 510 struct sge *s = &adap->sge; 511 unsigned int i, nb_ports = 0, qidx = 0; 512 unsigned int q_per_port = 0; 513 514 if (!(adap->flags & CFG_QUEUES)) { 515 for_each_port(adap, i) { 516 struct port_info *tpi = adap2pinfo(adap, i); 517 518 nb_ports += (is_x_10g_port(&tpi->link_cfg)) || 519 is_x_1g_port(&tpi->link_cfg) ? 1 : 0; 520 } 521 522 /* 523 * We default up to # of cores queues per 1G/10G port. 524 */ 525 if (nb_ports) 526 q_per_port = (s->max_ethqsets - 527 (adap->params.nports - nb_ports)) / 528 nb_ports; 529 530 if (q_per_port > rte_lcore_count()) 531 q_per_port = rte_lcore_count(); 532 533 for_each_port(adap, i) { 534 struct port_info *pi = adap2pinfo(adap, i); 535 536 pi->first_qset = qidx; 537 538 /* Initially n_rx_qsets == n_tx_qsets */ 539 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) || 540 is_x_1g_port(&pi->link_cfg)) ? 541 q_per_port : 1; 542 pi->n_tx_qsets = pi->n_rx_qsets; 543 544 if (pi->n_rx_qsets > pi->rss_size) 545 pi->n_rx_qsets = pi->rss_size; 546 547 qidx += pi->n_rx_qsets; 548 } 549 550 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 551 struct sge_eth_rxq *r = &s->ethrxq[i]; 552 553 init_rspq(adap, &r->rspq, 5, 32, 1024, 64); 554 r->usembufs = 1; 555 r->fl.size = (r->usembufs ? 1024 : 72); 556 } 557 558 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 559 s->ethtxq[i].q.size = 1024; 560 561 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 562 adap->flags |= CFG_QUEUES; 563 } 564 } 565 566 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 567 { 568 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 569 &pi->stats_base); 570 } 571 572 void cxgbe_stats_reset(struct port_info *pi) 573 { 574 t4_clr_port_stats(pi->adapter, pi->tx_chan); 575 } 576 577 static void setup_memwin(struct adapter *adap) 578 { 579 u32 mem_win0_base; 580 581 /* For T5, only relative offset inside the PCIe BAR is passed */ 582 mem_win0_base = MEMWIN0_BASE; 583 584 /* 585 * Set up memory window for accessing adapter memory ranges. (Read 586 * back MA register to ensure that changes propagate before we attempt 587 * to use the new values.) 588 */ 589 t4_write_reg(adap, 590 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 591 MEMWIN_NIC), 592 mem_win0_base | V_BIR(0) | 593 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 594 t4_read_reg(adap, 595 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 596 MEMWIN_NIC)); 597 } 598 599 int cxgbe_init_rss(struct adapter *adap) 600 { 601 unsigned int i; 602 603 if (is_pf4(adap)) { 604 int err; 605 606 err = t4_init_rss_mode(adap, adap->mbox); 607 if (err) 608 return err; 609 } 610 611 for_each_port(adap, i) { 612 struct port_info *pi = adap2pinfo(adap, i); 613 614 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 615 if (!pi->rss) 616 return -ENOMEM; 617 618 pi->rss_hf = CXGBE_RSS_HF_ALL; 619 } 620 return 0; 621 } 622 623 /** 624 * Dump basic information about the adapter. 625 */ 626 void cxgbe_print_adapter_info(struct adapter *adap) 627 { 628 /** 629 * Hardware/Firmware/etc. Version/Revision IDs. 630 */ 631 t4_dump_version_info(adap); 632 } 633 634 void cxgbe_print_port_info(struct adapter *adap) 635 { 636 int i; 637 char buf[80]; 638 struct rte_pci_addr *loc = &adap->pdev->addr; 639 640 for_each_port(adap, i) { 641 const struct port_info *pi = adap2pinfo(adap, i); 642 char *bufp = buf; 643 644 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 645 bufp += sprintf(bufp, "100M/"); 646 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 647 bufp += sprintf(bufp, "1G/"); 648 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 649 bufp += sprintf(bufp, "10G/"); 650 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 651 bufp += sprintf(bufp, "25G/"); 652 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 653 bufp += sprintf(bufp, "40G/"); 654 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 655 bufp += sprintf(bufp, "50G/"); 656 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 657 bufp += sprintf(bufp, "100G/"); 658 if (bufp != buf) 659 --bufp; 660 sprintf(bufp, "BASE-%s", 661 t4_get_port_type_description( 662 (enum fw_port_type)pi->port_type)); 663 664 dev_info(adap, 665 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 666 loc->domain, loc->bus, loc->devid, loc->function, 667 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 668 (adap->flags & USING_MSIX) ? " MSI-X" : 669 (adap->flags & USING_MSI) ? " MSI" : ""); 670 } 671 } 672 673 static int check_devargs_handler(const char *key, const char *value, void *p) 674 { 675 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) || 676 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) || 677 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) { 678 if (!strncmp(value, "1", 1)) { 679 bool *dst_val = (bool *)p; 680 681 *dst_val = true; 682 } 683 } 684 685 return 0; 686 } 687 688 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key, 689 void *p) 690 { 691 struct rte_kvargs *kvlist; 692 int ret = 0; 693 694 if (!devargs) 695 return 0; 696 697 kvlist = rte_kvargs_parse(devargs->args, NULL); 698 if (!kvlist) 699 return 0; 700 701 if (!rte_kvargs_count(kvlist, key)) 702 goto out; 703 704 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p); 705 706 out: 707 rte_kvargs_free(kvlist); 708 709 return ret; 710 } 711 712 static void cxgbe_get_devargs_int(struct adapter *adap, int *dst, 713 const char *key, int default_value) 714 { 715 struct rte_pci_device *pdev = adap->pdev; 716 int ret, devarg_value = default_value; 717 718 *dst = default_value; 719 if (!pdev) 720 return; 721 722 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); 723 if (ret) 724 return; 725 726 *dst = devarg_value; 727 } 728 729 void cxgbe_process_devargs(struct adapter *adap) 730 { 731 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan, 732 CXGBE_DEVARG_CMN_KEEP_OVLAN, 0); 733 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency, 734 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, 0); 735 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up, 736 CXGBE_DEVARG_VF_FORCE_LINK_UP, 0); 737 } 738 739 static void configure_vlan_types(struct adapter *adapter) 740 { 741 int i; 742 743 for_each_port(adapter, i) { 744 /* OVLAN Type 0x88a8 */ 745 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0), 746 V_OVLAN_MASK(M_OVLAN_MASK) | 747 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 748 V_OVLAN_MASK(M_OVLAN_MASK) | 749 V_OVLAN_ETYPE(0x88a8)); 750 /* OVLAN Type 0x9100 */ 751 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1), 752 V_OVLAN_MASK(M_OVLAN_MASK) | 753 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 754 V_OVLAN_MASK(M_OVLAN_MASK) | 755 V_OVLAN_ETYPE(0x9100)); 756 757 /* IVLAN 0X8100 */ 758 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), 759 V_IVLAN_ETYPE(M_IVLAN_ETYPE), 760 V_IVLAN_ETYPE(0x8100)); 761 762 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), 763 F_OVLAN_EN0 | F_OVLAN_EN1 | 764 F_IVLAN_EN, 765 F_OVLAN_EN0 | F_OVLAN_EN1 | 766 F_IVLAN_EN); 767 } 768 769 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1), 770 V_RM_OVLAN(!adapter->devargs.keep_ovlan)); 771 } 772 773 static void configure_pcie_ext_tag(struct adapter *adapter) 774 { 775 u16 v; 776 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 777 778 if (!pos) 779 return; 780 781 if (pos > 0) { 782 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v); 783 v |= PCI_EXP_DEVCTL_EXT_TAG; 784 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v); 785 if (is_t6(adapter->params.chip)) { 786 t4_set_reg_field(adapter, A_PCIE_CFG2, 787 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG), 788 V_T6_TOTMAXTAG(7)); 789 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 790 V_T6_MINTAG(M_T6_MINTAG), 791 V_T6_MINTAG(8)); 792 } else { 793 t4_set_reg_field(adapter, A_PCIE_CFG2, 794 V_TOTMAXTAG(M_TOTMAXTAG), 795 V_TOTMAXTAG(3)); 796 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 797 V_MINTAG(M_MINTAG), 798 V_MINTAG(8)); 799 } 800 } 801 } 802 803 /* Figure out how many Queue Sets we can support */ 804 void cxgbe_configure_max_ethqsets(struct adapter *adapter) 805 { 806 unsigned int ethqsets; 807 808 /* 809 * We need to reserve an Ingress Queue for the Asynchronous Firmware 810 * Event Queue. 811 * 812 * For each Queue Set, we'll need the ability to allocate two Egress 813 * Contexts -- one for the Ingress Queue Free List and one for the TX 814 * Ethernet Queue. 815 */ 816 if (is_pf4(adapter)) { 817 struct pf_resources *pfres = &adapter->params.pfres; 818 819 ethqsets = pfres->niqflint - 1; 820 if (pfres->neq < ethqsets * 2) 821 ethqsets = pfres->neq / 2; 822 } else { 823 struct vf_resources *vfres = &adapter->params.vfres; 824 825 ethqsets = vfres->niqflint - 1; 826 if (vfres->nethctrl != ethqsets) 827 ethqsets = min(vfres->nethctrl, ethqsets); 828 if (vfres->neq < ethqsets * 2) 829 ethqsets = vfres->neq / 2; 830 } 831 832 if (ethqsets > MAX_ETH_QSETS) 833 ethqsets = MAX_ETH_QSETS; 834 adapter->sge.max_ethqsets = ethqsets; 835 } 836 837 /* 838 * Tweak configuration based on system architecture, etc. Most of these have 839 * defaults assigned to them by Firmware Configuration Files (if we're using 840 * them) but need to be explicitly set if we're using hard-coded 841 * initialization. So these are essentially common tweaks/settings for 842 * Configuration Files and hard-coded initialization ... 843 */ 844 static int adap_init0_tweaks(struct adapter *adapter) 845 { 846 u8 rx_dma_offset; 847 848 /* 849 * Fix up various Host-Dependent Parameters like Page Size, Cache 850 * Line Size, etc. The firmware default is for a 4KB Page Size and 851 * 64B Cache Line Size ... 852 */ 853 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 854 T5_LAST_REV); 855 856 /* 857 * Keep the chip default offset to deliver Ingress packets into our 858 * DMA buffers to zero 859 */ 860 rx_dma_offset = 0; 861 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 862 V_PKTSHIFT(rx_dma_offset)); 863 864 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 865 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 866 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 867 868 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD, 869 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U)); 870 871 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 872 V_IDMAARBROUNDROBIN(1U)); 873 874 /* 875 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 876 * adds the pseudo header itself. 877 */ 878 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 879 F_CSUM_HAS_PSEUDO_HDR, 0); 880 881 return 0; 882 } 883 884 /* 885 * Attempt to initialize the adapter via a Firmware Configuration File. 886 */ 887 static int adap_init0_config(struct adapter *adapter, int reset) 888 { 889 struct fw_caps_config_cmd caps_cmd; 890 unsigned long mtype = 0, maddr = 0; 891 u32 finiver, finicsum, cfcsum; 892 int ret; 893 int config_issued = 0; 894 int cfg_addr; 895 char config_name[20]; 896 897 /* 898 * Reset device if necessary. 899 */ 900 if (reset) { 901 ret = t4_fw_reset(adapter, adapter->mbox, 902 F_PIORSTMODE | F_PIORST); 903 if (ret < 0) { 904 dev_warn(adapter, "Firmware reset failed, error %d\n", 905 -ret); 906 goto bye; 907 } 908 } 909 910 cfg_addr = t4_flash_cfg_addr(adapter); 911 if (cfg_addr < 0) { 912 ret = cfg_addr; 913 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 914 -ret); 915 goto bye; 916 } 917 918 strcpy(config_name, "On Flash"); 919 mtype = FW_MEMTYPE_CF_FLASH; 920 maddr = cfg_addr; 921 922 /* 923 * Issue a Capability Configuration command to the firmware to get it 924 * to parse the Configuration File. We don't use t4_fw_config_file() 925 * because we want the ability to modify various features after we've 926 * processed the configuration file ... 927 */ 928 memset(&caps_cmd, 0, sizeof(caps_cmd)); 929 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 930 F_FW_CMD_REQUEST | F_FW_CMD_READ); 931 caps_cmd.cfvalid_to_len16 = 932 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 933 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 934 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 935 FW_LEN16(caps_cmd)); 936 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 937 &caps_cmd); 938 /* 939 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 940 * Configuration File in FLASH), our last gasp effort is to use the 941 * Firmware Configuration File which is embedded in the firmware. A 942 * very few early versions of the firmware didn't have one embedded 943 * but we can ignore those. 944 */ 945 if (ret == -ENOENT) { 946 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 947 __func__); 948 949 memset(&caps_cmd, 0, sizeof(caps_cmd)); 950 caps_cmd.op_to_write = 951 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 952 F_FW_CMD_REQUEST | F_FW_CMD_READ); 953 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 954 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 955 sizeof(caps_cmd), &caps_cmd); 956 strcpy(config_name, "Firmware Default"); 957 } 958 959 config_issued = 1; 960 if (ret < 0) 961 goto bye; 962 963 finiver = be32_to_cpu(caps_cmd.finiver); 964 finicsum = be32_to_cpu(caps_cmd.finicsum); 965 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 966 if (finicsum != cfcsum) 967 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 968 finicsum, cfcsum); 969 970 /* 971 * If we're a pure NIC driver then disable all offloading facilities. 972 * This will allow the firmware to optimize aspects of the hardware 973 * configuration which will result in improved performance. 974 */ 975 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD); 976 caps_cmd.toecaps = 0; 977 caps_cmd.iscsicaps = 0; 978 caps_cmd.rdmacaps = 0; 979 caps_cmd.fcoecaps = 0; 980 981 /* 982 * And now tell the firmware to use the configuration we just loaded. 983 */ 984 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 985 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 986 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 987 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 988 NULL); 989 if (ret < 0) { 990 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 991 -ret); 992 goto bye; 993 } 994 995 /* 996 * Tweak configuration based on system architecture, etc. 997 */ 998 ret = adap_init0_tweaks(adapter); 999 if (ret < 0) { 1000 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 1001 goto bye; 1002 } 1003 1004 /* 1005 * And finally tell the firmware to initialize itself using the 1006 * parameters from the Configuration File. 1007 */ 1008 ret = t4_fw_initialize(adapter, adapter->mbox); 1009 if (ret < 0) { 1010 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 1011 -ret); 1012 goto bye; 1013 } 1014 1015 /* 1016 * Return successfully and note that we're operating with parameters 1017 * not supplied by the driver, rather than from hard-wired 1018 * initialization constants buried in the driver. 1019 */ 1020 dev_info(adapter, 1021 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 1022 config_name, finiver, cfcsum); 1023 1024 return 0; 1025 1026 /* 1027 * Something bad happened. Return the error ... (If the "error" 1028 * is that there's no Configuration File on the adapter we don't 1029 * want to issue a warning since this is fairly common.) 1030 */ 1031 bye: 1032 if (config_issued && ret != -ENOENT) 1033 dev_warn(adapter, "\"%s\" configuration file error %d\n", 1034 config_name, -ret); 1035 1036 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 1037 return ret; 1038 } 1039 1040 static int adap_init0(struct adapter *adap) 1041 { 1042 struct fw_caps_config_cmd caps_cmd; 1043 int ret = 0; 1044 u32 v, port_vec; 1045 enum dev_state state; 1046 u32 params[7], val[7]; 1047 int reset = 1; 1048 int mbox = adap->mbox; 1049 1050 /* 1051 * Contact FW, advertising Master capability. 1052 */ 1053 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 1054 if (ret < 0) { 1055 dev_err(adap, "%s: could not connect to FW, error %d\n", 1056 __func__, -ret); 1057 goto bye; 1058 } 1059 1060 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 1061 adap->mbox, ret); 1062 1063 if (ret == mbox) 1064 adap->flags |= MASTER_PF; 1065 1066 if (state == DEV_STATE_INIT) { 1067 /* 1068 * Force halt and reset FW because a previous instance may have 1069 * exited abnormally without properly shutting down 1070 */ 1071 ret = t4_fw_halt(adap, adap->mbox, reset); 1072 if (ret < 0) { 1073 dev_err(adap, "Failed to halt. Exit.\n"); 1074 goto bye; 1075 } 1076 1077 ret = t4_fw_restart(adap, adap->mbox, reset); 1078 if (ret < 0) { 1079 dev_err(adap, "Failed to restart. Exit.\n"); 1080 goto bye; 1081 } 1082 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 1083 } 1084 1085 t4_get_version_info(adap); 1086 1087 ret = t4_get_core_clock(adap, &adap->params.vpd); 1088 if (ret < 0) { 1089 dev_err(adap, "%s: could not get core clock, error %d\n", 1090 __func__, -ret); 1091 goto bye; 1092 } 1093 1094 /* 1095 * If the firmware is initialized already (and we're not forcing a 1096 * master initialization), note that we're living with existing 1097 * adapter parameters. Otherwise, it's time to try initializing the 1098 * adapter ... 1099 */ 1100 if (state == DEV_STATE_INIT) { 1101 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 1102 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 1103 } else { 1104 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 1105 1106 ret = adap_init0_config(adap, reset); 1107 if (ret == -ENOENT) { 1108 dev_err(adap, 1109 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 1110 goto bye; 1111 } 1112 } 1113 if (ret < 0) { 1114 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 1115 goto bye; 1116 } 1117 1118 /* Now that we've successfully configured and initialized the adapter 1119 * (or found it already initialized), we can ask the Firmware what 1120 * resources it has provisioned for us. 1121 */ 1122 ret = t4_get_pfres(adap); 1123 if (ret) { 1124 dev_err(adap->pdev_dev, 1125 "Unable to retrieve resource provisioning info\n"); 1126 goto bye; 1127 } 1128 1129 /* Find out what ports are available to us. */ 1130 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1131 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 1132 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 1133 if (ret < 0) { 1134 dev_err(adap, "%s: failure in t4_query_params; error = %d\n", 1135 __func__, ret); 1136 goto bye; 1137 } 1138 1139 adap->params.nports = hweight32(port_vec); 1140 adap->params.portvec = port_vec; 1141 1142 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 1143 adap->params.nports); 1144 1145 /* 1146 * Give the SGE code a chance to pull in anything that it needs ... 1147 * Note that this must be called after we retrieve our VPD parameters 1148 * in order to know how to convert core ticks to seconds, etc. 1149 */ 1150 ret = t4_sge_init(adap); 1151 if (ret < 0) { 1152 dev_err(adap, "t4_sge_init failed with error %d\n", 1153 -ret); 1154 goto bye; 1155 } 1156 1157 /* 1158 * Grab some of our basic fundamental operating parameters. 1159 */ 1160 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START); 1161 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END); 1162 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START); 1163 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END); 1164 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); 1165 if (ret < 0) 1166 goto bye; 1167 adap->l2t_start = val[0]; 1168 adap->l2t_end = val[1]; 1169 adap->tids.ftid_base = val[2]; 1170 adap->tids.nftids = val[3] - val[2] + 1; 1171 1172 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START); 1173 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END); 1174 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 1175 if (ret < 0) 1176 goto bye; 1177 adap->clipt_start = val[0]; 1178 adap->clipt_end = val[1]; 1179 1180 /* 1181 * Get device capabilities so we can determine what resources we need 1182 * to manage. 1183 */ 1184 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1185 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1186 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1187 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1188 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1189 &caps_cmd); 1190 if (ret < 0) 1191 goto bye; 1192 1193 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) && 1194 is_t6(adap->params.chip)) { 1195 if (cxgbe_init_hash_filter(adap) < 0) 1196 goto bye; 1197 } 1198 1199 /* See if FW supports FW_FILTER2 work request */ 1200 if (is_t4(adap->params.chip)) { 1201 adap->params.filter2_wr_support = 0; 1202 } else { 1203 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR); 1204 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1205 1, params, val); 1206 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 1207 } 1208 1209 /* query tid-related parameters */ 1210 params[0] = CXGBE_FW_PARAM_DEV(NTID); 1211 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 1212 params, val); 1213 if (ret < 0) 1214 goto bye; 1215 adap->tids.ntids = val[0]; 1216 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 1217 1218 /* If we're running on newer firmware, let it know that we're 1219 * prepared to deal with encapsulated CPL messages. Older 1220 * firmware won't understand this and we'll just get 1221 * unencapsulated messages ... 1222 */ 1223 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1224 val[0] = 1; 1225 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1226 1227 /* 1228 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 1229 * capability. Earlier versions of the firmware didn't have the 1230 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 1231 * permission to use ULPTX MEMWRITE DSGL. 1232 */ 1233 if (is_t4(adap->params.chip)) { 1234 adap->params.ulptx_memwrite_dsgl = false; 1235 } else { 1236 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 1237 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1238 1, params, val); 1239 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 1240 } 1241 1242 /* Query for max number of packets that can be coalesced for Tx */ 1243 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 1244 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1245 if (!ret && val[0] > 0) 1246 adap->params.max_tx_coalesce_num = val[0]; 1247 else 1248 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; 1249 1250 /* 1251 * The MTU/MSS Table is initialized by now, so load their values. If 1252 * we're initializing the adapter, then we'll make any modifications 1253 * we want to the MTU/MSS Table and also initialize the congestion 1254 * parameters. 1255 */ 1256 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 1257 if (state != DEV_STATE_INIT) { 1258 int i; 1259 1260 /* 1261 * The default MTU Table contains values 1492 and 1500. 1262 * However, for TCP, it's better to have two values which are 1263 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 1264 * This allows us to have a TCP Data Payload which is a 1265 * multiple of 8 regardless of what combination of TCP Options 1266 * are in use (always a multiple of 4 bytes) which is 1267 * important for performance reasons. For instance, if no 1268 * options are in use, then we have a 20-byte IP header and a 1269 * 20-byte TCP header. In this case, a 1500-byte MSS would 1270 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 1271 * which is not a multiple of 8. So using an MSS of 1488 in 1272 * this case results in a TCP Data Payload of 1448 bytes which 1273 * is a multiple of 8. On the other hand, if 12-byte TCP Time 1274 * Stamps have been negotiated, then an MTU of 1500 bytes 1275 * results in a TCP Data Payload of 1448 bytes which, as 1276 * above, is a multiple of 8 bytes ... 1277 */ 1278 for (i = 0; i < NMTUS; i++) 1279 if (adap->params.mtus[i] == 1492) { 1280 adap->params.mtus[i] = 1488; 1281 break; 1282 } 1283 1284 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 1285 adap->params.b_wnd); 1286 } 1287 t4_init_sge_params(adap); 1288 t4_init_tp_params(adap); 1289 configure_pcie_ext_tag(adap); 1290 configure_vlan_types(adap); 1291 cxgbe_configure_max_ethqsets(adap); 1292 1293 adap->params.drv_memwin = MEMWIN_NIC; 1294 adap->flags |= FW_OK; 1295 dev_debug(adap, "%s: returning zero..\n", __func__); 1296 return 0; 1297 1298 /* 1299 * Something bad happened. If a command timed out or failed with EIO 1300 * FW does not operate within its spec or something catastrophic 1301 * happened to HW/FW, stop issuing commands. 1302 */ 1303 bye: 1304 if (ret != -ETIMEDOUT && ret != -EIO) 1305 t4_fw_bye(adap, adap->mbox); 1306 return ret; 1307 } 1308 1309 /** 1310 * t4_os_portmod_changed - handle port module changes 1311 * @adap: the adapter associated with the module change 1312 * @port_id: the port index whose module status has changed 1313 * 1314 * This is the OS-dependent handler for port module changes. It is 1315 * invoked when a port module is removed or inserted for any OS-specific 1316 * processing. 1317 */ 1318 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 1319 { 1320 static const char * const mod_str[] = { 1321 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 1322 }; 1323 1324 const struct port_info *pi = adap2pinfo(adap, port_id); 1325 1326 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 1327 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 1328 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 1329 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 1330 mod_str[pi->mod_type]); 1331 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 1332 dev_info(adap, "Port%d: unsupported port module inserted\n", 1333 pi->port_id); 1334 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 1335 dev_info(adap, "Port%d: unknown port module inserted\n", 1336 pi->port_id); 1337 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 1338 dev_info(adap, "Port%d: transceiver module error\n", 1339 pi->port_id); 1340 else 1341 dev_info(adap, "Port%d: unknown module type %d inserted\n", 1342 pi->port_id, pi->mod_type); 1343 } 1344 1345 bool cxgbe_force_linkup(struct adapter *adap) 1346 { 1347 if (is_pf4(adap)) 1348 return false; /* force_linkup not required for pf driver */ 1349 1350 return adap->devargs.force_link_up; 1351 } 1352 1353 /** 1354 * link_start - enable a port 1355 * @dev: the port to enable 1356 * 1357 * Performs the MAC and PHY actions needed to enable a port. 1358 */ 1359 int cxgbe_link_start(struct port_info *pi) 1360 { 1361 struct adapter *adapter = pi->adapter; 1362 u64 conf_offloads; 1363 unsigned int mtu; 1364 int ret; 1365 1366 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1367 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 1368 1369 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads; 1370 1371 /* 1372 * We do not set address filters and promiscuity here, the stack does 1373 * that step explicitly. 1374 */ 1375 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1, 1376 !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP), 1377 true); 1378 if (ret == 0) { 1379 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, 1380 (u8 *)&pi->eth_dev->data->mac_addrs[0]); 1381 if (ret >= 0) { 1382 pi->xact_addr_filt = ret; 1383 ret = 0; 1384 } 1385 } 1386 if (ret == 0 && is_pf4(adapter)) 1387 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 1388 &pi->link_cfg); 1389 if (ret == 0) { 1390 /* 1391 * Enabling a Virtual Interface can result in an interrupt 1392 * during the processing of the VI Enable command and, in some 1393 * paths, result in an attempt to issue another command in the 1394 * interrupt context. Thus, we disable interrupts during the 1395 * course of the VI Enable command ... 1396 */ 1397 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 1398 true, true, false); 1399 } 1400 1401 if (ret == 0 && cxgbe_force_linkup(adapter)) 1402 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP; 1403 return ret; 1404 } 1405 1406 /** 1407 * cxgbe_write_rss_conf - flash the RSS configuration for a given port 1408 * @pi: the port 1409 * @rss_hf: Hash configuration to apply 1410 */ 1411 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) 1412 { 1413 struct adapter *adapter = pi->adapter; 1414 const struct sge_eth_rxq *rxq; 1415 u64 flags = 0; 1416 u16 rss; 1417 int err; 1418 1419 /* Should never be called before setting up sge eth rx queues */ 1420 if (!(adapter->flags & FULL_INIT_DONE)) { 1421 dev_err(adap, "%s No RXQs available on port %d\n", 1422 __func__, pi->port_id); 1423 return -EINVAL; 1424 } 1425 1426 /* Don't allow unsupported hash functions */ 1427 if (rss_hf & ~CXGBE_RSS_HF_ALL) 1428 return -EINVAL; 1429 1430 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) 1431 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 1432 1433 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 1434 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 1435 1436 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 1437 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 1438 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1439 1440 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK) 1441 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 1442 1443 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK) 1444 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1445 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 1446 1447 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK) 1448 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1449 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 1450 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1451 1452 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1453 rss = rxq[0].rspq.abs_id; 1454 1455 /* If Tunnel All Lookup isn't specified in the global RSS 1456 * Configuration, then we need to specify a default Ingress 1457 * Queue for any ingress packets which aren't hashed. We'll 1458 * use our first ingress queue ... 1459 */ 1460 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 1461 flags, rss); 1462 return err; 1463 } 1464 1465 /** 1466 * cxgbe_write_rss - write the RSS table for a given port 1467 * @pi: the port 1468 * @queues: array of queue indices for RSS 1469 * 1470 * Sets up the portion of the HW RSS table for the port's VI to distribute 1471 * packets to the Rx queues in @queues. 1472 */ 1473 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues) 1474 { 1475 u16 *rss; 1476 int i, err; 1477 struct adapter *adapter = pi->adapter; 1478 const struct sge_eth_rxq *rxq; 1479 1480 /* Should never be called before setting up sge eth rx queues */ 1481 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 1482 1483 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1484 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 1485 if (!rss) 1486 return -ENOMEM; 1487 1488 /* map the queue indices to queue ids */ 1489 for (i = 0; i < pi->rss_size; i++, queues++) 1490 rss[i] = rxq[*queues].rspq.abs_id; 1491 1492 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 1493 pi->rss_size, rss, pi->rss_size); 1494 rte_free(rss); 1495 return err; 1496 } 1497 1498 /** 1499 * setup_rss - configure RSS 1500 * @adapter: the adapter 1501 * 1502 * Sets up RSS to distribute packets to multiple receive queues. We 1503 * configure the RSS CPU lookup table to distribute to the number of HW 1504 * receive queues, and the response queue lookup table to narrow that 1505 * down to the response queues actually configured for each port. 1506 * We always configure the RSS mapping for all ports since the mapping 1507 * table has plenty of entries. 1508 */ 1509 int cxgbe_setup_rss(struct port_info *pi) 1510 { 1511 int j, err; 1512 struct adapter *adapter = pi->adapter; 1513 1514 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 1515 __func__, pi->rss_size, pi->n_rx_qsets); 1516 1517 if (!(pi->flags & PORT_RSS_DONE)) { 1518 if (adapter->flags & FULL_INIT_DONE) { 1519 /* Fill default values with equal distribution */ 1520 for (j = 0; j < pi->rss_size; j++) 1521 pi->rss[j] = j % pi->n_rx_qsets; 1522 1523 err = cxgbe_write_rss(pi, pi->rss); 1524 if (err) 1525 return err; 1526 1527 err = cxgbe_write_rss_conf(pi, pi->rss_hf); 1528 if (err) 1529 return err; 1530 pi->flags |= PORT_RSS_DONE; 1531 } 1532 } 1533 return 0; 1534 } 1535 1536 /* 1537 * Enable NAPI scheduling and interrupt generation for all Rx queues. 1538 */ 1539 static void enable_rx(struct adapter *adap, struct sge_rspq *q) 1540 { 1541 /* 0-increment GTS to start the timer and enable interrupts */ 1542 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) : 1543 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS, 1544 V_SEINTARM(q->intr_params) | 1545 V_INGRESSQID(q->cntxt_id)); 1546 } 1547 1548 void cxgbe_enable_rx_queues(struct port_info *pi) 1549 { 1550 struct adapter *adap = pi->adapter; 1551 struct sge *s = &adap->sge; 1552 unsigned int i; 1553 1554 for (i = 0; i < pi->n_rx_qsets; i++) 1555 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq); 1556 } 1557 1558 /** 1559 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps. 1560 * @port_type: Firmware Port Type 1561 * @fw_caps: Firmware Port Capabilities 1562 * @speed_caps: Device Info Speed Capabilities 1563 * 1564 * Translate a Firmware Port Capabilities specification to Device Info 1565 * Speed Capabilities. 1566 */ 1567 static void fw_caps_to_speed_caps(enum fw_port_type port_type, 1568 unsigned int fw_caps, 1569 u32 *speed_caps) 1570 { 1571 #define SET_SPEED(__speed_name) \ 1572 do { \ 1573 *speed_caps |= ETH_LINK_ ## __speed_name; \ 1574 } while (0) 1575 1576 #define FW_CAPS_TO_SPEED(__fw_name) \ 1577 do { \ 1578 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \ 1579 SET_SPEED(__fw_name); \ 1580 } while (0) 1581 1582 switch (port_type) { 1583 case FW_PORT_TYPE_BT_SGMII: 1584 case FW_PORT_TYPE_BT_XFI: 1585 case FW_PORT_TYPE_BT_XAUI: 1586 FW_CAPS_TO_SPEED(SPEED_100M); 1587 FW_CAPS_TO_SPEED(SPEED_1G); 1588 FW_CAPS_TO_SPEED(SPEED_10G); 1589 break; 1590 1591 case FW_PORT_TYPE_KX4: 1592 case FW_PORT_TYPE_KX: 1593 case FW_PORT_TYPE_FIBER_XFI: 1594 case FW_PORT_TYPE_FIBER_XAUI: 1595 case FW_PORT_TYPE_SFP: 1596 case FW_PORT_TYPE_QSFP_10G: 1597 case FW_PORT_TYPE_QSA: 1598 FW_CAPS_TO_SPEED(SPEED_1G); 1599 FW_CAPS_TO_SPEED(SPEED_10G); 1600 break; 1601 1602 case FW_PORT_TYPE_KR: 1603 SET_SPEED(SPEED_10G); 1604 break; 1605 1606 case FW_PORT_TYPE_BP_AP: 1607 case FW_PORT_TYPE_BP4_AP: 1608 SET_SPEED(SPEED_1G); 1609 SET_SPEED(SPEED_10G); 1610 break; 1611 1612 case FW_PORT_TYPE_BP40_BA: 1613 case FW_PORT_TYPE_QSFP: 1614 SET_SPEED(SPEED_40G); 1615 break; 1616 1617 case FW_PORT_TYPE_CR_QSFP: 1618 case FW_PORT_TYPE_SFP28: 1619 case FW_PORT_TYPE_KR_SFP28: 1620 FW_CAPS_TO_SPEED(SPEED_1G); 1621 FW_CAPS_TO_SPEED(SPEED_10G); 1622 FW_CAPS_TO_SPEED(SPEED_25G); 1623 break; 1624 1625 case FW_PORT_TYPE_CR2_QSFP: 1626 SET_SPEED(SPEED_50G); 1627 break; 1628 1629 case FW_PORT_TYPE_KR4_100G: 1630 case FW_PORT_TYPE_CR4_QSFP: 1631 FW_CAPS_TO_SPEED(SPEED_25G); 1632 FW_CAPS_TO_SPEED(SPEED_40G); 1633 FW_CAPS_TO_SPEED(SPEED_50G); 1634 FW_CAPS_TO_SPEED(SPEED_100G); 1635 break; 1636 1637 default: 1638 break; 1639 } 1640 1641 #undef FW_CAPS_TO_SPEED 1642 #undef SET_SPEED 1643 } 1644 1645 /** 1646 * cxgbe_get_speed_caps - Fetch supported speed capabilities 1647 * @pi: Underlying port's info 1648 * @speed_caps: Device Info speed capabilities 1649 * 1650 * Fetch supported speed capabilities of the underlying port. 1651 */ 1652 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) 1653 { 1654 *speed_caps = 0; 1655 1656 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps, 1657 speed_caps); 1658 1659 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) 1660 *speed_caps |= ETH_LINK_SPEED_FIXED; 1661 } 1662 1663 /** 1664 * cxgbe_set_link_status - Set device link up or down. 1665 * @pi: Underlying port's info 1666 * @status: 0 - down, 1 - up 1667 * 1668 * Set the device link up or down. 1669 */ 1670 int cxgbe_set_link_status(struct port_info *pi, bool status) 1671 { 1672 struct adapter *adapter = pi->adapter; 1673 int err = 0; 1674 1675 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status); 1676 if (err) { 1677 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1678 return err; 1679 } 1680 1681 if (!status) 1682 t4_reset_link_config(adapter, pi->pidx); 1683 1684 return 0; 1685 } 1686 1687 /** 1688 * cxgb_up - enable the adapter 1689 * @adap: adapter being enabled 1690 * 1691 * Called when the first port is enabled, this function performs the 1692 * actions necessary to make an adapter operational, such as completing 1693 * the initialization of HW modules, and enabling interrupts. 1694 */ 1695 int cxgbe_up(struct adapter *adap) 1696 { 1697 enable_rx(adap, &adap->sge.fw_evtq); 1698 t4_sge_tx_monitor_start(adap); 1699 if (is_pf4(adap)) 1700 t4_intr_enable(adap); 1701 adap->flags |= FULL_INIT_DONE; 1702 1703 /* TODO: deadman watchdog ?? */ 1704 return 0; 1705 } 1706 1707 /* 1708 * Close the port 1709 */ 1710 int cxgbe_down(struct port_info *pi) 1711 { 1712 return cxgbe_set_link_status(pi, false); 1713 } 1714 1715 /* 1716 * Release resources when all the ports have been stopped. 1717 */ 1718 void cxgbe_close(struct adapter *adapter) 1719 { 1720 struct port_info *pi; 1721 int i; 1722 1723 if (adapter->flags & FULL_INIT_DONE) { 1724 tid_free(&adapter->tids); 1725 t4_cleanup_mpstcam(adapter); 1726 t4_cleanup_clip_tbl(adapter); 1727 t4_cleanup_l2t(adapter); 1728 if (is_pf4(adapter)) 1729 t4_intr_disable(adapter); 1730 t4_sge_tx_monitor_stop(adapter); 1731 t4_free_sge_resources(adapter); 1732 for_each_port(adapter, i) { 1733 pi = adap2pinfo(adapter, i); 1734 if (pi->viid != 0) 1735 t4_free_vi(adapter, adapter->mbox, 1736 adapter->pf, 0, pi->viid); 1737 rte_eth_dev_release_port(pi->eth_dev); 1738 } 1739 adapter->flags &= ~FULL_INIT_DONE; 1740 } 1741 1742 if (is_pf4(adapter) && (adapter->flags & FW_OK)) 1743 t4_fw_bye(adapter, adapter->mbox); 1744 } 1745 1746 int cxgbe_probe(struct adapter *adapter) 1747 { 1748 struct port_info *pi; 1749 int chip; 1750 int func, i; 1751 int err = 0; 1752 u32 whoami; 1753 1754 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 1755 chip = t4_get_chip_type(adapter, 1756 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id)); 1757 if (chip < 0) 1758 return chip; 1759 1760 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 1761 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami); 1762 1763 adapter->mbox = func; 1764 adapter->pf = func; 1765 1766 t4_os_lock_init(&adapter->mbox_lock); 1767 TAILQ_INIT(&adapter->mbox_list); 1768 t4_os_lock_init(&adapter->win0_lock); 1769 1770 err = t4_prep_adapter(adapter); 1771 if (err) 1772 return err; 1773 1774 setup_memwin(adapter); 1775 err = adap_init0(adapter); 1776 if (err) { 1777 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 1778 __func__, err); 1779 goto out_free; 1780 } 1781 1782 if (!is_t4(adapter->params.chip)) { 1783 /* 1784 * The userspace doorbell BAR is split evenly into doorbell 1785 * regions, each associated with an egress queue. If this 1786 * per-queue region is large enough (at least UDBS_SEG_SIZE) 1787 * then it can be used to submit a tx work request with an 1788 * implied doorbell. Enable write combining on the BAR if 1789 * there is room for such work requests. 1790 */ 1791 int s_qpp, qpp, num_seg; 1792 1793 s_qpp = (S_QUEUESPERPAGEPF0 + 1794 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 1795 adapter->pf); 1796 qpp = 1 << ((t4_read_reg(adapter, 1797 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 1798 & M_QUEUESPERPAGEPF0); 1799 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 1800 if (qpp > num_seg) 1801 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 1802 1803 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 1804 if (!adapter->bar2) { 1805 dev_err(adapter, "cannot map device bar2 region\n"); 1806 err = -ENOMEM; 1807 goto out_free; 1808 } 1809 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 1810 V_STATMODE(0)); 1811 } 1812 1813 for_each_port(adapter, i) { 1814 const unsigned int numa_node = rte_socket_id(); 1815 char name[RTE_ETH_NAME_MAX_LEN]; 1816 struct rte_eth_dev *eth_dev; 1817 1818 snprintf(name, sizeof(name), "%s_%d", 1819 adapter->pdev->device.name, i); 1820 1821 if (i == 0) { 1822 /* First port is already allocated by DPDK */ 1823 eth_dev = adapter->eth_dev; 1824 goto allocate_mac; 1825 } 1826 1827 /* 1828 * now do all data allocation - for eth_dev structure, 1829 * and internal (private) data for the remaining ports 1830 */ 1831 1832 /* reserve an ethdev entry */ 1833 eth_dev = rte_eth_dev_allocate(name); 1834 if (!eth_dev) 1835 goto out_free; 1836 1837 eth_dev->data->dev_private = 1838 rte_zmalloc_socket(name, sizeof(struct port_info), 1839 RTE_CACHE_LINE_SIZE, numa_node); 1840 if (!eth_dev->data->dev_private) 1841 goto out_free; 1842 1843 allocate_mac: 1844 pi = eth_dev->data->dev_private; 1845 adapter->port[i] = pi; 1846 pi->eth_dev = eth_dev; 1847 pi->adapter = adapter; 1848 pi->xact_addr_filt = -1; 1849 pi->port_id = i; 1850 pi->pidx = i; 1851 1852 pi->eth_dev->device = &adapter->pdev->device; 1853 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 1854 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 1855 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 1856 1857 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 1858 1859 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 1860 RTE_ETHER_ADDR_LEN, 0); 1861 if (!pi->eth_dev->data->mac_addrs) { 1862 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 1863 __func__); 1864 err = -1; 1865 goto out_free; 1866 } 1867 1868 if (i > 0) { 1869 /* First port will be notified by upper layer */ 1870 rte_eth_dev_probing_finish(eth_dev); 1871 } 1872 } 1873 1874 if (adapter->flags & FW_OK) { 1875 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 1876 if (err) { 1877 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 1878 __func__, err); 1879 goto out_free; 1880 } 1881 } 1882 1883 cxgbe_cfg_queues(adapter->eth_dev); 1884 1885 cxgbe_print_adapter_info(adapter); 1886 cxgbe_print_port_info(adapter); 1887 1888 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 1889 adapter->clipt_end); 1890 if (!adapter->clipt) { 1891 /* We tolerate a lack of clip_table, giving up some 1892 * functionality 1893 */ 1894 dev_warn(adapter, "could not allocate CLIP. Continuing\n"); 1895 } 1896 1897 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 1898 if (!adapter->l2t) { 1899 /* We tolerate a lack of L2T, giving up some functionality */ 1900 dev_warn(adapter, "could not allocate L2T. Continuing\n"); 1901 } 1902 1903 if (tid_init(&adapter->tids) < 0) { 1904 /* Disable filtering support */ 1905 dev_warn(adapter, "could not allocate TID table, " 1906 "filter support disabled. Continuing\n"); 1907 } 1908 1909 t4_os_lock_init(&adapter->flow_lock); 1910 1911 adapter->mpstcam = t4_init_mpstcam(adapter); 1912 if (!adapter->mpstcam) 1913 dev_warn(adapter, "could not allocate mps tcam table." 1914 " Continuing\n"); 1915 1916 if (is_hashfilter(adapter)) { 1917 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) { 1918 u32 hash_base, hash_reg; 1919 1920 hash_reg = A_LE_DB_TID_HASHBASE; 1921 hash_base = t4_read_reg(adapter, hash_reg); 1922 adapter->tids.hash_base = hash_base / 4; 1923 } 1924 } else { 1925 /* Disable hash filtering support */ 1926 dev_warn(adapter, 1927 "Maskless filter support disabled. Continuing\n"); 1928 } 1929 1930 err = cxgbe_init_rss(adapter); 1931 if (err) 1932 goto out_free; 1933 1934 return 0; 1935 1936 out_free: 1937 for_each_port(adapter, i) { 1938 pi = adap2pinfo(adapter, i); 1939 if (pi->viid != 0) 1940 t4_free_vi(adapter, adapter->mbox, adapter->pf, 1941 0, pi->viid); 1942 rte_eth_dev_release_port(pi->eth_dev); 1943 } 1944 1945 if (adapter->flags & FW_OK) 1946 t4_fw_bye(adapter, adapter->mbox); 1947 return -err; 1948 } 1949