1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_tailq.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <ethdev_driver.h> 30 #include <ethdev_pci.h> 31 #include <rte_random.h> 32 #include <rte_dev.h> 33 #include <rte_kvargs.h> 34 35 #include "base/common.h" 36 #include "base/t4_regs.h" 37 #include "base/t4_msg.h" 38 #include "cxgbe.h" 39 #include "cxgbe_pfvf.h" 40 #include "clip_tbl.h" 41 #include "l2t.h" 42 #include "smt.h" 43 #include "mps_tcam.h" 44 45 static const u16 cxgbe_filter_mode_features[] = { 46 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | 47 F_PROTOCOL | F_PORT), 48 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | 49 F_PROTOCOL | F_FCOE), 50 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | 51 F_PORT), 52 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | 53 F_FCOE), 54 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PORT | 55 F_FCOE), 56 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_TOS | 57 F_PORT | F_FCOE), 58 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | 59 F_FCOE), 60 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | 61 F_FCOE), 62 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | 63 F_FCOE), 64 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | 65 F_FCOE), 66 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VLAN | F_PORT | 67 F_FCOE), 68 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VNIC_ID | F_PORT | 69 F_FCOE), 70 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_PROTOCOL | F_TOS | 71 F_PORT | F_FCOE), 72 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT), 73 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_FCOE), 74 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT), 75 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_FCOE), 76 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT), 77 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE), 78 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | 79 F_PORT), 80 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | 81 F_FCOE), 82 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VLAN | F_PORT | 83 F_FCOE), 84 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VNIC_ID | F_PORT | 85 F_FCOE), 86 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VLAN | F_PORT | F_FCOE), 87 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 88 (F_FRAGMENTATION | F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_FCOE), 89 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT | 90 F_FCOE), 91 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE), 92 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT | F_FCOE), 93 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT | 94 F_FCOE), 95 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VLAN | F_PORT | F_FCOE), 96 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 97 (F_FRAGMENTATION | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE), 98 (F_FRAGMENTATION | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE), 99 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE), 100 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VNIC_ID | F_FCOE), 101 (F_FRAGMENTATION | F_VLAN | F_VNIC_ID | F_PORT | F_FCOE), 102 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT | 103 F_FCOE), 104 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE), 105 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT), 106 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT), 107 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | F_PORT), 108 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT), 109 (F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE), 110 (F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE), 111 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT | F_FCOE), 112 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 113 (F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_PORT), 114 }; 115 116 /** 117 * Allocate a chunk of memory. The allocated memory is cleared. 118 */ 119 void *t4_alloc_mem(size_t size) 120 { 121 return rte_zmalloc(NULL, size, 0); 122 } 123 124 /** 125 * Free memory allocated through t4_alloc_mem(). 126 */ 127 void t4_free_mem(void *addr) 128 { 129 rte_free(addr); 130 } 131 132 /* 133 * Response queue handler for the FW event queue. 134 */ 135 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 136 __rte_unused const struct pkt_gl *gl) 137 { 138 u8 opcode = ((const struct rss_header *)rsp)->opcode; 139 140 rsp++; /* skip RSS header */ 141 142 /* 143 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 144 */ 145 if (unlikely(opcode == CPL_FW4_MSG && 146 ((const struct cpl_fw4_msg *)rsp)->type == 147 FW_TYPE_RSSCPL)) { 148 rsp++; 149 opcode = ((const struct rss_header *)rsp)->opcode; 150 rsp++; 151 if (opcode != CPL_SGE_EGR_UPDATE) { 152 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 153 opcode); 154 goto out; 155 } 156 } 157 158 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 159 /* do nothing */ 160 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 161 const struct cpl_fw6_msg *msg = (const void *)rsp; 162 163 t4_handle_fw_rpl(q->adapter, msg->data); 164 } else if (opcode == CPL_ABORT_RPL_RSS) { 165 const struct cpl_abort_rpl_rss *p = (const void *)rsp; 166 167 cxgbe_hash_del_filter_rpl(q->adapter, p); 168 } else if (opcode == CPL_SET_TCB_RPL) { 169 const struct cpl_set_tcb_rpl *p = (const void *)rsp; 170 171 cxgbe_filter_rpl(q->adapter, p); 172 } else if (opcode == CPL_ACT_OPEN_RPL) { 173 const struct cpl_act_open_rpl *p = (const void *)rsp; 174 175 cxgbe_hash_filter_rpl(q->adapter, p); 176 } else if (opcode == CPL_L2T_WRITE_RPL) { 177 const struct cpl_l2t_write_rpl *p = (const void *)rsp; 178 179 cxgbe_do_l2t_write_rpl(q->adapter, p); 180 } else if (opcode == CPL_SMT_WRITE_RPL) { 181 const struct cpl_smt_write_rpl *p = (const void *)rsp; 182 183 cxgbe_do_smt_write_rpl(q->adapter, p); 184 } else { 185 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 186 opcode); 187 } 188 out: 189 return 0; 190 } 191 192 /** 193 * Setup sge control queues to pass control information. 194 */ 195 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter) 196 { 197 struct sge *s = &adapter->sge; 198 int err = 0, i = 0; 199 200 for_each_port(adapter, i) { 201 struct port_info *pi = adap2pinfo(adapter, i); 202 char name[RTE_ETH_NAME_MAX_LEN]; 203 struct sge_ctrl_txq *q = &s->ctrlq[i]; 204 205 q->q.size = 1024; 206 err = t4_sge_alloc_ctrl_txq(adapter, q, 207 adapter->eth_dev, i, 208 s->fw_evtq.cntxt_id, 209 rte_socket_id()); 210 if (err) { 211 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d", 212 err); 213 goto out; 214 } 215 snprintf(name, sizeof(name), "%s_ctrl_pool_%d", 216 pi->eth_dev->device->driver->name, 217 pi->eth_dev->data->port_id); 218 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size, 219 RTE_CACHE_LINE_SIZE, 220 RTE_MBUF_PRIV_ALIGN, 221 RTE_MBUF_DEFAULT_BUF_SIZE, 222 SOCKET_ID_ANY); 223 if (!q->mb_pool) { 224 err = -rte_errno; 225 dev_err(adapter, 226 "Can't create ctrl pool for port %d. Err: %d\n", 227 pi->eth_dev->data->port_id, err); 228 goto out; 229 } 230 } 231 return 0; 232 out: 233 t4_free_sge_resources(adapter); 234 return err; 235 } 236 237 /** 238 * cxgbe_poll_for_completion: Poll rxq for completion 239 * @q: rxq to poll 240 * @ms: milliseconds to delay 241 * @cnt: number of times to poll 242 * @c: completion to check for 'done' status 243 * 244 * Polls the rxq for reples until completion is done or the count 245 * expires. 246 */ 247 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms, 248 unsigned int cnt, struct t4_completion *c) 249 { 250 unsigned int i; 251 unsigned int work_done, budget = 32; 252 253 if (!c) 254 return -EINVAL; 255 256 for (i = 0; i < cnt; i++) { 257 cxgbe_poll(q, NULL, budget, &work_done); 258 t4_os_lock(&c->lock); 259 if (c->done) { 260 t4_os_unlock(&c->lock); 261 return 0; 262 } 263 t4_os_unlock(&c->lock); 264 rte_delay_ms(ms); 265 } 266 return -ETIMEDOUT; 267 } 268 269 int cxgbe_setup_sge_fwevtq(struct adapter *adapter) 270 { 271 struct sge *s = &adapter->sge; 272 int err = 0; 273 int msi_idx = 0; 274 275 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 276 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 277 rte_socket_id()); 278 return err; 279 } 280 281 static int closest_timer(const struct sge *s, int time) 282 { 283 unsigned int i, match = 0; 284 int delta, min_delta = INT_MAX; 285 286 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 287 delta = time - s->timer_val[i]; 288 if (delta < 0) 289 delta = -delta; 290 if (delta < min_delta) { 291 min_delta = delta; 292 match = i; 293 } 294 } 295 return match; 296 } 297 298 static int closest_thres(const struct sge *s, int thres) 299 { 300 unsigned int i, match = 0; 301 int delta, min_delta = INT_MAX; 302 303 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 304 delta = thres - s->counter_val[i]; 305 if (delta < 0) 306 delta = -delta; 307 if (delta < min_delta) { 308 min_delta = delta; 309 match = i; 310 } 311 } 312 return match; 313 } 314 315 /** 316 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 317 * @q: the Rx queue 318 * @us: the hold-off time in us, or 0 to disable timer 319 * @cnt: the hold-off packet count, or 0 to disable counter 320 * 321 * Sets an Rx queue's interrupt hold-off time and packet count. At least 322 * one of the two needs to be enabled for the queue to generate interrupts. 323 */ 324 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 325 unsigned int cnt) 326 { 327 struct adapter *adap = q->adapter; 328 unsigned int timer_val; 329 330 if (cnt) { 331 int err; 332 u32 v, new_idx; 333 334 new_idx = closest_thres(&adap->sge, cnt); 335 if (q->desc && q->pktcnt_idx != new_idx) { 336 /* the queue has already been created, update it */ 337 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 338 V_FW_PARAMS_PARAM_X( 339 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 340 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 341 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 342 &v, &new_idx); 343 if (err) 344 return err; 345 } 346 q->pktcnt_idx = new_idx; 347 } 348 349 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 350 closest_timer(&adap->sge, us); 351 352 if ((us | cnt) == 0) 353 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 354 else 355 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 356 V_QINTR_CNT_EN(cnt > 0); 357 return 0; 358 } 359 360 /** 361 * Allocate an active-open TID and set it to the supplied value. 362 */ 363 int cxgbe_alloc_atid(struct tid_info *t, void *data) 364 { 365 int atid = -1; 366 367 t4_os_lock(&t->atid_lock); 368 if (t->afree) { 369 union aopen_entry *p = t->afree; 370 371 atid = p - t->atid_tab; 372 t->afree = p->next; 373 p->data = data; 374 t->atids_in_use++; 375 } 376 t4_os_unlock(&t->atid_lock); 377 return atid; 378 } 379 380 /** 381 * Release an active-open TID. 382 */ 383 void cxgbe_free_atid(struct tid_info *t, unsigned int atid) 384 { 385 union aopen_entry *p = &t->atid_tab[atid]; 386 387 t4_os_lock(&t->atid_lock); 388 p->next = t->afree; 389 t->afree = p; 390 t->atids_in_use--; 391 t4_os_unlock(&t->atid_lock); 392 } 393 394 /** 395 * Populate a TID_RELEASE WR. Caller must properly size the skb. 396 */ 397 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid) 398 { 399 struct cpl_tid_release *req; 400 401 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *); 402 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 403 } 404 405 /** 406 * Release a TID and inform HW. If we are unable to allocate the release 407 * message we defer to a work queue. 408 */ 409 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 410 unsigned short family) 411 { 412 struct rte_mbuf *mbuf; 413 struct adapter *adap = container_of(t, struct adapter, tids); 414 415 WARN_ON(tid >= t->ntids); 416 417 if (t->tid_tab[tid]) { 418 t->tid_tab[tid] = NULL; 419 __atomic_sub_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); 420 if (t->hash_base && tid >= t->hash_base) { 421 if (family == FILTER_TYPE_IPV4) 422 __atomic_sub_fetch(&t->hash_tids_in_use, 1, 423 __ATOMIC_RELAXED); 424 } else { 425 if (family == FILTER_TYPE_IPV4) 426 __atomic_sub_fetch(&t->tids_in_use, 1, 427 __ATOMIC_RELAXED); 428 } 429 } 430 431 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool); 432 if (mbuf) { 433 mbuf->data_len = sizeof(struct cpl_tid_release); 434 mbuf->pkt_len = mbuf->data_len; 435 mk_tid_release(mbuf, tid); 436 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf); 437 } 438 } 439 440 /** 441 * Insert a TID. 442 */ 443 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, 444 unsigned short family) 445 { 446 t->tid_tab[tid] = data; 447 if (t->hash_base && tid >= t->hash_base) { 448 if (family == FILTER_TYPE_IPV4) 449 __atomic_add_fetch(&t->hash_tids_in_use, 1, 450 __ATOMIC_RELAXED); 451 } else { 452 if (family == FILTER_TYPE_IPV4) 453 __atomic_add_fetch(&t->tids_in_use, 1, 454 __ATOMIC_RELAXED); 455 } 456 457 __atomic_add_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); 458 } 459 460 /** 461 * Free TID tables. 462 */ 463 static void tid_free(struct tid_info *t) 464 { 465 if (t->tid_tab) { 466 rte_bitmap_free(t->ftid_bmap); 467 468 if (t->ftid_bmap_array) 469 t4_os_free(t->ftid_bmap_array); 470 471 t4_os_free(t->tid_tab); 472 } 473 474 memset(t, 0, sizeof(struct tid_info)); 475 } 476 477 /** 478 * Allocate and initialize the TID tables. Returns 0 on success. 479 */ 480 static int tid_init(struct tid_info *t) 481 { 482 size_t size; 483 unsigned int ftid_bmap_size; 484 unsigned int natids = t->natids; 485 unsigned int max_ftids = t->nftids; 486 487 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids); 488 size = t->ntids * sizeof(*t->tid_tab) + 489 max_ftids * sizeof(*t->ftid_tab) + 490 natids * sizeof(*t->atid_tab); 491 492 t->tid_tab = t4_os_alloc(size); 493 if (!t->tid_tab) 494 return -ENOMEM; 495 496 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 497 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids]; 498 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size); 499 if (!t->ftid_bmap_array) { 500 tid_free(t); 501 return -ENOMEM; 502 } 503 504 t4_os_lock_init(&t->atid_lock); 505 t4_os_lock_init(&t->ftid_lock); 506 507 t->afree = NULL; 508 t->atids_in_use = 0; 509 t->tids_in_use = 0; 510 t->conns_in_use = 0; 511 512 /* Setup the free list for atid_tab and clear the stid bitmap. */ 513 if (natids) { 514 while (--natids) 515 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 516 t->afree = t->atid_tab; 517 } 518 519 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array, 520 ftid_bmap_size); 521 if (!t->ftid_bmap) { 522 tid_free(t); 523 return -ENOMEM; 524 } 525 526 return 0; 527 } 528 529 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 530 unsigned int us, unsigned int cnt, 531 unsigned int size, unsigned int iqe_size) 532 { 533 q->adapter = adap; 534 cxgb4_set_rspq_intr_params(q, us, cnt); 535 q->iqe_len = iqe_size; 536 q->size = size; 537 } 538 539 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev) 540 { 541 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 542 struct adapter *adap = pi->adapter; 543 u16 first_txq = 0, first_rxq = 0; 544 struct sge *s = &adap->sge; 545 u16 i, max_rxqs, max_txqs; 546 547 max_rxqs = s->max_ethqsets; 548 max_txqs = s->max_ethqsets; 549 for_each_port(adap, i) { 550 temp_pi = adap2pinfo(adap, i); 551 if (i == pi->port_id) 552 break; 553 554 if (max_rxqs <= temp_pi->n_rx_qsets || 555 max_txqs <= temp_pi->n_tx_qsets) 556 return -ENOMEM; 557 558 first_rxq += temp_pi->n_rx_qsets; 559 first_txq += temp_pi->n_tx_qsets; 560 max_rxqs -= temp_pi->n_rx_qsets; 561 max_txqs -= temp_pi->n_tx_qsets; 562 } 563 564 if ((eth_dev->data->nb_rx_queues < 1) || 565 (eth_dev->data->nb_tx_queues < 1)) 566 return -EINVAL; 567 568 if (eth_dev->data->nb_rx_queues > max_rxqs || 569 eth_dev->data->nb_tx_queues > max_txqs) 570 return -EINVAL; 571 572 /* We must configure RSS, since config has changed*/ 573 pi->flags &= ~PORT_RSS_DONE; 574 575 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 576 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 577 pi->first_rxqset = first_rxq; 578 pi->first_txqset = first_txq; 579 580 return 0; 581 } 582 583 void cxgbe_cfg_queues_free(struct adapter *adap) 584 { 585 if (adap->sge.ethtxq) { 586 rte_free(adap->sge.ethtxq); 587 adap->sge.ethtxq = NULL; 588 } 589 590 if (adap->sge.ethrxq) { 591 rte_free(adap->sge.ethrxq); 592 adap->sge.ethrxq = NULL; 593 } 594 595 adap->flags &= ~CFG_QUEUES; 596 } 597 598 int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev) 599 { 600 struct port_info *pi = eth_dev->data->dev_private; 601 struct adapter *adap = pi->adapter; 602 struct sge *s = &adap->sge; 603 u16 i; 604 605 if (!(adap->flags & CFG_QUEUES)) { 606 s->ethrxq = rte_calloc_socket(NULL, s->max_ethqsets, 607 sizeof(struct sge_eth_rxq), 0, 608 rte_socket_id()); 609 if (!s->ethrxq) 610 return -ENOMEM; 611 612 s->ethtxq = rte_calloc_socket(NULL, s->max_ethqsets, 613 sizeof(struct sge_eth_txq), 0, 614 rte_socket_id()); 615 if (!s->ethtxq) { 616 rte_free(s->ethrxq); 617 s->ethrxq = NULL; 618 return -ENOMEM; 619 } 620 621 for (i = 0; i < s->max_ethqsets; i++) { 622 struct sge_eth_rxq *r = &s->ethrxq[i]; 623 struct sge_eth_txq *t = &s->ethtxq[i]; 624 625 init_rspq(adap, &r->rspq, 5, 32, 1024, 64); 626 r->fl.size = 1024; 627 628 t->q.size = 1024; 629 } 630 631 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 632 adap->flags |= CFG_QUEUES; 633 } 634 635 return 0; 636 } 637 638 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 639 { 640 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 641 &pi->stats_base); 642 } 643 644 void cxgbe_stats_reset(struct port_info *pi) 645 { 646 t4_clr_port_stats(pi->adapter, pi->tx_chan); 647 } 648 649 static void setup_memwin(struct adapter *adap) 650 { 651 u32 mem_win0_base; 652 653 /* For T5, only relative offset inside the PCIe BAR is passed */ 654 mem_win0_base = MEMWIN0_BASE; 655 656 /* 657 * Set up memory window for accessing adapter memory ranges. (Read 658 * back MA register to ensure that changes propagate before we attempt 659 * to use the new values.) 660 */ 661 t4_write_reg(adap, 662 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 663 MEMWIN_NIC), 664 mem_win0_base | V_BIR(0) | 665 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 666 t4_read_reg(adap, 667 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 668 MEMWIN_NIC)); 669 } 670 671 int cxgbe_init_rss(struct adapter *adap) 672 { 673 unsigned int i; 674 675 if (is_pf4(adap)) { 676 int err; 677 678 err = t4_init_rss_mode(adap, adap->mbox); 679 if (err) 680 return err; 681 } 682 683 for_each_port(adap, i) { 684 struct port_info *pi = adap2pinfo(adap, i); 685 686 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 687 if (!pi->rss) 688 return -ENOMEM; 689 690 pi->rss_hf = CXGBE_RSS_HF_ALL; 691 } 692 return 0; 693 } 694 695 /** 696 * Dump basic information about the adapter. 697 */ 698 void cxgbe_print_adapter_info(struct adapter *adap) 699 { 700 /** 701 * Hardware/Firmware/etc. Version/Revision IDs. 702 */ 703 t4_dump_version_info(adap); 704 } 705 706 void cxgbe_print_port_info(struct adapter *adap) 707 { 708 int i; 709 char buf[80]; 710 struct rte_pci_addr *loc = &adap->pdev->addr; 711 712 for_each_port(adap, i) { 713 const struct port_info *pi = adap2pinfo(adap, i); 714 char *bufp = buf; 715 716 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 717 bufp += sprintf(bufp, "100M/"); 718 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 719 bufp += sprintf(bufp, "1G/"); 720 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 721 bufp += sprintf(bufp, "10G/"); 722 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 723 bufp += sprintf(bufp, "25G/"); 724 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 725 bufp += sprintf(bufp, "40G/"); 726 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 727 bufp += sprintf(bufp, "50G/"); 728 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 729 bufp += sprintf(bufp, "100G/"); 730 if (bufp != buf) 731 --bufp; 732 sprintf(bufp, "BASE-%s", 733 t4_get_port_type_description( 734 (enum fw_port_type)pi->link_cfg.port_type)); 735 736 dev_info(adap, 737 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 738 loc->domain, loc->bus, loc->devid, loc->function, 739 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 740 (adap->flags & USING_MSIX) ? " MSI-X" : 741 (adap->flags & USING_MSI) ? " MSI" : ""); 742 } 743 } 744 745 static int check_devargs_handler(const char *key, const char *value, void *p) 746 { 747 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) || 748 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) || 749 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) { 750 if (!strncmp(value, "1", 1)) { 751 bool *dst_val = (bool *)p; 752 753 *dst_val = true; 754 } 755 } 756 757 if (!strncmp(key, CXGBE_DEVARG_PF_FILTER_MODE, strlen(key)) || 758 !strncmp(key, CXGBE_DEVARG_PF_FILTER_MASK, strlen(key))) { 759 u32 *dst_val = (u32 *)p; 760 char *endptr = NULL; 761 u32 arg_val; 762 763 arg_val = strtoul(value, &endptr, 16); 764 if (errno || endptr == value) 765 return -EINVAL; 766 767 *dst_val = arg_val; 768 } 769 770 return 0; 771 } 772 773 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key, 774 void *p) 775 { 776 struct rte_kvargs *kvlist; 777 int ret = 0; 778 779 if (!devargs) 780 return 0; 781 782 kvlist = rte_kvargs_parse(devargs->args, NULL); 783 if (!kvlist) 784 return 0; 785 786 if (!rte_kvargs_count(kvlist, key)) 787 goto out; 788 789 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p); 790 791 out: 792 rte_kvargs_free(kvlist); 793 794 return ret; 795 } 796 797 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst, 798 const char *key, bool default_value) 799 { 800 struct rte_pci_device *pdev = adap->pdev; 801 int ret; 802 bool devarg_value = default_value; 803 804 *dst = default_value; 805 if (!pdev) 806 return; 807 808 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); 809 if (ret) 810 return; 811 812 *dst = devarg_value; 813 } 814 815 static void cxgbe_get_devargs_u32(struct adapter *adap, u32 *dst, 816 const char *key, u32 default_value) 817 { 818 struct rte_pci_device *pdev = adap->pdev; 819 u32 devarg_value = default_value; 820 int ret; 821 822 *dst = default_value; 823 if (!pdev) 824 return; 825 826 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); 827 if (ret) 828 return; 829 830 *dst = devarg_value; 831 } 832 833 void cxgbe_process_devargs(struct adapter *adap) 834 { 835 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan, 836 CXGBE_DEVARG_CMN_KEEP_OVLAN, false); 837 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency, 838 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false); 839 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up, 840 CXGBE_DEVARG_VF_FORCE_LINK_UP, false); 841 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermode, 842 CXGBE_DEVARG_PF_FILTER_MODE, 0); 843 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermask, 844 CXGBE_DEVARG_PF_FILTER_MASK, 0); 845 } 846 847 static void configure_vlan_types(struct adapter *adapter) 848 { 849 int i; 850 851 for_each_port(adapter, i) { 852 /* OVLAN Type 0x88a8 */ 853 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0), 854 V_OVLAN_MASK(M_OVLAN_MASK) | 855 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 856 V_OVLAN_MASK(M_OVLAN_MASK) | 857 V_OVLAN_ETYPE(0x88a8)); 858 /* OVLAN Type 0x9100 */ 859 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1), 860 V_OVLAN_MASK(M_OVLAN_MASK) | 861 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 862 V_OVLAN_MASK(M_OVLAN_MASK) | 863 V_OVLAN_ETYPE(0x9100)); 864 865 /* IVLAN 0X8100 */ 866 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), 867 V_IVLAN_ETYPE(M_IVLAN_ETYPE), 868 V_IVLAN_ETYPE(0x8100)); 869 870 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), 871 F_OVLAN_EN0 | F_OVLAN_EN1 | 872 F_IVLAN_EN, 873 F_OVLAN_EN0 | F_OVLAN_EN1 | 874 F_IVLAN_EN); 875 } 876 877 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1), 878 V_RM_OVLAN(!adapter->devargs.keep_ovlan)); 879 } 880 881 static int cxgbe_get_filter_vnic_mode_from_devargs(u32 val) 882 { 883 u32 vnic_mode; 884 885 vnic_mode = val & (CXGBE_DEVARGS_FILTER_MODE_PF_VF | 886 CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER); 887 if (vnic_mode) { 888 switch (vnic_mode) { 889 case CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER: 890 return CXGBE_FILTER_VNIC_MODE_OVLAN; 891 case CXGBE_DEVARGS_FILTER_MODE_PF_VF: 892 return CXGBE_FILTER_VNIC_MODE_PFVF; 893 default: 894 return -EINVAL; 895 } 896 } 897 898 return CXGBE_FILTER_VNIC_MODE_NONE; 899 } 900 901 static int cxgbe_get_filter_mode_from_devargs(u32 val, bool closest_match) 902 { 903 int vnic_mode, fmode = 0; 904 bool found = false; 905 u8 i; 906 907 if (val >= CXGBE_DEVARGS_FILTER_MODE_MAX) { 908 pr_err("Unsupported flags set in filter mode. Must be < 0x%x\n", 909 CXGBE_DEVARGS_FILTER_MODE_MAX); 910 return -ERANGE; 911 } 912 913 vnic_mode = cxgbe_get_filter_vnic_mode_from_devargs(val); 914 if (vnic_mode < 0) { 915 pr_err("Unsupported Vnic-mode, more than 1 Vnic-mode selected\n"); 916 return vnic_mode; 917 } 918 919 if (vnic_mode) 920 fmode |= F_VNIC_ID; 921 if (val & CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT) 922 fmode |= F_PORT; 923 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC) 924 fmode |= F_MACMATCH; 925 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE) 926 fmode |= F_ETHERTYPE; 927 if (val & CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER) 928 fmode |= F_VLAN; 929 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_TOS) 930 fmode |= F_TOS; 931 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL) 932 fmode |= F_PROTOCOL; 933 934 for (i = 0; i < ARRAY_SIZE(cxgbe_filter_mode_features); i++) { 935 if ((cxgbe_filter_mode_features[i] & fmode) == fmode) { 936 found = true; 937 break; 938 } 939 } 940 941 if (!found) 942 return -EINVAL; 943 944 return closest_match ? cxgbe_filter_mode_features[i] : fmode; 945 } 946 947 static int configure_filter_mode_mask(struct adapter *adap) 948 { 949 u32 params[2], val[2], nparams = 0; 950 int ret; 951 952 if (!adap->devargs.filtermode && !adap->devargs.filtermask) 953 return 0; 954 955 if (!adap->devargs.filtermode || !adap->devargs.filtermask) { 956 pr_err("Unsupported, Provide both filtermode and filtermask devargs\n"); 957 return -EINVAL; 958 } 959 960 if (adap->devargs.filtermask & ~adap->devargs.filtermode) { 961 pr_err("Unsupported, filtermask (0x%x) must be subset of filtermode (0x%x)\n", 962 adap->devargs.filtermask, adap->devargs.filtermode); 963 964 return -EINVAL; 965 } 966 967 params[0] = CXGBE_FW_PARAM_DEV(FILTER) | 968 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 969 970 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermode, 971 true); 972 if (ret < 0) { 973 pr_err("Unsupported filtermode devargs combination:0x%x\n", 974 adap->devargs.filtermode); 975 return ret; 976 } 977 978 val[0] = V_FW_PARAMS_PARAM_FILTER_MODE(ret); 979 980 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermask, 981 false); 982 if (ret < 0) { 983 pr_err("Unsupported filtermask devargs combination:0x%x\n", 984 adap->devargs.filtermask); 985 return ret; 986 } 987 988 val[0] |= V_FW_PARAMS_PARAM_FILTER_MASK(ret); 989 990 nparams++; 991 992 ret = cxgbe_get_filter_vnic_mode_from_devargs(adap->devargs.filtermode); 993 if (ret < 0) 994 return ret; 995 996 if (ret) { 997 params[1] = CXGBE_FW_PARAM_DEV(FILTER) | 998 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 999 1000 val[1] = ret - 1; 1001 1002 nparams++; 1003 } 1004 1005 return t4_set_params(adap, adap->mbox, adap->pf, 0, nparams, 1006 params, val); 1007 } 1008 1009 static void configure_pcie_ext_tag(struct adapter *adapter) 1010 { 1011 u16 v; 1012 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 1013 1014 if (!pos) 1015 return; 1016 1017 if (pos > 0) { 1018 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v); 1019 v |= PCI_EXP_DEVCTL_EXT_TAG; 1020 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v); 1021 if (is_t6(adapter->params.chip)) { 1022 t4_set_reg_field(adapter, A_PCIE_CFG2, 1023 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG), 1024 V_T6_TOTMAXTAG(7)); 1025 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 1026 V_T6_MINTAG(M_T6_MINTAG), 1027 V_T6_MINTAG(8)); 1028 } else { 1029 t4_set_reg_field(adapter, A_PCIE_CFG2, 1030 V_TOTMAXTAG(M_TOTMAXTAG), 1031 V_TOTMAXTAG(3)); 1032 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 1033 V_MINTAG(M_MINTAG), 1034 V_MINTAG(8)); 1035 } 1036 } 1037 } 1038 1039 /* Figure out how many Queue Sets we can support */ 1040 void cxgbe_configure_max_ethqsets(struct adapter *adapter) 1041 { 1042 unsigned int ethqsets, reserved; 1043 1044 /* We need to reserve an Ingress Queue for the Asynchronous Firmware 1045 * Event Queue and 1 Control Queue per port. 1046 * 1047 * For each Queue Set, we'll need the ability to allocate two Egress 1048 * Contexts -- one for the Ingress Queue Free List and one for the TX 1049 * Ethernet Queue. 1050 */ 1051 reserved = max(adapter->params.nports, 1); 1052 if (is_pf4(adapter)) { 1053 struct pf_resources *pfres = &adapter->params.pfres; 1054 1055 ethqsets = min(pfres->niqflint, pfres->nethctrl); 1056 if (ethqsets > (pfres->neq / 2)) 1057 ethqsets = pfres->neq / 2; 1058 } else { 1059 struct vf_resources *vfres = &adapter->params.vfres; 1060 1061 ethqsets = min(vfres->niqflint, vfres->nethctrl); 1062 if (ethqsets > (vfres->neq / 2)) 1063 ethqsets = vfres->neq / 2; 1064 } 1065 1066 ethqsets -= reserved; 1067 adapter->sge.max_ethqsets = ethqsets; 1068 } 1069 1070 /* 1071 * Tweak configuration based on system architecture, etc. Most of these have 1072 * defaults assigned to them by Firmware Configuration Files (if we're using 1073 * them) but need to be explicitly set if we're using hard-coded 1074 * initialization. So these are essentially common tweaks/settings for 1075 * Configuration Files and hard-coded initialization ... 1076 */ 1077 static int adap_init0_tweaks(struct adapter *adapter) 1078 { 1079 u8 rx_dma_offset; 1080 1081 /* 1082 * Fix up various Host-Dependent Parameters like Page Size, Cache 1083 * Line Size, etc. The firmware default is for a 4KB Page Size and 1084 * 64B Cache Line Size ... 1085 */ 1086 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 1087 T5_LAST_REV); 1088 1089 /* 1090 * Keep the chip default offset to deliver Ingress packets into our 1091 * DMA buffers to zero 1092 */ 1093 rx_dma_offset = 0; 1094 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 1095 V_PKTSHIFT(rx_dma_offset)); 1096 1097 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 1098 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 1099 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 1100 1101 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD, 1102 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U)); 1103 1104 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 1105 V_IDMAARBROUNDROBIN(1U)); 1106 1107 /* 1108 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 1109 * adds the pseudo header itself. 1110 */ 1111 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 1112 F_CSUM_HAS_PSEUDO_HDR, 0); 1113 1114 return 0; 1115 } 1116 1117 /* 1118 * Attempt to initialize the adapter via a Firmware Configuration File. 1119 */ 1120 static int adap_init0_config(struct adapter *adapter, int reset) 1121 { 1122 u32 finiver, finicsum, cfcsum, param, val; 1123 struct fw_caps_config_cmd caps_cmd; 1124 unsigned long mtype = 0, maddr = 0; 1125 u8 config_issued = 0; 1126 char config_name[20]; 1127 int cfg_addr, ret; 1128 1129 /* 1130 * Reset device if necessary. 1131 */ 1132 if (reset) { 1133 ret = t4_fw_reset(adapter, adapter->mbox, 1134 F_PIORSTMODE | F_PIORST); 1135 if (ret < 0) { 1136 dev_warn(adapter, "Firmware reset failed, error %d\n", 1137 -ret); 1138 goto bye; 1139 } 1140 } 1141 1142 cfg_addr = t4_flash_cfg_addr(adapter); 1143 if (cfg_addr < 0) { 1144 ret = cfg_addr; 1145 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 1146 -ret); 1147 goto bye; 1148 } 1149 1150 strcpy(config_name, "On Flash"); 1151 mtype = FW_MEMTYPE_CF_FLASH; 1152 maddr = cfg_addr; 1153 1154 /* Enable HASH filter region when support is available. */ 1155 val = 1; 1156 param = CXGBE_FW_PARAM_DEV(HASHFILTER_WITH_OFLD); 1157 t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 1, 1158 ¶m, &val); 1159 1160 /* 1161 * Issue a Capability Configuration command to the firmware to get it 1162 * to parse the Configuration File. We don't use t4_fw_config_file() 1163 * because we want the ability to modify various features after we've 1164 * processed the configuration file ... 1165 */ 1166 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1167 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1168 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1169 caps_cmd.cfvalid_to_len16 = 1170 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 1171 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1172 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 1173 FW_LEN16(caps_cmd)); 1174 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 1175 &caps_cmd); 1176 /* 1177 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 1178 * Configuration File in FLASH), our last gasp effort is to use the 1179 * Firmware Configuration File which is embedded in the firmware. A 1180 * very few early versions of the firmware didn't have one embedded 1181 * but we can ignore those. 1182 */ 1183 if (ret == -ENOENT) { 1184 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 1185 __func__); 1186 1187 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1188 caps_cmd.op_to_write = 1189 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1190 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1191 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 1192 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 1193 sizeof(caps_cmd), &caps_cmd); 1194 strcpy(config_name, "Firmware Default"); 1195 } 1196 1197 config_issued = 1; 1198 if (ret < 0) 1199 goto bye; 1200 1201 finiver = be32_to_cpu(caps_cmd.finiver); 1202 finicsum = be32_to_cpu(caps_cmd.finicsum); 1203 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 1204 if (finicsum != cfcsum) 1205 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 1206 finicsum, cfcsum); 1207 1208 /* 1209 * If we're a pure NIC driver then disable all offloading facilities. 1210 * This will allow the firmware to optimize aspects of the hardware 1211 * configuration which will result in improved performance. 1212 */ 1213 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD); 1214 caps_cmd.toecaps = 0; 1215 caps_cmd.iscsicaps = 0; 1216 caps_cmd.rdmacaps = 0; 1217 caps_cmd.fcoecaps = 0; 1218 caps_cmd.cryptocaps = 0; 1219 1220 /* 1221 * And now tell the firmware to use the configuration we just loaded. 1222 */ 1223 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1224 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1225 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1226 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 1227 NULL); 1228 if (ret < 0) { 1229 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 1230 -ret); 1231 goto bye; 1232 } 1233 1234 /* 1235 * Tweak configuration based on system architecture, etc. 1236 */ 1237 ret = adap_init0_tweaks(adapter); 1238 if (ret < 0) { 1239 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 1240 goto bye; 1241 } 1242 1243 /* 1244 * And finally tell the firmware to initialize itself using the 1245 * parameters from the Configuration File. 1246 */ 1247 ret = t4_fw_initialize(adapter, adapter->mbox); 1248 if (ret < 0) { 1249 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 1250 -ret); 1251 goto bye; 1252 } 1253 1254 /* 1255 * Return successfully and note that we're operating with parameters 1256 * not supplied by the driver, rather than from hard-wired 1257 * initialization constants buried in the driver. 1258 */ 1259 dev_info(adapter, 1260 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 1261 config_name, finiver, cfcsum); 1262 1263 return 0; 1264 1265 /* 1266 * Something bad happened. Return the error ... (If the "error" 1267 * is that there's no Configuration File on the adapter we don't 1268 * want to issue a warning since this is fairly common.) 1269 */ 1270 bye: 1271 if (config_issued && ret != -ENOENT) 1272 dev_warn(adapter, "\"%s\" configuration file error %d\n", 1273 config_name, -ret); 1274 1275 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 1276 return ret; 1277 } 1278 1279 static int adap_init0(struct adapter *adap) 1280 { 1281 struct fw_caps_config_cmd caps_cmd; 1282 int ret = 0; 1283 u32 v, port_vec; 1284 enum dev_state state; 1285 u32 params[7], val[7]; 1286 int reset = 1; 1287 int mbox = adap->mbox; 1288 1289 /* 1290 * Contact FW, advertising Master capability. 1291 */ 1292 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 1293 if (ret < 0) { 1294 dev_err(adap, "%s: could not connect to FW, error %d\n", 1295 __func__, -ret); 1296 goto bye; 1297 } 1298 1299 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 1300 adap->mbox, ret); 1301 1302 if (ret == mbox) 1303 adap->flags |= MASTER_PF; 1304 1305 if (state == DEV_STATE_INIT) { 1306 /* 1307 * Force halt and reset FW because a previous instance may have 1308 * exited abnormally without properly shutting down 1309 */ 1310 ret = t4_fw_halt(adap, adap->mbox, reset); 1311 if (ret < 0) { 1312 dev_err(adap, "Failed to halt. Exit.\n"); 1313 goto bye; 1314 } 1315 1316 ret = t4_fw_restart(adap, adap->mbox, reset); 1317 if (ret < 0) { 1318 dev_err(adap, "Failed to restart. Exit.\n"); 1319 goto bye; 1320 } 1321 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 1322 } 1323 1324 t4_get_version_info(adap); 1325 1326 ret = t4_get_core_clock(adap, &adap->params.vpd); 1327 if (ret < 0) { 1328 dev_err(adap, "%s: could not get core clock, error %d\n", 1329 __func__, -ret); 1330 goto bye; 1331 } 1332 1333 /* 1334 * If the firmware is initialized already (and we're not forcing a 1335 * master initialization), note that we're living with existing 1336 * adapter parameters. Otherwise, it's time to try initializing the 1337 * adapter ... 1338 */ 1339 if (state == DEV_STATE_INIT) { 1340 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 1341 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 1342 } else { 1343 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 1344 1345 ret = adap_init0_config(adap, reset); 1346 if (ret == -ENOENT) { 1347 dev_err(adap, 1348 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 1349 goto bye; 1350 } 1351 } 1352 if (ret < 0) { 1353 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 1354 goto bye; 1355 } 1356 1357 /* Now that we've successfully configured and initialized the adapter 1358 * (or found it already initialized), we can ask the Firmware what 1359 * resources it has provisioned for us. 1360 */ 1361 ret = t4_get_pfres(adap); 1362 if (ret) { 1363 dev_err(adap->pdev_dev, 1364 "Unable to retrieve resource provisioning info\n"); 1365 goto bye; 1366 } 1367 1368 /* Find out what ports are available to us. */ 1369 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1370 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 1371 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 1372 if (ret < 0) { 1373 dev_err(adap, "%s: failure in t4_query_params; error = %d\n", 1374 __func__, ret); 1375 goto bye; 1376 } 1377 1378 adap->params.nports = hweight32(port_vec); 1379 adap->params.portvec = port_vec; 1380 1381 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 1382 adap->params.nports); 1383 1384 /* 1385 * Give the SGE code a chance to pull in anything that it needs ... 1386 * Note that this must be called after we retrieve our VPD parameters 1387 * in order to know how to convert core ticks to seconds, etc. 1388 */ 1389 ret = t4_sge_init(adap); 1390 if (ret < 0) { 1391 dev_err(adap, "t4_sge_init failed with error %d\n", 1392 -ret); 1393 goto bye; 1394 } 1395 1396 /* 1397 * Grab some of our basic fundamental operating parameters. 1398 */ 1399 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START); 1400 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END); 1401 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START); 1402 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END); 1403 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); 1404 if (ret < 0) 1405 goto bye; 1406 adap->l2t_start = val[0]; 1407 adap->l2t_end = val[1]; 1408 adap->tids.ftid_base = val[2]; 1409 adap->tids.nftids = val[3] - val[2] + 1; 1410 1411 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START); 1412 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END); 1413 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 1414 if (ret < 0) 1415 goto bye; 1416 adap->clipt_start = val[0]; 1417 adap->clipt_end = val[1]; 1418 1419 /* 1420 * Get device capabilities so we can determine what resources we need 1421 * to manage. 1422 */ 1423 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1424 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1425 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1426 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1427 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1428 &caps_cmd); 1429 if (ret < 0) 1430 goto bye; 1431 1432 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) && 1433 is_t6(adap->params.chip)) { 1434 if (cxgbe_init_hash_filter(adap) < 0) 1435 goto bye; 1436 } 1437 1438 /* See if FW supports FW_FILTER2 work request */ 1439 if (is_t4(adap->params.chip)) { 1440 adap->params.filter2_wr_support = 0; 1441 } else { 1442 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR); 1443 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1444 1, params, val); 1445 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 1446 } 1447 1448 /* Check if FW supports returning vin. 1449 * If this is not supported, driver will interpret 1450 * these values from viid. 1451 */ 1452 params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 1453 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1454 1, params, val); 1455 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); 1456 1457 /* query tid-related parameters */ 1458 params[0] = CXGBE_FW_PARAM_DEV(NTID); 1459 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 1460 params, val); 1461 if (ret < 0) 1462 goto bye; 1463 adap->tids.ntids = val[0]; 1464 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 1465 1466 /* If we're running on newer firmware, let it know that we're 1467 * prepared to deal with encapsulated CPL messages. Older 1468 * firmware won't understand this and we'll just get 1469 * unencapsulated messages ... 1470 */ 1471 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1472 val[0] = 1; 1473 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1474 1475 /* 1476 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 1477 * capability. Earlier versions of the firmware didn't have the 1478 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 1479 * permission to use ULPTX MEMWRITE DSGL. 1480 */ 1481 if (is_t4(adap->params.chip)) { 1482 adap->params.ulptx_memwrite_dsgl = false; 1483 } else { 1484 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 1485 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1486 1, params, val); 1487 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 1488 } 1489 1490 /* Query for max number of packets that can be coalesced for Tx */ 1491 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 1492 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1493 if (!ret && val[0] > 0) 1494 adap->params.max_tx_coalesce_num = val[0]; 1495 else 1496 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; 1497 1498 params[0] = CXGBE_FW_PARAM_DEV(VI_ENABLE_INGRESS_AFTER_LINKUP); 1499 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1500 adap->params.vi_enable_rx = (ret == 0 && val[0] != 0); 1501 1502 /* Read the RAW MPS entries. In T6, the last 2 TCAM entries 1503 * are reserved for RAW MAC addresses (rawf = 2, one per port). 1504 */ 1505 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 1506 params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START); 1507 params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END); 1508 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 1509 params, val); 1510 if (ret == 0) { 1511 adap->params.rawf_start = val[0]; 1512 adap->params.rawf_size = val[1] - val[0] + 1; 1513 } 1514 } 1515 1516 /* 1517 * The MTU/MSS Table is initialized by now, so load their values. If 1518 * we're initializing the adapter, then we'll make any modifications 1519 * we want to the MTU/MSS Table and also initialize the congestion 1520 * parameters. 1521 */ 1522 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 1523 if (state != DEV_STATE_INIT) { 1524 int i; 1525 1526 /* 1527 * The default MTU Table contains values 1492 and 1500. 1528 * However, for TCP, it's better to have two values which are 1529 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 1530 * This allows us to have a TCP Data Payload which is a 1531 * multiple of 8 regardless of what combination of TCP Options 1532 * are in use (always a multiple of 4 bytes) which is 1533 * important for performance reasons. For instance, if no 1534 * options are in use, then we have a 20-byte IP header and a 1535 * 20-byte TCP header. In this case, a 1500-byte MSS would 1536 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 1537 * which is not a multiple of 8. So using an MSS of 1488 in 1538 * this case results in a TCP Data Payload of 1448 bytes which 1539 * is a multiple of 8. On the other hand, if 12-byte TCP Time 1540 * Stamps have been negotiated, then an MTU of 1500 bytes 1541 * results in a TCP Data Payload of 1448 bytes which, as 1542 * above, is a multiple of 8 bytes ... 1543 */ 1544 for (i = 0; i < NMTUS; i++) 1545 if (adap->params.mtus[i] == 1492) { 1546 adap->params.mtus[i] = 1488; 1547 break; 1548 } 1549 1550 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 1551 adap->params.b_wnd); 1552 } 1553 t4_init_sge_params(adap); 1554 ret = configure_filter_mode_mask(adap); 1555 if (ret < 0) 1556 goto bye; 1557 t4_init_tp_params(adap); 1558 configure_pcie_ext_tag(adap); 1559 configure_vlan_types(adap); 1560 cxgbe_configure_max_ethqsets(adap); 1561 1562 adap->params.drv_memwin = MEMWIN_NIC; 1563 adap->flags |= FW_OK; 1564 dev_debug(adap, "%s: returning zero..\n", __func__); 1565 return 0; 1566 1567 /* 1568 * Something bad happened. If a command timed out or failed with EIO 1569 * FW does not operate within its spec or something catastrophic 1570 * happened to HW/FW, stop issuing commands. 1571 */ 1572 bye: 1573 if (ret != -ETIMEDOUT && ret != -EIO) 1574 t4_fw_bye(adap, adap->mbox); 1575 return ret; 1576 } 1577 1578 /** 1579 * t4_os_portmod_changed - handle port module changes 1580 * @adap: the adapter associated with the module change 1581 * @port_id: the port index whose module status has changed 1582 * 1583 * This is the OS-dependent handler for port module changes. It is 1584 * invoked when a port module is removed or inserted for any OS-specific 1585 * processing. 1586 */ 1587 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 1588 { 1589 static const char * const mod_str[] = { 1590 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 1591 }; 1592 1593 const struct port_info *pi = adap2pinfo(adap, port_id); 1594 1595 if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NONE) 1596 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 1597 else if (pi->link_cfg.mod_type < ARRAY_SIZE(mod_str)) 1598 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 1599 mod_str[pi->link_cfg.mod_type]); 1600 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 1601 dev_info(adap, "Port%d: unsupported port module inserted\n", 1602 pi->port_id); 1603 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 1604 dev_info(adap, "Port%d: unknown port module inserted\n", 1605 pi->port_id); 1606 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_ERROR) 1607 dev_info(adap, "Port%d: transceiver module error\n", 1608 pi->port_id); 1609 else 1610 dev_info(adap, "Port%d: unknown module type %d inserted\n", 1611 pi->port_id, pi->link_cfg.mod_type); 1612 } 1613 1614 void t4_os_link_changed(struct adapter *adap, int port_id) 1615 { 1616 struct port_info *pi = adap2pinfo(adap, port_id); 1617 1618 /* If link status has not changed or if firmware doesn't 1619 * support enabling/disabling VI's Rx path during runtime, 1620 * then return. 1621 */ 1622 if (adap->params.vi_enable_rx == 0 || 1623 pi->vi_en_rx == pi->link_cfg.link_ok) 1624 return; 1625 1626 /* Don't enable VI Rx path, if link has been administratively 1627 * turned off. 1628 */ 1629 if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0) 1630 return; 1631 1632 /* When link goes down, disable the port's Rx path to drop 1633 * Rx traffic closer to the wire, instead of processing it 1634 * further in the Rx pipeline. The Rx path will be re-enabled 1635 * once the link up message comes in firmware event queue. 1636 */ 1637 pi->vi_en_rx = pi->link_cfg.link_ok; 1638 t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx); 1639 } 1640 1641 bool cxgbe_force_linkup(struct adapter *adap) 1642 { 1643 if (is_pf4(adap)) 1644 return false; /* force_linkup not required for pf driver */ 1645 1646 return adap->devargs.force_link_up; 1647 } 1648 1649 /** 1650 * link_start - enable a port 1651 * @dev: the port to enable 1652 * 1653 * Performs the MAC and PHY actions needed to enable a port. 1654 */ 1655 int cxgbe_link_start(struct port_info *pi) 1656 { 1657 struct adapter *adapter = pi->adapter; 1658 u64 conf_offloads; 1659 unsigned int mtu; 1660 int ret; 1661 1662 mtu = pi->eth_dev->data->mtu; 1663 1664 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads; 1665 1666 /* 1667 * We do not set address filters and promiscuity here, the stack does 1668 * that step explicitly. 1669 */ 1670 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1, 1671 !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP), 1672 true); 1673 if (ret == 0) { 1674 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, 1675 (u8 *)&pi->eth_dev->data->mac_addrs[0]); 1676 if (ret >= 0) { 1677 pi->xact_addr_filt = ret; 1678 ret = 0; 1679 } 1680 } 1681 if (ret == 0 && is_pf4(adapter)) 1682 ret = t4_link_l1cfg(pi, pi->link_cfg.admin_caps); 1683 if (ret == 0) { 1684 /* Disable VI Rx until link up message is received in 1685 * firmware event queue, if firmware supports enabling/ 1686 * disabling VI Rx at runtime. 1687 */ 1688 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : 1; 1689 pi->vi_en_tx = 1; 1690 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 1691 pi->vi_en_rx, pi->vi_en_tx, false); 1692 } 1693 1694 if (ret == 0 && cxgbe_force_linkup(adapter)) 1695 pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 1696 return ret; 1697 } 1698 1699 /** 1700 * cxgbe_write_rss_conf - flash the RSS configuration for a given port 1701 * @pi: the port 1702 * @rss_hf: Hash configuration to apply 1703 */ 1704 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) 1705 { 1706 struct adapter *adapter = pi->adapter; 1707 const struct sge_eth_rxq *rxq; 1708 u64 flags = 0; 1709 u16 rss; 1710 int err; 1711 1712 /* Should never be called before setting up sge eth rx queues */ 1713 if (!(adapter->flags & FULL_INIT_DONE)) { 1714 dev_err(adap, "%s No RXQs available on port %d\n", 1715 __func__, pi->port_id); 1716 return -EINVAL; 1717 } 1718 1719 /* Don't allow unsupported hash functions */ 1720 if (rss_hf & ~CXGBE_RSS_HF_ALL) 1721 return -EINVAL; 1722 1723 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) 1724 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 1725 1726 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 1727 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 1728 1729 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 1730 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 1731 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1732 1733 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK) 1734 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 1735 1736 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK) 1737 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1738 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 1739 1740 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK) 1741 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1742 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 1743 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1744 1745 rxq = &adapter->sge.ethrxq[pi->first_rxqset]; 1746 rss = rxq[0].rspq.abs_id; 1747 1748 /* If Tunnel All Lookup isn't specified in the global RSS 1749 * Configuration, then we need to specify a default Ingress 1750 * Queue for any ingress packets which aren't hashed. We'll 1751 * use our first ingress queue ... 1752 */ 1753 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 1754 flags, rss); 1755 return err; 1756 } 1757 1758 /** 1759 * cxgbe_write_rss - write the RSS table for a given port 1760 * @pi: the port 1761 * @queues: array of queue indices for RSS 1762 * 1763 * Sets up the portion of the HW RSS table for the port's VI to distribute 1764 * packets to the Rx queues in @queues. 1765 */ 1766 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues) 1767 { 1768 u16 *rss; 1769 int i, err; 1770 struct adapter *adapter = pi->adapter; 1771 const struct sge_eth_rxq *rxq; 1772 1773 /* Should never be called before setting up sge eth rx queues */ 1774 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 1775 1776 rxq = &adapter->sge.ethrxq[pi->first_rxqset]; 1777 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 1778 if (!rss) 1779 return -ENOMEM; 1780 1781 /* map the queue indices to queue ids */ 1782 for (i = 0; i < pi->rss_size; i++, queues++) 1783 rss[i] = rxq[*queues].rspq.abs_id; 1784 1785 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 1786 pi->rss_size, rss, pi->rss_size); 1787 rte_free(rss); 1788 return err; 1789 } 1790 1791 /** 1792 * setup_rss - configure RSS 1793 * @adapter: the adapter 1794 * 1795 * Sets up RSS to distribute packets to multiple receive queues. We 1796 * configure the RSS CPU lookup table to distribute to the number of HW 1797 * receive queues, and the response queue lookup table to narrow that 1798 * down to the response queues actually configured for each port. 1799 * We always configure the RSS mapping for all ports since the mapping 1800 * table has plenty of entries. 1801 */ 1802 int cxgbe_setup_rss(struct port_info *pi) 1803 { 1804 int j, err; 1805 struct adapter *adapter = pi->adapter; 1806 1807 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 1808 __func__, pi->rss_size, pi->n_rx_qsets); 1809 1810 if (!(pi->flags & PORT_RSS_DONE)) { 1811 if (adapter->flags & FULL_INIT_DONE) { 1812 /* Fill default values with equal distribution */ 1813 for (j = 0; j < pi->rss_size; j++) 1814 pi->rss[j] = j % pi->n_rx_qsets; 1815 1816 err = cxgbe_write_rss(pi, pi->rss); 1817 if (err) 1818 return err; 1819 1820 err = cxgbe_write_rss_conf(pi, pi->rss_hf); 1821 if (err) 1822 return err; 1823 pi->flags |= PORT_RSS_DONE; 1824 } 1825 } 1826 return 0; 1827 } 1828 1829 /* 1830 * Enable NAPI scheduling and interrupt generation for all Rx queues. 1831 */ 1832 static void enable_rx(struct adapter *adap, struct sge_rspq *q) 1833 { 1834 /* 0-increment GTS to start the timer and enable interrupts */ 1835 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) : 1836 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS, 1837 V_SEINTARM(q->intr_params) | 1838 V_INGRESSQID(q->cntxt_id)); 1839 } 1840 1841 void cxgbe_enable_rx_queues(struct port_info *pi) 1842 { 1843 struct adapter *adap = pi->adapter; 1844 struct sge *s = &adap->sge; 1845 unsigned int i; 1846 1847 for (i = 0; i < pi->n_rx_qsets; i++) 1848 enable_rx(adap, &s->ethrxq[pi->first_rxqset + i].rspq); 1849 } 1850 1851 /** 1852 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps. 1853 * @port_type: Firmware Port Type 1854 * @fw_caps: Firmware Port Capabilities 1855 * @speed_caps: Device Info Speed Capabilities 1856 * 1857 * Translate a Firmware Port Capabilities specification to Device Info 1858 * Speed Capabilities. 1859 */ 1860 static void fw_caps_to_speed_caps(enum fw_port_type port_type, 1861 unsigned int fw_caps, 1862 u32 *speed_caps) 1863 { 1864 #define SET_SPEED(__speed_name) \ 1865 do { \ 1866 *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \ 1867 } while (0) 1868 1869 #define FW_CAPS_TO_SPEED(__fw_name) \ 1870 do { \ 1871 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \ 1872 SET_SPEED(__fw_name); \ 1873 } while (0) 1874 1875 switch (port_type) { 1876 case FW_PORT_TYPE_BT_SGMII: 1877 case FW_PORT_TYPE_BT_XFI: 1878 case FW_PORT_TYPE_BT_XAUI: 1879 FW_CAPS_TO_SPEED(SPEED_100M); 1880 FW_CAPS_TO_SPEED(SPEED_1G); 1881 FW_CAPS_TO_SPEED(SPEED_10G); 1882 break; 1883 1884 case FW_PORT_TYPE_KX4: 1885 case FW_PORT_TYPE_KX: 1886 case FW_PORT_TYPE_FIBER_XFI: 1887 case FW_PORT_TYPE_FIBER_XAUI: 1888 case FW_PORT_TYPE_SFP: 1889 case FW_PORT_TYPE_QSFP_10G: 1890 case FW_PORT_TYPE_QSA: 1891 FW_CAPS_TO_SPEED(SPEED_1G); 1892 FW_CAPS_TO_SPEED(SPEED_10G); 1893 break; 1894 1895 case FW_PORT_TYPE_KR: 1896 SET_SPEED(SPEED_10G); 1897 break; 1898 1899 case FW_PORT_TYPE_BP_AP: 1900 case FW_PORT_TYPE_BP4_AP: 1901 SET_SPEED(SPEED_1G); 1902 SET_SPEED(SPEED_10G); 1903 break; 1904 1905 case FW_PORT_TYPE_BP40_BA: 1906 case FW_PORT_TYPE_QSFP: 1907 SET_SPEED(SPEED_40G); 1908 break; 1909 1910 case FW_PORT_TYPE_CR_QSFP: 1911 case FW_PORT_TYPE_SFP28: 1912 case FW_PORT_TYPE_KR_SFP28: 1913 FW_CAPS_TO_SPEED(SPEED_1G); 1914 FW_CAPS_TO_SPEED(SPEED_10G); 1915 FW_CAPS_TO_SPEED(SPEED_25G); 1916 break; 1917 1918 case FW_PORT_TYPE_CR2_QSFP: 1919 SET_SPEED(SPEED_50G); 1920 break; 1921 1922 case FW_PORT_TYPE_KR4_100G: 1923 case FW_PORT_TYPE_CR4_QSFP: 1924 FW_CAPS_TO_SPEED(SPEED_25G); 1925 FW_CAPS_TO_SPEED(SPEED_40G); 1926 FW_CAPS_TO_SPEED(SPEED_50G); 1927 FW_CAPS_TO_SPEED(SPEED_100G); 1928 break; 1929 1930 default: 1931 break; 1932 } 1933 1934 #undef FW_CAPS_TO_SPEED 1935 #undef SET_SPEED 1936 } 1937 1938 /** 1939 * cxgbe_get_speed_caps - Fetch supported speed capabilities 1940 * @pi: Underlying port's info 1941 * @speed_caps: Device Info speed capabilities 1942 * 1943 * Fetch supported speed capabilities of the underlying port. 1944 */ 1945 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) 1946 { 1947 *speed_caps = 0; 1948 1949 fw_caps_to_speed_caps(pi->link_cfg.port_type, pi->link_cfg.pcaps, 1950 speed_caps); 1951 1952 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) 1953 *speed_caps |= RTE_ETH_LINK_SPEED_FIXED; 1954 } 1955 1956 /** 1957 * cxgbe_set_link_status - Set device link up or down. 1958 * @pi: Underlying port's info 1959 * @status: 0 - down, 1 - up 1960 * 1961 * Set the device link up or down. 1962 */ 1963 int cxgbe_set_link_status(struct port_info *pi, bool status) 1964 { 1965 struct adapter *adapter = pi->adapter; 1966 int err = 0; 1967 1968 /* Wait for link up message from firmware to enable Rx path, 1969 * if firmware supports enabling/disabling VI Rx at runtime. 1970 */ 1971 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : status; 1972 pi->vi_en_tx = status; 1973 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, pi->vi_en_rx, 1974 pi->vi_en_tx); 1975 if (err) { 1976 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1977 return err; 1978 } 1979 1980 if (!status) 1981 t4_reset_link_config(adapter, pi->pidx); 1982 1983 return 0; 1984 } 1985 1986 /** 1987 * cxgb_up - enable the adapter 1988 * @adap: adapter being enabled 1989 * 1990 * Called when the first port is enabled, this function performs the 1991 * actions necessary to make an adapter operational, such as completing 1992 * the initialization of HW modules, and enabling interrupts. 1993 */ 1994 int cxgbe_up(struct adapter *adap) 1995 { 1996 enable_rx(adap, &adap->sge.fw_evtq); 1997 t4_sge_tx_monitor_start(adap); 1998 if (is_pf4(adap)) 1999 t4_intr_enable(adap); 2000 adap->flags |= FULL_INIT_DONE; 2001 2002 /* TODO: deadman watchdog ?? */ 2003 return 0; 2004 } 2005 2006 /* 2007 * Close the port 2008 */ 2009 int cxgbe_down(struct port_info *pi) 2010 { 2011 return cxgbe_set_link_status(pi, false); 2012 } 2013 2014 /* 2015 * Release resources when all the ports have been stopped. 2016 */ 2017 void cxgbe_close(struct adapter *adapter) 2018 { 2019 if (adapter->flags & FULL_INIT_DONE) { 2020 tid_free(&adapter->tids); 2021 t4_cleanup_mpstcam(adapter); 2022 t4_cleanup_clip_tbl(adapter); 2023 t4_cleanup_l2t(adapter); 2024 t4_cleanup_smt(adapter); 2025 if (is_pf4(adapter)) 2026 t4_intr_disable(adapter); 2027 t4_sge_tx_monitor_stop(adapter); 2028 t4_free_sge_resources(adapter); 2029 adapter->flags &= ~FULL_INIT_DONE; 2030 } 2031 2032 cxgbe_cfg_queues_free(adapter); 2033 2034 if (is_pf4(adapter) && (adapter->flags & FW_OK)) 2035 t4_fw_bye(adapter, adapter->mbox); 2036 } 2037 2038 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx, 2039 u32 *smt_size) 2040 { 2041 u32 params[2], smt_val[2]; 2042 int ret; 2043 2044 params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START); 2045 params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE); 2046 2047 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 2048 2, params, smt_val); 2049 2050 /* if FW doesn't recognize this command then set it to default setting 2051 * which is start index as 0 and size as 256. 2052 */ 2053 if (ret < 0) { 2054 *smt_start_idx = 0; 2055 *smt_size = SMT_SIZE; 2056 } else { 2057 *smt_start_idx = smt_val[0]; 2058 /* smt size can be zero, if nsmt is not yet configured in 2059 * the config file or set as zero, then configure all the 2060 * remaining entries to this PF itself. 2061 */ 2062 if (!smt_val[1]) 2063 *smt_size = SMT_SIZE - *smt_start_idx; 2064 else 2065 *smt_size = smt_val[1]; 2066 } 2067 } 2068 2069 int cxgbe_probe(struct adapter *adapter) 2070 { 2071 u32 smt_start_idx, smt_size; 2072 struct port_info *pi; 2073 int func, i; 2074 int err = 0; 2075 u32 whoami; 2076 int chip; 2077 2078 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 2079 chip = t4_get_chip_type(adapter, 2080 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id)); 2081 if (chip < 0) 2082 return chip; 2083 2084 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 2085 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami); 2086 2087 adapter->mbox = func; 2088 adapter->pf = func; 2089 2090 t4_os_lock_init(&adapter->mbox_lock); 2091 TAILQ_INIT(&adapter->mbox_list); 2092 t4_os_lock_init(&adapter->win0_lock); 2093 2094 err = t4_prep_adapter(adapter); 2095 if (err) 2096 return err; 2097 2098 setup_memwin(adapter); 2099 err = adap_init0(adapter); 2100 if (err) { 2101 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 2102 __func__, err); 2103 goto out_free; 2104 } 2105 2106 if (!is_t4(adapter->params.chip)) { 2107 /* 2108 * The userspace doorbell BAR is split evenly into doorbell 2109 * regions, each associated with an egress queue. If this 2110 * per-queue region is large enough (at least UDBS_SEG_SIZE) 2111 * then it can be used to submit a tx work request with an 2112 * implied doorbell. Enable write combining on the BAR if 2113 * there is room for such work requests. 2114 */ 2115 int s_qpp, qpp, num_seg; 2116 2117 s_qpp = (S_QUEUESPERPAGEPF0 + 2118 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 2119 adapter->pf); 2120 qpp = 1 << ((t4_read_reg(adapter, 2121 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 2122 & M_QUEUESPERPAGEPF0); 2123 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 2124 if (qpp > num_seg) 2125 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 2126 2127 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 2128 if (!adapter->bar2) { 2129 dev_err(adapter, "cannot map device bar2 region\n"); 2130 err = -ENOMEM; 2131 goto out_free; 2132 } 2133 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 2134 V_STATMODE(0)); 2135 } 2136 2137 for_each_port(adapter, i) { 2138 const unsigned int numa_node = rte_socket_id(); 2139 char name[RTE_ETH_NAME_MAX_LEN]; 2140 struct rte_eth_dev *eth_dev; 2141 2142 snprintf(name, sizeof(name), "%s_%d", 2143 adapter->pdev->device.name, i); 2144 2145 if (i == 0) { 2146 /* First port is already allocated by DPDK */ 2147 eth_dev = adapter->eth_dev; 2148 goto allocate_mac; 2149 } 2150 2151 /* 2152 * now do all data allocation - for eth_dev structure, 2153 * and internal (private) data for the remaining ports 2154 */ 2155 2156 /* reserve an ethdev entry */ 2157 eth_dev = rte_eth_dev_allocate(name); 2158 if (!eth_dev) 2159 goto out_free; 2160 2161 eth_dev->data->dev_private = 2162 rte_zmalloc_socket(name, sizeof(struct port_info), 2163 RTE_CACHE_LINE_SIZE, numa_node); 2164 if (!eth_dev->data->dev_private) 2165 goto out_free; 2166 2167 allocate_mac: 2168 pi = eth_dev->data->dev_private; 2169 adapter->port[i] = pi; 2170 pi->eth_dev = eth_dev; 2171 pi->adapter = adapter; 2172 pi->xact_addr_filt = -1; 2173 pi->port_id = i; 2174 pi->pidx = i; 2175 2176 pi->eth_dev->device = &adapter->pdev->device; 2177 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 2178 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 2179 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 2180 2181 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 2182 2183 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 2184 RTE_ETHER_ADDR_LEN, 0); 2185 if (!pi->eth_dev->data->mac_addrs) { 2186 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 2187 __func__); 2188 err = -1; 2189 goto out_free; 2190 } 2191 2192 if (i > 0) { 2193 /* First port will be notified by upper layer */ 2194 rte_eth_dev_probing_finish(eth_dev); 2195 } 2196 } 2197 2198 if (adapter->flags & FW_OK) { 2199 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 2200 if (err) { 2201 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 2202 __func__, err); 2203 goto out_free; 2204 } 2205 } 2206 2207 err = cxgbe_cfg_queues(adapter->eth_dev); 2208 if (err) 2209 goto out_free; 2210 2211 cxgbe_print_adapter_info(adapter); 2212 cxgbe_print_port_info(adapter); 2213 2214 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 2215 adapter->clipt_end); 2216 if (!adapter->clipt) { 2217 /* We tolerate a lack of clip_table, giving up some 2218 * functionality 2219 */ 2220 dev_warn(adapter, "could not allocate CLIP. Continuing\n"); 2221 } 2222 2223 adap_smt_index(adapter, &smt_start_idx, &smt_size); 2224 adapter->smt = t4_init_smt(smt_start_idx, smt_size); 2225 if (!adapter->smt) 2226 dev_warn(adapter, "could not allocate SMT, continuing\n"); 2227 2228 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 2229 if (!adapter->l2t) { 2230 /* We tolerate a lack of L2T, giving up some functionality */ 2231 dev_warn(adapter, "could not allocate L2T. Continuing\n"); 2232 } 2233 2234 if (tid_init(&adapter->tids) < 0) { 2235 /* Disable filtering support */ 2236 dev_warn(adapter, "could not allocate TID table, " 2237 "filter support disabled. Continuing\n"); 2238 } 2239 2240 t4_os_lock_init(&adapter->flow_lock); 2241 2242 adapter->mpstcam = t4_init_mpstcam(adapter); 2243 if (!adapter->mpstcam) 2244 dev_warn(adapter, "could not allocate mps tcam table." 2245 " Continuing\n"); 2246 2247 if (is_hashfilter(adapter)) { 2248 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) { 2249 u32 hash_base, hash_reg; 2250 2251 hash_reg = A_LE_DB_TID_HASHBASE; 2252 hash_base = t4_read_reg(adapter, hash_reg); 2253 adapter->tids.hash_base = hash_base / 4; 2254 } 2255 } else { 2256 /* Disable hash filtering support */ 2257 dev_warn(adapter, 2258 "Maskless filter support disabled. Continuing\n"); 2259 } 2260 2261 err = cxgbe_init_rss(adapter); 2262 if (err) 2263 goto out_free; 2264 2265 return 0; 2266 2267 out_free: 2268 cxgbe_cfg_queues_free(adapter); 2269 2270 for_each_port(adapter, i) { 2271 pi = adap2pinfo(adapter, i); 2272 if (pi->viid != 0) 2273 t4_free_vi(adapter, adapter->mbox, adapter->pf, 2274 0, pi->viid); 2275 rte_eth_dev_release_port(pi->eth_dev); 2276 } 2277 2278 if (adapter->flags & FW_OK) 2279 t4_fw_bye(adapter, adapter->mbox); 2280 return -err; 2281 } 2282