1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <sys/stat.h> 8 #include <stdio.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <string.h> 12 #include <unistd.h> 13 #include <stdarg.h> 14 #include <inttypes.h> 15 #include <fcntl.h> 16 #include <netinet/in.h> 17 18 #include <rte_byteorder.h> 19 #include <rte_common.h> 20 #include <rte_cycles.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <ethdev_driver.h> 32 #include <ethdev_pci.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 #include <rte_kvargs.h> 36 37 #include "base/common.h" 38 #include "base/t4_regs.h" 39 #include "base/t4_msg.h" 40 #include "cxgbe.h" 41 #include "cxgbe_pfvf.h" 42 #include "clip_tbl.h" 43 #include "l2t.h" 44 #include "smt.h" 45 #include "mps_tcam.h" 46 47 static const u16 cxgbe_filter_mode_features[] = { 48 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | 49 F_PROTOCOL | F_PORT), 50 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | 51 F_PROTOCOL | F_FCOE), 52 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | 53 F_PORT), 54 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | 55 F_FCOE), 56 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PORT | 57 F_FCOE), 58 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_TOS | 59 F_PORT | F_FCOE), 60 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | 61 F_FCOE), 62 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | 63 F_FCOE), 64 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | 65 F_FCOE), 66 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | 67 F_FCOE), 68 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VLAN | F_PORT | 69 F_FCOE), 70 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VNIC_ID | F_PORT | 71 F_FCOE), 72 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_PROTOCOL | F_TOS | 73 F_PORT | F_FCOE), 74 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT), 75 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_FCOE), 76 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT), 77 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_FCOE), 78 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT), 79 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE), 80 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | 81 F_PORT), 82 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | 83 F_FCOE), 84 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VLAN | F_PORT | 85 F_FCOE), 86 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VNIC_ID | F_PORT | 87 F_FCOE), 88 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VLAN | F_PORT | F_FCOE), 89 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 90 (F_FRAGMENTATION | F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_FCOE), 91 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT | 92 F_FCOE), 93 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE), 94 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT | F_FCOE), 95 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT | 96 F_FCOE), 97 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VLAN | F_PORT | F_FCOE), 98 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 99 (F_FRAGMENTATION | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE), 100 (F_FRAGMENTATION | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE), 101 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE), 102 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VNIC_ID | F_FCOE), 103 (F_FRAGMENTATION | F_VLAN | F_VNIC_ID | F_PORT | F_FCOE), 104 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT | 105 F_FCOE), 106 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE), 107 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT), 108 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT), 109 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | F_PORT), 110 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT), 111 (F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE), 112 (F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE), 113 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT | F_FCOE), 114 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | F_PORT | F_FCOE), 115 (F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_PORT), 116 }; 117 118 /** 119 * Allocate a chunk of memory. The allocated memory is cleared. 120 */ 121 void *t4_alloc_mem(size_t size) 122 { 123 return rte_zmalloc(NULL, size, 0); 124 } 125 126 /** 127 * Free memory allocated through t4_alloc_mem(). 128 */ 129 void t4_free_mem(void *addr) 130 { 131 rte_free(addr); 132 } 133 134 /* 135 * Response queue handler for the FW event queue. 136 */ 137 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 138 __rte_unused const struct pkt_gl *gl) 139 { 140 u8 opcode = ((const struct rss_header *)rsp)->opcode; 141 142 rsp++; /* skip RSS header */ 143 144 /* 145 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 146 */ 147 if (unlikely(opcode == CPL_FW4_MSG && 148 ((const struct cpl_fw4_msg *)rsp)->type == 149 FW_TYPE_RSSCPL)) { 150 rsp++; 151 opcode = ((const struct rss_header *)rsp)->opcode; 152 rsp++; 153 if (opcode != CPL_SGE_EGR_UPDATE) { 154 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 155 opcode); 156 goto out; 157 } 158 } 159 160 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 161 /* do nothing */ 162 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 163 const struct cpl_fw6_msg *msg = (const void *)rsp; 164 165 t4_handle_fw_rpl(q->adapter, msg->data); 166 } else if (opcode == CPL_ABORT_RPL_RSS) { 167 const struct cpl_abort_rpl_rss *p = (const void *)rsp; 168 169 cxgbe_hash_del_filter_rpl(q->adapter, p); 170 } else if (opcode == CPL_SET_TCB_RPL) { 171 const struct cpl_set_tcb_rpl *p = (const void *)rsp; 172 173 cxgbe_filter_rpl(q->adapter, p); 174 } else if (opcode == CPL_ACT_OPEN_RPL) { 175 const struct cpl_act_open_rpl *p = (const void *)rsp; 176 177 cxgbe_hash_filter_rpl(q->adapter, p); 178 } else if (opcode == CPL_L2T_WRITE_RPL) { 179 const struct cpl_l2t_write_rpl *p = (const void *)rsp; 180 181 cxgbe_do_l2t_write_rpl(q->adapter, p); 182 } else if (opcode == CPL_SMT_WRITE_RPL) { 183 const struct cpl_smt_write_rpl *p = (const void *)rsp; 184 185 cxgbe_do_smt_write_rpl(q->adapter, p); 186 } else { 187 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 188 opcode); 189 } 190 out: 191 return 0; 192 } 193 194 /** 195 * Setup sge control queues to pass control information. 196 */ 197 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter) 198 { 199 struct sge *s = &adapter->sge; 200 int err = 0, i = 0; 201 202 for_each_port(adapter, i) { 203 struct port_info *pi = adap2pinfo(adapter, i); 204 char name[RTE_ETH_NAME_MAX_LEN]; 205 struct sge_ctrl_txq *q = &s->ctrlq[i]; 206 207 q->q.size = 1024; 208 err = t4_sge_alloc_ctrl_txq(adapter, q, 209 adapter->eth_dev, i, 210 s->fw_evtq.cntxt_id, 211 rte_socket_id()); 212 if (err) { 213 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d", 214 err); 215 goto out; 216 } 217 snprintf(name, sizeof(name), "%s_ctrl_pool_%d", 218 pi->eth_dev->device->driver->name, 219 pi->eth_dev->data->port_id); 220 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size, 221 RTE_CACHE_LINE_SIZE, 222 RTE_MBUF_PRIV_ALIGN, 223 RTE_MBUF_DEFAULT_BUF_SIZE, 224 SOCKET_ID_ANY); 225 if (!q->mb_pool) { 226 err = -rte_errno; 227 dev_err(adapter, 228 "Can't create ctrl pool for port %d. Err: %d\n", 229 pi->eth_dev->data->port_id, err); 230 goto out; 231 } 232 } 233 return 0; 234 out: 235 t4_free_sge_resources(adapter); 236 return err; 237 } 238 239 /** 240 * cxgbe_poll_for_completion: Poll rxq for completion 241 * @q: rxq to poll 242 * @ms: milliseconds to delay 243 * @cnt: number of times to poll 244 * @c: completion to check for 'done' status 245 * 246 * Polls the rxq for reples until completion is done or the count 247 * expires. 248 */ 249 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms, 250 unsigned int cnt, struct t4_completion *c) 251 { 252 unsigned int i; 253 unsigned int work_done, budget = 32; 254 255 if (!c) 256 return -EINVAL; 257 258 for (i = 0; i < cnt; i++) { 259 cxgbe_poll(q, NULL, budget, &work_done); 260 t4_os_lock(&c->lock); 261 if (c->done) { 262 t4_os_unlock(&c->lock); 263 return 0; 264 } 265 t4_os_unlock(&c->lock); 266 rte_delay_ms(ms); 267 } 268 return -ETIMEDOUT; 269 } 270 271 int cxgbe_setup_sge_fwevtq(struct adapter *adapter) 272 { 273 struct sge *s = &adapter->sge; 274 int err = 0; 275 int msi_idx = 0; 276 277 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 278 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 279 rte_socket_id()); 280 return err; 281 } 282 283 static int closest_timer(const struct sge *s, int time) 284 { 285 unsigned int i, match = 0; 286 int delta, min_delta = INT_MAX; 287 288 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 289 delta = time - s->timer_val[i]; 290 if (delta < 0) 291 delta = -delta; 292 if (delta < min_delta) { 293 min_delta = delta; 294 match = i; 295 } 296 } 297 return match; 298 } 299 300 static int closest_thres(const struct sge *s, int thres) 301 { 302 unsigned int i, match = 0; 303 int delta, min_delta = INT_MAX; 304 305 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 306 delta = thres - s->counter_val[i]; 307 if (delta < 0) 308 delta = -delta; 309 if (delta < min_delta) { 310 min_delta = delta; 311 match = i; 312 } 313 } 314 return match; 315 } 316 317 /** 318 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 319 * @q: the Rx queue 320 * @us: the hold-off time in us, or 0 to disable timer 321 * @cnt: the hold-off packet count, or 0 to disable counter 322 * 323 * Sets an Rx queue's interrupt hold-off time and packet count. At least 324 * one of the two needs to be enabled for the queue to generate interrupts. 325 */ 326 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 327 unsigned int cnt) 328 { 329 struct adapter *adap = q->adapter; 330 unsigned int timer_val; 331 332 if (cnt) { 333 int err; 334 u32 v, new_idx; 335 336 new_idx = closest_thres(&adap->sge, cnt); 337 if (q->desc && q->pktcnt_idx != new_idx) { 338 /* the queue has already been created, update it */ 339 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 340 V_FW_PARAMS_PARAM_X( 341 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 342 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 343 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 344 &v, &new_idx); 345 if (err) 346 return err; 347 } 348 q->pktcnt_idx = new_idx; 349 } 350 351 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 352 closest_timer(&adap->sge, us); 353 354 if ((us | cnt) == 0) 355 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 356 else 357 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 358 V_QINTR_CNT_EN(cnt > 0); 359 return 0; 360 } 361 362 /** 363 * Allocate an active-open TID and set it to the supplied value. 364 */ 365 int cxgbe_alloc_atid(struct tid_info *t, void *data) 366 { 367 int atid = -1; 368 369 t4_os_lock(&t->atid_lock); 370 if (t->afree) { 371 union aopen_entry *p = t->afree; 372 373 atid = p - t->atid_tab; 374 t->afree = p->next; 375 p->data = data; 376 t->atids_in_use++; 377 } 378 t4_os_unlock(&t->atid_lock); 379 return atid; 380 } 381 382 /** 383 * Release an active-open TID. 384 */ 385 void cxgbe_free_atid(struct tid_info *t, unsigned int atid) 386 { 387 union aopen_entry *p = &t->atid_tab[atid]; 388 389 t4_os_lock(&t->atid_lock); 390 p->next = t->afree; 391 t->afree = p; 392 t->atids_in_use--; 393 t4_os_unlock(&t->atid_lock); 394 } 395 396 /** 397 * Populate a TID_RELEASE WR. Caller must properly size the skb. 398 */ 399 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid) 400 { 401 struct cpl_tid_release *req; 402 403 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *); 404 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 405 } 406 407 /** 408 * Release a TID and inform HW. If we are unable to allocate the release 409 * message we defer to a work queue. 410 */ 411 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 412 unsigned short family) 413 { 414 struct rte_mbuf *mbuf; 415 struct adapter *adap = container_of(t, struct adapter, tids); 416 417 WARN_ON(tid >= t->ntids); 418 419 if (t->tid_tab[tid]) { 420 t->tid_tab[tid] = NULL; 421 __atomic_sub_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); 422 if (t->hash_base && tid >= t->hash_base) { 423 if (family == FILTER_TYPE_IPV4) 424 __atomic_sub_fetch(&t->hash_tids_in_use, 1, 425 __ATOMIC_RELAXED); 426 } else { 427 if (family == FILTER_TYPE_IPV4) 428 __atomic_sub_fetch(&t->tids_in_use, 1, 429 __ATOMIC_RELAXED); 430 } 431 } 432 433 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool); 434 if (mbuf) { 435 mbuf->data_len = sizeof(struct cpl_tid_release); 436 mbuf->pkt_len = mbuf->data_len; 437 mk_tid_release(mbuf, tid); 438 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf); 439 } 440 } 441 442 /** 443 * Insert a TID. 444 */ 445 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, 446 unsigned short family) 447 { 448 t->tid_tab[tid] = data; 449 if (t->hash_base && tid >= t->hash_base) { 450 if (family == FILTER_TYPE_IPV4) 451 __atomic_add_fetch(&t->hash_tids_in_use, 1, 452 __ATOMIC_RELAXED); 453 } else { 454 if (family == FILTER_TYPE_IPV4) 455 __atomic_add_fetch(&t->tids_in_use, 1, 456 __ATOMIC_RELAXED); 457 } 458 459 __atomic_add_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED); 460 } 461 462 /** 463 * Free TID tables. 464 */ 465 static void tid_free(struct tid_info *t) 466 { 467 if (t->tid_tab) { 468 rte_bitmap_free(t->ftid_bmap); 469 470 if (t->ftid_bmap_array) 471 t4_os_free(t->ftid_bmap_array); 472 473 t4_os_free(t->tid_tab); 474 } 475 476 memset(t, 0, sizeof(struct tid_info)); 477 } 478 479 /** 480 * Allocate and initialize the TID tables. Returns 0 on success. 481 */ 482 static int tid_init(struct tid_info *t) 483 { 484 size_t size; 485 unsigned int ftid_bmap_size; 486 unsigned int natids = t->natids; 487 unsigned int max_ftids = t->nftids; 488 489 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids); 490 size = t->ntids * sizeof(*t->tid_tab) + 491 max_ftids * sizeof(*t->ftid_tab) + 492 natids * sizeof(*t->atid_tab); 493 494 t->tid_tab = t4_os_alloc(size); 495 if (!t->tid_tab) 496 return -ENOMEM; 497 498 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 499 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids]; 500 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size); 501 if (!t->ftid_bmap_array) { 502 tid_free(t); 503 return -ENOMEM; 504 } 505 506 t4_os_lock_init(&t->atid_lock); 507 t4_os_lock_init(&t->ftid_lock); 508 509 t->afree = NULL; 510 t->atids_in_use = 0; 511 t->tids_in_use = 0; 512 t->conns_in_use = 0; 513 514 /* Setup the free list for atid_tab and clear the stid bitmap. */ 515 if (natids) { 516 while (--natids) 517 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 518 t->afree = t->atid_tab; 519 } 520 521 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array, 522 ftid_bmap_size); 523 if (!t->ftid_bmap) { 524 tid_free(t); 525 return -ENOMEM; 526 } 527 528 return 0; 529 } 530 531 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 532 unsigned int us, unsigned int cnt, 533 unsigned int size, unsigned int iqe_size) 534 { 535 q->adapter = adap; 536 cxgb4_set_rspq_intr_params(q, us, cnt); 537 q->iqe_len = iqe_size; 538 q->size = size; 539 } 540 541 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev) 542 { 543 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 544 struct adapter *adap = pi->adapter; 545 u16 first_txq = 0, first_rxq = 0; 546 struct sge *s = &adap->sge; 547 u16 i, max_rxqs, max_txqs; 548 549 max_rxqs = s->max_ethqsets; 550 max_txqs = s->max_ethqsets; 551 for_each_port(adap, i) { 552 temp_pi = adap2pinfo(adap, i); 553 if (i == pi->port_id) 554 break; 555 556 if (max_rxqs <= temp_pi->n_rx_qsets || 557 max_txqs <= temp_pi->n_tx_qsets) 558 return -ENOMEM; 559 560 first_rxq += temp_pi->n_rx_qsets; 561 first_txq += temp_pi->n_tx_qsets; 562 max_rxqs -= temp_pi->n_rx_qsets; 563 max_txqs -= temp_pi->n_tx_qsets; 564 } 565 566 if ((eth_dev->data->nb_rx_queues < 1) || 567 (eth_dev->data->nb_tx_queues < 1)) 568 return -EINVAL; 569 570 if (eth_dev->data->nb_rx_queues > max_rxqs || 571 eth_dev->data->nb_tx_queues > max_txqs) 572 return -EINVAL; 573 574 /* We must configure RSS, since config has changed*/ 575 pi->flags &= ~PORT_RSS_DONE; 576 577 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 578 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 579 pi->first_rxqset = first_rxq; 580 pi->first_txqset = first_txq; 581 582 return 0; 583 } 584 585 void cxgbe_cfg_queues_free(struct adapter *adap) 586 { 587 if (adap->sge.ethtxq) { 588 rte_free(adap->sge.ethtxq); 589 adap->sge.ethtxq = NULL; 590 } 591 592 if (adap->sge.ethrxq) { 593 rte_free(adap->sge.ethrxq); 594 adap->sge.ethrxq = NULL; 595 } 596 597 adap->flags &= ~CFG_QUEUES; 598 } 599 600 int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev) 601 { 602 struct port_info *pi = eth_dev->data->dev_private; 603 struct adapter *adap = pi->adapter; 604 struct sge *s = &adap->sge; 605 u16 i; 606 607 if (!(adap->flags & CFG_QUEUES)) { 608 s->ethrxq = rte_calloc_socket(NULL, s->max_ethqsets, 609 sizeof(struct sge_eth_rxq), 0, 610 rte_socket_id()); 611 if (!s->ethrxq) 612 return -ENOMEM; 613 614 s->ethtxq = rte_calloc_socket(NULL, s->max_ethqsets, 615 sizeof(struct sge_eth_txq), 0, 616 rte_socket_id()); 617 if (!s->ethtxq) { 618 rte_free(s->ethrxq); 619 s->ethrxq = NULL; 620 return -ENOMEM; 621 } 622 623 for (i = 0; i < s->max_ethqsets; i++) { 624 struct sge_eth_rxq *r = &s->ethrxq[i]; 625 struct sge_eth_txq *t = &s->ethtxq[i]; 626 627 init_rspq(adap, &r->rspq, 5, 32, 1024, 64); 628 r->fl.size = 1024; 629 630 t->q.size = 1024; 631 } 632 633 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 634 adap->flags |= CFG_QUEUES; 635 } 636 637 return 0; 638 } 639 640 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 641 { 642 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 643 &pi->stats_base); 644 } 645 646 void cxgbe_stats_reset(struct port_info *pi) 647 { 648 t4_clr_port_stats(pi->adapter, pi->tx_chan); 649 } 650 651 static void setup_memwin(struct adapter *adap) 652 { 653 u32 mem_win0_base; 654 655 /* For T5, only relative offset inside the PCIe BAR is passed */ 656 mem_win0_base = MEMWIN0_BASE; 657 658 /* 659 * Set up memory window for accessing adapter memory ranges. (Read 660 * back MA register to ensure that changes propagate before we attempt 661 * to use the new values.) 662 */ 663 t4_write_reg(adap, 664 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 665 MEMWIN_NIC), 666 mem_win0_base | V_BIR(0) | 667 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 668 t4_read_reg(adap, 669 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 670 MEMWIN_NIC)); 671 } 672 673 int cxgbe_init_rss(struct adapter *adap) 674 { 675 unsigned int i; 676 677 if (is_pf4(adap)) { 678 int err; 679 680 err = t4_init_rss_mode(adap, adap->mbox); 681 if (err) 682 return err; 683 } 684 685 for_each_port(adap, i) { 686 struct port_info *pi = adap2pinfo(adap, i); 687 688 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 689 if (!pi->rss) 690 return -ENOMEM; 691 692 pi->rss_hf = CXGBE_RSS_HF_ALL; 693 } 694 return 0; 695 } 696 697 /** 698 * Dump basic information about the adapter. 699 */ 700 void cxgbe_print_adapter_info(struct adapter *adap) 701 { 702 /** 703 * Hardware/Firmware/etc. Version/Revision IDs. 704 */ 705 t4_dump_version_info(adap); 706 } 707 708 void cxgbe_print_port_info(struct adapter *adap) 709 { 710 int i; 711 char buf[80]; 712 struct rte_pci_addr *loc = &adap->pdev->addr; 713 714 for_each_port(adap, i) { 715 const struct port_info *pi = adap2pinfo(adap, i); 716 char *bufp = buf; 717 718 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 719 bufp += sprintf(bufp, "100M/"); 720 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 721 bufp += sprintf(bufp, "1G/"); 722 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 723 bufp += sprintf(bufp, "10G/"); 724 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 725 bufp += sprintf(bufp, "25G/"); 726 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 727 bufp += sprintf(bufp, "40G/"); 728 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 729 bufp += sprintf(bufp, "50G/"); 730 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 731 bufp += sprintf(bufp, "100G/"); 732 if (bufp != buf) 733 --bufp; 734 sprintf(bufp, "BASE-%s", 735 t4_get_port_type_description( 736 (enum fw_port_type)pi->link_cfg.port_type)); 737 738 dev_info(adap, 739 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 740 loc->domain, loc->bus, loc->devid, loc->function, 741 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 742 (adap->flags & USING_MSIX) ? " MSI-X" : 743 (adap->flags & USING_MSI) ? " MSI" : ""); 744 } 745 } 746 747 static int check_devargs_handler(const char *key, const char *value, void *p) 748 { 749 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) || 750 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) || 751 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) { 752 if (!strncmp(value, "1", 1)) { 753 bool *dst_val = (bool *)p; 754 755 *dst_val = true; 756 } 757 } 758 759 if (!strncmp(key, CXGBE_DEVARG_PF_FILTER_MODE, strlen(key)) || 760 !strncmp(key, CXGBE_DEVARG_PF_FILTER_MASK, strlen(key))) { 761 u32 *dst_val = (u32 *)p; 762 char *endptr = NULL; 763 u32 arg_val; 764 765 arg_val = strtoul(value, &endptr, 16); 766 if (errno || endptr == value) 767 return -EINVAL; 768 769 *dst_val = arg_val; 770 } 771 772 return 0; 773 } 774 775 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key, 776 void *p) 777 { 778 struct rte_kvargs *kvlist; 779 int ret = 0; 780 781 if (!devargs) 782 return 0; 783 784 kvlist = rte_kvargs_parse(devargs->args, NULL); 785 if (!kvlist) 786 return 0; 787 788 if (!rte_kvargs_count(kvlist, key)) 789 goto out; 790 791 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p); 792 793 out: 794 rte_kvargs_free(kvlist); 795 796 return ret; 797 } 798 799 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst, 800 const char *key, bool default_value) 801 { 802 struct rte_pci_device *pdev = adap->pdev; 803 int ret; 804 bool devarg_value = default_value; 805 806 *dst = default_value; 807 if (!pdev) 808 return; 809 810 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); 811 if (ret) 812 return; 813 814 *dst = devarg_value; 815 } 816 817 static void cxgbe_get_devargs_u32(struct adapter *adap, u32 *dst, 818 const char *key, u32 default_value) 819 { 820 struct rte_pci_device *pdev = adap->pdev; 821 u32 devarg_value = default_value; 822 int ret; 823 824 *dst = default_value; 825 if (!pdev) 826 return; 827 828 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value); 829 if (ret) 830 return; 831 832 *dst = devarg_value; 833 } 834 835 void cxgbe_process_devargs(struct adapter *adap) 836 { 837 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan, 838 CXGBE_DEVARG_CMN_KEEP_OVLAN, false); 839 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency, 840 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false); 841 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up, 842 CXGBE_DEVARG_VF_FORCE_LINK_UP, false); 843 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermode, 844 CXGBE_DEVARG_PF_FILTER_MODE, 0); 845 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermask, 846 CXGBE_DEVARG_PF_FILTER_MASK, 0); 847 } 848 849 static void configure_vlan_types(struct adapter *adapter) 850 { 851 int i; 852 853 for_each_port(adapter, i) { 854 /* OVLAN Type 0x88a8 */ 855 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0), 856 V_OVLAN_MASK(M_OVLAN_MASK) | 857 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 858 V_OVLAN_MASK(M_OVLAN_MASK) | 859 V_OVLAN_ETYPE(0x88a8)); 860 /* OVLAN Type 0x9100 */ 861 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1), 862 V_OVLAN_MASK(M_OVLAN_MASK) | 863 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 864 V_OVLAN_MASK(M_OVLAN_MASK) | 865 V_OVLAN_ETYPE(0x9100)); 866 867 /* IVLAN 0X8100 */ 868 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), 869 V_IVLAN_ETYPE(M_IVLAN_ETYPE), 870 V_IVLAN_ETYPE(0x8100)); 871 872 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), 873 F_OVLAN_EN0 | F_OVLAN_EN1 | 874 F_IVLAN_EN, 875 F_OVLAN_EN0 | F_OVLAN_EN1 | 876 F_IVLAN_EN); 877 } 878 879 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1), 880 V_RM_OVLAN(!adapter->devargs.keep_ovlan)); 881 } 882 883 static int cxgbe_get_filter_vnic_mode_from_devargs(u32 val) 884 { 885 u32 vnic_mode; 886 887 vnic_mode = val & (CXGBE_DEVARGS_FILTER_MODE_PF_VF | 888 CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER); 889 if (vnic_mode) { 890 switch (vnic_mode) { 891 case CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER: 892 return CXGBE_FILTER_VNIC_MODE_OVLAN; 893 case CXGBE_DEVARGS_FILTER_MODE_PF_VF: 894 return CXGBE_FILTER_VNIC_MODE_PFVF; 895 default: 896 return -EINVAL; 897 } 898 } 899 900 return CXGBE_FILTER_VNIC_MODE_NONE; 901 } 902 903 static int cxgbe_get_filter_mode_from_devargs(u32 val, bool closest_match) 904 { 905 int vnic_mode, fmode = 0; 906 bool found = false; 907 u8 i; 908 909 if (val >= CXGBE_DEVARGS_FILTER_MODE_MAX) { 910 pr_err("Unsupported flags set in filter mode. Must be < 0x%x\n", 911 CXGBE_DEVARGS_FILTER_MODE_MAX); 912 return -ERANGE; 913 } 914 915 vnic_mode = cxgbe_get_filter_vnic_mode_from_devargs(val); 916 if (vnic_mode < 0) { 917 pr_err("Unsupported Vnic-mode, more than 1 Vnic-mode selected\n"); 918 return vnic_mode; 919 } 920 921 if (vnic_mode) 922 fmode |= F_VNIC_ID; 923 if (val & CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT) 924 fmode |= F_PORT; 925 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC) 926 fmode |= F_MACMATCH; 927 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE) 928 fmode |= F_ETHERTYPE; 929 if (val & CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER) 930 fmode |= F_VLAN; 931 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_TOS) 932 fmode |= F_TOS; 933 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL) 934 fmode |= F_PROTOCOL; 935 936 for (i = 0; i < ARRAY_SIZE(cxgbe_filter_mode_features); i++) { 937 if ((cxgbe_filter_mode_features[i] & fmode) == fmode) { 938 found = true; 939 break; 940 } 941 } 942 943 if (!found) 944 return -EINVAL; 945 946 return closest_match ? cxgbe_filter_mode_features[i] : fmode; 947 } 948 949 static int configure_filter_mode_mask(struct adapter *adap) 950 { 951 u32 params[2], val[2], nparams = 0; 952 int ret; 953 954 if (!adap->devargs.filtermode && !adap->devargs.filtermask) 955 return 0; 956 957 if (!adap->devargs.filtermode || !adap->devargs.filtermask) { 958 pr_err("Unsupported, Provide both filtermode and filtermask devargs\n"); 959 return -EINVAL; 960 } 961 962 if (adap->devargs.filtermask & ~adap->devargs.filtermode) { 963 pr_err("Unsupported, filtermask (0x%x) must be subset of filtermode (0x%x)\n", 964 adap->devargs.filtermask, adap->devargs.filtermode); 965 966 return -EINVAL; 967 } 968 969 params[0] = CXGBE_FW_PARAM_DEV(FILTER) | 970 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 971 972 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermode, 973 true); 974 if (ret < 0) { 975 pr_err("Unsupported filtermode devargs combination:0x%x\n", 976 adap->devargs.filtermode); 977 return ret; 978 } 979 980 val[0] = V_FW_PARAMS_PARAM_FILTER_MODE(ret); 981 982 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermask, 983 false); 984 if (ret < 0) { 985 pr_err("Unsupported filtermask devargs combination:0x%x\n", 986 adap->devargs.filtermask); 987 return ret; 988 } 989 990 val[0] |= V_FW_PARAMS_PARAM_FILTER_MASK(ret); 991 992 nparams++; 993 994 ret = cxgbe_get_filter_vnic_mode_from_devargs(adap->devargs.filtermode); 995 if (ret < 0) 996 return ret; 997 998 if (ret) { 999 params[1] = CXGBE_FW_PARAM_DEV(FILTER) | 1000 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 1001 1002 val[1] = ret - 1; 1003 1004 nparams++; 1005 } 1006 1007 return t4_set_params(adap, adap->mbox, adap->pf, 0, nparams, 1008 params, val); 1009 } 1010 1011 #define CXGBE_FW_CONFIG_PATH_T5 "/lib/firmware/cxgb4/t5-config.txt" 1012 #define CXGBE_FW_CONFIG_PATH_T6 "/lib/firmware/cxgb4/t6-config.txt" 1013 1014 /* 1015 * Load firmware configuration from file in /lib/firmware/cxgb4/ path, 1016 * if it is present. 1017 */ 1018 static int cxgbe_load_fw_config_from_filesystem(struct adapter *adap, 1019 const char **config_name, 1020 u32 *mem_type, u32 *mem_addr) 1021 { 1022 u32 param, val, mtype, maddr; 1023 const char *fw_cfg_path; 1024 char *fw_cfg = NULL; 1025 struct stat st; 1026 int ret, fd; 1027 1028 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { 1029 case CHELSIO_T5: 1030 fw_cfg_path = CXGBE_FW_CONFIG_PATH_T5; 1031 break; 1032 case CHELSIO_T6: 1033 fw_cfg_path = CXGBE_FW_CONFIG_PATH_T6; 1034 break; 1035 default: 1036 return -ENOENT; 1037 } 1038 1039 ret = open(fw_cfg_path, O_RDONLY); 1040 if (ret < 0) { 1041 dev_debug(adap, "Couldn't open FW config file\n"); 1042 return ret; 1043 } 1044 1045 fd = ret; 1046 1047 ret = fstat(fd, &st); 1048 if (ret < 0) { 1049 dev_debug(adap, "Couldn't get FW config file size\n"); 1050 goto out_err; 1051 } 1052 1053 if (st.st_size >= FLASH_CFG_MAX_SIZE) { 1054 dev_debug(adap, "FW config file size >= max(%u)\n", 1055 FLASH_CFG_MAX_SIZE); 1056 ret = -ENOMEM; 1057 goto out_err; 1058 } 1059 1060 fw_cfg = rte_zmalloc(NULL, st.st_size, 0); 1061 if (fw_cfg == NULL) { 1062 ret = -ENOMEM; 1063 goto out_err; 1064 } 1065 1066 if (read(fd, fw_cfg, st.st_size) != st.st_size) { 1067 dev_debug(adap, "Couldn't read FW config file data\n"); 1068 ret = -EIO; 1069 goto out_err; 1070 } 1071 1072 close(fd); 1073 1074 /* Send it to FW to verify and update to new configuration */ 1075 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1076 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF); 1077 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 1078 if (ret < 0) { 1079 dev_debug(adap, "FW config param query failed: %d\n", ret); 1080 goto out_free; 1081 } 1082 1083 mtype = val >> 8; 1084 maddr = (val & 0xff) << 16; 1085 1086 t4_os_lock(&adap->win0_lock); 1087 ret = t4_memory_rw(adap, MEMWIN_NIC, mtype, maddr, st.st_size, 1088 fw_cfg, T4_MEMORY_WRITE); 1089 t4_os_unlock(&adap->win0_lock); 1090 if (ret < 0) { 1091 dev_debug(adap, "FW config file update failed: %d\n", ret); 1092 goto out_free; 1093 } 1094 1095 rte_free(fw_cfg); 1096 1097 *mem_type = mtype; 1098 *mem_addr = maddr; 1099 *config_name = fw_cfg_path; 1100 return 0; 1101 1102 out_err: 1103 close(fd); 1104 out_free: 1105 rte_free(fw_cfg); 1106 return ret; 1107 } 1108 1109 static int cxgbe_load_fw_config(struct adapter *adap) 1110 { 1111 u32 finiver, finicsum, cfcsum, mtype, maddr, param, val; 1112 struct fw_caps_config_cmd caps_cmd = { 0 }; 1113 const char *config_name = NULL; 1114 int ret; 1115 1116 ret = cxgbe_load_fw_config_from_filesystem(adap, &config_name, 1117 &mtype, &maddr); 1118 if (ret < 0) { 1119 config_name = "On Flash"; 1120 1121 ret = t4_flash_cfg_addr(adap); 1122 if (ret < 0) { 1123 dev_warn(adap, 1124 "Finding address for FW config file in flash failed: %d\n", 1125 ret); 1126 goto out_default_config; 1127 } 1128 1129 mtype = FW_MEMTYPE_CF_FLASH; 1130 maddr = ret; 1131 } 1132 1133 /* Enable HASH filter region when support is available. */ 1134 val = 1; 1135 param = CXGBE_FW_PARAM_DEV(HASHFILTER_WITH_OFLD); 1136 t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 1137 1138 /* 1139 * Issue a Capability Configuration command to the firmware to get it 1140 * to parse the Configuration File. 1141 */ 1142 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1143 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1144 caps_cmd.cfvalid_to_len16 = 1145 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 1146 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1147 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 1148 FW_LEN16(caps_cmd)); 1149 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1150 &caps_cmd); 1151 1152 out_default_config: 1153 /* 1154 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 1155 * Configuration File in filesystem or FLASH), our last gasp 1156 * effort is to use the Firmware Configuration File which is 1157 * embedded in the firmware. 1158 */ 1159 if (ret == -ENOENT) { 1160 config_name = "Firmware Default"; 1161 1162 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1163 caps_cmd.op_to_write = 1164 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1165 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1166 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 1167 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1168 &caps_cmd); 1169 } 1170 1171 if (ret < 0) { 1172 dev_info(adap, 1173 "Failed to configure using %s Firmware Configuration file: %d\n", 1174 config_name, ret); 1175 return ret; 1176 } 1177 1178 finiver = be32_to_cpu(caps_cmd.finiver); 1179 finicsum = be32_to_cpu(caps_cmd.finicsum); 1180 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 1181 if (finicsum != cfcsum) 1182 dev_warn(adap, 1183 "Configuration File checksum mismatch: [fini] csum=0x%x, computed csum=0x%x\n", 1184 finicsum, cfcsum); 1185 1186 /* 1187 * If we're a pure NIC driver then disable all offloading facilities. 1188 * This will allow the firmware to optimize aspects of the hardware 1189 * configuration which will result in improved performance. 1190 */ 1191 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD); 1192 caps_cmd.toecaps = 0; 1193 caps_cmd.iscsicaps = 0; 1194 caps_cmd.rdmacaps = 0; 1195 caps_cmd.fcoecaps = 0; 1196 caps_cmd.cryptocaps = 0; 1197 1198 /* 1199 * And now tell the firmware to use the configuration we just loaded. 1200 */ 1201 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1202 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1203 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1204 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1205 NULL); 1206 if (ret < 0) { 1207 dev_warn(adap, "Unable to finalize Firmware Capabilities %d\n", 1208 ret); 1209 return ret; 1210 } 1211 1212 /* 1213 * Return successfully and note that we're operating with parameters 1214 * not supplied by the driver, rather than from hard-wired 1215 * initialization constants buried in the driver. 1216 */ 1217 dev_info(adap, 1218 "Successfully configured using Firmware Configuration File \"%s\", version: 0x%x, computed csum: 0x%x\n", 1219 config_name, finiver, cfcsum); 1220 return 0; 1221 } 1222 1223 static void configure_pcie_ext_tag(struct adapter *adapter) 1224 { 1225 u16 v; 1226 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 1227 1228 if (!pos) 1229 return; 1230 1231 if (pos > 0) { 1232 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v); 1233 v |= PCI_EXP_DEVCTL_EXT_TAG; 1234 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v); 1235 if (is_t6(adapter->params.chip)) { 1236 t4_set_reg_field(adapter, A_PCIE_CFG2, 1237 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG), 1238 V_T6_TOTMAXTAG(7)); 1239 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 1240 V_T6_MINTAG(M_T6_MINTAG), 1241 V_T6_MINTAG(8)); 1242 } else { 1243 t4_set_reg_field(adapter, A_PCIE_CFG2, 1244 V_TOTMAXTAG(M_TOTMAXTAG), 1245 V_TOTMAXTAG(3)); 1246 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 1247 V_MINTAG(M_MINTAG), 1248 V_MINTAG(8)); 1249 } 1250 } 1251 } 1252 1253 /* Figure out how many Queue Sets we can support */ 1254 void cxgbe_configure_max_ethqsets(struct adapter *adapter) 1255 { 1256 unsigned int ethqsets, reserved; 1257 1258 /* We need to reserve an Ingress Queue for the Asynchronous Firmware 1259 * Event Queue and 1 Control Queue per port. 1260 * 1261 * For each Queue Set, we'll need the ability to allocate two Egress 1262 * Contexts -- one for the Ingress Queue Free List and one for the TX 1263 * Ethernet Queue. 1264 */ 1265 reserved = max(adapter->params.nports, 1); 1266 if (is_pf4(adapter)) { 1267 struct pf_resources *pfres = &adapter->params.pfres; 1268 1269 ethqsets = min(pfres->niqflint, pfres->nethctrl); 1270 if (ethqsets > (pfres->neq / 2)) 1271 ethqsets = pfres->neq / 2; 1272 } else { 1273 struct vf_resources *vfres = &adapter->params.vfres; 1274 1275 ethqsets = min(vfres->niqflint, vfres->nethctrl); 1276 if (ethqsets > (vfres->neq / 2)) 1277 ethqsets = vfres->neq / 2; 1278 } 1279 1280 ethqsets -= reserved; 1281 adapter->sge.max_ethqsets = ethqsets; 1282 } 1283 1284 /* 1285 * Tweak configuration based on system architecture, etc. Most of these have 1286 * defaults assigned to them by Firmware Configuration Files (if we're using 1287 * them) but need to be explicitly set if we're using hard-coded 1288 * initialization. So these are essentially common tweaks/settings for 1289 * Configuration Files and hard-coded initialization ... 1290 */ 1291 static int adap_init0_tweaks(struct adapter *adapter) 1292 { 1293 u8 rx_dma_offset; 1294 1295 /* 1296 * Fix up various Host-Dependent Parameters like Page Size, Cache 1297 * Line Size, etc. The firmware default is for a 4KB Page Size and 1298 * 64B Cache Line Size ... 1299 */ 1300 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 1301 T5_LAST_REV); 1302 1303 /* 1304 * Keep the chip default offset to deliver Ingress packets into our 1305 * DMA buffers to zero 1306 */ 1307 rx_dma_offset = 0; 1308 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 1309 V_PKTSHIFT(rx_dma_offset)); 1310 1311 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 1312 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 1313 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 1314 1315 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD, 1316 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U)); 1317 1318 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 1319 V_IDMAARBROUNDROBIN(1U)); 1320 1321 /* 1322 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 1323 * adds the pseudo header itself. 1324 */ 1325 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 1326 F_CSUM_HAS_PSEUDO_HDR, 0); 1327 1328 return 0; 1329 } 1330 1331 /* 1332 * Attempt to initialize the adapter via a Firmware Configuration File. 1333 */ 1334 static int adap_init0_config(struct adapter *adapter, int reset) 1335 { 1336 int ret; 1337 1338 /* 1339 * Reset device if necessary. 1340 */ 1341 if (reset) { 1342 ret = t4_fw_reset(adapter, adapter->mbox, 1343 F_PIORSTMODE | F_PIORST); 1344 if (ret < 0) { 1345 dev_warn(adapter, "Firmware reset failed, error %d\n", 1346 -ret); 1347 goto bye; 1348 } 1349 } 1350 1351 ret = cxgbe_load_fw_config(adapter); 1352 if (ret < 0) 1353 goto bye; 1354 1355 /* 1356 * Tweak configuration based on system architecture, etc. 1357 */ 1358 ret = adap_init0_tweaks(adapter); 1359 if (ret < 0) { 1360 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 1361 goto bye; 1362 } 1363 1364 /* 1365 * And finally tell the firmware to initialize itself using the 1366 * parameters from the Configuration File. 1367 */ 1368 ret = t4_fw_initialize(adapter, adapter->mbox); 1369 if (ret < 0) { 1370 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 1371 -ret); 1372 goto bye; 1373 } 1374 1375 return 0; 1376 1377 bye: 1378 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 1379 return ret; 1380 } 1381 1382 static int adap_init0(struct adapter *adap) 1383 { 1384 struct fw_caps_config_cmd caps_cmd; 1385 int ret = 0; 1386 u32 v, port_vec; 1387 enum dev_state state; 1388 u32 params[7], val[7]; 1389 int reset = 1; 1390 int mbox = adap->mbox; 1391 1392 /* 1393 * Contact FW, advertising Master capability. 1394 */ 1395 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 1396 if (ret < 0) { 1397 dev_err(adap, "%s: could not connect to FW, error %d\n", 1398 __func__, -ret); 1399 goto bye; 1400 } 1401 1402 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 1403 adap->mbox, ret); 1404 1405 if (ret == mbox) 1406 adap->flags |= MASTER_PF; 1407 1408 if (state == DEV_STATE_INIT) { 1409 /* 1410 * Force halt and reset FW because a previous instance may have 1411 * exited abnormally without properly shutting down 1412 */ 1413 ret = t4_fw_halt(adap, adap->mbox, reset); 1414 if (ret < 0) { 1415 dev_err(adap, "Failed to halt. Exit.\n"); 1416 goto bye; 1417 } 1418 1419 ret = t4_fw_restart(adap, adap->mbox, reset); 1420 if (ret < 0) { 1421 dev_err(adap, "Failed to restart. Exit.\n"); 1422 goto bye; 1423 } 1424 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 1425 } 1426 1427 t4_get_version_info(adap); 1428 1429 ret = t4_get_core_clock(adap, &adap->params.vpd); 1430 if (ret < 0) { 1431 dev_err(adap, "%s: could not get core clock, error %d\n", 1432 __func__, -ret); 1433 goto bye; 1434 } 1435 1436 /* 1437 * If the firmware is initialized already (and we're not forcing a 1438 * master initialization), note that we're living with existing 1439 * adapter parameters. Otherwise, it's time to try initializing the 1440 * adapter ... 1441 */ 1442 if (state == DEV_STATE_INIT) { 1443 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 1444 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 1445 } else { 1446 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 1447 1448 ret = adap_init0_config(adap, reset); 1449 if (ret == -ENOENT) { 1450 dev_err(adap, 1451 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 1452 goto bye; 1453 } 1454 } 1455 if (ret < 0) { 1456 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 1457 goto bye; 1458 } 1459 1460 /* Now that we've successfully configured and initialized the adapter 1461 * (or found it already initialized), we can ask the Firmware what 1462 * resources it has provisioned for us. 1463 */ 1464 ret = t4_get_pfres(adap); 1465 if (ret) { 1466 dev_err(adap->pdev_dev, 1467 "Unable to retrieve resource provisioning info\n"); 1468 goto bye; 1469 } 1470 1471 /* Find out what ports are available to us. */ 1472 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1473 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 1474 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 1475 if (ret < 0) { 1476 dev_err(adap, "%s: failure in t4_query_params; error = %d\n", 1477 __func__, ret); 1478 goto bye; 1479 } 1480 1481 adap->params.nports = hweight32(port_vec); 1482 adap->params.portvec = port_vec; 1483 1484 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 1485 adap->params.nports); 1486 1487 /* 1488 * Give the SGE code a chance to pull in anything that it needs ... 1489 * Note that this must be called after we retrieve our VPD parameters 1490 * in order to know how to convert core ticks to seconds, etc. 1491 */ 1492 ret = t4_sge_init(adap); 1493 if (ret < 0) { 1494 dev_err(adap, "t4_sge_init failed with error %d\n", 1495 -ret); 1496 goto bye; 1497 } 1498 1499 /* 1500 * Grab some of our basic fundamental operating parameters. 1501 */ 1502 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START); 1503 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END); 1504 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START); 1505 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END); 1506 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); 1507 if (ret < 0) 1508 goto bye; 1509 adap->l2t_start = val[0]; 1510 adap->l2t_end = val[1]; 1511 adap->tids.ftid_base = val[2]; 1512 adap->tids.nftids = val[3] - val[2] + 1; 1513 1514 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START); 1515 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END); 1516 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 1517 if (ret < 0) 1518 goto bye; 1519 adap->clipt_start = val[0]; 1520 adap->clipt_end = val[1]; 1521 1522 /* 1523 * Get device capabilities so we can determine what resources we need 1524 * to manage. 1525 */ 1526 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1527 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1528 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1529 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1530 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1531 &caps_cmd); 1532 if (ret < 0) 1533 goto bye; 1534 1535 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) && 1536 is_t6(adap->params.chip)) { 1537 if (cxgbe_init_hash_filter(adap) < 0) 1538 goto bye; 1539 } 1540 1541 /* See if FW supports FW_FILTER2 work request */ 1542 if (is_t4(adap->params.chip)) { 1543 adap->params.filter2_wr_support = 0; 1544 } else { 1545 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR); 1546 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1547 1, params, val); 1548 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 1549 } 1550 1551 /* Check if FW supports returning vin. 1552 * If this is not supported, driver will interpret 1553 * these values from viid. 1554 */ 1555 params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 1556 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1557 1, params, val); 1558 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); 1559 1560 /* query tid-related parameters */ 1561 params[0] = CXGBE_FW_PARAM_DEV(NTID); 1562 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 1563 params, val); 1564 if (ret < 0) 1565 goto bye; 1566 adap->tids.ntids = val[0]; 1567 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 1568 1569 /* If we're running on newer firmware, let it know that we're 1570 * prepared to deal with encapsulated CPL messages. Older 1571 * firmware won't understand this and we'll just get 1572 * unencapsulated messages ... 1573 */ 1574 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1575 val[0] = 1; 1576 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1577 1578 /* 1579 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 1580 * capability. Earlier versions of the firmware didn't have the 1581 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 1582 * permission to use ULPTX MEMWRITE DSGL. 1583 */ 1584 if (is_t4(adap->params.chip)) { 1585 adap->params.ulptx_memwrite_dsgl = false; 1586 } else { 1587 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 1588 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1589 1, params, val); 1590 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 1591 } 1592 1593 /* Query for max number of packets that can be coalesced for Tx */ 1594 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 1595 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1596 if (!ret && val[0] > 0) 1597 adap->params.max_tx_coalesce_num = val[0]; 1598 else 1599 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; 1600 1601 params[0] = CXGBE_FW_PARAM_DEV(VI_ENABLE_INGRESS_AFTER_LINKUP); 1602 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1603 adap->params.vi_enable_rx = (ret == 0 && val[0] != 0); 1604 1605 /* Read the RAW MPS entries. In T6, the last 2 TCAM entries 1606 * are reserved for RAW MAC addresses (rawf = 2, one per port). 1607 */ 1608 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 1609 params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START); 1610 params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END); 1611 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 1612 params, val); 1613 if (ret == 0) { 1614 adap->params.rawf_start = val[0]; 1615 adap->params.rawf_size = val[1] - val[0] + 1; 1616 } 1617 } 1618 1619 /* 1620 * The MTU/MSS Table is initialized by now, so load their values. If 1621 * we're initializing the adapter, then we'll make any modifications 1622 * we want to the MTU/MSS Table and also initialize the congestion 1623 * parameters. 1624 */ 1625 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 1626 if (state != DEV_STATE_INIT) { 1627 int i; 1628 1629 /* 1630 * The default MTU Table contains values 1492 and 1500. 1631 * However, for TCP, it's better to have two values which are 1632 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 1633 * This allows us to have a TCP Data Payload which is a 1634 * multiple of 8 regardless of what combination of TCP Options 1635 * are in use (always a multiple of 4 bytes) which is 1636 * important for performance reasons. For instance, if no 1637 * options are in use, then we have a 20-byte IP header and a 1638 * 20-byte TCP header. In this case, a 1500-byte MSS would 1639 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 1640 * which is not a multiple of 8. So using an MSS of 1488 in 1641 * this case results in a TCP Data Payload of 1448 bytes which 1642 * is a multiple of 8. On the other hand, if 12-byte TCP Time 1643 * Stamps have been negotiated, then an MTU of 1500 bytes 1644 * results in a TCP Data Payload of 1448 bytes which, as 1645 * above, is a multiple of 8 bytes ... 1646 */ 1647 for (i = 0; i < NMTUS; i++) 1648 if (adap->params.mtus[i] == 1492) { 1649 adap->params.mtus[i] = 1488; 1650 break; 1651 } 1652 1653 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 1654 adap->params.b_wnd); 1655 } 1656 t4_init_sge_params(adap); 1657 ret = configure_filter_mode_mask(adap); 1658 if (ret < 0) 1659 goto bye; 1660 t4_init_tp_params(adap); 1661 configure_pcie_ext_tag(adap); 1662 configure_vlan_types(adap); 1663 cxgbe_configure_max_ethqsets(adap); 1664 1665 adap->params.drv_memwin = MEMWIN_NIC; 1666 adap->flags |= FW_OK; 1667 dev_debug(adap, "%s: returning zero..\n", __func__); 1668 return 0; 1669 1670 /* 1671 * Something bad happened. If a command timed out or failed with EIO 1672 * FW does not operate within its spec or something catastrophic 1673 * happened to HW/FW, stop issuing commands. 1674 */ 1675 bye: 1676 if (ret != -ETIMEDOUT && ret != -EIO) 1677 t4_fw_bye(adap, adap->mbox); 1678 return ret; 1679 } 1680 1681 /** 1682 * t4_os_portmod_changed - handle port module changes 1683 * @adap: the adapter associated with the module change 1684 * @port_id: the port index whose module status has changed 1685 * 1686 * This is the OS-dependent handler for port module changes. It is 1687 * invoked when a port module is removed or inserted for any OS-specific 1688 * processing. 1689 */ 1690 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 1691 { 1692 static const char * const mod_str[] = { 1693 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 1694 }; 1695 1696 const struct port_info *pi = adap2pinfo(adap, port_id); 1697 1698 if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NONE) 1699 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 1700 else if (pi->link_cfg.mod_type < ARRAY_SIZE(mod_str)) 1701 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 1702 mod_str[pi->link_cfg.mod_type]); 1703 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 1704 dev_info(adap, "Port%d: unsupported port module inserted\n", 1705 pi->port_id); 1706 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 1707 dev_info(adap, "Port%d: unknown port module inserted\n", 1708 pi->port_id); 1709 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_ERROR) 1710 dev_info(adap, "Port%d: transceiver module error\n", 1711 pi->port_id); 1712 else 1713 dev_info(adap, "Port%d: unknown module type %d inserted\n", 1714 pi->port_id, pi->link_cfg.mod_type); 1715 } 1716 1717 void t4_os_link_changed(struct adapter *adap, int port_id) 1718 { 1719 struct port_info *pi = adap2pinfo(adap, port_id); 1720 1721 /* If link status has not changed or if firmware doesn't 1722 * support enabling/disabling VI's Rx path during runtime, 1723 * then return. 1724 */ 1725 if (adap->params.vi_enable_rx == 0 || 1726 pi->vi_en_rx == pi->link_cfg.link_ok) 1727 return; 1728 1729 /* Don't enable VI Rx path, if link has been administratively 1730 * turned off. 1731 */ 1732 if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0) 1733 return; 1734 1735 /* When link goes down, disable the port's Rx path to drop 1736 * Rx traffic closer to the wire, instead of processing it 1737 * further in the Rx pipeline. The Rx path will be re-enabled 1738 * once the link up message comes in firmware event queue. 1739 */ 1740 pi->vi_en_rx = pi->link_cfg.link_ok; 1741 t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx); 1742 } 1743 1744 bool cxgbe_force_linkup(struct adapter *adap) 1745 { 1746 if (is_pf4(adap)) 1747 return false; /* force_linkup not required for pf driver */ 1748 1749 return adap->devargs.force_link_up; 1750 } 1751 1752 /** 1753 * link_start - enable a port 1754 * @dev: the port to enable 1755 * 1756 * Performs the MAC and PHY actions needed to enable a port. 1757 */ 1758 int cxgbe_link_start(struct port_info *pi) 1759 { 1760 struct adapter *adapter = pi->adapter; 1761 u64 conf_offloads; 1762 unsigned int mtu; 1763 int ret; 1764 1765 mtu = pi->eth_dev->data->mtu; 1766 1767 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads; 1768 1769 /* 1770 * We do not set address filters and promiscuity here, the stack does 1771 * that step explicitly. 1772 */ 1773 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1, 1774 !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP), 1775 true); 1776 if (ret == 0) { 1777 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, 1778 (u8 *)&pi->eth_dev->data->mac_addrs[0]); 1779 if (ret >= 0) { 1780 pi->xact_addr_filt = ret; 1781 ret = 0; 1782 } 1783 } 1784 if (ret == 0 && is_pf4(adapter)) 1785 ret = t4_link_l1cfg(pi, pi->link_cfg.admin_caps); 1786 if (ret == 0) { 1787 /* Disable VI Rx until link up message is received in 1788 * firmware event queue, if firmware supports enabling/ 1789 * disabling VI Rx at runtime. 1790 */ 1791 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : 1; 1792 pi->vi_en_tx = 1; 1793 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 1794 pi->vi_en_rx, pi->vi_en_tx, false); 1795 } 1796 1797 if (ret == 0 && cxgbe_force_linkup(adapter)) 1798 pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; 1799 return ret; 1800 } 1801 1802 /** 1803 * cxgbe_write_rss_conf - flash the RSS configuration for a given port 1804 * @pi: the port 1805 * @rss_hf: Hash configuration to apply 1806 */ 1807 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) 1808 { 1809 struct adapter *adapter = pi->adapter; 1810 const struct sge_eth_rxq *rxq; 1811 u64 flags = 0; 1812 u16 rss; 1813 int err; 1814 1815 /* Should never be called before setting up sge eth rx queues */ 1816 if (!(adapter->flags & FULL_INIT_DONE)) { 1817 dev_err(adap, "%s No RXQs available on port %d\n", 1818 __func__, pi->port_id); 1819 return -EINVAL; 1820 } 1821 1822 /* Don't allow unsupported hash functions */ 1823 if (rss_hf & ~CXGBE_RSS_HF_ALL) 1824 return -EINVAL; 1825 1826 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) 1827 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 1828 1829 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 1830 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 1831 1832 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 1833 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 1834 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1835 1836 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK) 1837 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 1838 1839 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK) 1840 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1841 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 1842 1843 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK) 1844 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1845 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 1846 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1847 1848 rxq = &adapter->sge.ethrxq[pi->first_rxqset]; 1849 rss = rxq[0].rspq.abs_id; 1850 1851 /* If Tunnel All Lookup isn't specified in the global RSS 1852 * Configuration, then we need to specify a default Ingress 1853 * Queue for any ingress packets which aren't hashed. We'll 1854 * use our first ingress queue ... 1855 */ 1856 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 1857 flags, rss); 1858 return err; 1859 } 1860 1861 /** 1862 * cxgbe_write_rss - write the RSS table for a given port 1863 * @pi: the port 1864 * @queues: array of queue indices for RSS 1865 * 1866 * Sets up the portion of the HW RSS table for the port's VI to distribute 1867 * packets to the Rx queues in @queues. 1868 */ 1869 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues) 1870 { 1871 u16 *rss; 1872 int i, err; 1873 struct adapter *adapter = pi->adapter; 1874 const struct sge_eth_rxq *rxq; 1875 1876 /* Should never be called before setting up sge eth rx queues */ 1877 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 1878 1879 rxq = &adapter->sge.ethrxq[pi->first_rxqset]; 1880 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 1881 if (!rss) 1882 return -ENOMEM; 1883 1884 /* map the queue indices to queue ids */ 1885 for (i = 0; i < pi->rss_size; i++, queues++) 1886 rss[i] = rxq[*queues].rspq.abs_id; 1887 1888 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 1889 pi->rss_size, rss, pi->rss_size); 1890 rte_free(rss); 1891 return err; 1892 } 1893 1894 /** 1895 * setup_rss - configure RSS 1896 * @adapter: the adapter 1897 * 1898 * Sets up RSS to distribute packets to multiple receive queues. We 1899 * configure the RSS CPU lookup table to distribute to the number of HW 1900 * receive queues, and the response queue lookup table to narrow that 1901 * down to the response queues actually configured for each port. 1902 * We always configure the RSS mapping for all ports since the mapping 1903 * table has plenty of entries. 1904 */ 1905 int cxgbe_setup_rss(struct port_info *pi) 1906 { 1907 int j, err; 1908 struct adapter *adapter = pi->adapter; 1909 1910 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 1911 __func__, pi->rss_size, pi->n_rx_qsets); 1912 1913 if (!(pi->flags & PORT_RSS_DONE)) { 1914 if (adapter->flags & FULL_INIT_DONE) { 1915 /* Fill default values with equal distribution */ 1916 for (j = 0; j < pi->rss_size; j++) 1917 pi->rss[j] = j % pi->n_rx_qsets; 1918 1919 err = cxgbe_write_rss(pi, pi->rss); 1920 if (err) 1921 return err; 1922 1923 err = cxgbe_write_rss_conf(pi, pi->rss_hf); 1924 if (err) 1925 return err; 1926 pi->flags |= PORT_RSS_DONE; 1927 } 1928 } 1929 return 0; 1930 } 1931 1932 /* 1933 * Enable NAPI scheduling and interrupt generation for all Rx queues. 1934 */ 1935 static void enable_rx(struct adapter *adap, struct sge_rspq *q) 1936 { 1937 /* 0-increment GTS to start the timer and enable interrupts */ 1938 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) : 1939 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS, 1940 V_SEINTARM(q->intr_params) | 1941 V_INGRESSQID(q->cntxt_id)); 1942 } 1943 1944 void cxgbe_enable_rx_queues(struct port_info *pi) 1945 { 1946 struct adapter *adap = pi->adapter; 1947 struct sge *s = &adap->sge; 1948 unsigned int i; 1949 1950 for (i = 0; i < pi->n_rx_qsets; i++) 1951 enable_rx(adap, &s->ethrxq[pi->first_rxqset + i].rspq); 1952 } 1953 1954 /** 1955 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps. 1956 * @port_type: Firmware Port Type 1957 * @fw_caps: Firmware Port Capabilities 1958 * @speed_caps: Device Info Speed Capabilities 1959 * 1960 * Translate a Firmware Port Capabilities specification to Device Info 1961 * Speed Capabilities. 1962 */ 1963 static void fw_caps_to_speed_caps(enum fw_port_type port_type, 1964 unsigned int fw_caps, 1965 u32 *speed_caps) 1966 { 1967 #define SET_SPEED(__speed_name) \ 1968 do { \ 1969 *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \ 1970 } while (0) 1971 1972 #define FW_CAPS_TO_SPEED(__fw_name) \ 1973 do { \ 1974 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \ 1975 SET_SPEED(__fw_name); \ 1976 } while (0) 1977 1978 switch (port_type) { 1979 case FW_PORT_TYPE_BT_SGMII: 1980 case FW_PORT_TYPE_BT_XFI: 1981 case FW_PORT_TYPE_BT_XAUI: 1982 FW_CAPS_TO_SPEED(SPEED_100M); 1983 FW_CAPS_TO_SPEED(SPEED_1G); 1984 FW_CAPS_TO_SPEED(SPEED_10G); 1985 break; 1986 1987 case FW_PORT_TYPE_KX4: 1988 case FW_PORT_TYPE_KX: 1989 case FW_PORT_TYPE_FIBER_XFI: 1990 case FW_PORT_TYPE_FIBER_XAUI: 1991 case FW_PORT_TYPE_SFP: 1992 case FW_PORT_TYPE_QSFP_10G: 1993 case FW_PORT_TYPE_QSA: 1994 FW_CAPS_TO_SPEED(SPEED_1G); 1995 FW_CAPS_TO_SPEED(SPEED_10G); 1996 break; 1997 1998 case FW_PORT_TYPE_KR: 1999 SET_SPEED(SPEED_10G); 2000 break; 2001 2002 case FW_PORT_TYPE_BP_AP: 2003 case FW_PORT_TYPE_BP4_AP: 2004 SET_SPEED(SPEED_1G); 2005 SET_SPEED(SPEED_10G); 2006 break; 2007 2008 case FW_PORT_TYPE_BP40_BA: 2009 case FW_PORT_TYPE_QSFP: 2010 SET_SPEED(SPEED_40G); 2011 break; 2012 2013 case FW_PORT_TYPE_CR_QSFP: 2014 case FW_PORT_TYPE_SFP28: 2015 case FW_PORT_TYPE_KR_SFP28: 2016 FW_CAPS_TO_SPEED(SPEED_1G); 2017 FW_CAPS_TO_SPEED(SPEED_10G); 2018 FW_CAPS_TO_SPEED(SPEED_25G); 2019 break; 2020 2021 case FW_PORT_TYPE_CR2_QSFP: 2022 SET_SPEED(SPEED_50G); 2023 break; 2024 2025 case FW_PORT_TYPE_KR4_100G: 2026 case FW_PORT_TYPE_CR4_QSFP: 2027 FW_CAPS_TO_SPEED(SPEED_25G); 2028 FW_CAPS_TO_SPEED(SPEED_40G); 2029 FW_CAPS_TO_SPEED(SPEED_50G); 2030 FW_CAPS_TO_SPEED(SPEED_100G); 2031 break; 2032 2033 default: 2034 break; 2035 } 2036 2037 #undef FW_CAPS_TO_SPEED 2038 #undef SET_SPEED 2039 } 2040 2041 /** 2042 * cxgbe_get_speed_caps - Fetch supported speed capabilities 2043 * @pi: Underlying port's info 2044 * @speed_caps: Device Info speed capabilities 2045 * 2046 * Fetch supported speed capabilities of the underlying port. 2047 */ 2048 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) 2049 { 2050 *speed_caps = 0; 2051 2052 fw_caps_to_speed_caps(pi->link_cfg.port_type, pi->link_cfg.pcaps, 2053 speed_caps); 2054 2055 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) 2056 *speed_caps |= RTE_ETH_LINK_SPEED_FIXED; 2057 } 2058 2059 /** 2060 * cxgbe_set_link_status - Set device link up or down. 2061 * @pi: Underlying port's info 2062 * @status: 0 - down, 1 - up 2063 * 2064 * Set the device link up or down. 2065 */ 2066 int cxgbe_set_link_status(struct port_info *pi, bool status) 2067 { 2068 struct adapter *adapter = pi->adapter; 2069 int err = 0; 2070 2071 /* Wait for link up message from firmware to enable Rx path, 2072 * if firmware supports enabling/disabling VI Rx at runtime. 2073 */ 2074 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : status; 2075 pi->vi_en_tx = status; 2076 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, pi->vi_en_rx, 2077 pi->vi_en_tx); 2078 if (err) { 2079 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 2080 return err; 2081 } 2082 2083 if (!status) 2084 t4_reset_link_config(adapter, pi->pidx); 2085 2086 return 0; 2087 } 2088 2089 /** 2090 * cxgb_up - enable the adapter 2091 * @adap: adapter being enabled 2092 * 2093 * Called when the first port is enabled, this function performs the 2094 * actions necessary to make an adapter operational, such as completing 2095 * the initialization of HW modules, and enabling interrupts. 2096 */ 2097 int cxgbe_up(struct adapter *adap) 2098 { 2099 enable_rx(adap, &adap->sge.fw_evtq); 2100 t4_sge_tx_monitor_start(adap); 2101 if (is_pf4(adap)) 2102 t4_intr_enable(adap); 2103 adap->flags |= FULL_INIT_DONE; 2104 2105 /* TODO: deadman watchdog ?? */ 2106 return 0; 2107 } 2108 2109 /* 2110 * Close the port 2111 */ 2112 int cxgbe_down(struct port_info *pi) 2113 { 2114 return cxgbe_set_link_status(pi, false); 2115 } 2116 2117 /* 2118 * Release resources when all the ports have been stopped. 2119 */ 2120 void cxgbe_close(struct adapter *adapter) 2121 { 2122 if (adapter->flags & FULL_INIT_DONE) { 2123 tid_free(&adapter->tids); 2124 t4_cleanup_mpstcam(adapter); 2125 t4_cleanup_clip_tbl(adapter); 2126 t4_cleanup_l2t(adapter); 2127 t4_cleanup_smt(adapter); 2128 if (is_pf4(adapter)) 2129 t4_intr_disable(adapter); 2130 t4_sge_tx_monitor_stop(adapter); 2131 t4_free_sge_resources(adapter); 2132 adapter->flags &= ~FULL_INIT_DONE; 2133 } 2134 2135 cxgbe_cfg_queues_free(adapter); 2136 2137 if (is_pf4(adapter) && (adapter->flags & FW_OK)) 2138 t4_fw_bye(adapter, adapter->mbox); 2139 } 2140 2141 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx, 2142 u32 *smt_size) 2143 { 2144 u32 params[2], smt_val[2]; 2145 int ret; 2146 2147 params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START); 2148 params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE); 2149 2150 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 2151 2, params, smt_val); 2152 2153 /* if FW doesn't recognize this command then set it to default setting 2154 * which is start index as 0 and size as 256. 2155 */ 2156 if (ret < 0) { 2157 *smt_start_idx = 0; 2158 *smt_size = SMT_SIZE; 2159 } else { 2160 *smt_start_idx = smt_val[0]; 2161 /* smt size can be zero, if nsmt is not yet configured in 2162 * the config file or set as zero, then configure all the 2163 * remaining entries to this PF itself. 2164 */ 2165 if (!smt_val[1]) 2166 *smt_size = SMT_SIZE - *smt_start_idx; 2167 else 2168 *smt_size = smt_val[1]; 2169 } 2170 } 2171 2172 int cxgbe_probe(struct adapter *adapter) 2173 { 2174 u32 smt_start_idx, smt_size; 2175 struct port_info *pi; 2176 int func, i; 2177 int err = 0; 2178 u32 whoami; 2179 int chip; 2180 2181 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 2182 chip = t4_get_chip_type(adapter, 2183 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id)); 2184 if (chip < 0) 2185 return chip; 2186 2187 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 2188 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami); 2189 2190 adapter->mbox = func; 2191 adapter->pf = func; 2192 2193 t4_os_lock_init(&adapter->mbox_lock); 2194 TAILQ_INIT(&adapter->mbox_list); 2195 t4_os_lock_init(&adapter->win0_lock); 2196 2197 err = t4_prep_adapter(adapter); 2198 if (err) 2199 return err; 2200 2201 setup_memwin(adapter); 2202 err = adap_init0(adapter); 2203 if (err) { 2204 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 2205 __func__, err); 2206 goto out_free; 2207 } 2208 2209 if (!is_t4(adapter->params.chip)) { 2210 /* 2211 * The userspace doorbell BAR is split evenly into doorbell 2212 * regions, each associated with an egress queue. If this 2213 * per-queue region is large enough (at least UDBS_SEG_SIZE) 2214 * then it can be used to submit a tx work request with an 2215 * implied doorbell. Enable write combining on the BAR if 2216 * there is room for such work requests. 2217 */ 2218 int s_qpp, qpp, num_seg; 2219 2220 s_qpp = (S_QUEUESPERPAGEPF0 + 2221 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 2222 adapter->pf); 2223 qpp = 1 << ((t4_read_reg(adapter, 2224 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 2225 & M_QUEUESPERPAGEPF0); 2226 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 2227 if (qpp > num_seg) 2228 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 2229 2230 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 2231 if (!adapter->bar2) { 2232 dev_err(adapter, "cannot map device bar2 region\n"); 2233 err = -ENOMEM; 2234 goto out_free; 2235 } 2236 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 2237 V_STATMODE(0)); 2238 } 2239 2240 for_each_port(adapter, i) { 2241 const unsigned int numa_node = rte_socket_id(); 2242 char name[RTE_ETH_NAME_MAX_LEN]; 2243 struct rte_eth_dev *eth_dev; 2244 2245 snprintf(name, sizeof(name), "%s_%d", 2246 adapter->pdev->device.name, i); 2247 2248 if (i == 0) { 2249 /* First port is already allocated by DPDK */ 2250 eth_dev = adapter->eth_dev; 2251 goto allocate_mac; 2252 } 2253 2254 /* 2255 * now do all data allocation - for eth_dev structure, 2256 * and internal (private) data for the remaining ports 2257 */ 2258 2259 /* reserve an ethdev entry */ 2260 eth_dev = rte_eth_dev_allocate(name); 2261 if (!eth_dev) 2262 goto out_free; 2263 2264 eth_dev->data->dev_private = 2265 rte_zmalloc_socket(name, sizeof(struct port_info), 2266 RTE_CACHE_LINE_SIZE, numa_node); 2267 if (!eth_dev->data->dev_private) 2268 goto out_free; 2269 2270 allocate_mac: 2271 pi = eth_dev->data->dev_private; 2272 adapter->port[i] = pi; 2273 pi->eth_dev = eth_dev; 2274 pi->adapter = adapter; 2275 pi->xact_addr_filt = -1; 2276 pi->port_id = i; 2277 pi->pidx = i; 2278 2279 pi->eth_dev->device = &adapter->pdev->device; 2280 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 2281 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 2282 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 2283 2284 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 2285 2286 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 2287 RTE_ETHER_ADDR_LEN, 0); 2288 if (!pi->eth_dev->data->mac_addrs) { 2289 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 2290 __func__); 2291 err = -1; 2292 goto out_free; 2293 } 2294 2295 if (i > 0) { 2296 /* First port will be notified by upper layer */ 2297 rte_eth_dev_probing_finish(eth_dev); 2298 } 2299 } 2300 2301 if (adapter->flags & FW_OK) { 2302 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 2303 if (err) { 2304 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 2305 __func__, err); 2306 goto out_free; 2307 } 2308 } 2309 2310 err = cxgbe_cfg_queues(adapter->eth_dev); 2311 if (err) 2312 goto out_free; 2313 2314 cxgbe_print_adapter_info(adapter); 2315 cxgbe_print_port_info(adapter); 2316 2317 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 2318 adapter->clipt_end); 2319 if (!adapter->clipt) { 2320 /* We tolerate a lack of clip_table, giving up some 2321 * functionality 2322 */ 2323 dev_warn(adapter, "could not allocate CLIP. Continuing\n"); 2324 } 2325 2326 adap_smt_index(adapter, &smt_start_idx, &smt_size); 2327 adapter->smt = t4_init_smt(smt_start_idx, smt_size); 2328 if (!adapter->smt) 2329 dev_warn(adapter, "could not allocate SMT, continuing\n"); 2330 2331 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 2332 if (!adapter->l2t) { 2333 /* We tolerate a lack of L2T, giving up some functionality */ 2334 dev_warn(adapter, "could not allocate L2T. Continuing\n"); 2335 } 2336 2337 if (tid_init(&adapter->tids) < 0) { 2338 /* Disable filtering support */ 2339 dev_warn(adapter, "could not allocate TID table, " 2340 "filter support disabled. Continuing\n"); 2341 } 2342 2343 t4_os_lock_init(&adapter->flow_lock); 2344 2345 adapter->mpstcam = t4_init_mpstcam(adapter); 2346 if (!adapter->mpstcam) 2347 dev_warn(adapter, "could not allocate mps tcam table." 2348 " Continuing\n"); 2349 2350 if (is_hashfilter(adapter)) { 2351 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) { 2352 u32 hash_base, hash_reg; 2353 2354 hash_reg = A_LE_DB_TID_HASHBASE; 2355 hash_base = t4_read_reg(adapter, hash_reg); 2356 adapter->tids.hash_base = hash_base / 4; 2357 } 2358 } else { 2359 /* Disable hash filtering support */ 2360 dev_warn(adapter, 2361 "Maskless filter support disabled. Continuing\n"); 2362 } 2363 2364 err = cxgbe_init_rss(adapter); 2365 if (err) 2366 goto out_free; 2367 2368 return 0; 2369 2370 out_free: 2371 cxgbe_cfg_queues_free(adapter); 2372 2373 for_each_port(adapter, i) { 2374 pi = adap2pinfo(adapter, i); 2375 if (pi->viid != 0) 2376 t4_free_vi(adapter, adapter->mbox, adapter->pf, 2377 0, pi->viid); 2378 rte_eth_dev_release_port(pi->eth_dev); 2379 } 2380 2381 if (adapter->flags & FW_OK) 2382 t4_fw_bye(adapter, adapter->mbox); 2383 return -err; 2384 } 2385