1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2016 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 44 #include <rte_byteorder.h> 45 #include <rte_common.h> 46 #include <rte_cycles.h> 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_tailq.h> 56 #include <rte_eal.h> 57 #include <rte_alarm.h> 58 #include <rte_ether.h> 59 #include <rte_ethdev.h> 60 #include <rte_ethdev_pci.h> 61 #include <rte_atomic.h> 62 #include <rte_malloc.h> 63 #include <rte_random.h> 64 #include <rte_dev.h> 65 66 #include "common.h" 67 #include "t4_regs.h" 68 #include "t4_msg.h" 69 #include "cxgbe.h" 70 71 /* 72 * Response queue handler for the FW event queue. 73 */ 74 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 75 __rte_unused const struct pkt_gl *gl) 76 { 77 u8 opcode = ((const struct rss_header *)rsp)->opcode; 78 79 rsp++; /* skip RSS header */ 80 81 /* 82 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 83 */ 84 if (unlikely(opcode == CPL_FW4_MSG && 85 ((const struct cpl_fw4_msg *)rsp)->type == 86 FW_TYPE_RSSCPL)) { 87 rsp++; 88 opcode = ((const struct rss_header *)rsp)->opcode; 89 rsp++; 90 if (opcode != CPL_SGE_EGR_UPDATE) { 91 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 92 opcode); 93 goto out; 94 } 95 } 96 97 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 98 /* do nothing */ 99 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 100 const struct cpl_fw6_msg *msg = (const void *)rsp; 101 102 t4_handle_fw_rpl(q->adapter, msg->data); 103 } else { 104 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 105 opcode); 106 } 107 out: 108 return 0; 109 } 110 111 int setup_sge_fwevtq(struct adapter *adapter) 112 { 113 struct sge *s = &adapter->sge; 114 int err = 0; 115 int msi_idx = 0; 116 117 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 118 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 119 rte_socket_id()); 120 return err; 121 } 122 123 static int closest_timer(const struct sge *s, int time) 124 { 125 unsigned int i, match = 0; 126 int delta, min_delta = INT_MAX; 127 128 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 129 delta = time - s->timer_val[i]; 130 if (delta < 0) 131 delta = -delta; 132 if (delta < min_delta) { 133 min_delta = delta; 134 match = i; 135 } 136 } 137 return match; 138 } 139 140 static int closest_thres(const struct sge *s, int thres) 141 { 142 unsigned int i, match = 0; 143 int delta, min_delta = INT_MAX; 144 145 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 146 delta = thres - s->counter_val[i]; 147 if (delta < 0) 148 delta = -delta; 149 if (delta < min_delta) { 150 min_delta = delta; 151 match = i; 152 } 153 } 154 return match; 155 } 156 157 /** 158 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 159 * @q: the Rx queue 160 * @us: the hold-off time in us, or 0 to disable timer 161 * @cnt: the hold-off packet count, or 0 to disable counter 162 * 163 * Sets an Rx queue's interrupt hold-off time and packet count. At least 164 * one of the two needs to be enabled for the queue to generate interrupts. 165 */ 166 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 167 unsigned int cnt) 168 { 169 struct adapter *adap = q->adapter; 170 unsigned int timer_val; 171 172 if (cnt) { 173 int err; 174 u32 v, new_idx; 175 176 new_idx = closest_thres(&adap->sge, cnt); 177 if (q->desc && q->pktcnt_idx != new_idx) { 178 /* the queue has already been created, update it */ 179 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 180 V_FW_PARAMS_PARAM_X( 181 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 182 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 183 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 184 &v, &new_idx); 185 if (err) 186 return err; 187 } 188 q->pktcnt_idx = new_idx; 189 } 190 191 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 192 closest_timer(&adap->sge, us); 193 194 if ((us | cnt) == 0) 195 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 196 else 197 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 198 V_QINTR_CNT_EN(cnt > 0); 199 return 0; 200 } 201 202 static inline bool is_x_1g_port(const struct link_config *lc) 203 { 204 return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0; 205 } 206 207 static inline bool is_x_10g_port(const struct link_config *lc) 208 { 209 return ((lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || 210 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0 || 211 (lc->supported & FW_PORT_CAP_SPEED_100G) != 0); 212 } 213 214 inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 215 unsigned int us, unsigned int cnt, 216 unsigned int size, unsigned int iqe_size) 217 { 218 q->adapter = adap; 219 cxgb4_set_rspq_intr_params(q, us, cnt); 220 q->iqe_len = iqe_size; 221 q->size = size; 222 } 223 224 int cfg_queue_count(struct rte_eth_dev *eth_dev) 225 { 226 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 227 struct adapter *adap = pi->adapter; 228 struct sge *s = &adap->sge; 229 unsigned int max_queues = s->max_ethqsets / adap->params.nports; 230 231 if ((eth_dev->data->nb_rx_queues < 1) || 232 (eth_dev->data->nb_tx_queues < 1)) 233 return -EINVAL; 234 235 if ((eth_dev->data->nb_rx_queues > max_queues) || 236 (eth_dev->data->nb_tx_queues > max_queues)) 237 return -EINVAL; 238 239 if (eth_dev->data->nb_rx_queues > pi->rss_size) 240 return -EINVAL; 241 242 /* We must configure RSS, since config has changed*/ 243 pi->flags &= ~PORT_RSS_DONE; 244 245 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 246 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 247 248 return 0; 249 } 250 251 void cfg_queues(struct rte_eth_dev *eth_dev) 252 { 253 struct rte_config *config = rte_eal_get_configuration(); 254 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 255 struct adapter *adap = pi->adapter; 256 struct sge *s = &adap->sge; 257 unsigned int i, nb_ports = 0, qidx = 0; 258 unsigned int q_per_port = 0; 259 260 if (!(adap->flags & CFG_QUEUES)) { 261 for_each_port(adap, i) { 262 struct port_info *tpi = adap2pinfo(adap, i); 263 264 nb_ports += (is_x_10g_port(&tpi->link_cfg)) || 265 is_x_1g_port(&tpi->link_cfg) ? 1 : 0; 266 } 267 268 /* 269 * We default up to # of cores queues per 1G/10G port. 270 */ 271 if (nb_ports) 272 q_per_port = (MAX_ETH_QSETS - 273 (adap->params.nports - nb_ports)) / 274 nb_ports; 275 276 if (q_per_port > config->lcore_count) 277 q_per_port = config->lcore_count; 278 279 for_each_port(adap, i) { 280 struct port_info *pi = adap2pinfo(adap, i); 281 282 pi->first_qset = qidx; 283 284 /* Initially n_rx_qsets == n_tx_qsets */ 285 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) || 286 is_x_1g_port(&pi->link_cfg)) ? 287 q_per_port : 1; 288 pi->n_tx_qsets = pi->n_rx_qsets; 289 290 if (pi->n_rx_qsets > pi->rss_size) 291 pi->n_rx_qsets = pi->rss_size; 292 293 qidx += pi->n_rx_qsets; 294 } 295 296 s->max_ethqsets = qidx; 297 298 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 299 struct sge_eth_rxq *r = &s->ethrxq[i]; 300 301 init_rspq(adap, &r->rspq, 0, 0, 1024, 64); 302 r->usembufs = 1; 303 r->fl.size = (r->usembufs ? 1024 : 72); 304 } 305 306 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 307 s->ethtxq[i].q.size = 1024; 308 309 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 310 adap->flags |= CFG_QUEUES; 311 } 312 } 313 314 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 315 { 316 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 317 &pi->stats_base); 318 } 319 320 void cxgbe_stats_reset(struct port_info *pi) 321 { 322 t4_clr_port_stats(pi->adapter, pi->tx_chan); 323 } 324 325 static void setup_memwin(struct adapter *adap) 326 { 327 u32 mem_win0_base; 328 329 /* For T5, only relative offset inside the PCIe BAR is passed */ 330 mem_win0_base = MEMWIN0_BASE; 331 332 /* 333 * Set up memory window for accessing adapter memory ranges. (Read 334 * back MA register to ensure that changes propagate before we attempt 335 * to use the new values.) 336 */ 337 t4_write_reg(adap, 338 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 339 MEMWIN_NIC), 340 mem_win0_base | V_BIR(0) | 341 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 342 t4_read_reg(adap, 343 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 344 MEMWIN_NIC)); 345 } 346 347 static int init_rss(struct adapter *adap) 348 { 349 unsigned int i; 350 int err; 351 352 err = t4_init_rss_mode(adap, adap->mbox); 353 if (err) 354 return err; 355 356 for_each_port(adap, i) { 357 struct port_info *pi = adap2pinfo(adap, i); 358 359 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 360 if (!pi->rss) 361 return -ENOMEM; 362 } 363 return 0; 364 } 365 366 static void print_port_info(struct adapter *adap) 367 { 368 int i; 369 char buf[80]; 370 struct rte_pci_addr *loc = &adap->pdev->addr; 371 372 for_each_port(adap, i) { 373 const struct port_info *pi = &adap->port[i]; 374 char *bufp = buf; 375 376 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) 377 bufp += sprintf(bufp, "100/"); 378 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 379 bufp += sprintf(bufp, "1000/"); 380 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 381 bufp += sprintf(bufp, "10G/"); 382 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 383 bufp += sprintf(bufp, "40G/"); 384 if (bufp != buf) 385 --bufp; 386 sprintf(bufp, "BASE-%s", 387 t4_get_port_type_description( 388 (enum fw_port_type)pi->port_type)); 389 390 dev_info(adap, 391 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 392 loc->domain, loc->bus, loc->devid, loc->function, 393 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 394 (adap->flags & USING_MSIX) ? " MSI-X" : 395 (adap->flags & USING_MSI) ? " MSI" : ""); 396 } 397 } 398 399 /* 400 * Tweak configuration based on system architecture, etc. Most of these have 401 * defaults assigned to them by Firmware Configuration Files (if we're using 402 * them) but need to be explicitly set if we're using hard-coded 403 * initialization. So these are essentially common tweaks/settings for 404 * Configuration Files and hard-coded initialization ... 405 */ 406 static int adap_init0_tweaks(struct adapter *adapter) 407 { 408 u8 rx_dma_offset; 409 410 /* 411 * Fix up various Host-Dependent Parameters like Page Size, Cache 412 * Line Size, etc. The firmware default is for a 4KB Page Size and 413 * 64B Cache Line Size ... 414 */ 415 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 416 T5_LAST_REV); 417 418 /* 419 * Keep the chip default offset to deliver Ingress packets into our 420 * DMA buffers to zero 421 */ 422 rx_dma_offset = 0; 423 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 424 V_PKTSHIFT(rx_dma_offset)); 425 426 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 427 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 428 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 429 430 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 431 V_IDMAARBROUNDROBIN(1U)); 432 433 /* 434 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 435 * adds the pseudo header itself. 436 */ 437 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 438 F_CSUM_HAS_PSEUDO_HDR, 0); 439 440 return 0; 441 } 442 443 /* 444 * Attempt to initialize the adapter via a Firmware Configuration File. 445 */ 446 static int adap_init0_config(struct adapter *adapter, int reset) 447 { 448 struct fw_caps_config_cmd caps_cmd; 449 unsigned long mtype = 0, maddr = 0; 450 u32 finiver, finicsum, cfcsum; 451 int ret; 452 int config_issued = 0; 453 int cfg_addr; 454 char config_name[20]; 455 456 /* 457 * Reset device if necessary. 458 */ 459 if (reset) { 460 ret = t4_fw_reset(adapter, adapter->mbox, 461 F_PIORSTMODE | F_PIORST); 462 if (ret < 0) { 463 dev_warn(adapter, "Firmware reset failed, error %d\n", 464 -ret); 465 goto bye; 466 } 467 } 468 469 cfg_addr = t4_flash_cfg_addr(adapter); 470 if (cfg_addr < 0) { 471 ret = cfg_addr; 472 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 473 -ret); 474 goto bye; 475 } 476 477 strcpy(config_name, "On Flash"); 478 mtype = FW_MEMTYPE_CF_FLASH; 479 maddr = cfg_addr; 480 481 /* 482 * Issue a Capability Configuration command to the firmware to get it 483 * to parse the Configuration File. We don't use t4_fw_config_file() 484 * because we want the ability to modify various features after we've 485 * processed the configuration file ... 486 */ 487 memset(&caps_cmd, 0, sizeof(caps_cmd)); 488 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 489 F_FW_CMD_REQUEST | F_FW_CMD_READ); 490 caps_cmd.cfvalid_to_len16 = 491 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 492 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 493 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 494 FW_LEN16(caps_cmd)); 495 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 496 &caps_cmd); 497 /* 498 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 499 * Configuration File in FLASH), our last gasp effort is to use the 500 * Firmware Configuration File which is embedded in the firmware. A 501 * very few early versions of the firmware didn't have one embedded 502 * but we can ignore those. 503 */ 504 if (ret == -ENOENT) { 505 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 506 __func__); 507 508 memset(&caps_cmd, 0, sizeof(caps_cmd)); 509 caps_cmd.op_to_write = 510 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 511 F_FW_CMD_REQUEST | F_FW_CMD_READ); 512 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 513 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 514 sizeof(caps_cmd), &caps_cmd); 515 strcpy(config_name, "Firmware Default"); 516 } 517 518 config_issued = 1; 519 if (ret < 0) 520 goto bye; 521 522 finiver = be32_to_cpu(caps_cmd.finiver); 523 finicsum = be32_to_cpu(caps_cmd.finicsum); 524 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 525 if (finicsum != cfcsum) 526 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 527 finicsum, cfcsum); 528 529 /* 530 * If we're a pure NIC driver then disable all offloading facilities. 531 * This will allow the firmware to optimize aspects of the hardware 532 * configuration which will result in improved performance. 533 */ 534 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER | 535 FW_CAPS_CONFIG_NIC_ETHOFLD)); 536 caps_cmd.toecaps = 0; 537 caps_cmd.iscsicaps = 0; 538 caps_cmd.rdmacaps = 0; 539 caps_cmd.fcoecaps = 0; 540 541 /* 542 * And now tell the firmware to use the configuration we just loaded. 543 */ 544 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 545 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 546 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 547 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 548 NULL); 549 if (ret < 0) { 550 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 551 -ret); 552 goto bye; 553 } 554 555 /* 556 * Tweak configuration based on system architecture, etc. 557 */ 558 ret = adap_init0_tweaks(adapter); 559 if (ret < 0) { 560 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 561 goto bye; 562 } 563 564 /* 565 * And finally tell the firmware to initialize itself using the 566 * parameters from the Configuration File. 567 */ 568 ret = t4_fw_initialize(adapter, adapter->mbox); 569 if (ret < 0) { 570 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 571 -ret); 572 goto bye; 573 } 574 575 /* 576 * Return successfully and note that we're operating with parameters 577 * not supplied by the driver, rather than from hard-wired 578 * initialization constants burried in the driver. 579 */ 580 dev_info(adapter, 581 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 582 config_name, finiver, cfcsum); 583 584 return 0; 585 586 /* 587 * Something bad happened. Return the error ... (If the "error" 588 * is that there's no Configuration File on the adapter we don't 589 * want to issue a warning since this is fairly common.) 590 */ 591 bye: 592 if (config_issued && ret != -ENOENT) 593 dev_warn(adapter, "\"%s\" configuration file error %d\n", 594 config_name, -ret); 595 596 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 597 return ret; 598 } 599 600 static int adap_init0(struct adapter *adap) 601 { 602 int ret = 0; 603 u32 v, port_vec; 604 enum dev_state state; 605 u32 params[7], val[7]; 606 int reset = 1; 607 int mbox = adap->mbox; 608 609 /* 610 * Contact FW, advertising Master capability. 611 */ 612 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 613 if (ret < 0) { 614 dev_err(adap, "%s: could not connect to FW, error %d\n", 615 __func__, -ret); 616 goto bye; 617 } 618 619 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 620 adap->mbox, ret); 621 622 if (ret == mbox) 623 adap->flags |= MASTER_PF; 624 625 if (state == DEV_STATE_INIT) { 626 /* 627 * Force halt and reset FW because a previous instance may have 628 * exited abnormally without properly shutting down 629 */ 630 ret = t4_fw_halt(adap, adap->mbox, reset); 631 if (ret < 0) { 632 dev_err(adap, "Failed to halt. Exit.\n"); 633 goto bye; 634 } 635 636 ret = t4_fw_restart(adap, adap->mbox, reset); 637 if (ret < 0) { 638 dev_err(adap, "Failed to restart. Exit.\n"); 639 goto bye; 640 } 641 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 642 } 643 644 t4_get_fw_version(adap, &adap->params.fw_vers); 645 t4_get_tp_version(adap, &adap->params.tp_vers); 646 647 dev_info(adap, "fw: %u.%u.%u.%u, TP: %u.%u.%u.%u\n", 648 G_FW_HDR_FW_VER_MAJOR(adap->params.fw_vers), 649 G_FW_HDR_FW_VER_MINOR(adap->params.fw_vers), 650 G_FW_HDR_FW_VER_MICRO(adap->params.fw_vers), 651 G_FW_HDR_FW_VER_BUILD(adap->params.fw_vers), 652 G_FW_HDR_FW_VER_MAJOR(adap->params.tp_vers), 653 G_FW_HDR_FW_VER_MINOR(adap->params.tp_vers), 654 G_FW_HDR_FW_VER_MICRO(adap->params.tp_vers), 655 G_FW_HDR_FW_VER_BUILD(adap->params.tp_vers)); 656 657 ret = t4_get_core_clock(adap, &adap->params.vpd); 658 if (ret < 0) { 659 dev_err(adap, "%s: could not get core clock, error %d\n", 660 __func__, -ret); 661 goto bye; 662 } 663 664 /* 665 * Find out what ports are available to us. Note that we need to do 666 * this before calling adap_init0_no_config() since it needs nports 667 * and portvec ... 668 */ 669 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 670 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 671 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 672 if (ret < 0) { 673 dev_err(adap, "%s: failure in t4_queury_params; error = %d\n", 674 __func__, ret); 675 goto bye; 676 } 677 678 adap->params.nports = hweight32(port_vec); 679 adap->params.portvec = port_vec; 680 681 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 682 adap->params.nports); 683 684 /* 685 * If the firmware is initialized already (and we're not forcing a 686 * master initialization), note that we're living with existing 687 * adapter parameters. Otherwise, it's time to try initializing the 688 * adapter ... 689 */ 690 if (state == DEV_STATE_INIT) { 691 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 692 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 693 } else { 694 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 695 696 ret = adap_init0_config(adap, reset); 697 if (ret == -ENOENT) { 698 dev_err(adap, 699 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 700 goto bye; 701 } 702 } 703 if (ret < 0) { 704 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 705 goto bye; 706 } 707 708 /* 709 * Give the SGE code a chance to pull in anything that it needs ... 710 * Note that this must be called after we retrieve our VPD parameters 711 * in order to know how to convert core ticks to seconds, etc. 712 */ 713 ret = t4_sge_init(adap); 714 if (ret < 0) { 715 dev_err(adap, "t4_sge_init failed with error %d\n", 716 -ret); 717 goto bye; 718 } 719 720 /* 721 * Grab some of our basic fundamental operating parameters. 722 */ 723 #define FW_PARAM_DEV(param) \ 724 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 725 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 726 727 #define FW_PARAM_PFVF(param) \ 728 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 729 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ 730 V_FW_PARAMS_PARAM_Y(0) | \ 731 V_FW_PARAMS_PARAM_Z(0)) 732 733 /* If we're running on newer firmware, let it know that we're 734 * prepared to deal with encapsulated CPL messages. Older 735 * firmware won't understand this and we'll just get 736 * unencapsulated messages ... 737 */ 738 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 739 val[0] = 1; 740 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 741 742 /* 743 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 744 * capability. Earlier versions of the firmware didn't have the 745 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 746 * permission to use ULPTX MEMWRITE DSGL. 747 */ 748 if (is_t4(adap->params.chip)) { 749 adap->params.ulptx_memwrite_dsgl = false; 750 } else { 751 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 752 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 753 1, params, val); 754 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 755 } 756 757 /* 758 * The MTU/MSS Table is initialized by now, so load their values. If 759 * we're initializing the adapter, then we'll make any modifications 760 * we want to the MTU/MSS Table and also initialize the congestion 761 * parameters. 762 */ 763 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 764 if (state != DEV_STATE_INIT) { 765 int i; 766 767 /* 768 * The default MTU Table contains values 1492 and 1500. 769 * However, for TCP, it's better to have two values which are 770 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 771 * This allows us to have a TCP Data Payload which is a 772 * multiple of 8 regardless of what combination of TCP Options 773 * are in use (always a multiple of 4 bytes) which is 774 * important for performance reasons. For instance, if no 775 * options are in use, then we have a 20-byte IP header and a 776 * 20-byte TCP header. In this case, a 1500-byte MSS would 777 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 778 * which is not a multiple of 8. So using an MSS of 1488 in 779 * this case results in a TCP Data Payload of 1448 bytes which 780 * is a multiple of 8. On the other hand, if 12-byte TCP Time 781 * Stamps have been negotiated, then an MTU of 1500 bytes 782 * results in a TCP Data Payload of 1448 bytes which, as 783 * above, is a multiple of 8 bytes ... 784 */ 785 for (i = 0; i < NMTUS; i++) 786 if (adap->params.mtus[i] == 1492) { 787 adap->params.mtus[i] = 1488; 788 break; 789 } 790 791 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 792 adap->params.b_wnd); 793 } 794 t4_init_sge_params(adap); 795 t4_init_tp_params(adap); 796 797 adap->params.drv_memwin = MEMWIN_NIC; 798 adap->flags |= FW_OK; 799 dev_debug(adap, "%s: returning zero..\n", __func__); 800 return 0; 801 802 /* 803 * Something bad happened. If a command timed out or failed with EIO 804 * FW does not operate within its spec or something catastrophic 805 * happened to HW/FW, stop issuing commands. 806 */ 807 bye: 808 if (ret != -ETIMEDOUT && ret != -EIO) 809 t4_fw_bye(adap, adap->mbox); 810 return ret; 811 } 812 813 /** 814 * t4_os_portmod_changed - handle port module changes 815 * @adap: the adapter associated with the module change 816 * @port_id: the port index whose module status has changed 817 * 818 * This is the OS-dependent handler for port module changes. It is 819 * invoked when a port module is removed or inserted for any OS-specific 820 * processing. 821 */ 822 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 823 { 824 static const char * const mod_str[] = { 825 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 826 }; 827 828 const struct port_info *pi = &adap->port[port_id]; 829 830 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 831 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 832 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 833 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 834 mod_str[pi->mod_type]); 835 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 836 dev_info(adap, "Port%d: unsupported optical port module inserted\n", 837 pi->port_id); 838 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 839 dev_info(adap, "Port%d: unknown port module inserted, forcing TWINAX\n", 840 pi->port_id); 841 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 842 dev_info(adap, "Port%d: transceiver module error\n", 843 pi->port_id); 844 else 845 dev_info(adap, "Port%d: unknown module type %d inserted\n", 846 pi->port_id, pi->mod_type); 847 } 848 849 /** 850 * link_start - enable a port 851 * @dev: the port to enable 852 * 853 * Performs the MAC and PHY actions needed to enable a port. 854 */ 855 int link_start(struct port_info *pi) 856 { 857 struct adapter *adapter = pi->adapter; 858 int ret; 859 unsigned int mtu; 860 861 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 862 (ETHER_HDR_LEN + ETHER_CRC_LEN); 863 864 /* 865 * We do not set address filters and promiscuity here, the stack does 866 * that step explicitly. 867 */ 868 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, 869 -1, 1, true); 870 if (ret == 0) { 871 ret = t4_change_mac(adapter, adapter->mbox, pi->viid, 872 pi->xact_addr_filt, 873 (u8 *)&pi->eth_dev->data->mac_addrs[0], 874 true, true); 875 if (ret >= 0) { 876 pi->xact_addr_filt = ret; 877 ret = 0; 878 } 879 } 880 if (ret == 0) 881 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 882 &pi->link_cfg); 883 if (ret == 0) { 884 /* 885 * Enabling a Virtual Interface can result in an interrupt 886 * during the processing of the VI Enable command and, in some 887 * paths, result in an attempt to issue another command in the 888 * interrupt context. Thus, we disable interrupts during the 889 * course of the VI Enable command ... 890 */ 891 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 892 true, true, false); 893 } 894 return ret; 895 } 896 897 /** 898 * cxgb4_write_rss - write the RSS table for a given port 899 * @pi: the port 900 * @queues: array of queue indices for RSS 901 * 902 * Sets up the portion of the HW RSS table for the port's VI to distribute 903 * packets to the Rx queues in @queues. 904 */ 905 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 906 { 907 u16 *rss; 908 int i, err; 909 struct adapter *adapter = pi->adapter; 910 const struct sge_eth_rxq *rxq; 911 912 /* Should never be called before setting up sge eth rx queues */ 913 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 914 915 rxq = &adapter->sge.ethrxq[pi->first_qset]; 916 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 917 if (!rss) 918 return -ENOMEM; 919 920 /* map the queue indices to queue ids */ 921 for (i = 0; i < pi->rss_size; i++, queues++) 922 rss[i] = rxq[*queues].rspq.abs_id; 923 924 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 925 pi->rss_size, rss, pi->rss_size); 926 /* 927 * If Tunnel All Lookup isn't specified in the global RSS 928 * Configuration, then we need to specify a default Ingress 929 * Queue for any ingress packets which aren't hashed. We'll 930 * use our first ingress queue ... 931 */ 932 if (!err) 933 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 934 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 935 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 936 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 937 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | 938 F_FW_RSS_VI_CONFIG_CMD_UDPEN, 939 rss[0]); 940 rte_free(rss); 941 return err; 942 } 943 944 /** 945 * setup_rss - configure RSS 946 * @adapter: the adapter 947 * 948 * Sets up RSS to distribute packets to multiple receive queues. We 949 * configure the RSS CPU lookup table to distribute to the number of HW 950 * receive queues, and the response queue lookup table to narrow that 951 * down to the response queues actually configured for each port. 952 * We always configure the RSS mapping for all ports since the mapping 953 * table has plenty of entries. 954 */ 955 int setup_rss(struct port_info *pi) 956 { 957 int j, err; 958 struct adapter *adapter = pi->adapter; 959 960 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 961 __func__, pi->rss_size, pi->n_rx_qsets); 962 963 if (!(pi->flags & PORT_RSS_DONE)) { 964 if (adapter->flags & FULL_INIT_DONE) { 965 /* Fill default values with equal distribution */ 966 for (j = 0; j < pi->rss_size; j++) 967 pi->rss[j] = j % pi->n_rx_qsets; 968 969 err = cxgb4_write_rss(pi, pi->rss); 970 if (err) 971 return err; 972 pi->flags |= PORT_RSS_DONE; 973 } 974 } 975 return 0; 976 } 977 978 /* 979 * Enable NAPI scheduling and interrupt generation for all Rx queues. 980 */ 981 static void enable_rx(struct adapter *adap) 982 { 983 struct sge *s = &adap->sge; 984 struct sge_rspq *q = &s->fw_evtq; 985 int i, j; 986 987 /* 0-increment GTS to start the timer and enable interrupts */ 988 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), 989 V_SEINTARM(q->intr_params) | 990 V_INGRESSQID(q->cntxt_id)); 991 992 for_each_port(adap, i) { 993 const struct port_info *pi = &adap->port[i]; 994 struct rte_eth_dev *eth_dev = pi->eth_dev; 995 996 for (j = 0; j < eth_dev->data->nb_rx_queues; j++) { 997 q = eth_dev->data->rx_queues[j]; 998 999 /* 1000 * 0-increment GTS to start the timer and enable 1001 * interrupts 1002 */ 1003 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), 1004 V_SEINTARM(q->intr_params) | 1005 V_INGRESSQID(q->cntxt_id)); 1006 } 1007 } 1008 } 1009 1010 /** 1011 * cxgb_up - enable the adapter 1012 * @adap: adapter being enabled 1013 * 1014 * Called when the first port is enabled, this function performs the 1015 * actions necessary to make an adapter operational, such as completing 1016 * the initialization of HW modules, and enabling interrupts. 1017 */ 1018 int cxgbe_up(struct adapter *adap) 1019 { 1020 enable_rx(adap); 1021 t4_sge_tx_monitor_start(adap); 1022 t4_intr_enable(adap); 1023 adap->flags |= FULL_INIT_DONE; 1024 1025 /* TODO: deadman watchdog ?? */ 1026 return 0; 1027 } 1028 1029 /* 1030 * Close the port 1031 */ 1032 int cxgbe_down(struct port_info *pi) 1033 { 1034 struct adapter *adapter = pi->adapter; 1035 int err = 0; 1036 1037 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false); 1038 if (err) { 1039 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1040 return err; 1041 } 1042 1043 t4_reset_link_config(adapter, pi->port_id); 1044 return 0; 1045 } 1046 1047 /* 1048 * Release resources when all the ports have been stopped. 1049 */ 1050 void cxgbe_close(struct adapter *adapter) 1051 { 1052 struct port_info *pi; 1053 int i; 1054 1055 if (adapter->flags & FULL_INIT_DONE) { 1056 t4_intr_disable(adapter); 1057 t4_sge_tx_monitor_stop(adapter); 1058 t4_free_sge_resources(adapter); 1059 for_each_port(adapter, i) { 1060 pi = adap2pinfo(adapter, i); 1061 if (pi->viid != 0) 1062 t4_free_vi(adapter, adapter->mbox, 1063 adapter->pf, 0, pi->viid); 1064 rte_free(pi->eth_dev->data->mac_addrs); 1065 } 1066 adapter->flags &= ~FULL_INIT_DONE; 1067 } 1068 1069 if (adapter->flags & FW_OK) 1070 t4_fw_bye(adapter, adapter->mbox); 1071 } 1072 1073 int cxgbe_probe(struct adapter *adapter) 1074 { 1075 struct port_info *pi; 1076 int func, i; 1077 int err = 0; 1078 1079 func = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); 1080 adapter->mbox = func; 1081 adapter->pf = func; 1082 1083 t4_os_lock_init(&adapter->mbox_lock); 1084 TAILQ_INIT(&adapter->mbox_list); 1085 1086 err = t4_prep_adapter(adapter); 1087 if (err) 1088 return err; 1089 1090 setup_memwin(adapter); 1091 err = adap_init0(adapter); 1092 if (err) { 1093 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 1094 __func__, err); 1095 goto out_free; 1096 } 1097 1098 if (!is_t4(adapter->params.chip)) { 1099 /* 1100 * The userspace doorbell BAR is split evenly into doorbell 1101 * regions, each associated with an egress queue. If this 1102 * per-queue region is large enough (at least UDBS_SEG_SIZE) 1103 * then it can be used to submit a tx work request with an 1104 * implied doorbell. Enable write combining on the BAR if 1105 * there is room for such work requests. 1106 */ 1107 int s_qpp, qpp, num_seg; 1108 1109 s_qpp = (S_QUEUESPERPAGEPF0 + 1110 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 1111 adapter->pf); 1112 qpp = 1 << ((t4_read_reg(adapter, 1113 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 1114 & M_QUEUESPERPAGEPF0); 1115 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 1116 if (qpp > num_seg) 1117 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 1118 1119 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 1120 if (!adapter->bar2) { 1121 dev_err(adapter, "cannot map device bar2 region\n"); 1122 err = -ENOMEM; 1123 goto out_free; 1124 } 1125 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 1126 V_STATMODE(0)); 1127 } 1128 1129 for_each_port(adapter, i) { 1130 char name[RTE_ETH_NAME_MAX_LEN]; 1131 struct rte_eth_dev_data *data = NULL; 1132 const unsigned int numa_node = rte_socket_id(); 1133 1134 pi = &adapter->port[i]; 1135 pi->adapter = adapter; 1136 pi->xact_addr_filt = -1; 1137 pi->port_id = i; 1138 1139 snprintf(name, sizeof(name), "cxgbe%d", 1140 adapter->eth_dev->data->port_id + i); 1141 1142 if (i == 0) { 1143 /* First port is already allocated by DPDK */ 1144 pi->eth_dev = adapter->eth_dev; 1145 goto allocate_mac; 1146 } 1147 1148 /* 1149 * now do all data allocation - for eth_dev structure, 1150 * and internal (private) data for the remaining ports 1151 */ 1152 1153 /* reserve an ethdev entry */ 1154 pi->eth_dev = rte_eth_dev_allocate(name); 1155 if (!pi->eth_dev) 1156 goto out_free; 1157 1158 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node); 1159 if (!data) 1160 goto out_free; 1161 1162 data->port_id = adapter->eth_dev->data->port_id + i; 1163 1164 pi->eth_dev->data = data; 1165 1166 allocate_mac: 1167 pi->eth_dev->device = &adapter->pdev->device; 1168 pi->eth_dev->data->dev_private = pi; 1169 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 1170 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 1171 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 1172 1173 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 1174 1175 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 1176 ETHER_ADDR_LEN, 0); 1177 if (!pi->eth_dev->data->mac_addrs) { 1178 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 1179 __func__); 1180 err = -1; 1181 goto out_free; 1182 } 1183 } 1184 1185 if (adapter->flags & FW_OK) { 1186 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 1187 if (err) { 1188 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 1189 __func__, err); 1190 goto out_free; 1191 } 1192 } 1193 1194 cfg_queues(adapter->eth_dev); 1195 1196 print_port_info(adapter); 1197 1198 err = init_rss(adapter); 1199 if (err) 1200 goto out_free; 1201 1202 return 0; 1203 1204 out_free: 1205 for_each_port(adapter, i) { 1206 pi = adap2pinfo(adapter, i); 1207 if (pi->viid != 0) 1208 t4_free_vi(adapter, adapter->mbox, adapter->pf, 1209 0, pi->viid); 1210 /* Skip first port since it'll be de-allocated by DPDK */ 1211 if (i == 0) 1212 continue; 1213 if (pi->eth_dev->data) 1214 rte_free(pi->eth_dev->data); 1215 } 1216 1217 if (adapter->flags & FW_OK) 1218 t4_fw_bye(adapter, adapter->mbox); 1219 return -err; 1220 } 1221