1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_atomic.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_random.h> 33 #include <rte_dev.h> 34 #include <rte_kvargs.h> 35 36 #include "base/common.h" 37 #include "base/t4_regs.h" 38 #include "base/t4_msg.h" 39 #include "cxgbe.h" 40 #include "clip_tbl.h" 41 #include "l2t.h" 42 #include "mps_tcam.h" 43 44 /** 45 * Allocate a chunk of memory. The allocated memory is cleared. 46 */ 47 void *t4_alloc_mem(size_t size) 48 { 49 return rte_zmalloc(NULL, size, 0); 50 } 51 52 /** 53 * Free memory allocated through t4_alloc_mem(). 54 */ 55 void t4_free_mem(void *addr) 56 { 57 rte_free(addr); 58 } 59 60 /* 61 * Response queue handler for the FW event queue. 62 */ 63 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 64 __rte_unused const struct pkt_gl *gl) 65 { 66 u8 opcode = ((const struct rss_header *)rsp)->opcode; 67 68 rsp++; /* skip RSS header */ 69 70 /* 71 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 72 */ 73 if (unlikely(opcode == CPL_FW4_MSG && 74 ((const struct cpl_fw4_msg *)rsp)->type == 75 FW_TYPE_RSSCPL)) { 76 rsp++; 77 opcode = ((const struct rss_header *)rsp)->opcode; 78 rsp++; 79 if (opcode != CPL_SGE_EGR_UPDATE) { 80 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 81 opcode); 82 goto out; 83 } 84 } 85 86 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 87 /* do nothing */ 88 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 89 const struct cpl_fw6_msg *msg = (const void *)rsp; 90 91 t4_handle_fw_rpl(q->adapter, msg->data); 92 } else if (opcode == CPL_ABORT_RPL_RSS) { 93 const struct cpl_abort_rpl_rss *p = (const void *)rsp; 94 95 hash_del_filter_rpl(q->adapter, p); 96 } else if (opcode == CPL_SET_TCB_RPL) { 97 const struct cpl_set_tcb_rpl *p = (const void *)rsp; 98 99 filter_rpl(q->adapter, p); 100 } else if (opcode == CPL_ACT_OPEN_RPL) { 101 const struct cpl_act_open_rpl *p = (const void *)rsp; 102 103 hash_filter_rpl(q->adapter, p); 104 } else if (opcode == CPL_L2T_WRITE_RPL) { 105 const struct cpl_l2t_write_rpl *p = (const void *)rsp; 106 107 do_l2t_write_rpl(q->adapter, p); 108 } else { 109 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 110 opcode); 111 } 112 out: 113 return 0; 114 } 115 116 /** 117 * Setup sge control queues to pass control information. 118 */ 119 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter) 120 { 121 struct sge *s = &adapter->sge; 122 int err = 0, i = 0; 123 124 for_each_port(adapter, i) { 125 struct port_info *pi = adap2pinfo(adapter, i); 126 char name[RTE_ETH_NAME_MAX_LEN]; 127 struct sge_ctrl_txq *q = &s->ctrlq[i]; 128 129 q->q.size = 1024; 130 err = t4_sge_alloc_ctrl_txq(adapter, q, 131 adapter->eth_dev, i, 132 s->fw_evtq.cntxt_id, 133 rte_socket_id()); 134 if (err) { 135 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d", 136 err); 137 goto out; 138 } 139 snprintf(name, sizeof(name), "%s_ctrl_pool_%d", 140 pi->eth_dev->device->driver->name, 141 pi->eth_dev->data->port_id); 142 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size, 143 RTE_CACHE_LINE_SIZE, 144 RTE_MBUF_PRIV_ALIGN, 145 RTE_MBUF_DEFAULT_BUF_SIZE, 146 SOCKET_ID_ANY); 147 if (!q->mb_pool) { 148 err = -rte_errno; 149 dev_err(adapter, 150 "Can't create ctrl pool for port %d. Err: %d\n", 151 pi->eth_dev->data->port_id, err); 152 goto out; 153 } 154 } 155 return 0; 156 out: 157 t4_free_sge_resources(adapter); 158 return err; 159 } 160 161 /** 162 * cxgbe_poll_for_completion: Poll rxq for completion 163 * @q: rxq to poll 164 * @ms: milliseconds to delay 165 * @cnt: number of times to poll 166 * @c: completion to check for 'done' status 167 * 168 * Polls the rxq for reples until completion is done or the count 169 * expires. 170 */ 171 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms, 172 unsigned int cnt, struct t4_completion *c) 173 { 174 unsigned int i; 175 unsigned int work_done, budget = 32; 176 177 if (!c) 178 return -EINVAL; 179 180 for (i = 0; i < cnt; i++) { 181 cxgbe_poll(q, NULL, budget, &work_done); 182 t4_os_lock(&c->lock); 183 if (c->done) { 184 t4_os_unlock(&c->lock); 185 return 0; 186 } 187 t4_os_unlock(&c->lock); 188 rte_delay_ms(ms); 189 } 190 return -ETIMEDOUT; 191 } 192 193 int cxgbe_setup_sge_fwevtq(struct adapter *adapter) 194 { 195 struct sge *s = &adapter->sge; 196 int err = 0; 197 int msi_idx = 0; 198 199 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 200 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 201 rte_socket_id()); 202 return err; 203 } 204 205 static int closest_timer(const struct sge *s, int time) 206 { 207 unsigned int i, match = 0; 208 int delta, min_delta = INT_MAX; 209 210 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 211 delta = time - s->timer_val[i]; 212 if (delta < 0) 213 delta = -delta; 214 if (delta < min_delta) { 215 min_delta = delta; 216 match = i; 217 } 218 } 219 return match; 220 } 221 222 static int closest_thres(const struct sge *s, int thres) 223 { 224 unsigned int i, match = 0; 225 int delta, min_delta = INT_MAX; 226 227 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 228 delta = thres - s->counter_val[i]; 229 if (delta < 0) 230 delta = -delta; 231 if (delta < min_delta) { 232 min_delta = delta; 233 match = i; 234 } 235 } 236 return match; 237 } 238 239 /** 240 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 241 * @q: the Rx queue 242 * @us: the hold-off time in us, or 0 to disable timer 243 * @cnt: the hold-off packet count, or 0 to disable counter 244 * 245 * Sets an Rx queue's interrupt hold-off time and packet count. At least 246 * one of the two needs to be enabled for the queue to generate interrupts. 247 */ 248 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 249 unsigned int cnt) 250 { 251 struct adapter *adap = q->adapter; 252 unsigned int timer_val; 253 254 if (cnt) { 255 int err; 256 u32 v, new_idx; 257 258 new_idx = closest_thres(&adap->sge, cnt); 259 if (q->desc && q->pktcnt_idx != new_idx) { 260 /* the queue has already been created, update it */ 261 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 262 V_FW_PARAMS_PARAM_X( 263 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 264 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 265 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 266 &v, &new_idx); 267 if (err) 268 return err; 269 } 270 q->pktcnt_idx = new_idx; 271 } 272 273 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 274 closest_timer(&adap->sge, us); 275 276 if ((us | cnt) == 0) 277 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 278 else 279 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 280 V_QINTR_CNT_EN(cnt > 0); 281 return 0; 282 } 283 284 /** 285 * Allocate an active-open TID and set it to the supplied value. 286 */ 287 int cxgbe_alloc_atid(struct tid_info *t, void *data) 288 { 289 int atid = -1; 290 291 t4_os_lock(&t->atid_lock); 292 if (t->afree) { 293 union aopen_entry *p = t->afree; 294 295 atid = p - t->atid_tab; 296 t->afree = p->next; 297 p->data = data; 298 t->atids_in_use++; 299 } 300 t4_os_unlock(&t->atid_lock); 301 return atid; 302 } 303 304 /** 305 * Release an active-open TID. 306 */ 307 void cxgbe_free_atid(struct tid_info *t, unsigned int atid) 308 { 309 union aopen_entry *p = &t->atid_tab[atid]; 310 311 t4_os_lock(&t->atid_lock); 312 p->next = t->afree; 313 t->afree = p; 314 t->atids_in_use--; 315 t4_os_unlock(&t->atid_lock); 316 } 317 318 /** 319 * Populate a TID_RELEASE WR. Caller must properly size the skb. 320 */ 321 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid) 322 { 323 struct cpl_tid_release *req; 324 325 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *); 326 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 327 } 328 329 /** 330 * Release a TID and inform HW. If we are unable to allocate the release 331 * message we defer to a work queue. 332 */ 333 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 334 unsigned short family) 335 { 336 struct rte_mbuf *mbuf; 337 struct adapter *adap = container_of(t, struct adapter, tids); 338 339 WARN_ON(tid >= t->ntids); 340 341 if (t->tid_tab[tid]) { 342 t->tid_tab[tid] = NULL; 343 rte_atomic32_dec(&t->conns_in_use); 344 if (t->hash_base && tid >= t->hash_base) { 345 if (family == FILTER_TYPE_IPV4) 346 rte_atomic32_dec(&t->hash_tids_in_use); 347 } else { 348 if (family == FILTER_TYPE_IPV4) 349 rte_atomic32_dec(&t->tids_in_use); 350 } 351 } 352 353 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool); 354 if (mbuf) { 355 mbuf->data_len = sizeof(struct cpl_tid_release); 356 mbuf->pkt_len = mbuf->data_len; 357 mk_tid_release(mbuf, tid); 358 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf); 359 } 360 } 361 362 /** 363 * Insert a TID. 364 */ 365 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, 366 unsigned short family) 367 { 368 t->tid_tab[tid] = data; 369 if (t->hash_base && tid >= t->hash_base) { 370 if (family == FILTER_TYPE_IPV4) 371 rte_atomic32_inc(&t->hash_tids_in_use); 372 } else { 373 if (family == FILTER_TYPE_IPV4) 374 rte_atomic32_inc(&t->tids_in_use); 375 } 376 377 rte_atomic32_inc(&t->conns_in_use); 378 } 379 380 /** 381 * Free TID tables. 382 */ 383 static void tid_free(struct tid_info *t) 384 { 385 if (t->tid_tab) { 386 if (t->ftid_bmap) 387 rte_bitmap_free(t->ftid_bmap); 388 389 if (t->ftid_bmap_array) 390 t4_os_free(t->ftid_bmap_array); 391 392 t4_os_free(t->tid_tab); 393 } 394 395 memset(t, 0, sizeof(struct tid_info)); 396 } 397 398 /** 399 * Allocate and initialize the TID tables. Returns 0 on success. 400 */ 401 static int tid_init(struct tid_info *t) 402 { 403 size_t size; 404 unsigned int ftid_bmap_size; 405 unsigned int natids = t->natids; 406 unsigned int max_ftids = t->nftids; 407 408 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids); 409 size = t->ntids * sizeof(*t->tid_tab) + 410 max_ftids * sizeof(*t->ftid_tab) + 411 natids * sizeof(*t->atid_tab); 412 413 t->tid_tab = t4_os_alloc(size); 414 if (!t->tid_tab) 415 return -ENOMEM; 416 417 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 418 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids]; 419 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size); 420 if (!t->ftid_bmap_array) { 421 tid_free(t); 422 return -ENOMEM; 423 } 424 425 t4_os_lock_init(&t->atid_lock); 426 t4_os_lock_init(&t->ftid_lock); 427 428 t->afree = NULL; 429 t->atids_in_use = 0; 430 rte_atomic32_init(&t->tids_in_use); 431 rte_atomic32_set(&t->tids_in_use, 0); 432 rte_atomic32_init(&t->conns_in_use); 433 rte_atomic32_set(&t->conns_in_use, 0); 434 435 /* Setup the free list for atid_tab and clear the stid bitmap. */ 436 if (natids) { 437 while (--natids) 438 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 439 t->afree = t->atid_tab; 440 } 441 442 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array, 443 ftid_bmap_size); 444 if (!t->ftid_bmap) { 445 tid_free(t); 446 return -ENOMEM; 447 } 448 449 return 0; 450 } 451 452 static inline bool is_x_1g_port(const struct link_config *lc) 453 { 454 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0; 455 } 456 457 static inline bool is_x_10g_port(const struct link_config *lc) 458 { 459 unsigned int speeds, high_speeds; 460 461 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps)); 462 high_speeds = speeds & 463 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 464 465 return high_speeds != 0; 466 } 467 468 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 469 unsigned int us, unsigned int cnt, 470 unsigned int size, unsigned int iqe_size) 471 { 472 q->adapter = adap; 473 cxgb4_set_rspq_intr_params(q, us, cnt); 474 q->iqe_len = iqe_size; 475 q->size = size; 476 } 477 478 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev) 479 { 480 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 481 struct adapter *adap = pi->adapter; 482 struct sge *s = &adap->sge; 483 unsigned int max_queues = s->max_ethqsets / adap->params.nports; 484 485 if ((eth_dev->data->nb_rx_queues < 1) || 486 (eth_dev->data->nb_tx_queues < 1)) 487 return -EINVAL; 488 489 if ((eth_dev->data->nb_rx_queues > max_queues) || 490 (eth_dev->data->nb_tx_queues > max_queues)) 491 return -EINVAL; 492 493 if (eth_dev->data->nb_rx_queues > pi->rss_size) 494 return -EINVAL; 495 496 /* We must configure RSS, since config has changed*/ 497 pi->flags &= ~PORT_RSS_DONE; 498 499 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 500 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 501 502 return 0; 503 } 504 505 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev) 506 { 507 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 508 struct adapter *adap = pi->adapter; 509 struct sge *s = &adap->sge; 510 unsigned int i, nb_ports = 0, qidx = 0; 511 unsigned int q_per_port = 0; 512 513 if (!(adap->flags & CFG_QUEUES)) { 514 for_each_port(adap, i) { 515 struct port_info *tpi = adap2pinfo(adap, i); 516 517 nb_ports += (is_x_10g_port(&tpi->link_cfg)) || 518 is_x_1g_port(&tpi->link_cfg) ? 1 : 0; 519 } 520 521 /* 522 * We default up to # of cores queues per 1G/10G port. 523 */ 524 if (nb_ports) 525 q_per_port = (s->max_ethqsets - 526 (adap->params.nports - nb_ports)) / 527 nb_ports; 528 529 if (q_per_port > rte_lcore_count()) 530 q_per_port = rte_lcore_count(); 531 532 for_each_port(adap, i) { 533 struct port_info *pi = adap2pinfo(adap, i); 534 535 pi->first_qset = qidx; 536 537 /* Initially n_rx_qsets == n_tx_qsets */ 538 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) || 539 is_x_1g_port(&pi->link_cfg)) ? 540 q_per_port : 1; 541 pi->n_tx_qsets = pi->n_rx_qsets; 542 543 if (pi->n_rx_qsets > pi->rss_size) 544 pi->n_rx_qsets = pi->rss_size; 545 546 qidx += pi->n_rx_qsets; 547 } 548 549 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 550 struct sge_eth_rxq *r = &s->ethrxq[i]; 551 552 init_rspq(adap, &r->rspq, 5, 32, 1024, 64); 553 r->usembufs = 1; 554 r->fl.size = (r->usembufs ? 1024 : 72); 555 } 556 557 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 558 s->ethtxq[i].q.size = 1024; 559 560 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 561 adap->flags |= CFG_QUEUES; 562 } 563 } 564 565 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 566 { 567 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 568 &pi->stats_base); 569 } 570 571 void cxgbe_stats_reset(struct port_info *pi) 572 { 573 t4_clr_port_stats(pi->adapter, pi->tx_chan); 574 } 575 576 static void setup_memwin(struct adapter *adap) 577 { 578 u32 mem_win0_base; 579 580 /* For T5, only relative offset inside the PCIe BAR is passed */ 581 mem_win0_base = MEMWIN0_BASE; 582 583 /* 584 * Set up memory window for accessing adapter memory ranges. (Read 585 * back MA register to ensure that changes propagate before we attempt 586 * to use the new values.) 587 */ 588 t4_write_reg(adap, 589 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 590 MEMWIN_NIC), 591 mem_win0_base | V_BIR(0) | 592 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 593 t4_read_reg(adap, 594 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 595 MEMWIN_NIC)); 596 } 597 598 int cxgbe_init_rss(struct adapter *adap) 599 { 600 unsigned int i; 601 602 if (is_pf4(adap)) { 603 int err; 604 605 err = t4_init_rss_mode(adap, adap->mbox); 606 if (err) 607 return err; 608 } 609 610 for_each_port(adap, i) { 611 struct port_info *pi = adap2pinfo(adap, i); 612 613 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 614 if (!pi->rss) 615 return -ENOMEM; 616 617 pi->rss_hf = CXGBE_RSS_HF_ALL; 618 } 619 return 0; 620 } 621 622 /** 623 * Dump basic information about the adapter. 624 */ 625 void cxgbe_print_adapter_info(struct adapter *adap) 626 { 627 /** 628 * Hardware/Firmware/etc. Version/Revision IDs. 629 */ 630 t4_dump_version_info(adap); 631 } 632 633 void cxgbe_print_port_info(struct adapter *adap) 634 { 635 int i; 636 char buf[80]; 637 struct rte_pci_addr *loc = &adap->pdev->addr; 638 639 for_each_port(adap, i) { 640 const struct port_info *pi = adap2pinfo(adap, i); 641 char *bufp = buf; 642 643 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 644 bufp += sprintf(bufp, "100M/"); 645 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 646 bufp += sprintf(bufp, "1G/"); 647 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 648 bufp += sprintf(bufp, "10G/"); 649 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 650 bufp += sprintf(bufp, "25G/"); 651 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 652 bufp += sprintf(bufp, "40G/"); 653 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 654 bufp += sprintf(bufp, "50G/"); 655 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 656 bufp += sprintf(bufp, "100G/"); 657 if (bufp != buf) 658 --bufp; 659 sprintf(bufp, "BASE-%s", 660 t4_get_port_type_description( 661 (enum fw_port_type)pi->port_type)); 662 663 dev_info(adap, 664 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 665 loc->domain, loc->bus, loc->devid, loc->function, 666 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 667 (adap->flags & USING_MSIX) ? " MSI-X" : 668 (adap->flags & USING_MSI) ? " MSI" : ""); 669 } 670 } 671 672 static int 673 check_devargs_handler(__rte_unused const char *key, const char *value, 674 __rte_unused void *opaque) 675 { 676 if (strcmp(value, "1")) 677 return -1; 678 679 return 0; 680 } 681 682 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key) 683 { 684 struct rte_kvargs *kvlist; 685 686 if (!devargs) 687 return 0; 688 689 kvlist = rte_kvargs_parse(devargs->args, NULL); 690 if (!kvlist) 691 return 0; 692 693 if (!rte_kvargs_count(kvlist, key)) { 694 rte_kvargs_free(kvlist); 695 return 0; 696 } 697 698 if (rte_kvargs_process(kvlist, key, 699 check_devargs_handler, NULL) < 0) { 700 rte_kvargs_free(kvlist); 701 return 0; 702 } 703 rte_kvargs_free(kvlist); 704 705 return 1; 706 } 707 708 static void configure_vlan_types(struct adapter *adapter) 709 { 710 struct rte_pci_device *pdev = adapter->pdev; 711 int i; 712 713 for_each_port(adapter, i) { 714 /* OVLAN Type 0x88a8 */ 715 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0), 716 V_OVLAN_MASK(M_OVLAN_MASK) | 717 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 718 V_OVLAN_MASK(M_OVLAN_MASK) | 719 V_OVLAN_ETYPE(0x88a8)); 720 /* OVLAN Type 0x9100 */ 721 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1), 722 V_OVLAN_MASK(M_OVLAN_MASK) | 723 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 724 V_OVLAN_MASK(M_OVLAN_MASK) | 725 V_OVLAN_ETYPE(0x9100)); 726 /* OVLAN Type 0x8100 */ 727 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2), 728 V_OVLAN_MASK(M_OVLAN_MASK) | 729 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 730 V_OVLAN_MASK(M_OVLAN_MASK) | 731 V_OVLAN_ETYPE(0x8100)); 732 733 /* IVLAN 0X8100 */ 734 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), 735 V_IVLAN_ETYPE(M_IVLAN_ETYPE), 736 V_IVLAN_ETYPE(0x8100)); 737 738 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), 739 F_OVLAN_EN0 | F_OVLAN_EN1 | 740 F_OVLAN_EN2 | F_IVLAN_EN, 741 F_OVLAN_EN0 | F_OVLAN_EN1 | 742 F_OVLAN_EN2 | F_IVLAN_EN); 743 } 744 745 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN)) 746 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 747 V_RM_OVLAN(1), V_RM_OVLAN(0)); 748 } 749 750 static void configure_pcie_ext_tag(struct adapter *adapter) 751 { 752 u16 v; 753 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 754 755 if (!pos) 756 return; 757 758 if (pos > 0) { 759 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v); 760 v |= PCI_EXP_DEVCTL_EXT_TAG; 761 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v); 762 if (is_t6(adapter->params.chip)) { 763 t4_set_reg_field(adapter, A_PCIE_CFG2, 764 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG), 765 V_T6_TOTMAXTAG(7)); 766 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 767 V_T6_MINTAG(M_T6_MINTAG), 768 V_T6_MINTAG(8)); 769 } else { 770 t4_set_reg_field(adapter, A_PCIE_CFG2, 771 V_TOTMAXTAG(M_TOTMAXTAG), 772 V_TOTMAXTAG(3)); 773 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 774 V_MINTAG(M_MINTAG), 775 V_MINTAG(8)); 776 } 777 } 778 } 779 780 /* Figure out how many Queue Sets we can support */ 781 void cxgbe_configure_max_ethqsets(struct adapter *adapter) 782 { 783 unsigned int ethqsets; 784 785 /* 786 * We need to reserve an Ingress Queue for the Asynchronous Firmware 787 * Event Queue. 788 * 789 * For each Queue Set, we'll need the ability to allocate two Egress 790 * Contexts -- one for the Ingress Queue Free List and one for the TX 791 * Ethernet Queue. 792 */ 793 if (is_pf4(adapter)) { 794 struct pf_resources *pfres = &adapter->params.pfres; 795 796 ethqsets = pfres->niqflint - 1; 797 if (pfres->neq < ethqsets * 2) 798 ethqsets = pfres->neq / 2; 799 } else { 800 struct vf_resources *vfres = &adapter->params.vfres; 801 802 ethqsets = vfres->niqflint - 1; 803 if (vfres->nethctrl != ethqsets) 804 ethqsets = min(vfres->nethctrl, ethqsets); 805 if (vfres->neq < ethqsets * 2) 806 ethqsets = vfres->neq / 2; 807 } 808 809 if (ethqsets > MAX_ETH_QSETS) 810 ethqsets = MAX_ETH_QSETS; 811 adapter->sge.max_ethqsets = ethqsets; 812 } 813 814 /* 815 * Tweak configuration based on system architecture, etc. Most of these have 816 * defaults assigned to them by Firmware Configuration Files (if we're using 817 * them) but need to be explicitly set if we're using hard-coded 818 * initialization. So these are essentially common tweaks/settings for 819 * Configuration Files and hard-coded initialization ... 820 */ 821 static int adap_init0_tweaks(struct adapter *adapter) 822 { 823 u8 rx_dma_offset; 824 825 /* 826 * Fix up various Host-Dependent Parameters like Page Size, Cache 827 * Line Size, etc. The firmware default is for a 4KB Page Size and 828 * 64B Cache Line Size ... 829 */ 830 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 831 T5_LAST_REV); 832 833 /* 834 * Keep the chip default offset to deliver Ingress packets into our 835 * DMA buffers to zero 836 */ 837 rx_dma_offset = 0; 838 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 839 V_PKTSHIFT(rx_dma_offset)); 840 841 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 842 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 843 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 844 845 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD, 846 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U)); 847 848 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 849 V_IDMAARBROUNDROBIN(1U)); 850 851 /* 852 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 853 * adds the pseudo header itself. 854 */ 855 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 856 F_CSUM_HAS_PSEUDO_HDR, 0); 857 858 return 0; 859 } 860 861 /* 862 * Attempt to initialize the adapter via a Firmware Configuration File. 863 */ 864 static int adap_init0_config(struct adapter *adapter, int reset) 865 { 866 struct fw_caps_config_cmd caps_cmd; 867 unsigned long mtype = 0, maddr = 0; 868 u32 finiver, finicsum, cfcsum; 869 int ret; 870 int config_issued = 0; 871 int cfg_addr; 872 char config_name[20]; 873 874 /* 875 * Reset device if necessary. 876 */ 877 if (reset) { 878 ret = t4_fw_reset(adapter, adapter->mbox, 879 F_PIORSTMODE | F_PIORST); 880 if (ret < 0) { 881 dev_warn(adapter, "Firmware reset failed, error %d\n", 882 -ret); 883 goto bye; 884 } 885 } 886 887 cfg_addr = t4_flash_cfg_addr(adapter); 888 if (cfg_addr < 0) { 889 ret = cfg_addr; 890 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 891 -ret); 892 goto bye; 893 } 894 895 strcpy(config_name, "On Flash"); 896 mtype = FW_MEMTYPE_CF_FLASH; 897 maddr = cfg_addr; 898 899 /* 900 * Issue a Capability Configuration command to the firmware to get it 901 * to parse the Configuration File. We don't use t4_fw_config_file() 902 * because we want the ability to modify various features after we've 903 * processed the configuration file ... 904 */ 905 memset(&caps_cmd, 0, sizeof(caps_cmd)); 906 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 907 F_FW_CMD_REQUEST | F_FW_CMD_READ); 908 caps_cmd.cfvalid_to_len16 = 909 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 910 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 911 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 912 FW_LEN16(caps_cmd)); 913 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 914 &caps_cmd); 915 /* 916 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 917 * Configuration File in FLASH), our last gasp effort is to use the 918 * Firmware Configuration File which is embedded in the firmware. A 919 * very few early versions of the firmware didn't have one embedded 920 * but we can ignore those. 921 */ 922 if (ret == -ENOENT) { 923 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 924 __func__); 925 926 memset(&caps_cmd, 0, sizeof(caps_cmd)); 927 caps_cmd.op_to_write = 928 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 929 F_FW_CMD_REQUEST | F_FW_CMD_READ); 930 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 931 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 932 sizeof(caps_cmd), &caps_cmd); 933 strcpy(config_name, "Firmware Default"); 934 } 935 936 config_issued = 1; 937 if (ret < 0) 938 goto bye; 939 940 finiver = be32_to_cpu(caps_cmd.finiver); 941 finicsum = be32_to_cpu(caps_cmd.finicsum); 942 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 943 if (finicsum != cfcsum) 944 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 945 finicsum, cfcsum); 946 947 /* 948 * If we're a pure NIC driver then disable all offloading facilities. 949 * This will allow the firmware to optimize aspects of the hardware 950 * configuration which will result in improved performance. 951 */ 952 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD); 953 caps_cmd.toecaps = 0; 954 caps_cmd.iscsicaps = 0; 955 caps_cmd.rdmacaps = 0; 956 caps_cmd.fcoecaps = 0; 957 958 /* 959 * And now tell the firmware to use the configuration we just loaded. 960 */ 961 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 962 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 963 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 964 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 965 NULL); 966 if (ret < 0) { 967 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 968 -ret); 969 goto bye; 970 } 971 972 /* 973 * Tweak configuration based on system architecture, etc. 974 */ 975 ret = adap_init0_tweaks(adapter); 976 if (ret < 0) { 977 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 978 goto bye; 979 } 980 981 /* 982 * And finally tell the firmware to initialize itself using the 983 * parameters from the Configuration File. 984 */ 985 ret = t4_fw_initialize(adapter, adapter->mbox); 986 if (ret < 0) { 987 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 988 -ret); 989 goto bye; 990 } 991 992 /* 993 * Return successfully and note that we're operating with parameters 994 * not supplied by the driver, rather than from hard-wired 995 * initialization constants buried in the driver. 996 */ 997 dev_info(adapter, 998 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 999 config_name, finiver, cfcsum); 1000 1001 return 0; 1002 1003 /* 1004 * Something bad happened. Return the error ... (If the "error" 1005 * is that there's no Configuration File on the adapter we don't 1006 * want to issue a warning since this is fairly common.) 1007 */ 1008 bye: 1009 if (config_issued && ret != -ENOENT) 1010 dev_warn(adapter, "\"%s\" configuration file error %d\n", 1011 config_name, -ret); 1012 1013 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 1014 return ret; 1015 } 1016 1017 static int adap_init0(struct adapter *adap) 1018 { 1019 struct fw_caps_config_cmd caps_cmd; 1020 int ret = 0; 1021 u32 v, port_vec; 1022 enum dev_state state; 1023 u32 params[7], val[7]; 1024 int reset = 1; 1025 int mbox = adap->mbox; 1026 1027 /* 1028 * Contact FW, advertising Master capability. 1029 */ 1030 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 1031 if (ret < 0) { 1032 dev_err(adap, "%s: could not connect to FW, error %d\n", 1033 __func__, -ret); 1034 goto bye; 1035 } 1036 1037 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 1038 adap->mbox, ret); 1039 1040 if (ret == mbox) 1041 adap->flags |= MASTER_PF; 1042 1043 if (state == DEV_STATE_INIT) { 1044 /* 1045 * Force halt and reset FW because a previous instance may have 1046 * exited abnormally without properly shutting down 1047 */ 1048 ret = t4_fw_halt(adap, adap->mbox, reset); 1049 if (ret < 0) { 1050 dev_err(adap, "Failed to halt. Exit.\n"); 1051 goto bye; 1052 } 1053 1054 ret = t4_fw_restart(adap, adap->mbox, reset); 1055 if (ret < 0) { 1056 dev_err(adap, "Failed to restart. Exit.\n"); 1057 goto bye; 1058 } 1059 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 1060 } 1061 1062 t4_get_version_info(adap); 1063 1064 ret = t4_get_core_clock(adap, &adap->params.vpd); 1065 if (ret < 0) { 1066 dev_err(adap, "%s: could not get core clock, error %d\n", 1067 __func__, -ret); 1068 goto bye; 1069 } 1070 1071 /* 1072 * If the firmware is initialized already (and we're not forcing a 1073 * master initialization), note that we're living with existing 1074 * adapter parameters. Otherwise, it's time to try initializing the 1075 * adapter ... 1076 */ 1077 if (state == DEV_STATE_INIT) { 1078 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 1079 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 1080 } else { 1081 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 1082 1083 ret = adap_init0_config(adap, reset); 1084 if (ret == -ENOENT) { 1085 dev_err(adap, 1086 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 1087 goto bye; 1088 } 1089 } 1090 if (ret < 0) { 1091 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 1092 goto bye; 1093 } 1094 1095 /* Now that we've successfully configured and initialized the adapter 1096 * (or found it already initialized), we can ask the Firmware what 1097 * resources it has provisioned for us. 1098 */ 1099 ret = t4_get_pfres(adap); 1100 if (ret) { 1101 dev_err(adap->pdev_dev, 1102 "Unable to retrieve resource provisioning info\n"); 1103 goto bye; 1104 } 1105 1106 /* Find out what ports are available to us. */ 1107 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1108 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 1109 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 1110 if (ret < 0) { 1111 dev_err(adap, "%s: failure in t4_query_params; error = %d\n", 1112 __func__, ret); 1113 goto bye; 1114 } 1115 1116 adap->params.nports = hweight32(port_vec); 1117 adap->params.portvec = port_vec; 1118 1119 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 1120 adap->params.nports); 1121 1122 /* 1123 * Give the SGE code a chance to pull in anything that it needs ... 1124 * Note that this must be called after we retrieve our VPD parameters 1125 * in order to know how to convert core ticks to seconds, etc. 1126 */ 1127 ret = t4_sge_init(adap); 1128 if (ret < 0) { 1129 dev_err(adap, "t4_sge_init failed with error %d\n", 1130 -ret); 1131 goto bye; 1132 } 1133 1134 /* 1135 * Grab some of our basic fundamental operating parameters. 1136 */ 1137 #define FW_PARAM_DEV(param) \ 1138 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1139 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1140 1141 #define FW_PARAM_PFVF(param) \ 1142 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1143 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ 1144 V_FW_PARAMS_PARAM_Y(0) | \ 1145 V_FW_PARAMS_PARAM_Z(0)) 1146 1147 params[0] = FW_PARAM_PFVF(L2T_START); 1148 params[1] = FW_PARAM_PFVF(L2T_END); 1149 params[2] = FW_PARAM_PFVF(FILTER_START); 1150 params[3] = FW_PARAM_PFVF(FILTER_END); 1151 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); 1152 if (ret < 0) 1153 goto bye; 1154 adap->l2t_start = val[0]; 1155 adap->l2t_end = val[1]; 1156 adap->tids.ftid_base = val[2]; 1157 adap->tids.nftids = val[3] - val[2] + 1; 1158 1159 params[0] = FW_PARAM_PFVF(CLIP_START); 1160 params[1] = FW_PARAM_PFVF(CLIP_END); 1161 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 1162 if (ret < 0) 1163 goto bye; 1164 adap->clipt_start = val[0]; 1165 adap->clipt_end = val[1]; 1166 1167 /* 1168 * Get device capabilities so we can determine what resources we need 1169 * to manage. 1170 */ 1171 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1172 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1173 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1174 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1175 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1176 &caps_cmd); 1177 if (ret < 0) 1178 goto bye; 1179 1180 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) && 1181 is_t6(adap->params.chip)) { 1182 if (init_hash_filter(adap) < 0) 1183 goto bye; 1184 } 1185 1186 /* See if FW supports FW_FILTER2 work request */ 1187 if (is_t4(adap->params.chip)) { 1188 adap->params.filter2_wr_support = 0; 1189 } else { 1190 params[0] = FW_PARAM_DEV(FILTER2_WR); 1191 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1192 1, params, val); 1193 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 1194 } 1195 1196 /* query tid-related parameters */ 1197 params[0] = FW_PARAM_DEV(NTID); 1198 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 1199 params, val); 1200 if (ret < 0) 1201 goto bye; 1202 adap->tids.ntids = val[0]; 1203 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 1204 1205 /* If we're running on newer firmware, let it know that we're 1206 * prepared to deal with encapsulated CPL messages. Older 1207 * firmware won't understand this and we'll just get 1208 * unencapsulated messages ... 1209 */ 1210 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1211 val[0] = 1; 1212 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1213 1214 /* 1215 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 1216 * capability. Earlier versions of the firmware didn't have the 1217 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 1218 * permission to use ULPTX MEMWRITE DSGL. 1219 */ 1220 if (is_t4(adap->params.chip)) { 1221 adap->params.ulptx_memwrite_dsgl = false; 1222 } else { 1223 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 1224 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1225 1, params, val); 1226 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 1227 } 1228 1229 /* 1230 * The MTU/MSS Table is initialized by now, so load their values. If 1231 * we're initializing the adapter, then we'll make any modifications 1232 * we want to the MTU/MSS Table and also initialize the congestion 1233 * parameters. 1234 */ 1235 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 1236 if (state != DEV_STATE_INIT) { 1237 int i; 1238 1239 /* 1240 * The default MTU Table contains values 1492 and 1500. 1241 * However, for TCP, it's better to have two values which are 1242 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 1243 * This allows us to have a TCP Data Payload which is a 1244 * multiple of 8 regardless of what combination of TCP Options 1245 * are in use (always a multiple of 4 bytes) which is 1246 * important for performance reasons. For instance, if no 1247 * options are in use, then we have a 20-byte IP header and a 1248 * 20-byte TCP header. In this case, a 1500-byte MSS would 1249 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 1250 * which is not a multiple of 8. So using an MSS of 1488 in 1251 * this case results in a TCP Data Payload of 1448 bytes which 1252 * is a multiple of 8. On the other hand, if 12-byte TCP Time 1253 * Stamps have been negotiated, then an MTU of 1500 bytes 1254 * results in a TCP Data Payload of 1448 bytes which, as 1255 * above, is a multiple of 8 bytes ... 1256 */ 1257 for (i = 0; i < NMTUS; i++) 1258 if (adap->params.mtus[i] == 1492) { 1259 adap->params.mtus[i] = 1488; 1260 break; 1261 } 1262 1263 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 1264 adap->params.b_wnd); 1265 } 1266 t4_init_sge_params(adap); 1267 t4_init_tp_params(adap); 1268 configure_pcie_ext_tag(adap); 1269 configure_vlan_types(adap); 1270 cxgbe_configure_max_ethqsets(adap); 1271 1272 adap->params.drv_memwin = MEMWIN_NIC; 1273 adap->flags |= FW_OK; 1274 dev_debug(adap, "%s: returning zero..\n", __func__); 1275 return 0; 1276 1277 /* 1278 * Something bad happened. If a command timed out or failed with EIO 1279 * FW does not operate within its spec or something catastrophic 1280 * happened to HW/FW, stop issuing commands. 1281 */ 1282 bye: 1283 if (ret != -ETIMEDOUT && ret != -EIO) 1284 t4_fw_bye(adap, adap->mbox); 1285 return ret; 1286 } 1287 1288 /** 1289 * t4_os_portmod_changed - handle port module changes 1290 * @adap: the adapter associated with the module change 1291 * @port_id: the port index whose module status has changed 1292 * 1293 * This is the OS-dependent handler for port module changes. It is 1294 * invoked when a port module is removed or inserted for any OS-specific 1295 * processing. 1296 */ 1297 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 1298 { 1299 static const char * const mod_str[] = { 1300 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 1301 }; 1302 1303 const struct port_info *pi = adap2pinfo(adap, port_id); 1304 1305 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 1306 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 1307 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 1308 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 1309 mod_str[pi->mod_type]); 1310 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 1311 dev_info(adap, "Port%d: unsupported port module inserted\n", 1312 pi->port_id); 1313 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 1314 dev_info(adap, "Port%d: unknown port module inserted\n", 1315 pi->port_id); 1316 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 1317 dev_info(adap, "Port%d: transceiver module error\n", 1318 pi->port_id); 1319 else 1320 dev_info(adap, "Port%d: unknown module type %d inserted\n", 1321 pi->port_id, pi->mod_type); 1322 } 1323 1324 bool cxgbe_force_linkup(struct adapter *adap) 1325 { 1326 struct rte_pci_device *pdev = adap->pdev; 1327 1328 if (is_pf4(adap)) 1329 return false; /* force_linkup not required for pf driver*/ 1330 if (!cxgbe_get_devargs(pdev->device.devargs, 1331 CXGBE_DEVARG_FORCE_LINK_UP)) 1332 return false; 1333 return true; 1334 } 1335 1336 /** 1337 * link_start - enable a port 1338 * @dev: the port to enable 1339 * 1340 * Performs the MAC and PHY actions needed to enable a port. 1341 */ 1342 int cxgbe_link_start(struct port_info *pi) 1343 { 1344 struct adapter *adapter = pi->adapter; 1345 u64 conf_offloads; 1346 unsigned int mtu; 1347 int ret; 1348 1349 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1350 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 1351 1352 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads; 1353 1354 /* 1355 * We do not set address filters and promiscuity here, the stack does 1356 * that step explicitly. 1357 */ 1358 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1, 1359 !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP), 1360 true); 1361 if (ret == 0) { 1362 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, 1363 (u8 *)&pi->eth_dev->data->mac_addrs[0]); 1364 if (ret >= 0) { 1365 pi->xact_addr_filt = ret; 1366 ret = 0; 1367 } 1368 } 1369 if (ret == 0 && is_pf4(adapter)) 1370 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 1371 &pi->link_cfg); 1372 if (ret == 0) { 1373 /* 1374 * Enabling a Virtual Interface can result in an interrupt 1375 * during the processing of the VI Enable command and, in some 1376 * paths, result in an attempt to issue another command in the 1377 * interrupt context. Thus, we disable interrupts during the 1378 * course of the VI Enable command ... 1379 */ 1380 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 1381 true, true, false); 1382 } 1383 1384 if (ret == 0 && cxgbe_force_linkup(adapter)) 1385 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP; 1386 return ret; 1387 } 1388 1389 /** 1390 * cxgbe_write_rss_conf - flash the RSS configuration for a given port 1391 * @pi: the port 1392 * @rss_hf: Hash configuration to apply 1393 */ 1394 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) 1395 { 1396 struct adapter *adapter = pi->adapter; 1397 const struct sge_eth_rxq *rxq; 1398 u64 flags = 0; 1399 u16 rss; 1400 int err; 1401 1402 /* Should never be called before setting up sge eth rx queues */ 1403 if (!(adapter->flags & FULL_INIT_DONE)) { 1404 dev_err(adap, "%s No RXQs available on port %d\n", 1405 __func__, pi->port_id); 1406 return -EINVAL; 1407 } 1408 1409 /* Don't allow unsupported hash functions */ 1410 if (rss_hf & ~CXGBE_RSS_HF_ALL) 1411 return -EINVAL; 1412 1413 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) 1414 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 1415 1416 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 1417 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 1418 1419 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 1420 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 1421 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1422 1423 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK) 1424 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 1425 1426 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK) 1427 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1428 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 1429 1430 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK) 1431 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1432 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 1433 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1434 1435 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1436 rss = rxq[0].rspq.abs_id; 1437 1438 /* If Tunnel All Lookup isn't specified in the global RSS 1439 * Configuration, then we need to specify a default Ingress 1440 * Queue for any ingress packets which aren't hashed. We'll 1441 * use our first ingress queue ... 1442 */ 1443 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 1444 flags, rss); 1445 return err; 1446 } 1447 1448 /** 1449 * cxgbe_write_rss - write the RSS table for a given port 1450 * @pi: the port 1451 * @queues: array of queue indices for RSS 1452 * 1453 * Sets up the portion of the HW RSS table for the port's VI to distribute 1454 * packets to the Rx queues in @queues. 1455 */ 1456 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues) 1457 { 1458 u16 *rss; 1459 int i, err; 1460 struct adapter *adapter = pi->adapter; 1461 const struct sge_eth_rxq *rxq; 1462 1463 /* Should never be called before setting up sge eth rx queues */ 1464 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 1465 1466 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1467 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 1468 if (!rss) 1469 return -ENOMEM; 1470 1471 /* map the queue indices to queue ids */ 1472 for (i = 0; i < pi->rss_size; i++, queues++) 1473 rss[i] = rxq[*queues].rspq.abs_id; 1474 1475 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 1476 pi->rss_size, rss, pi->rss_size); 1477 rte_free(rss); 1478 return err; 1479 } 1480 1481 /** 1482 * setup_rss - configure RSS 1483 * @adapter: the adapter 1484 * 1485 * Sets up RSS to distribute packets to multiple receive queues. We 1486 * configure the RSS CPU lookup table to distribute to the number of HW 1487 * receive queues, and the response queue lookup table to narrow that 1488 * down to the response queues actually configured for each port. 1489 * We always configure the RSS mapping for all ports since the mapping 1490 * table has plenty of entries. 1491 */ 1492 int cxgbe_setup_rss(struct port_info *pi) 1493 { 1494 int j, err; 1495 struct adapter *adapter = pi->adapter; 1496 1497 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 1498 __func__, pi->rss_size, pi->n_rx_qsets); 1499 1500 if (!(pi->flags & PORT_RSS_DONE)) { 1501 if (adapter->flags & FULL_INIT_DONE) { 1502 /* Fill default values with equal distribution */ 1503 for (j = 0; j < pi->rss_size; j++) 1504 pi->rss[j] = j % pi->n_rx_qsets; 1505 1506 err = cxgbe_write_rss(pi, pi->rss); 1507 if (err) 1508 return err; 1509 1510 err = cxgbe_write_rss_conf(pi, pi->rss_hf); 1511 if (err) 1512 return err; 1513 pi->flags |= PORT_RSS_DONE; 1514 } 1515 } 1516 return 0; 1517 } 1518 1519 /* 1520 * Enable NAPI scheduling and interrupt generation for all Rx queues. 1521 */ 1522 static void enable_rx(struct adapter *adap, struct sge_rspq *q) 1523 { 1524 /* 0-increment GTS to start the timer and enable interrupts */ 1525 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) : 1526 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS, 1527 V_SEINTARM(q->intr_params) | 1528 V_INGRESSQID(q->cntxt_id)); 1529 } 1530 1531 void cxgbe_enable_rx_queues(struct port_info *pi) 1532 { 1533 struct adapter *adap = pi->adapter; 1534 struct sge *s = &adap->sge; 1535 unsigned int i; 1536 1537 for (i = 0; i < pi->n_rx_qsets; i++) 1538 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq); 1539 } 1540 1541 /** 1542 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps. 1543 * @port_type: Firmware Port Type 1544 * @fw_caps: Firmware Port Capabilities 1545 * @speed_caps: Device Info Speed Capabilities 1546 * 1547 * Translate a Firmware Port Capabilities specification to Device Info 1548 * Speed Capabilities. 1549 */ 1550 static void fw_caps_to_speed_caps(enum fw_port_type port_type, 1551 unsigned int fw_caps, 1552 u32 *speed_caps) 1553 { 1554 #define SET_SPEED(__speed_name) \ 1555 do { \ 1556 *speed_caps |= ETH_LINK_ ## __speed_name; \ 1557 } while (0) 1558 1559 #define FW_CAPS_TO_SPEED(__fw_name) \ 1560 do { \ 1561 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \ 1562 SET_SPEED(__fw_name); \ 1563 } while (0) 1564 1565 switch (port_type) { 1566 case FW_PORT_TYPE_BT_SGMII: 1567 case FW_PORT_TYPE_BT_XFI: 1568 case FW_PORT_TYPE_BT_XAUI: 1569 FW_CAPS_TO_SPEED(SPEED_100M); 1570 FW_CAPS_TO_SPEED(SPEED_1G); 1571 FW_CAPS_TO_SPEED(SPEED_10G); 1572 break; 1573 1574 case FW_PORT_TYPE_KX4: 1575 case FW_PORT_TYPE_KX: 1576 case FW_PORT_TYPE_FIBER_XFI: 1577 case FW_PORT_TYPE_FIBER_XAUI: 1578 case FW_PORT_TYPE_SFP: 1579 case FW_PORT_TYPE_QSFP_10G: 1580 case FW_PORT_TYPE_QSA: 1581 FW_CAPS_TO_SPEED(SPEED_1G); 1582 FW_CAPS_TO_SPEED(SPEED_10G); 1583 break; 1584 1585 case FW_PORT_TYPE_KR: 1586 SET_SPEED(SPEED_10G); 1587 break; 1588 1589 case FW_PORT_TYPE_BP_AP: 1590 case FW_PORT_TYPE_BP4_AP: 1591 SET_SPEED(SPEED_1G); 1592 SET_SPEED(SPEED_10G); 1593 break; 1594 1595 case FW_PORT_TYPE_BP40_BA: 1596 case FW_PORT_TYPE_QSFP: 1597 SET_SPEED(SPEED_40G); 1598 break; 1599 1600 case FW_PORT_TYPE_CR_QSFP: 1601 case FW_PORT_TYPE_SFP28: 1602 case FW_PORT_TYPE_KR_SFP28: 1603 FW_CAPS_TO_SPEED(SPEED_1G); 1604 FW_CAPS_TO_SPEED(SPEED_10G); 1605 FW_CAPS_TO_SPEED(SPEED_25G); 1606 break; 1607 1608 case FW_PORT_TYPE_CR2_QSFP: 1609 SET_SPEED(SPEED_50G); 1610 break; 1611 1612 case FW_PORT_TYPE_KR4_100G: 1613 case FW_PORT_TYPE_CR4_QSFP: 1614 FW_CAPS_TO_SPEED(SPEED_25G); 1615 FW_CAPS_TO_SPEED(SPEED_40G); 1616 FW_CAPS_TO_SPEED(SPEED_50G); 1617 FW_CAPS_TO_SPEED(SPEED_100G); 1618 break; 1619 1620 default: 1621 break; 1622 } 1623 1624 #undef FW_CAPS_TO_SPEED 1625 #undef SET_SPEED 1626 } 1627 1628 /** 1629 * cxgbe_get_speed_caps - Fetch supported speed capabilities 1630 * @pi: Underlying port's info 1631 * @speed_caps: Device Info speed capabilities 1632 * 1633 * Fetch supported speed capabilities of the underlying port. 1634 */ 1635 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) 1636 { 1637 *speed_caps = 0; 1638 1639 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps, 1640 speed_caps); 1641 1642 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) 1643 *speed_caps |= ETH_LINK_SPEED_FIXED; 1644 } 1645 1646 /** 1647 * cxgbe_set_link_status - Set device link up or down. 1648 * @pi: Underlying port's info 1649 * @status: 0 - down, 1 - up 1650 * 1651 * Set the device link up or down. 1652 */ 1653 int cxgbe_set_link_status(struct port_info *pi, bool status) 1654 { 1655 struct adapter *adapter = pi->adapter; 1656 int err = 0; 1657 1658 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status); 1659 if (err) { 1660 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1661 return err; 1662 } 1663 1664 if (!status) 1665 t4_reset_link_config(adapter, pi->pidx); 1666 1667 return 0; 1668 } 1669 1670 /** 1671 * cxgb_up - enable the adapter 1672 * @adap: adapter being enabled 1673 * 1674 * Called when the first port is enabled, this function performs the 1675 * actions necessary to make an adapter operational, such as completing 1676 * the initialization of HW modules, and enabling interrupts. 1677 */ 1678 int cxgbe_up(struct adapter *adap) 1679 { 1680 enable_rx(adap, &adap->sge.fw_evtq); 1681 t4_sge_tx_monitor_start(adap); 1682 if (is_pf4(adap)) 1683 t4_intr_enable(adap); 1684 adap->flags |= FULL_INIT_DONE; 1685 1686 /* TODO: deadman watchdog ?? */ 1687 return 0; 1688 } 1689 1690 /* 1691 * Close the port 1692 */ 1693 int cxgbe_down(struct port_info *pi) 1694 { 1695 return cxgbe_set_link_status(pi, false); 1696 } 1697 1698 /* 1699 * Release resources when all the ports have been stopped. 1700 */ 1701 void cxgbe_close(struct adapter *adapter) 1702 { 1703 struct port_info *pi; 1704 int i; 1705 1706 if (adapter->flags & FULL_INIT_DONE) { 1707 tid_free(&adapter->tids); 1708 t4_cleanup_mpstcam(adapter); 1709 t4_cleanup_clip_tbl(adapter); 1710 t4_cleanup_l2t(adapter); 1711 if (is_pf4(adapter)) 1712 t4_intr_disable(adapter); 1713 t4_sge_tx_monitor_stop(adapter); 1714 t4_free_sge_resources(adapter); 1715 for_each_port(adapter, i) { 1716 pi = adap2pinfo(adapter, i); 1717 if (pi->viid != 0) 1718 t4_free_vi(adapter, adapter->mbox, 1719 adapter->pf, 0, pi->viid); 1720 rte_eth_dev_release_port(pi->eth_dev); 1721 } 1722 adapter->flags &= ~FULL_INIT_DONE; 1723 } 1724 1725 if (is_pf4(adapter) && (adapter->flags & FW_OK)) 1726 t4_fw_bye(adapter, adapter->mbox); 1727 } 1728 1729 int cxgbe_probe(struct adapter *adapter) 1730 { 1731 struct port_info *pi; 1732 int chip; 1733 int func, i; 1734 int err = 0; 1735 u32 whoami; 1736 1737 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 1738 chip = t4_get_chip_type(adapter, 1739 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id)); 1740 if (chip < 0) 1741 return chip; 1742 1743 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 1744 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami); 1745 1746 adapter->mbox = func; 1747 adapter->pf = func; 1748 1749 t4_os_lock_init(&adapter->mbox_lock); 1750 TAILQ_INIT(&adapter->mbox_list); 1751 t4_os_lock_init(&adapter->win0_lock); 1752 1753 err = t4_prep_adapter(adapter); 1754 if (err) 1755 return err; 1756 1757 setup_memwin(adapter); 1758 err = adap_init0(adapter); 1759 if (err) { 1760 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 1761 __func__, err); 1762 goto out_free; 1763 } 1764 1765 if (!is_t4(adapter->params.chip)) { 1766 /* 1767 * The userspace doorbell BAR is split evenly into doorbell 1768 * regions, each associated with an egress queue. If this 1769 * per-queue region is large enough (at least UDBS_SEG_SIZE) 1770 * then it can be used to submit a tx work request with an 1771 * implied doorbell. Enable write combining on the BAR if 1772 * there is room for such work requests. 1773 */ 1774 int s_qpp, qpp, num_seg; 1775 1776 s_qpp = (S_QUEUESPERPAGEPF0 + 1777 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 1778 adapter->pf); 1779 qpp = 1 << ((t4_read_reg(adapter, 1780 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 1781 & M_QUEUESPERPAGEPF0); 1782 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 1783 if (qpp > num_seg) 1784 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 1785 1786 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 1787 if (!adapter->bar2) { 1788 dev_err(adapter, "cannot map device bar2 region\n"); 1789 err = -ENOMEM; 1790 goto out_free; 1791 } 1792 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 1793 V_STATMODE(0)); 1794 } 1795 1796 for_each_port(adapter, i) { 1797 const unsigned int numa_node = rte_socket_id(); 1798 char name[RTE_ETH_NAME_MAX_LEN]; 1799 struct rte_eth_dev *eth_dev; 1800 1801 snprintf(name, sizeof(name), "%s_%d", 1802 adapter->pdev->device.name, i); 1803 1804 if (i == 0) { 1805 /* First port is already allocated by DPDK */ 1806 eth_dev = adapter->eth_dev; 1807 goto allocate_mac; 1808 } 1809 1810 /* 1811 * now do all data allocation - for eth_dev structure, 1812 * and internal (private) data for the remaining ports 1813 */ 1814 1815 /* reserve an ethdev entry */ 1816 eth_dev = rte_eth_dev_allocate(name); 1817 if (!eth_dev) 1818 goto out_free; 1819 1820 eth_dev->data->dev_private = 1821 rte_zmalloc_socket(name, sizeof(struct port_info), 1822 RTE_CACHE_LINE_SIZE, numa_node); 1823 if (!eth_dev->data->dev_private) 1824 goto out_free; 1825 1826 allocate_mac: 1827 pi = (struct port_info *)eth_dev->data->dev_private; 1828 adapter->port[i] = pi; 1829 pi->eth_dev = eth_dev; 1830 pi->adapter = adapter; 1831 pi->xact_addr_filt = -1; 1832 pi->port_id = i; 1833 pi->pidx = i; 1834 1835 pi->eth_dev->device = &adapter->pdev->device; 1836 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 1837 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 1838 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 1839 1840 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 1841 1842 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 1843 RTE_ETHER_ADDR_LEN, 0); 1844 if (!pi->eth_dev->data->mac_addrs) { 1845 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 1846 __func__); 1847 err = -1; 1848 goto out_free; 1849 } 1850 1851 if (i > 0) { 1852 /* First port will be notified by upper layer */ 1853 rte_eth_dev_probing_finish(eth_dev); 1854 } 1855 } 1856 1857 if (adapter->flags & FW_OK) { 1858 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 1859 if (err) { 1860 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 1861 __func__, err); 1862 goto out_free; 1863 } 1864 } 1865 1866 cxgbe_cfg_queues(adapter->eth_dev); 1867 1868 cxgbe_print_adapter_info(adapter); 1869 cxgbe_print_port_info(adapter); 1870 1871 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 1872 adapter->clipt_end); 1873 if (!adapter->clipt) { 1874 /* We tolerate a lack of clip_table, giving up some 1875 * functionality 1876 */ 1877 dev_warn(adapter, "could not allocate CLIP. Continuing\n"); 1878 } 1879 1880 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 1881 if (!adapter->l2t) { 1882 /* We tolerate a lack of L2T, giving up some functionality */ 1883 dev_warn(adapter, "could not allocate L2T. Continuing\n"); 1884 } 1885 1886 if (tid_init(&adapter->tids) < 0) { 1887 /* Disable filtering support */ 1888 dev_warn(adapter, "could not allocate TID table, " 1889 "filter support disabled. Continuing\n"); 1890 } 1891 1892 adapter->mpstcam = t4_init_mpstcam(adapter); 1893 if (!adapter->mpstcam) 1894 dev_warn(adapter, "could not allocate mps tcam table." 1895 " Continuing\n"); 1896 1897 if (is_hashfilter(adapter)) { 1898 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) { 1899 u32 hash_base, hash_reg; 1900 1901 hash_reg = A_LE_DB_TID_HASHBASE; 1902 hash_base = t4_read_reg(adapter, hash_reg); 1903 adapter->tids.hash_base = hash_base / 4; 1904 } 1905 } else { 1906 /* Disable hash filtering support */ 1907 dev_warn(adapter, 1908 "Maskless filter support disabled. Continuing\n"); 1909 } 1910 1911 err = cxgbe_init_rss(adapter); 1912 if (err) 1913 goto out_free; 1914 1915 return 0; 1916 1917 out_free: 1918 for_each_port(adapter, i) { 1919 pi = adap2pinfo(adapter, i); 1920 if (pi->viid != 0) 1921 t4_free_vi(adapter, adapter->mbox, adapter->pf, 1922 0, pi->viid); 1923 rte_eth_dev_release_port(pi->eth_dev); 1924 } 1925 1926 if (adapter->flags & FW_OK) 1927 t4_fw_bye(adapter, adapter->mbox); 1928 return -err; 1929 } 1930