1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_atomic.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_random.h> 33 #include <rte_dev.h> 34 #include <rte_kvargs.h> 35 36 #include "common.h" 37 #include "t4_regs.h" 38 #include "t4_msg.h" 39 #include "cxgbe.h" 40 #include "clip_tbl.h" 41 #include "l2t.h" 42 #include "mps_tcam.h" 43 44 /** 45 * Allocate a chunk of memory. The allocated memory is cleared. 46 */ 47 void *t4_alloc_mem(size_t size) 48 { 49 return rte_zmalloc(NULL, size, 0); 50 } 51 52 /** 53 * Free memory allocated through t4_alloc_mem(). 54 */ 55 void t4_free_mem(void *addr) 56 { 57 rte_free(addr); 58 } 59 60 /* 61 * Response queue handler for the FW event queue. 62 */ 63 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 64 __rte_unused const struct pkt_gl *gl) 65 { 66 u8 opcode = ((const struct rss_header *)rsp)->opcode; 67 68 rsp++; /* skip RSS header */ 69 70 /* 71 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 72 */ 73 if (unlikely(opcode == CPL_FW4_MSG && 74 ((const struct cpl_fw4_msg *)rsp)->type == 75 FW_TYPE_RSSCPL)) { 76 rsp++; 77 opcode = ((const struct rss_header *)rsp)->opcode; 78 rsp++; 79 if (opcode != CPL_SGE_EGR_UPDATE) { 80 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 81 opcode); 82 goto out; 83 } 84 } 85 86 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 87 /* do nothing */ 88 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 89 const struct cpl_fw6_msg *msg = (const void *)rsp; 90 91 t4_handle_fw_rpl(q->adapter, msg->data); 92 } else if (opcode == CPL_ABORT_RPL_RSS) { 93 const struct cpl_abort_rpl_rss *p = (const void *)rsp; 94 95 hash_del_filter_rpl(q->adapter, p); 96 } else if (opcode == CPL_SET_TCB_RPL) { 97 const struct cpl_set_tcb_rpl *p = (const void *)rsp; 98 99 filter_rpl(q->adapter, p); 100 } else if (opcode == CPL_ACT_OPEN_RPL) { 101 const struct cpl_act_open_rpl *p = (const void *)rsp; 102 103 hash_filter_rpl(q->adapter, p); 104 } else if (opcode == CPL_L2T_WRITE_RPL) { 105 const struct cpl_l2t_write_rpl *p = (const void *)rsp; 106 107 do_l2t_write_rpl(q->adapter, p); 108 } else { 109 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 110 opcode); 111 } 112 out: 113 return 0; 114 } 115 116 /** 117 * Setup sge control queues to pass control information. 118 */ 119 int setup_sge_ctrl_txq(struct adapter *adapter) 120 { 121 struct sge *s = &adapter->sge; 122 int err = 0, i = 0; 123 124 for_each_port(adapter, i) { 125 char name[RTE_ETH_NAME_MAX_LEN]; 126 struct sge_ctrl_txq *q = &s->ctrlq[i]; 127 128 q->q.size = 1024; 129 err = t4_sge_alloc_ctrl_txq(adapter, q, 130 adapter->eth_dev, i, 131 s->fw_evtq.cntxt_id, 132 rte_socket_id()); 133 if (err) { 134 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d", 135 err); 136 goto out; 137 } 138 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i); 139 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size, 140 RTE_CACHE_LINE_SIZE, 141 RTE_MBUF_PRIV_ALIGN, 142 RTE_MBUF_DEFAULT_BUF_SIZE, 143 SOCKET_ID_ANY); 144 if (!q->mb_pool) { 145 dev_err(adapter, "Can't create ctrl pool for port: %d", 146 i); 147 err = -ENOMEM; 148 goto out; 149 } 150 } 151 return 0; 152 out: 153 t4_free_sge_resources(adapter); 154 return err; 155 } 156 157 /** 158 * cxgbe_poll_for_completion: Poll rxq for completion 159 * @q: rxq to poll 160 * @us: microseconds to delay 161 * @cnt: number of times to poll 162 * @c: completion to check for 'done' status 163 * 164 * Polls the rxq for reples until completion is done or the count 165 * expires. 166 */ 167 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us, 168 unsigned int cnt, struct t4_completion *c) 169 { 170 unsigned int i; 171 unsigned int work_done, budget = 4; 172 173 if (!c) 174 return -EINVAL; 175 176 for (i = 0; i < cnt; i++) { 177 cxgbe_poll(q, NULL, budget, &work_done); 178 t4_os_lock(&c->lock); 179 if (c->done) { 180 t4_os_unlock(&c->lock); 181 return 0; 182 } 183 t4_os_unlock(&c->lock); 184 udelay(us); 185 } 186 return -ETIMEDOUT; 187 } 188 189 int setup_sge_fwevtq(struct adapter *adapter) 190 { 191 struct sge *s = &adapter->sge; 192 int err = 0; 193 int msi_idx = 0; 194 195 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 196 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 197 rte_socket_id()); 198 return err; 199 } 200 201 static int closest_timer(const struct sge *s, int time) 202 { 203 unsigned int i, match = 0; 204 int delta, min_delta = INT_MAX; 205 206 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 207 delta = time - s->timer_val[i]; 208 if (delta < 0) 209 delta = -delta; 210 if (delta < min_delta) { 211 min_delta = delta; 212 match = i; 213 } 214 } 215 return match; 216 } 217 218 static int closest_thres(const struct sge *s, int thres) 219 { 220 unsigned int i, match = 0; 221 int delta, min_delta = INT_MAX; 222 223 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 224 delta = thres - s->counter_val[i]; 225 if (delta < 0) 226 delta = -delta; 227 if (delta < min_delta) { 228 min_delta = delta; 229 match = i; 230 } 231 } 232 return match; 233 } 234 235 /** 236 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 237 * @q: the Rx queue 238 * @us: the hold-off time in us, or 0 to disable timer 239 * @cnt: the hold-off packet count, or 0 to disable counter 240 * 241 * Sets an Rx queue's interrupt hold-off time and packet count. At least 242 * one of the two needs to be enabled for the queue to generate interrupts. 243 */ 244 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 245 unsigned int cnt) 246 { 247 struct adapter *adap = q->adapter; 248 unsigned int timer_val; 249 250 if (cnt) { 251 int err; 252 u32 v, new_idx; 253 254 new_idx = closest_thres(&adap->sge, cnt); 255 if (q->desc && q->pktcnt_idx != new_idx) { 256 /* the queue has already been created, update it */ 257 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 258 V_FW_PARAMS_PARAM_X( 259 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 260 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 261 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 262 &v, &new_idx); 263 if (err) 264 return err; 265 } 266 q->pktcnt_idx = new_idx; 267 } 268 269 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 270 closest_timer(&adap->sge, us); 271 272 if ((us | cnt) == 0) 273 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 274 else 275 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 276 V_QINTR_CNT_EN(cnt > 0); 277 return 0; 278 } 279 280 /** 281 * Allocate an active-open TID and set it to the supplied value. 282 */ 283 int cxgbe_alloc_atid(struct tid_info *t, void *data) 284 { 285 int atid = -1; 286 287 t4_os_lock(&t->atid_lock); 288 if (t->afree) { 289 union aopen_entry *p = t->afree; 290 291 atid = p - t->atid_tab; 292 t->afree = p->next; 293 p->data = data; 294 t->atids_in_use++; 295 } 296 t4_os_unlock(&t->atid_lock); 297 return atid; 298 } 299 300 /** 301 * Release an active-open TID. 302 */ 303 void cxgbe_free_atid(struct tid_info *t, unsigned int atid) 304 { 305 union aopen_entry *p = &t->atid_tab[atid]; 306 307 t4_os_lock(&t->atid_lock); 308 p->next = t->afree; 309 t->afree = p; 310 t->atids_in_use--; 311 t4_os_unlock(&t->atid_lock); 312 } 313 314 /** 315 * Populate a TID_RELEASE WR. Caller must properly size the skb. 316 */ 317 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid) 318 { 319 struct cpl_tid_release *req; 320 321 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *); 322 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 323 } 324 325 /** 326 * Release a TID and inform HW. If we are unable to allocate the release 327 * message we defer to a work queue. 328 */ 329 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 330 unsigned short family) 331 { 332 struct rte_mbuf *mbuf; 333 struct adapter *adap = container_of(t, struct adapter, tids); 334 335 WARN_ON(tid >= t->ntids); 336 337 if (t->tid_tab[tid]) { 338 t->tid_tab[tid] = NULL; 339 rte_atomic32_dec(&t->conns_in_use); 340 if (t->hash_base && tid >= t->hash_base) { 341 if (family == FILTER_TYPE_IPV4) 342 rte_atomic32_dec(&t->hash_tids_in_use); 343 } else { 344 if (family == FILTER_TYPE_IPV4) 345 rte_atomic32_dec(&t->tids_in_use); 346 } 347 } 348 349 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool); 350 if (mbuf) { 351 mbuf->data_len = sizeof(struct cpl_tid_release); 352 mbuf->pkt_len = mbuf->data_len; 353 mk_tid_release(mbuf, tid); 354 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf); 355 } 356 } 357 358 /** 359 * Insert a TID. 360 */ 361 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid, 362 unsigned short family) 363 { 364 t->tid_tab[tid] = data; 365 if (t->hash_base && tid >= t->hash_base) { 366 if (family == FILTER_TYPE_IPV4) 367 rte_atomic32_inc(&t->hash_tids_in_use); 368 } else { 369 if (family == FILTER_TYPE_IPV4) 370 rte_atomic32_inc(&t->tids_in_use); 371 } 372 373 rte_atomic32_inc(&t->conns_in_use); 374 } 375 376 /** 377 * Free TID tables. 378 */ 379 static void tid_free(struct tid_info *t) 380 { 381 if (t->tid_tab) { 382 if (t->ftid_bmap) 383 rte_bitmap_free(t->ftid_bmap); 384 385 if (t->ftid_bmap_array) 386 t4_os_free(t->ftid_bmap_array); 387 388 t4_os_free(t->tid_tab); 389 } 390 391 memset(t, 0, sizeof(struct tid_info)); 392 } 393 394 /** 395 * Allocate and initialize the TID tables. Returns 0 on success. 396 */ 397 static int tid_init(struct tid_info *t) 398 { 399 size_t size; 400 unsigned int ftid_bmap_size; 401 unsigned int natids = t->natids; 402 unsigned int max_ftids = t->nftids; 403 404 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids); 405 size = t->ntids * sizeof(*t->tid_tab) + 406 max_ftids * sizeof(*t->ftid_tab) + 407 natids * sizeof(*t->atid_tab); 408 409 t->tid_tab = t4_os_alloc(size); 410 if (!t->tid_tab) 411 return -ENOMEM; 412 413 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 414 t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids]; 415 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size); 416 if (!t->ftid_bmap_array) { 417 tid_free(t); 418 return -ENOMEM; 419 } 420 421 t4_os_lock_init(&t->atid_lock); 422 t4_os_lock_init(&t->ftid_lock); 423 424 t->afree = NULL; 425 t->atids_in_use = 0; 426 rte_atomic32_init(&t->tids_in_use); 427 rte_atomic32_set(&t->tids_in_use, 0); 428 rte_atomic32_init(&t->conns_in_use); 429 rte_atomic32_set(&t->conns_in_use, 0); 430 431 /* Setup the free list for atid_tab and clear the stid bitmap. */ 432 if (natids) { 433 while (--natids) 434 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 435 t->afree = t->atid_tab; 436 } 437 438 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array, 439 ftid_bmap_size); 440 if (!t->ftid_bmap) { 441 tid_free(t); 442 return -ENOMEM; 443 } 444 445 return 0; 446 } 447 448 static inline bool is_x_1g_port(const struct link_config *lc) 449 { 450 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0; 451 } 452 453 static inline bool is_x_10g_port(const struct link_config *lc) 454 { 455 unsigned int speeds, high_speeds; 456 457 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps)); 458 high_speeds = speeds & 459 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 460 461 return high_speeds != 0; 462 } 463 464 inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 465 unsigned int us, unsigned int cnt, 466 unsigned int size, unsigned int iqe_size) 467 { 468 q->adapter = adap; 469 cxgb4_set_rspq_intr_params(q, us, cnt); 470 q->iqe_len = iqe_size; 471 q->size = size; 472 } 473 474 int cfg_queue_count(struct rte_eth_dev *eth_dev) 475 { 476 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 477 struct adapter *adap = pi->adapter; 478 struct sge *s = &adap->sge; 479 unsigned int max_queues = s->max_ethqsets / adap->params.nports; 480 481 if ((eth_dev->data->nb_rx_queues < 1) || 482 (eth_dev->data->nb_tx_queues < 1)) 483 return -EINVAL; 484 485 if ((eth_dev->data->nb_rx_queues > max_queues) || 486 (eth_dev->data->nb_tx_queues > max_queues)) 487 return -EINVAL; 488 489 if (eth_dev->data->nb_rx_queues > pi->rss_size) 490 return -EINVAL; 491 492 /* We must configure RSS, since config has changed*/ 493 pi->flags &= ~PORT_RSS_DONE; 494 495 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 496 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 497 498 return 0; 499 } 500 501 void cfg_queues(struct rte_eth_dev *eth_dev) 502 { 503 struct rte_config *config = rte_eal_get_configuration(); 504 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 505 struct adapter *adap = pi->adapter; 506 struct sge *s = &adap->sge; 507 unsigned int i, nb_ports = 0, qidx = 0; 508 unsigned int q_per_port = 0; 509 510 if (!(adap->flags & CFG_QUEUES)) { 511 for_each_port(adap, i) { 512 struct port_info *tpi = adap2pinfo(adap, i); 513 514 nb_ports += (is_x_10g_port(&tpi->link_cfg)) || 515 is_x_1g_port(&tpi->link_cfg) ? 1 : 0; 516 } 517 518 /* 519 * We default up to # of cores queues per 1G/10G port. 520 */ 521 if (nb_ports) 522 q_per_port = (s->max_ethqsets - 523 (adap->params.nports - nb_ports)) / 524 nb_ports; 525 526 if (q_per_port > config->lcore_count) 527 q_per_port = config->lcore_count; 528 529 for_each_port(adap, i) { 530 struct port_info *pi = adap2pinfo(adap, i); 531 532 pi->first_qset = qidx; 533 534 /* Initially n_rx_qsets == n_tx_qsets */ 535 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) || 536 is_x_1g_port(&pi->link_cfg)) ? 537 q_per_port : 1; 538 pi->n_tx_qsets = pi->n_rx_qsets; 539 540 if (pi->n_rx_qsets > pi->rss_size) 541 pi->n_rx_qsets = pi->rss_size; 542 543 qidx += pi->n_rx_qsets; 544 } 545 546 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 547 struct sge_eth_rxq *r = &s->ethrxq[i]; 548 549 init_rspq(adap, &r->rspq, 5, 32, 1024, 64); 550 r->usembufs = 1; 551 r->fl.size = (r->usembufs ? 1024 : 72); 552 } 553 554 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 555 s->ethtxq[i].q.size = 1024; 556 557 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 558 adap->flags |= CFG_QUEUES; 559 } 560 } 561 562 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 563 { 564 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 565 &pi->stats_base); 566 } 567 568 void cxgbe_stats_reset(struct port_info *pi) 569 { 570 t4_clr_port_stats(pi->adapter, pi->tx_chan); 571 } 572 573 static void setup_memwin(struct adapter *adap) 574 { 575 u32 mem_win0_base; 576 577 /* For T5, only relative offset inside the PCIe BAR is passed */ 578 mem_win0_base = MEMWIN0_BASE; 579 580 /* 581 * Set up memory window for accessing adapter memory ranges. (Read 582 * back MA register to ensure that changes propagate before we attempt 583 * to use the new values.) 584 */ 585 t4_write_reg(adap, 586 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 587 MEMWIN_NIC), 588 mem_win0_base | V_BIR(0) | 589 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 590 t4_read_reg(adap, 591 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 592 MEMWIN_NIC)); 593 } 594 595 int init_rss(struct adapter *adap) 596 { 597 unsigned int i; 598 599 if (is_pf4(adap)) { 600 int err; 601 602 err = t4_init_rss_mode(adap, adap->mbox); 603 if (err) 604 return err; 605 } 606 607 for_each_port(adap, i) { 608 struct port_info *pi = adap2pinfo(adap, i); 609 610 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 611 if (!pi->rss) 612 return -ENOMEM; 613 614 pi->rss_hf = CXGBE_RSS_HF_ALL; 615 } 616 return 0; 617 } 618 619 /** 620 * Dump basic information about the adapter. 621 */ 622 void print_adapter_info(struct adapter *adap) 623 { 624 /** 625 * Hardware/Firmware/etc. Version/Revision IDs. 626 */ 627 t4_dump_version_info(adap); 628 } 629 630 void print_port_info(struct adapter *adap) 631 { 632 int i; 633 char buf[80]; 634 struct rte_pci_addr *loc = &adap->pdev->addr; 635 636 for_each_port(adap, i) { 637 const struct port_info *pi = adap2pinfo(adap, i); 638 char *bufp = buf; 639 640 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 641 bufp += sprintf(bufp, "100M/"); 642 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 643 bufp += sprintf(bufp, "1G/"); 644 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 645 bufp += sprintf(bufp, "10G/"); 646 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 647 bufp += sprintf(bufp, "25G/"); 648 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 649 bufp += sprintf(bufp, "40G/"); 650 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 651 bufp += sprintf(bufp, "50G/"); 652 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 653 bufp += sprintf(bufp, "100G/"); 654 if (bufp != buf) 655 --bufp; 656 sprintf(bufp, "BASE-%s", 657 t4_get_port_type_description( 658 (enum fw_port_type)pi->port_type)); 659 660 dev_info(adap, 661 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 662 loc->domain, loc->bus, loc->devid, loc->function, 663 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 664 (adap->flags & USING_MSIX) ? " MSI-X" : 665 (adap->flags & USING_MSI) ? " MSI" : ""); 666 } 667 } 668 669 static int 670 check_devargs_handler(__rte_unused const char *key, const char *value, 671 __rte_unused void *opaque) 672 { 673 if (strcmp(value, "1")) 674 return -1; 675 676 return 0; 677 } 678 679 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key) 680 { 681 struct rte_kvargs *kvlist; 682 683 if (!devargs) 684 return 0; 685 686 kvlist = rte_kvargs_parse(devargs->args, NULL); 687 if (!kvlist) 688 return 0; 689 690 if (!rte_kvargs_count(kvlist, key)) { 691 rte_kvargs_free(kvlist); 692 return 0; 693 } 694 695 if (rte_kvargs_process(kvlist, key, 696 check_devargs_handler, NULL) < 0) { 697 rte_kvargs_free(kvlist); 698 return 0; 699 } 700 rte_kvargs_free(kvlist); 701 702 return 1; 703 } 704 705 static void configure_vlan_types(struct adapter *adapter) 706 { 707 struct rte_pci_device *pdev = adapter->pdev; 708 int i; 709 710 for_each_port(adapter, i) { 711 /* OVLAN Type 0x88a8 */ 712 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0), 713 V_OVLAN_MASK(M_OVLAN_MASK) | 714 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 715 V_OVLAN_MASK(M_OVLAN_MASK) | 716 V_OVLAN_ETYPE(0x88a8)); 717 /* OVLAN Type 0x9100 */ 718 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1), 719 V_OVLAN_MASK(M_OVLAN_MASK) | 720 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 721 V_OVLAN_MASK(M_OVLAN_MASK) | 722 V_OVLAN_ETYPE(0x9100)); 723 /* OVLAN Type 0x8100 */ 724 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2), 725 V_OVLAN_MASK(M_OVLAN_MASK) | 726 V_OVLAN_ETYPE(M_OVLAN_ETYPE), 727 V_OVLAN_MASK(M_OVLAN_MASK) | 728 V_OVLAN_ETYPE(0x8100)); 729 730 /* IVLAN 0X8100 */ 731 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i), 732 V_IVLAN_ETYPE(M_IVLAN_ETYPE), 733 V_IVLAN_ETYPE(0x8100)); 734 735 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i), 736 F_OVLAN_EN0 | F_OVLAN_EN1 | 737 F_OVLAN_EN2 | F_IVLAN_EN, 738 F_OVLAN_EN0 | F_OVLAN_EN1 | 739 F_OVLAN_EN2 | F_IVLAN_EN); 740 } 741 742 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN)) 743 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 744 V_RM_OVLAN(1), V_RM_OVLAN(0)); 745 } 746 747 static void configure_pcie_ext_tag(struct adapter *adapter) 748 { 749 u16 v; 750 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 751 752 if (!pos) 753 return; 754 755 if (pos > 0) { 756 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v); 757 v |= PCI_EXP_DEVCTL_EXT_TAG; 758 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v); 759 if (is_t6(adapter->params.chip)) { 760 t4_set_reg_field(adapter, A_PCIE_CFG2, 761 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG), 762 V_T6_TOTMAXTAG(7)); 763 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 764 V_T6_MINTAG(M_T6_MINTAG), 765 V_T6_MINTAG(8)); 766 } else { 767 t4_set_reg_field(adapter, A_PCIE_CFG2, 768 V_TOTMAXTAG(M_TOTMAXTAG), 769 V_TOTMAXTAG(3)); 770 t4_set_reg_field(adapter, A_PCIE_CMD_CFG, 771 V_MINTAG(M_MINTAG), 772 V_MINTAG(8)); 773 } 774 } 775 } 776 777 /* Figure out how many Queue Sets we can support */ 778 void configure_max_ethqsets(struct adapter *adapter) 779 { 780 unsigned int ethqsets; 781 782 /* 783 * We need to reserve an Ingress Queue for the Asynchronous Firmware 784 * Event Queue. 785 * 786 * For each Queue Set, we'll need the ability to allocate two Egress 787 * Contexts -- one for the Ingress Queue Free List and one for the TX 788 * Ethernet Queue. 789 */ 790 if (is_pf4(adapter)) { 791 struct pf_resources *pfres = &adapter->params.pfres; 792 793 ethqsets = pfres->niqflint - 1; 794 if (pfres->neq < ethqsets * 2) 795 ethqsets = pfres->neq / 2; 796 } else { 797 struct vf_resources *vfres = &adapter->params.vfres; 798 799 ethqsets = vfres->niqflint - 1; 800 if (vfres->nethctrl != ethqsets) 801 ethqsets = min(vfres->nethctrl, ethqsets); 802 if (vfres->neq < ethqsets * 2) 803 ethqsets = vfres->neq / 2; 804 } 805 806 if (ethqsets > MAX_ETH_QSETS) 807 ethqsets = MAX_ETH_QSETS; 808 adapter->sge.max_ethqsets = ethqsets; 809 } 810 811 /* 812 * Tweak configuration based on system architecture, etc. Most of these have 813 * defaults assigned to them by Firmware Configuration Files (if we're using 814 * them) but need to be explicitly set if we're using hard-coded 815 * initialization. So these are essentially common tweaks/settings for 816 * Configuration Files and hard-coded initialization ... 817 */ 818 static int adap_init0_tweaks(struct adapter *adapter) 819 { 820 u8 rx_dma_offset; 821 822 /* 823 * Fix up various Host-Dependent Parameters like Page Size, Cache 824 * Line Size, etc. The firmware default is for a 4KB Page Size and 825 * 64B Cache Line Size ... 826 */ 827 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 828 T5_LAST_REV); 829 830 /* 831 * Keep the chip default offset to deliver Ingress packets into our 832 * DMA buffers to zero 833 */ 834 rx_dma_offset = 0; 835 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 836 V_PKTSHIFT(rx_dma_offset)); 837 838 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 839 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 840 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 841 842 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD, 843 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U)); 844 845 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 846 V_IDMAARBROUNDROBIN(1U)); 847 848 /* 849 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 850 * adds the pseudo header itself. 851 */ 852 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 853 F_CSUM_HAS_PSEUDO_HDR, 0); 854 855 return 0; 856 } 857 858 /* 859 * Attempt to initialize the adapter via a Firmware Configuration File. 860 */ 861 static int adap_init0_config(struct adapter *adapter, int reset) 862 { 863 struct fw_caps_config_cmd caps_cmd; 864 unsigned long mtype = 0, maddr = 0; 865 u32 finiver, finicsum, cfcsum; 866 int ret; 867 int config_issued = 0; 868 int cfg_addr; 869 char config_name[20]; 870 871 /* 872 * Reset device if necessary. 873 */ 874 if (reset) { 875 ret = t4_fw_reset(adapter, adapter->mbox, 876 F_PIORSTMODE | F_PIORST); 877 if (ret < 0) { 878 dev_warn(adapter, "Firmware reset failed, error %d\n", 879 -ret); 880 goto bye; 881 } 882 } 883 884 cfg_addr = t4_flash_cfg_addr(adapter); 885 if (cfg_addr < 0) { 886 ret = cfg_addr; 887 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 888 -ret); 889 goto bye; 890 } 891 892 strcpy(config_name, "On Flash"); 893 mtype = FW_MEMTYPE_CF_FLASH; 894 maddr = cfg_addr; 895 896 /* 897 * Issue a Capability Configuration command to the firmware to get it 898 * to parse the Configuration File. We don't use t4_fw_config_file() 899 * because we want the ability to modify various features after we've 900 * processed the configuration file ... 901 */ 902 memset(&caps_cmd, 0, sizeof(caps_cmd)); 903 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 904 F_FW_CMD_REQUEST | F_FW_CMD_READ); 905 caps_cmd.cfvalid_to_len16 = 906 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 907 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 908 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 909 FW_LEN16(caps_cmd)); 910 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 911 &caps_cmd); 912 /* 913 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 914 * Configuration File in FLASH), our last gasp effort is to use the 915 * Firmware Configuration File which is embedded in the firmware. A 916 * very few early versions of the firmware didn't have one embedded 917 * but we can ignore those. 918 */ 919 if (ret == -ENOENT) { 920 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 921 __func__); 922 923 memset(&caps_cmd, 0, sizeof(caps_cmd)); 924 caps_cmd.op_to_write = 925 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 926 F_FW_CMD_REQUEST | F_FW_CMD_READ); 927 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 928 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 929 sizeof(caps_cmd), &caps_cmd); 930 strcpy(config_name, "Firmware Default"); 931 } 932 933 config_issued = 1; 934 if (ret < 0) 935 goto bye; 936 937 finiver = be32_to_cpu(caps_cmd.finiver); 938 finicsum = be32_to_cpu(caps_cmd.finicsum); 939 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 940 if (finicsum != cfcsum) 941 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 942 finicsum, cfcsum); 943 944 /* 945 * If we're a pure NIC driver then disable all offloading facilities. 946 * This will allow the firmware to optimize aspects of the hardware 947 * configuration which will result in improved performance. 948 */ 949 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD); 950 caps_cmd.toecaps = 0; 951 caps_cmd.iscsicaps = 0; 952 caps_cmd.rdmacaps = 0; 953 caps_cmd.fcoecaps = 0; 954 955 /* 956 * And now tell the firmware to use the configuration we just loaded. 957 */ 958 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 959 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 960 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 961 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 962 NULL); 963 if (ret < 0) { 964 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 965 -ret); 966 goto bye; 967 } 968 969 /* 970 * Tweak configuration based on system architecture, etc. 971 */ 972 ret = adap_init0_tweaks(adapter); 973 if (ret < 0) { 974 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 975 goto bye; 976 } 977 978 /* 979 * And finally tell the firmware to initialize itself using the 980 * parameters from the Configuration File. 981 */ 982 ret = t4_fw_initialize(adapter, adapter->mbox); 983 if (ret < 0) { 984 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 985 -ret); 986 goto bye; 987 } 988 989 /* 990 * Return successfully and note that we're operating with parameters 991 * not supplied by the driver, rather than from hard-wired 992 * initialization constants buried in the driver. 993 */ 994 dev_info(adapter, 995 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 996 config_name, finiver, cfcsum); 997 998 return 0; 999 1000 /* 1001 * Something bad happened. Return the error ... (If the "error" 1002 * is that there's no Configuration File on the adapter we don't 1003 * want to issue a warning since this is fairly common.) 1004 */ 1005 bye: 1006 if (config_issued && ret != -ENOENT) 1007 dev_warn(adapter, "\"%s\" configuration file error %d\n", 1008 config_name, -ret); 1009 1010 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 1011 return ret; 1012 } 1013 1014 static int adap_init0(struct adapter *adap) 1015 { 1016 struct fw_caps_config_cmd caps_cmd; 1017 int ret = 0; 1018 u32 v, port_vec; 1019 enum dev_state state; 1020 u32 params[7], val[7]; 1021 int reset = 1; 1022 int mbox = adap->mbox; 1023 1024 /* 1025 * Contact FW, advertising Master capability. 1026 */ 1027 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 1028 if (ret < 0) { 1029 dev_err(adap, "%s: could not connect to FW, error %d\n", 1030 __func__, -ret); 1031 goto bye; 1032 } 1033 1034 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 1035 adap->mbox, ret); 1036 1037 if (ret == mbox) 1038 adap->flags |= MASTER_PF; 1039 1040 if (state == DEV_STATE_INIT) { 1041 /* 1042 * Force halt and reset FW because a previous instance may have 1043 * exited abnormally without properly shutting down 1044 */ 1045 ret = t4_fw_halt(adap, adap->mbox, reset); 1046 if (ret < 0) { 1047 dev_err(adap, "Failed to halt. Exit.\n"); 1048 goto bye; 1049 } 1050 1051 ret = t4_fw_restart(adap, adap->mbox, reset); 1052 if (ret < 0) { 1053 dev_err(adap, "Failed to restart. Exit.\n"); 1054 goto bye; 1055 } 1056 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 1057 } 1058 1059 t4_get_version_info(adap); 1060 1061 ret = t4_get_core_clock(adap, &adap->params.vpd); 1062 if (ret < 0) { 1063 dev_err(adap, "%s: could not get core clock, error %d\n", 1064 __func__, -ret); 1065 goto bye; 1066 } 1067 1068 /* 1069 * If the firmware is initialized already (and we're not forcing a 1070 * master initialization), note that we're living with existing 1071 * adapter parameters. Otherwise, it's time to try initializing the 1072 * adapter ... 1073 */ 1074 if (state == DEV_STATE_INIT) { 1075 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 1076 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 1077 } else { 1078 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 1079 1080 ret = adap_init0_config(adap, reset); 1081 if (ret == -ENOENT) { 1082 dev_err(adap, 1083 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 1084 goto bye; 1085 } 1086 } 1087 if (ret < 0) { 1088 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 1089 goto bye; 1090 } 1091 1092 /* Now that we've successfully configured and initialized the adapter 1093 * (or found it already initialized), we can ask the Firmware what 1094 * resources it has provisioned for us. 1095 */ 1096 ret = t4_get_pfres(adap); 1097 if (ret) { 1098 dev_err(adap->pdev_dev, 1099 "Unable to retrieve resource provisioning info\n"); 1100 goto bye; 1101 } 1102 1103 /* Find out what ports are available to us. */ 1104 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1105 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 1106 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 1107 if (ret < 0) { 1108 dev_err(adap, "%s: failure in t4_query_params; error = %d\n", 1109 __func__, ret); 1110 goto bye; 1111 } 1112 1113 adap->params.nports = hweight32(port_vec); 1114 adap->params.portvec = port_vec; 1115 1116 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 1117 adap->params.nports); 1118 1119 /* 1120 * Give the SGE code a chance to pull in anything that it needs ... 1121 * Note that this must be called after we retrieve our VPD parameters 1122 * in order to know how to convert core ticks to seconds, etc. 1123 */ 1124 ret = t4_sge_init(adap); 1125 if (ret < 0) { 1126 dev_err(adap, "t4_sge_init failed with error %d\n", 1127 -ret); 1128 goto bye; 1129 } 1130 1131 /* 1132 * Grab some of our basic fundamental operating parameters. 1133 */ 1134 #define FW_PARAM_DEV(param) \ 1135 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1136 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1137 1138 #define FW_PARAM_PFVF(param) \ 1139 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1140 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ 1141 V_FW_PARAMS_PARAM_Y(0) | \ 1142 V_FW_PARAMS_PARAM_Z(0)) 1143 1144 params[0] = FW_PARAM_PFVF(L2T_START); 1145 params[1] = FW_PARAM_PFVF(L2T_END); 1146 params[2] = FW_PARAM_PFVF(FILTER_START); 1147 params[3] = FW_PARAM_PFVF(FILTER_END); 1148 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); 1149 if (ret < 0) 1150 goto bye; 1151 adap->l2t_start = val[0]; 1152 adap->l2t_end = val[1]; 1153 adap->tids.ftid_base = val[2]; 1154 adap->tids.nftids = val[3] - val[2] + 1; 1155 1156 params[0] = FW_PARAM_PFVF(CLIP_START); 1157 params[1] = FW_PARAM_PFVF(CLIP_END); 1158 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 1159 if (ret < 0) 1160 goto bye; 1161 adap->clipt_start = val[0]; 1162 adap->clipt_end = val[1]; 1163 1164 /* 1165 * Get device capabilities so we can determine what resources we need 1166 * to manage. 1167 */ 1168 memset(&caps_cmd, 0, sizeof(caps_cmd)); 1169 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1170 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1171 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 1172 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 1173 &caps_cmd); 1174 if (ret < 0) 1175 goto bye; 1176 1177 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) && 1178 is_t6(adap->params.chip)) { 1179 if (init_hash_filter(adap) < 0) 1180 goto bye; 1181 } 1182 1183 /* See if FW supports FW_FILTER2 work request */ 1184 if (is_t4(adap->params.chip)) { 1185 adap->params.filter2_wr_support = 0; 1186 } else { 1187 params[0] = FW_PARAM_DEV(FILTER2_WR); 1188 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1189 1, params, val); 1190 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 1191 } 1192 1193 /* query tid-related parameters */ 1194 params[0] = FW_PARAM_DEV(NTID); 1195 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 1196 params, val); 1197 if (ret < 0) 1198 goto bye; 1199 adap->tids.ntids = val[0]; 1200 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 1201 1202 /* If we're running on newer firmware, let it know that we're 1203 * prepared to deal with encapsulated CPL messages. Older 1204 * firmware won't understand this and we'll just get 1205 * unencapsulated messages ... 1206 */ 1207 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 1208 val[0] = 1; 1209 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 1210 1211 /* 1212 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 1213 * capability. Earlier versions of the firmware didn't have the 1214 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 1215 * permission to use ULPTX MEMWRITE DSGL. 1216 */ 1217 if (is_t4(adap->params.chip)) { 1218 adap->params.ulptx_memwrite_dsgl = false; 1219 } else { 1220 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 1221 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1222 1, params, val); 1223 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 1224 } 1225 1226 /* 1227 * The MTU/MSS Table is initialized by now, so load their values. If 1228 * we're initializing the adapter, then we'll make any modifications 1229 * we want to the MTU/MSS Table and also initialize the congestion 1230 * parameters. 1231 */ 1232 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 1233 if (state != DEV_STATE_INIT) { 1234 int i; 1235 1236 /* 1237 * The default MTU Table contains values 1492 and 1500. 1238 * However, for TCP, it's better to have two values which are 1239 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 1240 * This allows us to have a TCP Data Payload which is a 1241 * multiple of 8 regardless of what combination of TCP Options 1242 * are in use (always a multiple of 4 bytes) which is 1243 * important for performance reasons. For instance, if no 1244 * options are in use, then we have a 20-byte IP header and a 1245 * 20-byte TCP header. In this case, a 1500-byte MSS would 1246 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 1247 * which is not a multiple of 8. So using an MSS of 1488 in 1248 * this case results in a TCP Data Payload of 1448 bytes which 1249 * is a multiple of 8. On the other hand, if 12-byte TCP Time 1250 * Stamps have been negotiated, then an MTU of 1500 bytes 1251 * results in a TCP Data Payload of 1448 bytes which, as 1252 * above, is a multiple of 8 bytes ... 1253 */ 1254 for (i = 0; i < NMTUS; i++) 1255 if (adap->params.mtus[i] == 1492) { 1256 adap->params.mtus[i] = 1488; 1257 break; 1258 } 1259 1260 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 1261 adap->params.b_wnd); 1262 } 1263 t4_init_sge_params(adap); 1264 t4_init_tp_params(adap); 1265 configure_pcie_ext_tag(adap); 1266 configure_vlan_types(adap); 1267 configure_max_ethqsets(adap); 1268 1269 adap->params.drv_memwin = MEMWIN_NIC; 1270 adap->flags |= FW_OK; 1271 dev_debug(adap, "%s: returning zero..\n", __func__); 1272 return 0; 1273 1274 /* 1275 * Something bad happened. If a command timed out or failed with EIO 1276 * FW does not operate within its spec or something catastrophic 1277 * happened to HW/FW, stop issuing commands. 1278 */ 1279 bye: 1280 if (ret != -ETIMEDOUT && ret != -EIO) 1281 t4_fw_bye(adap, adap->mbox); 1282 return ret; 1283 } 1284 1285 /** 1286 * t4_os_portmod_changed - handle port module changes 1287 * @adap: the adapter associated with the module change 1288 * @port_id: the port index whose module status has changed 1289 * 1290 * This is the OS-dependent handler for port module changes. It is 1291 * invoked when a port module is removed or inserted for any OS-specific 1292 * processing. 1293 */ 1294 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 1295 { 1296 static const char * const mod_str[] = { 1297 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 1298 }; 1299 1300 const struct port_info *pi = adap2pinfo(adap, port_id); 1301 1302 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 1303 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 1304 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 1305 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 1306 mod_str[pi->mod_type]); 1307 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 1308 dev_info(adap, "Port%d: unsupported port module inserted\n", 1309 pi->port_id); 1310 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 1311 dev_info(adap, "Port%d: unknown port module inserted\n", 1312 pi->port_id); 1313 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 1314 dev_info(adap, "Port%d: transceiver module error\n", 1315 pi->port_id); 1316 else 1317 dev_info(adap, "Port%d: unknown module type %d inserted\n", 1318 pi->port_id, pi->mod_type); 1319 } 1320 1321 inline bool force_linkup(struct adapter *adap) 1322 { 1323 struct rte_pci_device *pdev = adap->pdev; 1324 1325 if (is_pf4(adap)) 1326 return false; /* force_linkup not required for pf driver*/ 1327 if (!cxgbe_get_devargs(pdev->device.devargs, 1328 CXGBE_DEVARG_FORCE_LINK_UP)) 1329 return false; 1330 return true; 1331 } 1332 1333 /** 1334 * link_start - enable a port 1335 * @dev: the port to enable 1336 * 1337 * Performs the MAC and PHY actions needed to enable a port. 1338 */ 1339 int link_start(struct port_info *pi) 1340 { 1341 struct adapter *adapter = pi->adapter; 1342 int ret; 1343 unsigned int mtu; 1344 1345 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1346 (ETHER_HDR_LEN + ETHER_CRC_LEN); 1347 1348 /* 1349 * We do not set address filters and promiscuity here, the stack does 1350 * that step explicitly. 1351 */ 1352 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, 1353 -1, 1, true); 1354 if (ret == 0) { 1355 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, 1356 (u8 *)&pi->eth_dev->data->mac_addrs[0]); 1357 if (ret >= 0) { 1358 pi->xact_addr_filt = ret; 1359 ret = 0; 1360 } 1361 } 1362 if (ret == 0 && is_pf4(adapter)) 1363 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 1364 &pi->link_cfg); 1365 if (ret == 0) { 1366 /* 1367 * Enabling a Virtual Interface can result in an interrupt 1368 * during the processing of the VI Enable command and, in some 1369 * paths, result in an attempt to issue another command in the 1370 * interrupt context. Thus, we disable interrupts during the 1371 * course of the VI Enable command ... 1372 */ 1373 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 1374 true, true, false); 1375 } 1376 1377 if (ret == 0 && force_linkup(adapter)) 1378 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP; 1379 return ret; 1380 } 1381 1382 /** 1383 * cxgbe_write_rss_conf - flash the RSS configuration for a given port 1384 * @pi: the port 1385 * @rss_hf: Hash configuration to apply 1386 */ 1387 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf) 1388 { 1389 struct adapter *adapter = pi->adapter; 1390 const struct sge_eth_rxq *rxq; 1391 u64 flags = 0; 1392 u16 rss; 1393 int err; 1394 1395 /* Should never be called before setting up sge eth rx queues */ 1396 if (!(adapter->flags & FULL_INIT_DONE)) { 1397 dev_err(adap, "%s No RXQs available on port %d\n", 1398 __func__, pi->port_id); 1399 return -EINVAL; 1400 } 1401 1402 /* Don't allow unsupported hash functions */ 1403 if (rss_hf & ~CXGBE_RSS_HF_ALL) 1404 return -EINVAL; 1405 1406 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK) 1407 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 1408 1409 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 1410 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 1411 1412 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 1413 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 1414 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1415 1416 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK) 1417 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 1418 1419 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK) 1420 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1421 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 1422 1423 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK) 1424 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 1425 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 1426 F_FW_RSS_VI_CONFIG_CMD_UDPEN; 1427 1428 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1429 rss = rxq[0].rspq.abs_id; 1430 1431 /* If Tunnel All Lookup isn't specified in the global RSS 1432 * Configuration, then we need to specify a default Ingress 1433 * Queue for any ingress packets which aren't hashed. We'll 1434 * use our first ingress queue ... 1435 */ 1436 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 1437 flags, rss); 1438 return err; 1439 } 1440 1441 /** 1442 * cxgbe_write_rss - write the RSS table for a given port 1443 * @pi: the port 1444 * @queues: array of queue indices for RSS 1445 * 1446 * Sets up the portion of the HW RSS table for the port's VI to distribute 1447 * packets to the Rx queues in @queues. 1448 */ 1449 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues) 1450 { 1451 u16 *rss; 1452 int i, err; 1453 struct adapter *adapter = pi->adapter; 1454 const struct sge_eth_rxq *rxq; 1455 1456 /* Should never be called before setting up sge eth rx queues */ 1457 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 1458 1459 rxq = &adapter->sge.ethrxq[pi->first_qset]; 1460 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 1461 if (!rss) 1462 return -ENOMEM; 1463 1464 /* map the queue indices to queue ids */ 1465 for (i = 0; i < pi->rss_size; i++, queues++) 1466 rss[i] = rxq[*queues].rspq.abs_id; 1467 1468 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 1469 pi->rss_size, rss, pi->rss_size); 1470 rte_free(rss); 1471 return err; 1472 } 1473 1474 /** 1475 * setup_rss - configure RSS 1476 * @adapter: the adapter 1477 * 1478 * Sets up RSS to distribute packets to multiple receive queues. We 1479 * configure the RSS CPU lookup table to distribute to the number of HW 1480 * receive queues, and the response queue lookup table to narrow that 1481 * down to the response queues actually configured for each port. 1482 * We always configure the RSS mapping for all ports since the mapping 1483 * table has plenty of entries. 1484 */ 1485 int setup_rss(struct port_info *pi) 1486 { 1487 int j, err; 1488 struct adapter *adapter = pi->adapter; 1489 1490 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 1491 __func__, pi->rss_size, pi->n_rx_qsets); 1492 1493 if (!(pi->flags & PORT_RSS_DONE)) { 1494 if (adapter->flags & FULL_INIT_DONE) { 1495 /* Fill default values with equal distribution */ 1496 for (j = 0; j < pi->rss_size; j++) 1497 pi->rss[j] = j % pi->n_rx_qsets; 1498 1499 err = cxgbe_write_rss(pi, pi->rss); 1500 if (err) 1501 return err; 1502 1503 err = cxgbe_write_rss_conf(pi, pi->rss_hf); 1504 if (err) 1505 return err; 1506 pi->flags |= PORT_RSS_DONE; 1507 } 1508 } 1509 return 0; 1510 } 1511 1512 /* 1513 * Enable NAPI scheduling and interrupt generation for all Rx queues. 1514 */ 1515 static void enable_rx(struct adapter *adap, struct sge_rspq *q) 1516 { 1517 /* 0-increment GTS to start the timer and enable interrupts */ 1518 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) : 1519 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS, 1520 V_SEINTARM(q->intr_params) | 1521 V_INGRESSQID(q->cntxt_id)); 1522 } 1523 1524 void cxgbe_enable_rx_queues(struct port_info *pi) 1525 { 1526 struct adapter *adap = pi->adapter; 1527 struct sge *s = &adap->sge; 1528 unsigned int i; 1529 1530 for (i = 0; i < pi->n_rx_qsets; i++) 1531 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq); 1532 } 1533 1534 /** 1535 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps. 1536 * @port_type: Firmware Port Type 1537 * @fw_caps: Firmware Port Capabilities 1538 * @speed_caps: Device Info Speed Capabilities 1539 * 1540 * Translate a Firmware Port Capabilities specification to Device Info 1541 * Speed Capabilities. 1542 */ 1543 static void fw_caps_to_speed_caps(enum fw_port_type port_type, 1544 unsigned int fw_caps, 1545 u32 *speed_caps) 1546 { 1547 #define SET_SPEED(__speed_name) \ 1548 do { \ 1549 *speed_caps |= ETH_LINK_ ## __speed_name; \ 1550 } while (0) 1551 1552 #define FW_CAPS_TO_SPEED(__fw_name) \ 1553 do { \ 1554 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \ 1555 SET_SPEED(__fw_name); \ 1556 } while (0) 1557 1558 switch (port_type) { 1559 case FW_PORT_TYPE_BT_SGMII: 1560 case FW_PORT_TYPE_BT_XFI: 1561 case FW_PORT_TYPE_BT_XAUI: 1562 FW_CAPS_TO_SPEED(SPEED_100M); 1563 FW_CAPS_TO_SPEED(SPEED_1G); 1564 FW_CAPS_TO_SPEED(SPEED_10G); 1565 break; 1566 1567 case FW_PORT_TYPE_KX4: 1568 case FW_PORT_TYPE_KX: 1569 case FW_PORT_TYPE_FIBER_XFI: 1570 case FW_PORT_TYPE_FIBER_XAUI: 1571 case FW_PORT_TYPE_SFP: 1572 case FW_PORT_TYPE_QSFP_10G: 1573 case FW_PORT_TYPE_QSA: 1574 FW_CAPS_TO_SPEED(SPEED_1G); 1575 FW_CAPS_TO_SPEED(SPEED_10G); 1576 break; 1577 1578 case FW_PORT_TYPE_KR: 1579 SET_SPEED(SPEED_10G); 1580 break; 1581 1582 case FW_PORT_TYPE_BP_AP: 1583 case FW_PORT_TYPE_BP4_AP: 1584 SET_SPEED(SPEED_1G); 1585 SET_SPEED(SPEED_10G); 1586 break; 1587 1588 case FW_PORT_TYPE_BP40_BA: 1589 case FW_PORT_TYPE_QSFP: 1590 SET_SPEED(SPEED_40G); 1591 break; 1592 1593 case FW_PORT_TYPE_CR_QSFP: 1594 case FW_PORT_TYPE_SFP28: 1595 case FW_PORT_TYPE_KR_SFP28: 1596 FW_CAPS_TO_SPEED(SPEED_1G); 1597 FW_CAPS_TO_SPEED(SPEED_10G); 1598 FW_CAPS_TO_SPEED(SPEED_25G); 1599 break; 1600 1601 case FW_PORT_TYPE_CR2_QSFP: 1602 SET_SPEED(SPEED_50G); 1603 break; 1604 1605 case FW_PORT_TYPE_KR4_100G: 1606 case FW_PORT_TYPE_CR4_QSFP: 1607 FW_CAPS_TO_SPEED(SPEED_25G); 1608 FW_CAPS_TO_SPEED(SPEED_40G); 1609 FW_CAPS_TO_SPEED(SPEED_50G); 1610 FW_CAPS_TO_SPEED(SPEED_100G); 1611 break; 1612 1613 default: 1614 break; 1615 } 1616 1617 #undef FW_CAPS_TO_SPEED 1618 #undef SET_SPEED 1619 } 1620 1621 /** 1622 * cxgbe_get_speed_caps - Fetch supported speed capabilities 1623 * @pi: Underlying port's info 1624 * @speed_caps: Device Info speed capabilities 1625 * 1626 * Fetch supported speed capabilities of the underlying port. 1627 */ 1628 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps) 1629 { 1630 *speed_caps = 0; 1631 1632 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps, 1633 speed_caps); 1634 1635 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)) 1636 *speed_caps |= ETH_LINK_SPEED_FIXED; 1637 } 1638 1639 /** 1640 * cxgbe_set_link_status - Set device link up or down. 1641 * @pi: Underlying port's info 1642 * @status: 0 - down, 1 - up 1643 * 1644 * Set the device link up or down. 1645 */ 1646 int cxgbe_set_link_status(struct port_info *pi, bool status) 1647 { 1648 struct adapter *adapter = pi->adapter; 1649 int err = 0; 1650 1651 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status); 1652 if (err) { 1653 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1654 return err; 1655 } 1656 1657 if (!status) 1658 t4_reset_link_config(adapter, pi->pidx); 1659 1660 return 0; 1661 } 1662 1663 /** 1664 * cxgb_up - enable the adapter 1665 * @adap: adapter being enabled 1666 * 1667 * Called when the first port is enabled, this function performs the 1668 * actions necessary to make an adapter operational, such as completing 1669 * the initialization of HW modules, and enabling interrupts. 1670 */ 1671 int cxgbe_up(struct adapter *adap) 1672 { 1673 enable_rx(adap, &adap->sge.fw_evtq); 1674 t4_sge_tx_monitor_start(adap); 1675 if (is_pf4(adap)) 1676 t4_intr_enable(adap); 1677 adap->flags |= FULL_INIT_DONE; 1678 1679 /* TODO: deadman watchdog ?? */ 1680 return 0; 1681 } 1682 1683 /* 1684 * Close the port 1685 */ 1686 int cxgbe_down(struct port_info *pi) 1687 { 1688 return cxgbe_set_link_status(pi, false); 1689 } 1690 1691 /* 1692 * Release resources when all the ports have been stopped. 1693 */ 1694 void cxgbe_close(struct adapter *adapter) 1695 { 1696 struct port_info *pi; 1697 int i; 1698 1699 if (adapter->flags & FULL_INIT_DONE) { 1700 tid_free(&adapter->tids); 1701 t4_cleanup_mpstcam(adapter); 1702 t4_cleanup_clip_tbl(adapter); 1703 t4_cleanup_l2t(adapter); 1704 if (is_pf4(adapter)) 1705 t4_intr_disable(adapter); 1706 t4_sge_tx_monitor_stop(adapter); 1707 t4_free_sge_resources(adapter); 1708 for_each_port(adapter, i) { 1709 pi = adap2pinfo(adapter, i); 1710 if (pi->viid != 0) 1711 t4_free_vi(adapter, adapter->mbox, 1712 adapter->pf, 0, pi->viid); 1713 rte_free(pi->eth_dev->data->mac_addrs); 1714 /* Skip first port since it'll be freed by DPDK stack */ 1715 if (i) { 1716 rte_free(pi->eth_dev->data->dev_private); 1717 rte_eth_dev_release_port(pi->eth_dev); 1718 } 1719 } 1720 adapter->flags &= ~FULL_INIT_DONE; 1721 } 1722 1723 if (is_pf4(adapter) && (adapter->flags & FW_OK)) 1724 t4_fw_bye(adapter, adapter->mbox); 1725 } 1726 1727 int cxgbe_probe(struct adapter *adapter) 1728 { 1729 struct port_info *pi; 1730 int chip; 1731 int func, i; 1732 int err = 0; 1733 u32 whoami; 1734 1735 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 1736 chip = t4_get_chip_type(adapter, 1737 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id)); 1738 if (chip < 0) 1739 return chip; 1740 1741 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 1742 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami); 1743 1744 adapter->mbox = func; 1745 adapter->pf = func; 1746 1747 t4_os_lock_init(&adapter->mbox_lock); 1748 TAILQ_INIT(&adapter->mbox_list); 1749 t4_os_lock_init(&adapter->win0_lock); 1750 1751 err = t4_prep_adapter(adapter); 1752 if (err) 1753 return err; 1754 1755 setup_memwin(adapter); 1756 err = adap_init0(adapter); 1757 if (err) { 1758 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 1759 __func__, err); 1760 goto out_free; 1761 } 1762 1763 if (!is_t4(adapter->params.chip)) { 1764 /* 1765 * The userspace doorbell BAR is split evenly into doorbell 1766 * regions, each associated with an egress queue. If this 1767 * per-queue region is large enough (at least UDBS_SEG_SIZE) 1768 * then it can be used to submit a tx work request with an 1769 * implied doorbell. Enable write combining on the BAR if 1770 * there is room for such work requests. 1771 */ 1772 int s_qpp, qpp, num_seg; 1773 1774 s_qpp = (S_QUEUESPERPAGEPF0 + 1775 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 1776 adapter->pf); 1777 qpp = 1 << ((t4_read_reg(adapter, 1778 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 1779 & M_QUEUESPERPAGEPF0); 1780 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 1781 if (qpp > num_seg) 1782 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 1783 1784 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 1785 if (!adapter->bar2) { 1786 dev_err(adapter, "cannot map device bar2 region\n"); 1787 err = -ENOMEM; 1788 goto out_free; 1789 } 1790 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 1791 V_STATMODE(0)); 1792 } 1793 1794 for_each_port(adapter, i) { 1795 const unsigned int numa_node = rte_socket_id(); 1796 char name[RTE_ETH_NAME_MAX_LEN]; 1797 struct rte_eth_dev *eth_dev; 1798 1799 snprintf(name, sizeof(name), "%s_%d", 1800 adapter->pdev->device.name, i); 1801 1802 if (i == 0) { 1803 /* First port is already allocated by DPDK */ 1804 eth_dev = adapter->eth_dev; 1805 goto allocate_mac; 1806 } 1807 1808 /* 1809 * now do all data allocation - for eth_dev structure, 1810 * and internal (private) data for the remaining ports 1811 */ 1812 1813 /* reserve an ethdev entry */ 1814 eth_dev = rte_eth_dev_allocate(name); 1815 if (!eth_dev) 1816 goto out_free; 1817 1818 eth_dev->data->dev_private = 1819 rte_zmalloc_socket(name, sizeof(struct port_info), 1820 RTE_CACHE_LINE_SIZE, numa_node); 1821 if (!eth_dev->data->dev_private) 1822 goto out_free; 1823 1824 allocate_mac: 1825 pi = (struct port_info *)eth_dev->data->dev_private; 1826 adapter->port[i] = pi; 1827 pi->eth_dev = eth_dev; 1828 pi->adapter = adapter; 1829 pi->xact_addr_filt = -1; 1830 pi->port_id = i; 1831 pi->pidx = i; 1832 1833 pi->eth_dev->device = &adapter->pdev->device; 1834 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 1835 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 1836 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 1837 1838 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev); 1839 1840 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 1841 ETHER_ADDR_LEN, 0); 1842 if (!pi->eth_dev->data->mac_addrs) { 1843 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 1844 __func__); 1845 err = -1; 1846 goto out_free; 1847 } 1848 1849 if (i > 0) { 1850 /* First port will be notified by upper layer */ 1851 rte_eth_dev_probing_finish(eth_dev); 1852 } 1853 } 1854 1855 if (adapter->flags & FW_OK) { 1856 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 1857 if (err) { 1858 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 1859 __func__, err); 1860 goto out_free; 1861 } 1862 } 1863 1864 cfg_queues(adapter->eth_dev); 1865 1866 print_adapter_info(adapter); 1867 print_port_info(adapter); 1868 1869 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 1870 adapter->clipt_end); 1871 if (!adapter->clipt) { 1872 /* We tolerate a lack of clip_table, giving up some 1873 * functionality 1874 */ 1875 dev_warn(adapter, "could not allocate CLIP. Continuing\n"); 1876 } 1877 1878 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 1879 if (!adapter->l2t) { 1880 /* We tolerate a lack of L2T, giving up some functionality */ 1881 dev_warn(adapter, "could not allocate L2T. Continuing\n"); 1882 } 1883 1884 if (tid_init(&adapter->tids) < 0) { 1885 /* Disable filtering support */ 1886 dev_warn(adapter, "could not allocate TID table, " 1887 "filter support disabled. Continuing\n"); 1888 } 1889 1890 adapter->mpstcam = t4_init_mpstcam(adapter); 1891 if (!adapter->mpstcam) 1892 dev_warn(adapter, "could not allocate mps tcam table." 1893 " Continuing\n"); 1894 1895 if (is_hashfilter(adapter)) { 1896 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) { 1897 u32 hash_base, hash_reg; 1898 1899 hash_reg = A_LE_DB_TID_HASHBASE; 1900 hash_base = t4_read_reg(adapter, hash_reg); 1901 adapter->tids.hash_base = hash_base / 4; 1902 } 1903 } else { 1904 /* Disable hash filtering support */ 1905 dev_warn(adapter, 1906 "Maskless filter support disabled. Continuing\n"); 1907 } 1908 1909 err = init_rss(adapter); 1910 if (err) 1911 goto out_free; 1912 1913 return 0; 1914 1915 out_free: 1916 for_each_port(adapter, i) { 1917 pi = adap2pinfo(adapter, i); 1918 if (pi->viid != 0) 1919 t4_free_vi(adapter, adapter->mbox, adapter->pf, 1920 0, pi->viid); 1921 /* Skip first port since it'll be de-allocated by DPDK */ 1922 if (i == 0) 1923 continue; 1924 if (pi->eth_dev) { 1925 if (pi->eth_dev->data->dev_private) 1926 rte_free(pi->eth_dev->data->dev_private); 1927 rte_eth_dev_release_port(pi->eth_dev); 1928 } 1929 } 1930 1931 if (adapter->flags & FW_OK) 1932 t4_fw_bye(adapter, adapter->mbox); 1933 return -err; 1934 } 1935