1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef __CHELSIO_COMMON_H 7 #define __CHELSIO_COMMON_H 8 9 #include "../cxgbe_compat.h" 10 #include "t4_hw.h" 11 #include "t4vf_hw.h" 12 #include "t4_chip_type.h" 13 #include "t4fw_interface.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K 20 21 #define T4_MEMORY_WRITE 0 22 #define T4_MEMORY_READ 1 23 24 enum { 25 MAX_NPORTS = 4, /* max # of ports */ 26 }; 27 28 enum { 29 T5_REGMAP_SIZE = (332 * 1024), 30 }; 31 32 enum { 33 MEMWIN0_APERTURE = 2048, 34 MEMWIN0_BASE = 0x1b800, 35 }; 36 37 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 38 39 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 40 41 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 42 43 struct port_stats { 44 u64 tx_octets; /* total # of octets in good frames */ 45 u64 tx_frames; /* all good frames */ 46 u64 tx_bcast_frames; /* all broadcast frames */ 47 u64 tx_mcast_frames; /* all multicast frames */ 48 u64 tx_ucast_frames; /* all unicast frames */ 49 u64 tx_error_frames; /* all error frames */ 50 51 u64 tx_frames_64; /* # of Tx frames in a particular range */ 52 u64 tx_frames_65_127; 53 u64 tx_frames_128_255; 54 u64 tx_frames_256_511; 55 u64 tx_frames_512_1023; 56 u64 tx_frames_1024_1518; 57 u64 tx_frames_1519_max; 58 59 u64 tx_drop; /* # of dropped Tx frames */ 60 u64 tx_pause; /* # of transmitted pause frames */ 61 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 62 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 63 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 64 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 65 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 66 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 67 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 68 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 69 70 u64 rx_octets; /* total # of octets in good frames */ 71 u64 rx_frames; /* all good frames */ 72 u64 rx_bcast_frames; /* all broadcast frames */ 73 u64 rx_mcast_frames; /* all multicast frames */ 74 u64 rx_ucast_frames; /* all unicast frames */ 75 u64 rx_too_long; /* # of frames exceeding MTU */ 76 u64 rx_jabber; /* # of jabber frames */ 77 u64 rx_fcs_err; /* # of received frames with bad FCS */ 78 u64 rx_len_err; /* # of received frames with length error */ 79 u64 rx_symbol_err; /* symbol errors */ 80 u64 rx_runt; /* # of short frames */ 81 82 u64 rx_frames_64; /* # of Rx frames in a particular range */ 83 u64 rx_frames_65_127; 84 u64 rx_frames_128_255; 85 u64 rx_frames_256_511; 86 u64 rx_frames_512_1023; 87 u64 rx_frames_1024_1518; 88 u64 rx_frames_1519_max; 89 90 u64 rx_pause; /* # of received pause frames */ 91 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 92 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 93 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 94 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 95 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 96 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 97 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 98 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 99 100 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 101 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 102 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 103 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 104 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 105 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 106 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 107 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 108 }; 109 110 struct sge_params { 111 u32 hps; /* host page size for our PF/VF */ 112 u32 eq_qpp; /* egress queues/page for our PF/VF */ 113 u32 iq_qpp; /* egress queues/page for our PF/VF */ 114 }; 115 116 struct tp_params { 117 unsigned int ntxchan; /* # of Tx channels */ 118 unsigned int tre; /* log2 of core clocks per TP tick */ 119 unsigned int dack_re; /* DACK timer resolution */ 120 unsigned int la_mask; /* what events are recorded by TP LA */ 121 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 122 123 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 124 u32 filter_mask; 125 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 126 127 /* cached TP_OUT_CONFIG compressed error vector 128 * and passing outer header info for encapsulated packets. 129 */ 130 int rx_pkt_encap; 131 132 /* 133 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 134 * subset of the set of fields which may be present in the Compressed 135 * Filter Tuple portion of filters and TCP TCB connections. The 136 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 137 * Since a variable number of fields may or may not be present, their 138 * shifted field positions within the Compressed Filter Tuple may 139 * vary, or not even be present if the field isn't selected in 140 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 141 * places we store their offsets here, or a -1 if the field isn't 142 * present. 143 */ 144 int vlan_shift; 145 int vnic_shift; 146 int port_shift; 147 int protocol_shift; 148 int ethertype_shift; 149 int macmatch_shift; 150 int tos_shift; 151 152 u64 hash_filter_mask; 153 }; 154 155 struct vpd_params { 156 unsigned int cclk; 157 }; 158 159 struct pci_params { 160 uint16_t vendor_id; 161 uint16_t device_id; 162 uint32_t vpd_cap_addr; 163 uint16_t speed; 164 uint8_t width; 165 }; 166 167 /* 168 * Firmware device log. 169 */ 170 struct devlog_params { 171 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 172 u32 start; /* start of log in firmware memory */ 173 u32 size; /* size of log */ 174 }; 175 176 struct arch_specific_params { 177 u8 nchan; 178 u8 cng_ch_bits_log; /* congestion channel map bits width */ 179 u16 mps_rplc_size; 180 u16 vfcount; 181 u32 sge_fl_db; 182 u16 mps_tcam_size; 183 }; 184 185 /* 186 * Global Receive Side Scaling (RSS) parameters in host-native format. 187 */ 188 struct rss_params { 189 unsigned int mode; /* RSS mode */ 190 union { 191 struct { 192 unsigned int synmapen:1; /* SYN Map Enable */ 193 unsigned int syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */ 194 unsigned int syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */ 195 unsigned int syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */ 196 unsigned int syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */ 197 unsigned int ofdmapen:1; /* Offload Map Enable */ 198 unsigned int tnlmapen:1; /* Tunnel Map Enable */ 199 unsigned int tnlalllookup:1; /* Tunnel All Lookup */ 200 unsigned int hashtoeplitz:1; /* use Toeplitz hash */ 201 } basicvirtual; 202 } u; 203 }; 204 205 /* 206 * Maximum resources provisioned for a PCI PF. 207 */ 208 struct pf_resources { 209 unsigned int neq; /* N egress Qs */ 210 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 211 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 212 }; 213 214 /* 215 * Maximum resources provisioned for a PCI VF. 216 */ 217 struct vf_resources { 218 unsigned int nvi; /* N virtual interfaces */ 219 unsigned int neq; /* N egress Qs */ 220 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 221 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 222 unsigned int niq; /* N ingress Qs */ 223 unsigned int tc; /* PCI-E traffic class */ 224 unsigned int pmask; /* port access rights mask */ 225 unsigned int nexactf; /* N exact MPS filters */ 226 unsigned int r_caps; /* read capabilities */ 227 unsigned int wx_caps; /* write/execute capabilities */ 228 }; 229 230 struct adapter_params { 231 struct sge_params sge; 232 struct tp_params tp; 233 struct vpd_params vpd; 234 struct pci_params pci; 235 struct devlog_params devlog; 236 struct rss_params rss; 237 struct pf_resources pfres; 238 struct vf_resources vfres; 239 enum pcie_memwin drv_memwin; 240 241 unsigned int sf_size; /* serial flash size in bytes */ 242 unsigned int sf_nsec; /* # of flash sectors */ 243 244 unsigned int fw_vers; 245 unsigned int bs_vers; 246 unsigned int tp_vers; 247 unsigned int er_vers; 248 249 unsigned short mtus[NMTUS]; 250 unsigned short a_wnd[NCCTRL_WIN]; 251 unsigned short b_wnd[NCCTRL_WIN]; 252 253 unsigned int mc_size; /* MC memory size */ 254 unsigned int cim_la_size; 255 256 unsigned char nports; /* # of ethernet ports */ 257 unsigned char portvec; 258 259 unsigned char hash_filter; 260 261 enum chip_type chip; /* chip code */ 262 struct arch_specific_params arch; /* chip specific params */ 263 264 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 265 u8 filter2_wr_support; /* FW support for FILTER2_WR */ 266 u32 viid_smt_extn_support:1; /* FW returns vin and smt index */ 267 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ 268 u8 vi_enable_rx; /* FW support for enable/disable VI Rx at runtime */ 269 270 u16 rawf_start; /* FW supports RAW MAC match-all filters */ 271 u16 rawf_size; 272 }; 273 274 /* Firmware Port Capabilities types. 275 */ 276 struct link_config { 277 u32 pcaps; /* Physically supported link caps */ 278 u32 acaps; /* Advertised link caps */ 279 280 u32 link_caps; /* Current link caps */ 281 u32 admin_caps; /* Admin configured link caps */ 282 283 u8 mdio_addr; /* Address of the PHY */ 284 u8 port_type; /* Firmware port type */ 285 u8 mod_type; /* Firmware module type */ 286 287 u8 link_ok; /* Link up? */ 288 u8 link_down_rc; /* Link down reason */ 289 }; 290 291 #include "adapter.h" 292 293 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 294 u32 val); 295 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 296 int polarity, 297 int attempts, int delay, u32 *valp); 298 299 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 300 int polarity, int attempts, int delay) 301 { 302 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 303 delay, NULL); 304 } 305 306 static inline int is_pf4(struct adapter *adap) 307 { 308 return adap->pf == 4; 309 } 310 311 #define for_each_port(adapter, iter) \ 312 for (iter = 0; iter < (adapter)->params.nports; ++iter) 313 314 static inline int is_hashfilter(const struct adapter *adap) 315 { 316 return adap->params.hash_filter; 317 } 318 319 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 320 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 321 unsigned int mask, unsigned int val); 322 void t4_intr_enable(struct adapter *adapter); 323 void t4_intr_disable(struct adapter *adapter); 324 int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok); 325 static inline int t4_link_l1cfg(struct port_info *pi, u32 caps) 326 { 327 return t4_link_l1cfg_core(pi, caps, true); 328 } 329 330 static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps) 331 { 332 return t4_link_l1cfg_core(pi, caps, false); 333 } 334 335 int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps); 336 int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx, 337 u8 pause_rx, u32 *new_caps); 338 int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser, 339 u8 fec_none, u32 *new_caps); 340 unsigned int t4_fwcap_to_speed(u32 caps); 341 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 342 const unsigned short *alpha, const unsigned short *beta); 343 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 344 enum dev_master master, enum dev_state *state); 345 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 346 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 347 int t4vf_fw_reset(struct adapter *adap); 348 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 349 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 350 int t4_fl_pkt_align(struct adapter *adap); 351 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2); 352 int t4vf_get_vfres(struct adapter *adap); 353 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 354 unsigned int cache_line_size, 355 enum chip_type chip_compat); 356 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 357 unsigned int cache_line_size); 358 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 359 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 360 unsigned int vf, unsigned int nparams, const u32 *params, 361 u32 *val); 362 int t4vf_query_params(struct adapter *adap, unsigned int nparams, 363 const u32 *params, u32 *vals); 364 int t4vf_get_dev_params(struct adapter *adap); 365 int t4vf_get_vpd_params(struct adapter *adap); 366 int t4vf_get_rss_glb_config(struct adapter *adap); 367 int t4vf_set_params(struct adapter *adapter, unsigned int nparams, 368 const u32 *params, const u32 *vals); 369 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 370 unsigned int pf, unsigned int vf, 371 unsigned int nparams, const u32 *params, 372 const u32 *val, int timeout); 373 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 374 unsigned int vf, unsigned int nparams, const u32 *params, 375 const u32 *val); 376 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 377 unsigned int port, unsigned int pf, unsigned int vf, 378 unsigned int nmac, u8 *mac, unsigned int *rss_size, 379 unsigned int portfunc, unsigned int idstype, 380 u8 *vivld, u8 *vin); 381 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 382 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 383 unsigned int *rss_size, u8 *vivild, u8 *vin); 384 int t4_free_vi(struct adapter *adap, unsigned int mbox, 385 unsigned int pf, unsigned int vf, 386 unsigned int viid); 387 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 388 int mtu, int promisc, int all_multi, int bcast, int vlanex, 389 bool sleep_ok); 390 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 391 const u8 *addr, const u8 *mask, unsigned int idx, 392 u8 lookup_type, u8 port_id, bool sleep_ok); 393 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 394 const u8 *addr, const u8 *mask, unsigned int idx, 395 u8 lookup_type, u8 port_id, bool sleep_ok); 396 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 397 int idx, const u8 *addr, bool persist, bool add_smt); 398 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 399 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 400 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 401 bool rx_en, bool tx_en); 402 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 403 unsigned int pf, unsigned int vf, unsigned int iqid, 404 unsigned int fl0id, unsigned int fl1id); 405 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 406 unsigned int vf, unsigned int iqtype, unsigned int iqid, 407 unsigned int fl0id, unsigned int fl1id); 408 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 409 unsigned int vf, unsigned int eqid); 410 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 411 unsigned int vf, unsigned int eqid); 412 413 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 414 { 415 return adap->params.vpd.cclk / 1000; 416 } 417 418 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 419 unsigned int us) 420 { 421 return (us * adap->params.vpd.cclk) / 1000; 422 } 423 424 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 425 unsigned int ticks) 426 { 427 /* add Core Clock / 2 to round ticks to nearest uS */ 428 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 429 adapter->params.vpd.cclk); 430 } 431 432 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 433 int size, void *rpl, bool sleep_ok, int timeout); 434 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 435 const void __attribute__((__may_alias__)) *cmd, int size, 436 void *rpl, bool sleep_ok); 437 438 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 439 const void *cmd, int size, void *rpl, 440 int timeout) 441 { 442 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 443 timeout); 444 } 445 446 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 447 448 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 449 int size, void *rpl) 450 { 451 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 452 } 453 454 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 455 int size, void *rpl) 456 { 457 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 458 } 459 460 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); 461 462 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, 463 int size, void *rpl) 464 { 465 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); 466 } 467 468 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, 469 int size, void *rpl) 470 { 471 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); 472 } 473 474 475 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 476 unsigned int data_reg, u32 *vals, unsigned int nregs, 477 unsigned int start_idx); 478 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 479 unsigned int data_reg, const u32 *vals, 480 unsigned int nregs, unsigned int start_idx); 481 482 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 483 int t4_get_pfres(struct adapter *adapter); 484 int t4_read_flash(struct adapter *adapter, unsigned int addr, 485 unsigned int nwords, u32 *data, int byte_oriented); 486 int t4_flash_cfg_addr(struct adapter *adapter); 487 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx); 488 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx); 489 const char *t4_get_port_type_description(enum fw_port_type port_type); 490 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 491 void t4vf_get_port_stats(struct adapter *adapter, int pidx, 492 struct port_stats *p); 493 void t4_get_port_stats_offset(struct adapter *adap, int idx, 494 struct port_stats *stats, 495 struct port_stats *offset); 496 void t4_clr_port_stats(struct adapter *adap, int idx); 497 void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps, 498 u8 mdio_addr, u8 port_type, u8 mod_type); 499 void t4_reset_link_config(struct adapter *adap, int idx); 500 int t4_get_version_info(struct adapter *adapter); 501 void t4_dump_version_info(struct adapter *adapter); 502 int t4_get_flash_params(struct adapter *adapter); 503 int t4_get_chip_type(struct adapter *adap, int ver); 504 int t4_prep_adapter(struct adapter *adapter); 505 int t4vf_prep_adapter(struct adapter *adapter); 506 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 507 int t4vf_port_init(struct adapter *adap); 508 int t4_init_rss_mode(struct adapter *adap, int mbox); 509 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 510 int start, int n, const u16 *rspq, unsigned int nrspq); 511 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 512 unsigned int flags, unsigned int defq); 513 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 514 u64 *flags, unsigned int *defq); 515 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 516 unsigned int start_index, unsigned int rw); 517 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 518 void t4_read_rss_key(struct adapter *adap, u32 *key); 519 520 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 521 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 522 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset, 523 unsigned int *pbar2_qid); 524 525 int t4_init_sge_params(struct adapter *adapter); 526 int t4_init_tp_params(struct adapter *adap); 527 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 528 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 529 unsigned int t4_get_regs_len(struct adapter *adap); 530 unsigned int t4vf_get_pf_from_vf(struct adapter *adap); 531 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 532 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 533 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 534 int t4_seeprom_wp(struct adapter *adapter, int enable); 535 int t4_memory_rw_addr(struct adapter *adap, int win, 536 u32 addr, u32 len, void *hbuf, int dir); 537 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, 538 u32 len, void *hbuf, int dir); 539 static inline int t4_memory_rw(struct adapter *adap, int win, 540 int mtype, u32 maddr, u32 len, 541 void *hbuf, int dir) 542 { 543 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); 544 } 545 #endif /* __CHELSIO_COMMON_H */ 546