1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef __CHELSIO_COMMON_H 7 #define __CHELSIO_COMMON_H 8 9 #include "../cxgbe_compat.h" 10 #include "t4_hw.h" 11 #include "t4vf_hw.h" 12 #include "t4_chip_type.h" 13 #include "t4fw_interface.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K 20 21 #define T4_MEMORY_WRITE 0 22 #define T4_MEMORY_READ 1 23 24 enum { 25 MAX_NPORTS = 4, /* max # of ports */ 26 }; 27 28 enum { 29 T5_REGMAP_SIZE = (332 * 1024), 30 }; 31 32 enum { 33 MEMWIN0_APERTURE = 2048, 34 MEMWIN0_BASE = 0x1b800, 35 }; 36 37 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 38 39 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 40 41 enum cc_pause { 42 PAUSE_RX = 1 << 0, 43 PAUSE_TX = 1 << 1, 44 PAUSE_AUTONEG = 1 << 2 45 }; 46 47 enum cc_fec { 48 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 49 FEC_RS = 1 << 1, /* Reed-Solomon */ 50 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ 51 }; 52 53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55 struct port_stats { 56 u64 tx_octets; /* total # of octets in good frames */ 57 u64 tx_frames; /* all good frames */ 58 u64 tx_bcast_frames; /* all broadcast frames */ 59 u64 tx_mcast_frames; /* all multicast frames */ 60 u64 tx_ucast_frames; /* all unicast frames */ 61 u64 tx_error_frames; /* all error frames */ 62 63 u64 tx_frames_64; /* # of Tx frames in a particular range */ 64 u64 tx_frames_65_127; 65 u64 tx_frames_128_255; 66 u64 tx_frames_256_511; 67 u64 tx_frames_512_1023; 68 u64 tx_frames_1024_1518; 69 u64 tx_frames_1519_max; 70 71 u64 tx_drop; /* # of dropped Tx frames */ 72 u64 tx_pause; /* # of transmitted pause frames */ 73 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 74 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 75 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 76 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 77 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 78 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 79 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 80 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 81 82 u64 rx_octets; /* total # of octets in good frames */ 83 u64 rx_frames; /* all good frames */ 84 u64 rx_bcast_frames; /* all broadcast frames */ 85 u64 rx_mcast_frames; /* all multicast frames */ 86 u64 rx_ucast_frames; /* all unicast frames */ 87 u64 rx_too_long; /* # of frames exceeding MTU */ 88 u64 rx_jabber; /* # of jabber frames */ 89 u64 rx_fcs_err; /* # of received frames with bad FCS */ 90 u64 rx_len_err; /* # of received frames with length error */ 91 u64 rx_symbol_err; /* symbol errors */ 92 u64 rx_runt; /* # of short frames */ 93 94 u64 rx_frames_64; /* # of Rx frames in a particular range */ 95 u64 rx_frames_65_127; 96 u64 rx_frames_128_255; 97 u64 rx_frames_256_511; 98 u64 rx_frames_512_1023; 99 u64 rx_frames_1024_1518; 100 u64 rx_frames_1519_max; 101 102 u64 rx_pause; /* # of received pause frames */ 103 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 104 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 105 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 106 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 107 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 108 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 109 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 110 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 111 112 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 113 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 114 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 115 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 116 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 117 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 118 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 119 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 120 }; 121 122 struct sge_params { 123 u32 hps; /* host page size for our PF/VF */ 124 u32 eq_qpp; /* egress queues/page for our PF/VF */ 125 u32 iq_qpp; /* egress queues/page for our PF/VF */ 126 }; 127 128 struct tp_params { 129 unsigned int ntxchan; /* # of Tx channels */ 130 unsigned int tre; /* log2 of core clocks per TP tick */ 131 unsigned int dack_re; /* DACK timer resolution */ 132 unsigned int la_mask; /* what events are recorded by TP LA */ 133 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 134 135 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 136 u32 filter_mask; 137 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 138 139 /* cached TP_OUT_CONFIG compressed error vector 140 * and passing outer header info for encapsulated packets. 141 */ 142 int rx_pkt_encap; 143 144 /* 145 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 146 * subset of the set of fields which may be present in the Compressed 147 * Filter Tuple portion of filters and TCP TCB connections. The 148 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 149 * Since a variable number of fields may or may not be present, their 150 * shifted field positions within the Compressed Filter Tuple may 151 * vary, or not even be present if the field isn't selected in 152 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 153 * places we store their offsets here, or a -1 if the field isn't 154 * present. 155 */ 156 int vlan_shift; 157 int vnic_shift; 158 int port_shift; 159 int protocol_shift; 160 int ethertype_shift; 161 int macmatch_shift; 162 int tos_shift; 163 164 u64 hash_filter_mask; 165 }; 166 167 struct vpd_params { 168 unsigned int cclk; 169 }; 170 171 struct pci_params { 172 uint16_t vendor_id; 173 uint16_t device_id; 174 uint32_t vpd_cap_addr; 175 uint16_t speed; 176 uint8_t width; 177 }; 178 179 /* 180 * Firmware device log. 181 */ 182 struct devlog_params { 183 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 184 u32 start; /* start of log in firmware memory */ 185 u32 size; /* size of log */ 186 }; 187 188 struct arch_specific_params { 189 u8 nchan; 190 u8 cng_ch_bits_log; /* congestion channel map bits width */ 191 u16 mps_rplc_size; 192 u16 vfcount; 193 u32 sge_fl_db; 194 u16 mps_tcam_size; 195 }; 196 197 /* 198 * Global Receive Side Scaling (RSS) parameters in host-native format. 199 */ 200 struct rss_params { 201 unsigned int mode; /* RSS mode */ 202 union { 203 struct { 204 uint synmapen:1; /* SYN Map Enable */ 205 uint syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */ 206 uint syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */ 207 uint syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */ 208 uint syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */ 209 uint ofdmapen:1; /* Offload Map Enable */ 210 uint tnlmapen:1; /* Tunnel Map Enable */ 211 uint tnlalllookup:1; /* Tunnel All Lookup */ 212 uint hashtoeplitz:1; /* use Toeplitz hash */ 213 } basicvirtual; 214 } u; 215 }; 216 217 /* 218 * Maximum resources provisioned for a PCI PF. 219 */ 220 struct pf_resources { 221 unsigned int neq; /* N egress Qs */ 222 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 223 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 224 }; 225 226 /* 227 * Maximum resources provisioned for a PCI VF. 228 */ 229 struct vf_resources { 230 unsigned int nvi; /* N virtual interfaces */ 231 unsigned int neq; /* N egress Qs */ 232 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 233 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 234 unsigned int niq; /* N ingress Qs */ 235 unsigned int tc; /* PCI-E traffic class */ 236 unsigned int pmask; /* port access rights mask */ 237 unsigned int nexactf; /* N exact MPS filters */ 238 unsigned int r_caps; /* read capabilities */ 239 unsigned int wx_caps; /* write/execute capabilities */ 240 }; 241 242 struct adapter_params { 243 struct sge_params sge; 244 struct tp_params tp; 245 struct vpd_params vpd; 246 struct pci_params pci; 247 struct devlog_params devlog; 248 struct rss_params rss; 249 struct pf_resources pfres; 250 struct vf_resources vfres; 251 enum pcie_memwin drv_memwin; 252 253 unsigned int sf_size; /* serial flash size in bytes */ 254 unsigned int sf_nsec; /* # of flash sectors */ 255 256 unsigned int fw_vers; 257 unsigned int bs_vers; 258 unsigned int tp_vers; 259 unsigned int er_vers; 260 261 unsigned short mtus[NMTUS]; 262 unsigned short a_wnd[NCCTRL_WIN]; 263 unsigned short b_wnd[NCCTRL_WIN]; 264 265 unsigned int mc_size; /* MC memory size */ 266 unsigned int cim_la_size; 267 268 unsigned char nports; /* # of ethernet ports */ 269 unsigned char portvec; 270 271 unsigned char hash_filter; 272 273 enum chip_type chip; /* chip code */ 274 struct arch_specific_params arch; /* chip specific params */ 275 276 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 277 u8 fw_caps_support; /* 32-bit Port Capabilities */ 278 u8 filter2_wr_support; /* FW support for FILTER2_WR */ 279 u32 viid_smt_extn_support:1; /* FW returns vin and smt index */ 280 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ 281 }; 282 283 /* Firmware Port Capabilities types. 284 */ 285 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 286 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 287 288 enum fw_caps { 289 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 290 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 291 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 292 }; 293 294 struct link_config { 295 fw_port_cap32_t pcaps; /* link capabilities */ 296 fw_port_cap32_t acaps; /* advertised capabilities */ 297 298 u32 requested_speed; /* speed (Mb/s) user has requested */ 299 u32 speed; /* actual link speed (Mb/s) */ 300 301 enum cc_pause requested_fc; /* flow control user has requested */ 302 enum cc_pause fc; /* actual link flow control */ 303 304 enum cc_fec auto_fec; /* Forward Error Correction 305 * "automatic" (IEEE 802.3) 306 */ 307 enum cc_fec requested_fec; /* Forward Error Correction requested */ 308 enum cc_fec fec; /* Forward Error Correction actual */ 309 310 unsigned char autoneg; /* autonegotiating? */ 311 312 unsigned char link_ok; /* link up? */ 313 unsigned char link_down_rc; /* link down reason */ 314 }; 315 316 #include "adapter.h" 317 318 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 319 u32 val); 320 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 321 int polarity, 322 int attempts, int delay, u32 *valp); 323 324 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 325 int polarity, int attempts, int delay) 326 { 327 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 328 delay, NULL); 329 } 330 331 static inline int is_pf4(struct adapter *adap) 332 { 333 return adap->pf == 4; 334 } 335 336 #define for_each_port(adapter, iter) \ 337 for (iter = 0; iter < (adapter)->params.nports; ++iter) 338 339 static inline int is_hashfilter(const struct adapter *adap) 340 { 341 return adap->params.hash_filter; 342 } 343 344 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 345 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 346 unsigned int mask, unsigned int val); 347 void t4_intr_enable(struct adapter *adapter); 348 void t4_intr_disable(struct adapter *adapter); 349 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 350 struct link_config *lc); 351 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 352 const unsigned short *alpha, const unsigned short *beta); 353 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 354 enum dev_master master, enum dev_state *state); 355 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 356 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 357 int t4vf_fw_reset(struct adapter *adap); 358 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 359 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 360 int t4_fl_pkt_align(struct adapter *adap); 361 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2); 362 int t4vf_get_vfres(struct adapter *adap); 363 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 364 unsigned int cache_line_size, 365 enum chip_type chip_compat); 366 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 367 unsigned int cache_line_size); 368 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 369 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 370 unsigned int vf, unsigned int nparams, const u32 *params, 371 u32 *val); 372 int t4vf_query_params(struct adapter *adap, unsigned int nparams, 373 const u32 *params, u32 *vals); 374 int t4vf_get_dev_params(struct adapter *adap); 375 int t4vf_get_vpd_params(struct adapter *adap); 376 int t4vf_get_rss_glb_config(struct adapter *adap); 377 int t4vf_set_params(struct adapter *adapter, unsigned int nparams, 378 const u32 *params, const u32 *vals); 379 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 380 unsigned int pf, unsigned int vf, 381 unsigned int nparams, const u32 *params, 382 const u32 *val, int timeout); 383 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 384 unsigned int vf, unsigned int nparams, const u32 *params, 385 const u32 *val); 386 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 387 unsigned int port, unsigned int pf, unsigned int vf, 388 unsigned int nmac, u8 *mac, unsigned int *rss_size, 389 unsigned int portfunc, unsigned int idstype, 390 u8 *vivld, u8 *vin); 391 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 392 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 393 unsigned int *rss_size, u8 *vivild, u8 *vin); 394 int t4_free_vi(struct adapter *adap, unsigned int mbox, 395 unsigned int pf, unsigned int vf, 396 unsigned int viid); 397 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 398 int mtu, int promisc, int all_multi, int bcast, int vlanex, 399 bool sleep_ok); 400 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 401 const u8 *addr, const u8 *mask, unsigned int idx, 402 u8 lookup_type, u8 port_id, bool sleep_ok); 403 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 404 const u8 *addr, const u8 *mask, unsigned int idx, 405 u8 lookup_type, u8 port_id, bool sleep_ok); 406 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 407 int idx, const u8 *addr, bool persist, bool add_smt); 408 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 409 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 410 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 411 bool rx_en, bool tx_en); 412 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 413 unsigned int pf, unsigned int vf, unsigned int iqid, 414 unsigned int fl0id, unsigned int fl1id); 415 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 416 unsigned int vf, unsigned int iqtype, unsigned int iqid, 417 unsigned int fl0id, unsigned int fl1id); 418 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 419 unsigned int vf, unsigned int eqid); 420 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 421 unsigned int vf, unsigned int eqid); 422 423 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 424 { 425 return adap->params.vpd.cclk / 1000; 426 } 427 428 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 429 unsigned int us) 430 { 431 return (us * adap->params.vpd.cclk) / 1000; 432 } 433 434 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 435 unsigned int ticks) 436 { 437 /* add Core Clock / 2 to round ticks to nearest uS */ 438 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 439 adapter->params.vpd.cclk); 440 } 441 442 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 443 int size, void *rpl, bool sleep_ok, int timeout); 444 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 445 const void __attribute__((__may_alias__)) *cmd, int size, 446 void *rpl, bool sleep_ok); 447 448 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 449 const void *cmd, int size, void *rpl, 450 int timeout) 451 { 452 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 453 timeout); 454 } 455 456 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 457 458 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 459 int size, void *rpl) 460 { 461 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 462 } 463 464 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 465 int size, void *rpl) 466 { 467 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 468 } 469 470 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); 471 472 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, 473 int size, void *rpl) 474 { 475 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); 476 } 477 478 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, 479 int size, void *rpl) 480 { 481 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); 482 } 483 484 485 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 486 unsigned int data_reg, u32 *vals, unsigned int nregs, 487 unsigned int start_idx); 488 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 489 unsigned int data_reg, const u32 *vals, 490 unsigned int nregs, unsigned int start_idx); 491 492 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 493 int t4_get_pfres(struct adapter *adapter); 494 int t4_read_flash(struct adapter *adapter, unsigned int addr, 495 unsigned int nwords, u32 *data, int byte_oriented); 496 int t4_flash_cfg_addr(struct adapter *adapter); 497 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx); 498 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx); 499 const char *t4_get_port_type_description(enum fw_port_type port_type); 500 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 501 void t4vf_get_port_stats(struct adapter *adapter, int pidx, 502 struct port_stats *p); 503 void t4_get_port_stats_offset(struct adapter *adap, int idx, 504 struct port_stats *stats, 505 struct port_stats *offset); 506 void t4_clr_port_stats(struct adapter *adap, int idx); 507 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps, 508 fw_port_cap32_t acaps); 509 void t4_reset_link_config(struct adapter *adap, int idx); 510 int t4_get_version_info(struct adapter *adapter); 511 void t4_dump_version_info(struct adapter *adapter); 512 int t4_get_flash_params(struct adapter *adapter); 513 int t4_get_chip_type(struct adapter *adap, int ver); 514 int t4_prep_adapter(struct adapter *adapter); 515 int t4vf_prep_adapter(struct adapter *adapter); 516 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 517 int t4vf_port_init(struct adapter *adap); 518 int t4_init_rss_mode(struct adapter *adap, int mbox); 519 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 520 int start, int n, const u16 *rspq, unsigned int nrspq); 521 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 522 unsigned int flags, unsigned int defq); 523 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 524 u64 *flags, unsigned int *defq); 525 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 526 unsigned int start_index, unsigned int rw); 527 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 528 void t4_read_rss_key(struct adapter *adap, u32 *key); 529 530 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 531 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 532 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset, 533 unsigned int *pbar2_qid); 534 535 int t4_init_sge_params(struct adapter *adapter); 536 int t4_init_tp_params(struct adapter *adap); 537 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 538 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 539 unsigned int t4_get_regs_len(struct adapter *adap); 540 unsigned int t4vf_get_pf_from_vf(struct adapter *adap); 541 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 542 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 543 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 544 int t4_seeprom_wp(struct adapter *adapter, int enable); 545 int t4_memory_rw_addr(struct adapter *adap, int win, 546 u32 addr, u32 len, void *hbuf, int dir); 547 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, 548 u32 len, void *hbuf, int dir); 549 static inline int t4_memory_rw(struct adapter *adap, int win, 550 int mtype, u32 maddr, u32 len, 551 void *hbuf, int dir) 552 { 553 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); 554 } 555 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16); 556 #endif /* __CHELSIO_COMMON_H */ 557