1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef __CHELSIO_COMMON_H 7 #define __CHELSIO_COMMON_H 8 9 #include "../cxgbe_compat.h" 10 #include "t4_hw.h" 11 #include "t4vf_hw.h" 12 #include "t4_chip_type.h" 13 #include "t4fw_interface.h" 14 15 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K 16 17 #define T4_MEMORY_WRITE 0 18 #define T4_MEMORY_READ 1 19 20 enum { 21 MAX_NPORTS = 4, /* max # of ports */ 22 }; 23 24 enum { 25 T5_REGMAP_SIZE = (332 * 1024), 26 }; 27 28 enum { 29 MEMWIN0_APERTURE = 2048, 30 MEMWIN0_BASE = 0x1b800, 31 }; 32 33 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 34 35 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 36 37 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 38 39 struct port_stats { 40 u64 tx_octets; /* total # of octets in good frames */ 41 u64 tx_frames; /* all good frames */ 42 u64 tx_bcast_frames; /* all broadcast frames */ 43 u64 tx_mcast_frames; /* all multicast frames */ 44 u64 tx_ucast_frames; /* all unicast frames */ 45 u64 tx_error_frames; /* all error frames */ 46 47 u64 tx_frames_64; /* # of Tx frames in a particular range */ 48 u64 tx_frames_65_127; 49 u64 tx_frames_128_255; 50 u64 tx_frames_256_511; 51 u64 tx_frames_512_1023; 52 u64 tx_frames_1024_1518; 53 u64 tx_frames_1519_max; 54 55 u64 tx_drop; /* # of dropped Tx frames */ 56 u64 tx_pause; /* # of transmitted pause frames */ 57 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 58 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 59 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 60 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 61 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 62 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 63 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 64 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 65 66 u64 rx_octets; /* total # of octets in good frames */ 67 u64 rx_frames; /* all good frames */ 68 u64 rx_bcast_frames; /* all broadcast frames */ 69 u64 rx_mcast_frames; /* all multicast frames */ 70 u64 rx_ucast_frames; /* all unicast frames */ 71 u64 rx_too_long; /* # of frames exceeding MTU */ 72 u64 rx_jabber; /* # of jabber frames */ 73 u64 rx_fcs_err; /* # of received frames with bad FCS */ 74 u64 rx_len_err; /* # of received frames with length error */ 75 u64 rx_symbol_err; /* symbol errors */ 76 u64 rx_runt; /* # of short frames */ 77 78 u64 rx_frames_64; /* # of Rx frames in a particular range */ 79 u64 rx_frames_65_127; 80 u64 rx_frames_128_255; 81 u64 rx_frames_256_511; 82 u64 rx_frames_512_1023; 83 u64 rx_frames_1024_1518; 84 u64 rx_frames_1519_max; 85 86 u64 rx_pause; /* # of received pause frames */ 87 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 88 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 89 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 90 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 91 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 92 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 93 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 94 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 95 96 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 97 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 98 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 99 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 100 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 101 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 102 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 103 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 104 }; 105 106 struct sge_params { 107 u32 hps; /* host page size for our PF/VF */ 108 u32 eq_qpp; /* egress queues/page for our PF/VF */ 109 u32 iq_qpp; /* egress queues/page for our PF/VF */ 110 }; 111 112 struct tp_params { 113 unsigned int ntxchan; /* # of Tx channels */ 114 unsigned int tre; /* log2 of core clocks per TP tick */ 115 unsigned int dack_re; /* DACK timer resolution */ 116 unsigned int la_mask; /* what events are recorded by TP LA */ 117 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 118 119 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 120 u32 filter_mask; 121 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 122 123 /* cached TP_OUT_CONFIG compressed error vector 124 * and passing outer header info for encapsulated packets. 125 */ 126 int rx_pkt_encap; 127 128 /* 129 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 130 * subset of the set of fields which may be present in the Compressed 131 * Filter Tuple portion of filters and TCP TCB connections. The 132 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 133 * Since a variable number of fields may or may not be present, their 134 * shifted field positions within the Compressed Filter Tuple may 135 * vary, or not even be present if the field isn't selected in 136 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 137 * places we store their offsets here, or a -1 if the field isn't 138 * present. 139 */ 140 int vlan_shift; 141 int vnic_shift; 142 int port_shift; 143 int protocol_shift; 144 int ethertype_shift; 145 int macmatch_shift; 146 int tos_shift; 147 148 u64 hash_filter_mask; 149 }; 150 151 struct vpd_params { 152 unsigned int cclk; 153 }; 154 155 struct pci_params { 156 uint16_t vendor_id; 157 uint16_t device_id; 158 uint32_t vpd_cap_addr; 159 uint16_t speed; 160 uint8_t width; 161 }; 162 163 /* 164 * Firmware device log. 165 */ 166 struct devlog_params { 167 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 168 u32 start; /* start of log in firmware memory */ 169 u32 size; /* size of log */ 170 }; 171 172 struct arch_specific_params { 173 u8 nchan; 174 u8 cng_ch_bits_log; /* congestion channel map bits width */ 175 u16 mps_rplc_size; 176 u16 vfcount; 177 u32 sge_fl_db; 178 u16 mps_tcam_size; 179 }; 180 181 /* 182 * Global Receive Side Scaling (RSS) parameters in host-native format. 183 */ 184 struct rss_params { 185 unsigned int mode; /* RSS mode */ 186 union { 187 struct { 188 unsigned int synmapen:1; /* SYN Map Enable */ 189 unsigned int syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */ 190 unsigned int syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */ 191 unsigned int syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */ 192 unsigned int syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */ 193 unsigned int ofdmapen:1; /* Offload Map Enable */ 194 unsigned int tnlmapen:1; /* Tunnel Map Enable */ 195 unsigned int tnlalllookup:1; /* Tunnel All Lookup */ 196 unsigned int hashtoeplitz:1; /* use Toeplitz hash */ 197 } basicvirtual; 198 } u; 199 }; 200 201 /* 202 * Maximum resources provisioned for a PCI PF. 203 */ 204 struct pf_resources { 205 unsigned int neq; /* N egress Qs */ 206 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 207 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 208 }; 209 210 /* 211 * Maximum resources provisioned for a PCI VF. 212 */ 213 struct vf_resources { 214 unsigned int nvi; /* N virtual interfaces */ 215 unsigned int neq; /* N egress Qs */ 216 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 217 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 218 unsigned int niq; /* N ingress Qs */ 219 unsigned int tc; /* PCI-E traffic class */ 220 unsigned int pmask; /* port access rights mask */ 221 unsigned int nexactf; /* N exact MPS filters */ 222 unsigned int r_caps; /* read capabilities */ 223 unsigned int wx_caps; /* write/execute capabilities */ 224 }; 225 226 struct adapter_params { 227 struct sge_params sge; 228 struct tp_params tp; 229 struct vpd_params vpd; 230 struct pci_params pci; 231 struct devlog_params devlog; 232 struct rss_params rss; 233 struct pf_resources pfres; 234 struct vf_resources vfres; 235 enum pcie_memwin drv_memwin; 236 237 unsigned int sf_size; /* serial flash size in bytes */ 238 unsigned int sf_nsec; /* # of flash sectors */ 239 240 unsigned int fw_vers; 241 unsigned int bs_vers; 242 unsigned int tp_vers; 243 unsigned int er_vers; 244 245 unsigned short mtus[NMTUS]; 246 unsigned short a_wnd[NCCTRL_WIN]; 247 unsigned short b_wnd[NCCTRL_WIN]; 248 249 unsigned int mc_size; /* MC memory size */ 250 unsigned int cim_la_size; 251 252 unsigned char nports; /* # of ethernet ports */ 253 unsigned char portvec; 254 255 unsigned char hash_filter; 256 257 enum chip_type chip; /* chip code */ 258 struct arch_specific_params arch; /* chip specific params */ 259 260 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 261 u8 filter2_wr_support; /* FW support for FILTER2_WR */ 262 u32 viid_smt_extn_support:1; /* FW returns vin and smt index */ 263 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ 264 u8 vi_enable_rx; /* FW support for enable/disable VI Rx at runtime */ 265 266 u16 rawf_start; /* FW supports RAW MAC match-all filters */ 267 u16 rawf_size; 268 }; 269 270 /* Firmware Port Capabilities types. 271 */ 272 struct link_config { 273 u32 pcaps; /* Physically supported link caps */ 274 u32 acaps; /* Advertised link caps */ 275 276 u32 link_caps; /* Current link caps */ 277 u32 admin_caps; /* Admin configured link caps */ 278 279 u8 mdio_addr; /* Address of the PHY */ 280 u8 port_type; /* Firmware port type */ 281 u8 mod_type; /* Firmware module type */ 282 283 u8 link_ok; /* Link up? */ 284 u8 link_down_rc; /* Link down reason */ 285 }; 286 287 #include "adapter.h" 288 289 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 290 u32 val); 291 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 292 int polarity, 293 int attempts, int delay, u32 *valp); 294 295 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 296 int polarity, int attempts, int delay) 297 { 298 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 299 delay, NULL); 300 } 301 302 static inline int is_pf4(struct adapter *adap) 303 { 304 return adap->pf == 4; 305 } 306 307 #define for_each_port(adapter, iter) \ 308 for (iter = 0; iter < (adapter)->params.nports; ++iter) 309 310 static inline int is_hashfilter(const struct adapter *adap) 311 { 312 return adap->params.hash_filter; 313 } 314 315 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 316 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 317 unsigned int mask, unsigned int val); 318 void t4_intr_enable(struct adapter *adapter); 319 void t4_intr_disable(struct adapter *adapter); 320 int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok); 321 static inline int t4_link_l1cfg(struct port_info *pi, u32 caps) 322 { 323 return t4_link_l1cfg_core(pi, caps, true); 324 } 325 326 static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps) 327 { 328 return t4_link_l1cfg_core(pi, caps, false); 329 } 330 331 int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps); 332 int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx, 333 u8 pause_rx, u32 *new_caps); 334 int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser, 335 u8 fec_none, u32 *new_caps); 336 unsigned int t4_fwcap_to_speed(u32 caps); 337 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 338 const unsigned short *alpha, const unsigned short *beta); 339 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 340 enum dev_master master, enum dev_state *state); 341 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 342 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 343 int t4vf_fw_reset(struct adapter *adap); 344 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 345 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 346 int t4vf_get_vfres(struct adapter *adap); 347 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 348 unsigned int cache_line_size, 349 enum chip_type chip_compat); 350 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 351 unsigned int cache_line_size); 352 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 353 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 354 unsigned int vf, unsigned int nparams, const u32 *params, 355 u32 *val); 356 int t4vf_query_params(struct adapter *adap, unsigned int nparams, 357 const u32 *params, u32 *vals); 358 int t4vf_get_dev_params(struct adapter *adap); 359 int t4vf_get_vpd_params(struct adapter *adap); 360 int t4vf_get_rss_glb_config(struct adapter *adap); 361 int t4vf_set_params(struct adapter *adapter, unsigned int nparams, 362 const u32 *params, const u32 *vals); 363 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 364 unsigned int pf, unsigned int vf, 365 unsigned int nparams, const u32 *params, 366 const u32 *val, int timeout); 367 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 368 unsigned int vf, unsigned int nparams, const u32 *params, 369 const u32 *val); 370 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 371 unsigned int port, unsigned int pf, unsigned int vf, 372 unsigned int nmac, u8 *mac, unsigned int *rss_size, 373 unsigned int portfunc, unsigned int idstype, 374 u8 *vivld, u8 *vin); 375 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 376 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 377 unsigned int *rss_size, u8 *vivild, u8 *vin); 378 int t4_free_vi(struct adapter *adap, unsigned int mbox, 379 unsigned int pf, unsigned int vf, 380 unsigned int viid); 381 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 382 int mtu, int promisc, int all_multi, int bcast, int vlanex, 383 bool sleep_ok); 384 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 385 const u8 *addr, const u8 *mask, unsigned int idx, 386 u8 lookup_type, u8 port_id, bool sleep_ok); 387 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 388 const u8 *addr, const u8 *mask, unsigned int idx, 389 u8 lookup_type, u8 port_id, bool sleep_ok); 390 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 391 int idx, const u8 *addr, bool persist, bool add_smt); 392 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 393 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 394 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 395 bool rx_en, bool tx_en); 396 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 397 unsigned int pf, unsigned int vf, unsigned int iqid, 398 unsigned int fl0id, unsigned int fl1id); 399 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 400 unsigned int vf, unsigned int iqtype, unsigned int iqid, 401 unsigned int fl0id, unsigned int fl1id); 402 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 403 unsigned int vf, unsigned int eqid); 404 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 405 unsigned int vf, unsigned int eqid); 406 407 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 408 { 409 return adap->params.vpd.cclk / 1000; 410 } 411 412 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 413 unsigned int us) 414 { 415 return (us * adap->params.vpd.cclk) / 1000; 416 } 417 418 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 419 unsigned int ticks) 420 { 421 /* add Core Clock / 2 to round ticks to nearest uS */ 422 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 423 adapter->params.vpd.cclk); 424 } 425 426 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 427 int size, void *rpl, bool sleep_ok, int timeout); 428 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 429 const void __attribute__((__may_alias__)) *cmd, int size, 430 void *rpl, bool sleep_ok); 431 432 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 433 const void *cmd, int size, void *rpl, 434 int timeout) 435 { 436 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 437 timeout); 438 } 439 440 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 441 442 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 443 int size, void *rpl) 444 { 445 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 446 } 447 448 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 449 int size, void *rpl) 450 { 451 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 452 } 453 454 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); 455 456 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, 457 int size, void *rpl) 458 { 459 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); 460 } 461 462 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, 463 int size, void *rpl) 464 { 465 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); 466 } 467 468 469 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 470 unsigned int data_reg, u32 *vals, unsigned int nregs, 471 unsigned int start_idx); 472 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 473 unsigned int data_reg, const u32 *vals, 474 unsigned int nregs, unsigned int start_idx); 475 476 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 477 int t4_get_pfres(struct adapter *adapter); 478 int t4_read_flash(struct adapter *adapter, unsigned int addr, 479 unsigned int nwords, u32 *data, int byte_oriented); 480 int t4_flash_cfg_addr(struct adapter *adapter); 481 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx); 482 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx); 483 const char *t4_get_port_type_description(enum fw_port_type port_type); 484 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 485 void t4vf_get_port_stats(struct adapter *adapter, int pidx, 486 struct port_stats *p); 487 void t4_get_port_stats_offset(struct adapter *adap, int idx, 488 struct port_stats *stats, 489 struct port_stats *offset); 490 void t4_clr_port_stats(struct adapter *adap, int idx); 491 void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps, 492 u8 mdio_addr, u8 port_type, u8 mod_type); 493 void t4_reset_link_config(struct adapter *adap, int idx); 494 int t4_get_version_info(struct adapter *adapter); 495 void t4_dump_version_info(struct adapter *adapter); 496 int t4_get_flash_params(struct adapter *adapter); 497 int t4_get_chip_type(struct adapter *adap, int ver); 498 int t4_prep_adapter(struct adapter *adapter); 499 int t4vf_prep_adapter(struct adapter *adapter); 500 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 501 int t4vf_port_init(struct adapter *adap); 502 int t4_init_rss_mode(struct adapter *adap, int mbox); 503 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 504 int start, int n, const u16 *rspq, unsigned int nrspq); 505 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 506 unsigned int flags, unsigned int defq); 507 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 508 u64 *flags, unsigned int *defq); 509 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 510 unsigned int start_index, unsigned int rw); 511 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 512 void t4_read_rss_key(struct adapter *adap, u32 *key); 513 514 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 515 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 516 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset, 517 unsigned int *pbar2_qid); 518 519 int t4_init_sge_params(struct adapter *adapter); 520 int t4_init_tp_params(struct adapter *adap); 521 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 522 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 523 unsigned int t4_get_regs_len(struct adapter *adap); 524 unsigned int t4vf_get_pf_from_vf(struct adapter *adap); 525 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 526 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 527 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 528 int t4_seeprom_wp(struct adapter *adapter, int enable); 529 int t4_memory_rw_addr(struct adapter *adap, int win, 530 u32 addr, u32 len, void *hbuf, int dir); 531 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, 532 u32 len, void *hbuf, int dir); 533 static inline int t4_memory_rw(struct adapter *adap, int win, 534 int mtype, u32 maddr, u32 len, 535 void *hbuf, int dir) 536 { 537 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); 538 } 539 #endif /* __CHELSIO_COMMON_H */ 540