1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2017 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef __CHELSIO_COMMON_H 35 #define __CHELSIO_COMMON_H 36 37 #include "cxgbe_compat.h" 38 #include "t4_hw.h" 39 #include "t4_chip_type.h" 40 #include "t4fw_interface.h" 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K 47 48 enum { 49 MAX_NPORTS = 4, /* max # of ports */ 50 }; 51 52 enum { 53 T5_REGMAP_SIZE = (332 * 1024), 54 }; 55 56 enum { 57 MEMWIN0_APERTURE = 2048, 58 MEMWIN0_BASE = 0x1b800, 59 }; 60 61 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 62 63 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 64 65 enum { 66 PAUSE_RX = 1 << 0, 67 PAUSE_TX = 1 << 1, 68 PAUSE_AUTONEG = 1 << 2 69 }; 70 71 enum { 72 FEC_RS = 1 << 0, 73 FEC_BASER_RS = 1 << 1, 74 FEC_RESERVED = 1 << 2, 75 }; 76 77 struct port_stats { 78 u64 tx_octets; /* total # of octets in good frames */ 79 u64 tx_frames; /* all good frames */ 80 u64 tx_bcast_frames; /* all broadcast frames */ 81 u64 tx_mcast_frames; /* all multicast frames */ 82 u64 tx_ucast_frames; /* all unicast frames */ 83 u64 tx_error_frames; /* all error frames */ 84 85 u64 tx_frames_64; /* # of Tx frames in a particular range */ 86 u64 tx_frames_65_127; 87 u64 tx_frames_128_255; 88 u64 tx_frames_256_511; 89 u64 tx_frames_512_1023; 90 u64 tx_frames_1024_1518; 91 u64 tx_frames_1519_max; 92 93 u64 tx_drop; /* # of dropped Tx frames */ 94 u64 tx_pause; /* # of transmitted pause frames */ 95 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 96 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 97 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 98 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 99 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 100 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 101 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 102 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 103 104 u64 rx_octets; /* total # of octets in good frames */ 105 u64 rx_frames; /* all good frames */ 106 u64 rx_bcast_frames; /* all broadcast frames */ 107 u64 rx_mcast_frames; /* all multicast frames */ 108 u64 rx_ucast_frames; /* all unicast frames */ 109 u64 rx_too_long; /* # of frames exceeding MTU */ 110 u64 rx_jabber; /* # of jabber frames */ 111 u64 rx_fcs_err; /* # of received frames with bad FCS */ 112 u64 rx_len_err; /* # of received frames with length error */ 113 u64 rx_symbol_err; /* symbol errors */ 114 u64 rx_runt; /* # of short frames */ 115 116 u64 rx_frames_64; /* # of Rx frames in a particular range */ 117 u64 rx_frames_65_127; 118 u64 rx_frames_128_255; 119 u64 rx_frames_256_511; 120 u64 rx_frames_512_1023; 121 u64 rx_frames_1024_1518; 122 u64 rx_frames_1519_max; 123 124 u64 rx_pause; /* # of received pause frames */ 125 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 126 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 127 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 128 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 129 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 130 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 131 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 132 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 133 134 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 135 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 136 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 137 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 138 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 139 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 140 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 141 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 142 }; 143 144 struct sge_params { 145 u32 hps; /* host page size for our PF/VF */ 146 u32 eq_qpp; /* egress queues/page for our PF/VF */ 147 u32 iq_qpp; /* egress queues/page for our PF/VF */ 148 }; 149 150 struct tp_params { 151 unsigned int ntxchan; /* # of Tx channels */ 152 unsigned int tre; /* log2 of core clocks per TP tick */ 153 unsigned int dack_re; /* DACK timer resolution */ 154 unsigned int la_mask; /* what events are recorded by TP LA */ 155 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 156 157 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 158 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 159 160 /* cached TP_OUT_CONFIG compressed error vector 161 * and passing outer header info for encapsulated packets. 162 */ 163 int rx_pkt_encap; 164 165 /* 166 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 167 * subset of the set of fields which may be present in the Compressed 168 * Filter Tuple portion of filters and TCP TCB connections. The 169 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 170 * Since a variable number of fields may or may not be present, their 171 * shifted field positions within the Compressed Filter Tuple may 172 * vary, or not even be present if the field isn't selected in 173 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 174 * places we store their offsets here, or a -1 if the field isn't 175 * present. 176 */ 177 int vlan_shift; 178 int vnic_shift; 179 int port_shift; 180 int protocol_shift; 181 }; 182 183 struct vpd_params { 184 unsigned int cclk; 185 }; 186 187 struct pci_params { 188 uint16_t vendor_id; 189 uint16_t device_id; 190 uint32_t vpd_cap_addr; 191 uint16_t speed; 192 uint8_t width; 193 }; 194 195 /* 196 * Firmware device log. 197 */ 198 struct devlog_params { 199 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 200 u32 start; /* start of log in firmware memory */ 201 u32 size; /* size of log */ 202 }; 203 204 struct arch_specific_params { 205 u8 nchan; 206 u16 mps_rplc_size; 207 u16 vfcount; 208 u32 sge_fl_db; 209 u16 mps_tcam_size; 210 }; 211 212 struct adapter_params { 213 struct sge_params sge; 214 struct tp_params tp; 215 struct vpd_params vpd; 216 struct pci_params pci; 217 struct devlog_params devlog; 218 enum pcie_memwin drv_memwin; 219 220 unsigned int sf_size; /* serial flash size in bytes */ 221 unsigned int sf_nsec; /* # of flash sectors */ 222 223 unsigned int fw_vers; 224 unsigned int bs_vers; 225 unsigned int tp_vers; 226 unsigned int er_vers; 227 228 unsigned short mtus[NMTUS]; 229 unsigned short a_wnd[NCCTRL_WIN]; 230 unsigned short b_wnd[NCCTRL_WIN]; 231 232 unsigned int mc_size; /* MC memory size */ 233 unsigned int cim_la_size; 234 235 unsigned char nports; /* # of ethernet ports */ 236 unsigned char portvec; 237 238 enum chip_type chip; /* chip code */ 239 struct arch_specific_params arch; /* chip specific params */ 240 241 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 242 }; 243 244 struct link_config { 245 unsigned short supported; /* link capabilities */ 246 unsigned short advertising; /* advertised capabilities */ 247 unsigned int requested_speed; /* speed user has requested */ 248 unsigned int speed; /* actual link speed */ 249 unsigned char requested_fc; /* flow control user has requested */ 250 unsigned char fc; /* actual link flow control */ 251 unsigned char requested_fec; /* Forward Error Correction user */ 252 unsigned char fec; /* has requested and actual FEC */ 253 unsigned char autoneg; /* autonegotiating? */ 254 unsigned char link_ok; /* link up? */ 255 }; 256 257 #include "adapter.h" 258 259 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 260 u32 val); 261 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 262 int polarity, 263 int attempts, int delay, u32 *valp); 264 265 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 266 int polarity, int attempts, int delay) 267 { 268 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 269 delay, NULL); 270 } 271 272 #define for_each_port(adapter, iter) \ 273 for (iter = 0; iter < (adapter)->params.nports; ++iter) 274 275 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 276 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 277 unsigned int mask, unsigned int val); 278 void t4_intr_enable(struct adapter *adapter); 279 void t4_intr_disable(struct adapter *adapter); 280 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 281 struct link_config *lc); 282 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 283 const unsigned short *alpha, const unsigned short *beta); 284 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 285 enum dev_master master, enum dev_state *state); 286 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 287 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 288 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 289 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 290 int t4_fl_pkt_align(struct adapter *adap); 291 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 292 unsigned int cache_line_size, 293 enum chip_type chip_compat); 294 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 295 unsigned int cache_line_size); 296 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 297 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 298 unsigned int vf, unsigned int nparams, const u32 *params, 299 u32 *val); 300 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 301 unsigned int pf, unsigned int vf, 302 unsigned int nparams, const u32 *params, 303 const u32 *val, int timeout); 304 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 305 unsigned int vf, unsigned int nparams, const u32 *params, 306 const u32 *val); 307 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 308 unsigned int port, unsigned int pf, unsigned int vf, 309 unsigned int nmac, u8 *mac, unsigned int *rss_size, 310 unsigned int portfunc, unsigned int idstype); 311 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 312 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 313 unsigned int *rss_size); 314 int t4_free_vi(struct adapter *adap, unsigned int mbox, 315 unsigned int pf, unsigned int vf, 316 unsigned int viid); 317 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 318 int mtu, int promisc, int all_multi, int bcast, int vlanex, 319 bool sleep_ok); 320 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 321 int idx, const u8 *addr, bool persist, bool add_smt); 322 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 323 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 324 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 325 bool rx_en, bool tx_en); 326 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 327 unsigned int pf, unsigned int vf, unsigned int iqid, 328 unsigned int fl0id, unsigned int fl1id); 329 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 330 unsigned int vf, unsigned int iqtype, unsigned int iqid, 331 unsigned int fl0id, unsigned int fl1id); 332 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 333 unsigned int vf, unsigned int eqid); 334 335 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 336 { 337 return adap->params.vpd.cclk / 1000; 338 } 339 340 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 341 unsigned int us) 342 { 343 return (us * adap->params.vpd.cclk) / 1000; 344 } 345 346 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 347 unsigned int ticks) 348 { 349 /* add Core Clock / 2 to round ticks to nearest uS */ 350 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 351 adapter->params.vpd.cclk); 352 } 353 354 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 355 int size, void *rpl, bool sleep_ok, int timeout); 356 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 357 const void __attribute__((__may_alias__)) *cmd, int size, 358 void *rpl, bool sleep_ok); 359 360 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 361 const void *cmd, int size, void *rpl, 362 int timeout) 363 { 364 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 365 timeout); 366 } 367 368 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 369 370 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 371 int size, void *rpl) 372 { 373 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 374 } 375 376 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 377 int size, void *rpl) 378 { 379 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 380 } 381 382 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 383 unsigned int data_reg, u32 *vals, unsigned int nregs, 384 unsigned int start_idx); 385 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 386 unsigned int data_reg, const u32 *vals, 387 unsigned int nregs, unsigned int start_idx); 388 389 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 390 int t4_read_flash(struct adapter *adapter, unsigned int addr, 391 unsigned int nwords, u32 *data, int byte_oriented); 392 int t4_flash_cfg_addr(struct adapter *adapter); 393 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx); 394 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx); 395 const char *t4_get_port_type_description(enum fw_port_type port_type); 396 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 397 void t4_get_port_stats_offset(struct adapter *adap, int idx, 398 struct port_stats *stats, 399 struct port_stats *offset); 400 void t4_clr_port_stats(struct adapter *adap, int idx); 401 void t4_reset_link_config(struct adapter *adap, int idx); 402 int t4_get_version_info(struct adapter *adapter); 403 void t4_dump_version_info(struct adapter *adapter); 404 int t4_get_flash_params(struct adapter *adapter); 405 int t4_get_chip_type(struct adapter *adap, int ver); 406 int t4_prep_adapter(struct adapter *adapter); 407 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 408 int t4_init_rss_mode(struct adapter *adap, int mbox); 409 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 410 int start, int n, const u16 *rspq, unsigned int nrspq); 411 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 412 unsigned int flags, unsigned int defq); 413 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 414 u64 *flags, unsigned int *defq); 415 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 416 unsigned int start_index, unsigned int rw); 417 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 418 void t4_read_rss_key(struct adapter *adap, u32 *key); 419 420 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 421 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 422 unsigned int qtype, u64 *pbar2_qoffset, 423 unsigned int *pbar2_qid); 424 425 int t4_init_sge_params(struct adapter *adapter); 426 int t4_init_tp_params(struct adapter *adap); 427 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 428 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 429 unsigned int t4_get_regs_len(struct adapter *adap); 430 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 431 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 432 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 433 int t4_seeprom_wp(struct adapter *adapter, int enable); 434 #endif /* __CHELSIO_COMMON_H */ 435