1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef __CHELSIO_COMMON_H 7 #define __CHELSIO_COMMON_H 8 9 #include "../cxgbe_compat.h" 10 #include "t4_hw.h" 11 #include "t4vf_hw.h" 12 #include "t4_chip_type.h" 13 #include "t4fw_interface.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K 20 21 #define T4_MEMORY_WRITE 0 22 #define T4_MEMORY_READ 1 23 24 enum { 25 MAX_NPORTS = 4, /* max # of ports */ 26 }; 27 28 enum { 29 T5_REGMAP_SIZE = (332 * 1024), 30 }; 31 32 enum { 33 MEMWIN0_APERTURE = 2048, 34 MEMWIN0_BASE = 0x1b800, 35 }; 36 37 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 38 39 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 40 41 enum cc_pause { 42 PAUSE_RX = 1 << 0, 43 PAUSE_TX = 1 << 1, 44 PAUSE_AUTONEG = 1 << 2 45 }; 46 47 enum cc_fec { 48 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 49 FEC_RS = 1 << 1, /* Reed-Solomon */ 50 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ 51 }; 52 53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55 struct port_stats { 56 u64 tx_octets; /* total # of octets in good frames */ 57 u64 tx_frames; /* all good frames */ 58 u64 tx_bcast_frames; /* all broadcast frames */ 59 u64 tx_mcast_frames; /* all multicast frames */ 60 u64 tx_ucast_frames; /* all unicast frames */ 61 u64 tx_error_frames; /* all error frames */ 62 63 u64 tx_frames_64; /* # of Tx frames in a particular range */ 64 u64 tx_frames_65_127; 65 u64 tx_frames_128_255; 66 u64 tx_frames_256_511; 67 u64 tx_frames_512_1023; 68 u64 tx_frames_1024_1518; 69 u64 tx_frames_1519_max; 70 71 u64 tx_drop; /* # of dropped Tx frames */ 72 u64 tx_pause; /* # of transmitted pause frames */ 73 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 74 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 75 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 76 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 77 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 78 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 79 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 80 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 81 82 u64 rx_octets; /* total # of octets in good frames */ 83 u64 rx_frames; /* all good frames */ 84 u64 rx_bcast_frames; /* all broadcast frames */ 85 u64 rx_mcast_frames; /* all multicast frames */ 86 u64 rx_ucast_frames; /* all unicast frames */ 87 u64 rx_too_long; /* # of frames exceeding MTU */ 88 u64 rx_jabber; /* # of jabber frames */ 89 u64 rx_fcs_err; /* # of received frames with bad FCS */ 90 u64 rx_len_err; /* # of received frames with length error */ 91 u64 rx_symbol_err; /* symbol errors */ 92 u64 rx_runt; /* # of short frames */ 93 94 u64 rx_frames_64; /* # of Rx frames in a particular range */ 95 u64 rx_frames_65_127; 96 u64 rx_frames_128_255; 97 u64 rx_frames_256_511; 98 u64 rx_frames_512_1023; 99 u64 rx_frames_1024_1518; 100 u64 rx_frames_1519_max; 101 102 u64 rx_pause; /* # of received pause frames */ 103 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 104 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 105 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 106 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 107 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 108 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 109 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 110 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 111 112 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 113 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 114 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 115 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 116 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 117 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 118 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 119 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 120 }; 121 122 struct sge_params { 123 u32 hps; /* host page size for our PF/VF */ 124 u32 eq_qpp; /* egress queues/page for our PF/VF */ 125 u32 iq_qpp; /* egress queues/page for our PF/VF */ 126 }; 127 128 struct tp_params { 129 unsigned int ntxchan; /* # of Tx channels */ 130 unsigned int tre; /* log2 of core clocks per TP tick */ 131 unsigned int dack_re; /* DACK timer resolution */ 132 unsigned int la_mask; /* what events are recorded by TP LA */ 133 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 134 135 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 136 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 137 138 /* cached TP_OUT_CONFIG compressed error vector 139 * and passing outer header info for encapsulated packets. 140 */ 141 int rx_pkt_encap; 142 143 /* 144 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 145 * subset of the set of fields which may be present in the Compressed 146 * Filter Tuple portion of filters and TCP TCB connections. The 147 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 148 * Since a variable number of fields may or may not be present, their 149 * shifted field positions within the Compressed Filter Tuple may 150 * vary, or not even be present if the field isn't selected in 151 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 152 * places we store their offsets here, or a -1 if the field isn't 153 * present. 154 */ 155 int vlan_shift; 156 int vnic_shift; 157 int port_shift; 158 int protocol_shift; 159 int ethertype_shift; 160 int macmatch_shift; 161 162 u64 hash_filter_mask; 163 }; 164 165 struct vpd_params { 166 unsigned int cclk; 167 }; 168 169 struct pci_params { 170 uint16_t vendor_id; 171 uint16_t device_id; 172 uint32_t vpd_cap_addr; 173 uint16_t speed; 174 uint8_t width; 175 }; 176 177 /* 178 * Firmware device log. 179 */ 180 struct devlog_params { 181 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 182 u32 start; /* start of log in firmware memory */ 183 u32 size; /* size of log */ 184 }; 185 186 struct arch_specific_params { 187 u8 nchan; 188 u16 mps_rplc_size; 189 u16 vfcount; 190 u32 sge_fl_db; 191 u16 mps_tcam_size; 192 }; 193 194 /* 195 * Global Receive Side Scaling (RSS) parameters in host-native format. 196 */ 197 struct rss_params { 198 unsigned int mode; /* RSS mode */ 199 union { 200 struct { 201 uint synmapen:1; /* SYN Map Enable */ 202 uint syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */ 203 uint syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */ 204 uint syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */ 205 uint syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */ 206 uint ofdmapen:1; /* Offload Map Enable */ 207 uint tnlmapen:1; /* Tunnel Map Enable */ 208 uint tnlalllookup:1; /* Tunnel All Lookup */ 209 uint hashtoeplitz:1; /* use Toeplitz hash */ 210 } basicvirtual; 211 } u; 212 }; 213 214 /* 215 * Maximum resources provisioned for a PCI PF. 216 */ 217 struct pf_resources { 218 unsigned int neq; /* N egress Qs */ 219 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 220 }; 221 222 /* 223 * Maximum resources provisioned for a PCI VF. 224 */ 225 struct vf_resources { 226 unsigned int nvi; /* N virtual interfaces */ 227 unsigned int neq; /* N egress Qs */ 228 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 229 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 230 unsigned int niq; /* N ingress Qs */ 231 unsigned int tc; /* PCI-E traffic class */ 232 unsigned int pmask; /* port access rights mask */ 233 unsigned int nexactf; /* N exact MPS filters */ 234 unsigned int r_caps; /* read capabilities */ 235 unsigned int wx_caps; /* write/execute capabilities */ 236 }; 237 238 struct adapter_params { 239 struct sge_params sge; 240 struct tp_params tp; 241 struct vpd_params vpd; 242 struct pci_params pci; 243 struct devlog_params devlog; 244 struct rss_params rss; 245 struct pf_resources pfres; 246 struct vf_resources vfres; 247 enum pcie_memwin drv_memwin; 248 249 unsigned int sf_size; /* serial flash size in bytes */ 250 unsigned int sf_nsec; /* # of flash sectors */ 251 252 unsigned int fw_vers; 253 unsigned int bs_vers; 254 unsigned int tp_vers; 255 unsigned int er_vers; 256 257 unsigned short mtus[NMTUS]; 258 unsigned short a_wnd[NCCTRL_WIN]; 259 unsigned short b_wnd[NCCTRL_WIN]; 260 261 unsigned int mc_size; /* MC memory size */ 262 unsigned int cim_la_size; 263 264 unsigned char nports; /* # of ethernet ports */ 265 unsigned char portvec; 266 267 unsigned char hash_filter; 268 269 enum chip_type chip; /* chip code */ 270 struct arch_specific_params arch; /* chip specific params */ 271 272 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 273 u8 fw_caps_support; /* 32-bit Port Capabilities */ 274 u8 filter2_wr_support; /* FW support for FILTER2_WR */ 275 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ 276 }; 277 278 /* Firmware Port Capabilities types. 279 */ 280 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 281 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 282 283 enum fw_caps { 284 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 285 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 286 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 287 }; 288 289 struct link_config { 290 fw_port_cap32_t pcaps; /* link capabilities */ 291 fw_port_cap32_t acaps; /* advertised capabilities */ 292 293 u32 requested_speed; /* speed (Mb/s) user has requested */ 294 u32 speed; /* actual link speed (Mb/s) */ 295 296 enum cc_pause requested_fc; /* flow control user has requested */ 297 enum cc_pause fc; /* actual link flow control */ 298 299 enum cc_fec auto_fec; /* Forward Error Correction 300 * "automatic" (IEEE 802.3) 301 */ 302 enum cc_fec requested_fec; /* Forward Error Correction requested */ 303 enum cc_fec fec; /* Forward Error Correction actual */ 304 305 unsigned char autoneg; /* autonegotiating? */ 306 307 unsigned char link_ok; /* link up? */ 308 unsigned char link_down_rc; /* link down reason */ 309 }; 310 311 #include "adapter.h" 312 313 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 314 u32 val); 315 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 316 int polarity, 317 int attempts, int delay, u32 *valp); 318 319 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 320 int polarity, int attempts, int delay) 321 { 322 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 323 delay, NULL); 324 } 325 326 static inline int is_pf4(struct adapter *adap) 327 { 328 return adap->pf == 4; 329 } 330 331 #define for_each_port(adapter, iter) \ 332 for (iter = 0; iter < (adapter)->params.nports; ++iter) 333 334 static inline int is_hashfilter(const struct adapter *adap) 335 { 336 return adap->params.hash_filter; 337 } 338 339 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 340 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 341 unsigned int mask, unsigned int val); 342 void t4_intr_enable(struct adapter *adapter); 343 void t4_intr_disable(struct adapter *adapter); 344 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 345 struct link_config *lc); 346 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 347 const unsigned short *alpha, const unsigned short *beta); 348 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 349 enum dev_master master, enum dev_state *state); 350 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 351 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 352 int t4vf_fw_reset(struct adapter *adap); 353 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 354 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 355 int t4_fl_pkt_align(struct adapter *adap); 356 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2); 357 int t4vf_get_vfres(struct adapter *adap); 358 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 359 unsigned int cache_line_size, 360 enum chip_type chip_compat); 361 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 362 unsigned int cache_line_size); 363 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 364 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 365 unsigned int vf, unsigned int nparams, const u32 *params, 366 u32 *val); 367 int t4vf_query_params(struct adapter *adap, unsigned int nparams, 368 const u32 *params, u32 *vals); 369 int t4vf_get_dev_params(struct adapter *adap); 370 int t4vf_get_vpd_params(struct adapter *adap); 371 int t4vf_get_rss_glb_config(struct adapter *adap); 372 int t4vf_set_params(struct adapter *adapter, unsigned int nparams, 373 const u32 *params, const u32 *vals); 374 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 375 unsigned int pf, unsigned int vf, 376 unsigned int nparams, const u32 *params, 377 const u32 *val, int timeout); 378 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 379 unsigned int vf, unsigned int nparams, const u32 *params, 380 const u32 *val); 381 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 382 unsigned int port, unsigned int pf, unsigned int vf, 383 unsigned int nmac, u8 *mac, unsigned int *rss_size, 384 unsigned int portfunc, unsigned int idstype); 385 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 386 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 387 unsigned int *rss_size); 388 int t4_free_vi(struct adapter *adap, unsigned int mbox, 389 unsigned int pf, unsigned int vf, 390 unsigned int viid); 391 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 392 int mtu, int promisc, int all_multi, int bcast, int vlanex, 393 bool sleep_ok); 394 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 395 const u8 *addr, const u8 *mask, unsigned int idx, 396 u8 lookup_type, u8 port_id, bool sleep_ok); 397 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 398 const u8 *addr, const u8 *mask, unsigned int idx, 399 u8 lookup_type, u8 port_id, bool sleep_ok); 400 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 401 int idx, const u8 *addr, bool persist, bool add_smt); 402 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 403 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 404 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 405 bool rx_en, bool tx_en); 406 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 407 unsigned int pf, unsigned int vf, unsigned int iqid, 408 unsigned int fl0id, unsigned int fl1id); 409 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 410 unsigned int vf, unsigned int iqtype, unsigned int iqid, 411 unsigned int fl0id, unsigned int fl1id); 412 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 413 unsigned int vf, unsigned int eqid); 414 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 415 unsigned int vf, unsigned int eqid); 416 417 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 418 { 419 return adap->params.vpd.cclk / 1000; 420 } 421 422 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 423 unsigned int us) 424 { 425 return (us * adap->params.vpd.cclk) / 1000; 426 } 427 428 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 429 unsigned int ticks) 430 { 431 /* add Core Clock / 2 to round ticks to nearest uS */ 432 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 433 adapter->params.vpd.cclk); 434 } 435 436 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 437 int size, void *rpl, bool sleep_ok, int timeout); 438 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 439 const void __attribute__((__may_alias__)) *cmd, int size, 440 void *rpl, bool sleep_ok); 441 442 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 443 const void *cmd, int size, void *rpl, 444 int timeout) 445 { 446 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 447 timeout); 448 } 449 450 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 451 452 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 453 int size, void *rpl) 454 { 455 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 456 } 457 458 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 459 int size, void *rpl) 460 { 461 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 462 } 463 464 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); 465 466 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, 467 int size, void *rpl) 468 { 469 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); 470 } 471 472 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, 473 int size, void *rpl) 474 { 475 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); 476 } 477 478 479 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 480 unsigned int data_reg, u32 *vals, unsigned int nregs, 481 unsigned int start_idx); 482 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 483 unsigned int data_reg, const u32 *vals, 484 unsigned int nregs, unsigned int start_idx); 485 486 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 487 int t4_get_pfres(struct adapter *adapter); 488 int t4_read_flash(struct adapter *adapter, unsigned int addr, 489 unsigned int nwords, u32 *data, int byte_oriented); 490 int t4_flash_cfg_addr(struct adapter *adapter); 491 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx); 492 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx); 493 const char *t4_get_port_type_description(enum fw_port_type port_type); 494 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 495 void t4vf_get_port_stats(struct adapter *adapter, int pidx, 496 struct port_stats *p); 497 void t4_get_port_stats_offset(struct adapter *adap, int idx, 498 struct port_stats *stats, 499 struct port_stats *offset); 500 void t4_clr_port_stats(struct adapter *adap, int idx); 501 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps, 502 fw_port_cap32_t acaps); 503 void t4_reset_link_config(struct adapter *adap, int idx); 504 int t4_get_version_info(struct adapter *adapter); 505 void t4_dump_version_info(struct adapter *adapter); 506 int t4_get_flash_params(struct adapter *adapter); 507 int t4_get_chip_type(struct adapter *adap, int ver); 508 int t4_prep_adapter(struct adapter *adapter); 509 int t4vf_prep_adapter(struct adapter *adapter); 510 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 511 int t4vf_port_init(struct adapter *adap); 512 int t4_init_rss_mode(struct adapter *adap, int mbox); 513 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 514 int start, int n, const u16 *rspq, unsigned int nrspq); 515 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 516 unsigned int flags, unsigned int defq); 517 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 518 u64 *flags, unsigned int *defq); 519 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 520 unsigned int start_index, unsigned int rw); 521 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 522 void t4_read_rss_key(struct adapter *adap, u32 *key); 523 524 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 525 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 526 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset, 527 unsigned int *pbar2_qid); 528 529 int t4_init_sge_params(struct adapter *adapter); 530 int t4_init_tp_params(struct adapter *adap); 531 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 532 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 533 unsigned int t4_get_regs_len(struct adapter *adap); 534 unsigned int t4vf_get_pf_from_vf(struct adapter *adap); 535 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 536 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 537 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 538 int t4_seeprom_wp(struct adapter *adapter, int enable); 539 int t4_memory_rw_addr(struct adapter *adap, int win, 540 u32 addr, u32 len, void *hbuf, int dir); 541 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, 542 u32 len, void *hbuf, int dir); 543 static inline int t4_memory_rw(struct adapter *adap, int win, 544 int mtype, u32 maddr, u32 len, 545 void *hbuf, int dir) 546 { 547 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); 548 } 549 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16); 550 #endif /* __CHELSIO_COMMON_H */ 551