1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2015 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef __CHELSIO_COMMON_H 35 #define __CHELSIO_COMMON_H 36 37 #include "cxgbe_compat.h" 38 #include "t4_hw.h" 39 #include "t4_chip_type.h" 40 #include "t4fw_interface.h" 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define PAGE_SIZE RTE_PGSIZE_4K 47 48 enum { 49 MAX_NPORTS = 4, /* max # of ports */ 50 }; 51 52 enum { 53 MEMWIN0_APERTURE = 2048, 54 MEMWIN0_BASE = 0x1b800, 55 }; 56 57 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 58 59 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 60 61 enum { 62 PAUSE_RX = 1 << 0, 63 PAUSE_TX = 1 << 1, 64 PAUSE_AUTONEG = 1 << 2 65 }; 66 67 struct port_stats { 68 u64 tx_octets; /* total # of octets in good frames */ 69 u64 tx_frames; /* all good frames */ 70 u64 tx_bcast_frames; /* all broadcast frames */ 71 u64 tx_mcast_frames; /* all multicast frames */ 72 u64 tx_ucast_frames; /* all unicast frames */ 73 u64 tx_error_frames; /* all error frames */ 74 75 u64 tx_frames_64; /* # of Tx frames in a particular range */ 76 u64 tx_frames_65_127; 77 u64 tx_frames_128_255; 78 u64 tx_frames_256_511; 79 u64 tx_frames_512_1023; 80 u64 tx_frames_1024_1518; 81 u64 tx_frames_1519_max; 82 83 u64 tx_drop; /* # of dropped Tx frames */ 84 u64 tx_pause; /* # of transmitted pause frames */ 85 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 86 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 87 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 88 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 89 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 90 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 91 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 92 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 93 94 u64 rx_octets; /* total # of octets in good frames */ 95 u64 rx_frames; /* all good frames */ 96 u64 rx_bcast_frames; /* all broadcast frames */ 97 u64 rx_mcast_frames; /* all multicast frames */ 98 u64 rx_ucast_frames; /* all unicast frames */ 99 u64 rx_too_long; /* # of frames exceeding MTU */ 100 u64 rx_jabber; /* # of jabber frames */ 101 u64 rx_fcs_err; /* # of received frames with bad FCS */ 102 u64 rx_len_err; /* # of received frames with length error */ 103 u64 rx_symbol_err; /* symbol errors */ 104 u64 rx_runt; /* # of short frames */ 105 106 u64 rx_frames_64; /* # of Rx frames in a particular range */ 107 u64 rx_frames_65_127; 108 u64 rx_frames_128_255; 109 u64 rx_frames_256_511; 110 u64 rx_frames_512_1023; 111 u64 rx_frames_1024_1518; 112 u64 rx_frames_1519_max; 113 114 u64 rx_pause; /* # of received pause frames */ 115 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 116 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 117 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 118 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 119 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 120 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 121 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 122 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 123 124 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 125 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 126 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 127 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 128 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 129 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 130 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 131 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 132 }; 133 134 struct sge_params { 135 u32 hps; /* host page size for our PF/VF */ 136 u32 eq_qpp; /* egress queues/page for our PF/VF */ 137 u32 iq_qpp; /* egress queues/page for our PF/VF */ 138 }; 139 140 struct tp_params { 141 unsigned int ntxchan; /* # of Tx channels */ 142 unsigned int tre; /* log2 of core clocks per TP tick */ 143 unsigned int dack_re; /* DACK timer resolution */ 144 unsigned int la_mask; /* what events are recorded by TP LA */ 145 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 146 147 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 148 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 149 150 /* 151 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 152 * subset of the set of fields which may be present in the Compressed 153 * Filter Tuple portion of filters and TCP TCB connections. The 154 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 155 * Since a variable number of fields may or may not be present, their 156 * shifted field positions within the Compressed Filter Tuple may 157 * vary, or not even be present if the field isn't selected in 158 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 159 * places we store their offsets here, or a -1 if the field isn't 160 * present. 161 */ 162 int vlan_shift; 163 int vnic_shift; 164 int port_shift; 165 int protocol_shift; 166 }; 167 168 struct vpd_params { 169 unsigned int cclk; 170 }; 171 172 struct pci_params { 173 uint16_t vendor_id; 174 uint16_t device_id; 175 uint32_t vpd_cap_addr; 176 uint16_t speed; 177 uint8_t width; 178 }; 179 180 /* 181 * Firmware device log. 182 */ 183 struct devlog_params { 184 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 185 u32 start; /* start of log in firmware memory */ 186 u32 size; /* size of log */ 187 }; 188 189 struct arch_specific_params { 190 u8 nchan; 191 u16 mps_rplc_size; 192 u16 vfcount; 193 u32 sge_fl_db; 194 u16 mps_tcam_size; 195 }; 196 197 struct adapter_params { 198 struct sge_params sge; 199 struct tp_params tp; 200 struct vpd_params vpd; 201 struct pci_params pci; 202 struct devlog_params devlog; 203 enum pcie_memwin drv_memwin; 204 205 unsigned int sf_size; /* serial flash size in bytes */ 206 unsigned int sf_nsec; /* # of flash sectors */ 207 208 unsigned int fw_vers; 209 unsigned int tp_vers; 210 211 unsigned short mtus[NMTUS]; 212 unsigned short a_wnd[NCCTRL_WIN]; 213 unsigned short b_wnd[NCCTRL_WIN]; 214 215 unsigned int mc_size; /* MC memory size */ 216 unsigned int cim_la_size; 217 218 unsigned char nports; /* # of ethernet ports */ 219 unsigned char portvec; 220 221 enum chip_type chip; /* chip code */ 222 struct arch_specific_params arch; /* chip specific params */ 223 224 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 225 }; 226 227 struct link_config { 228 unsigned short supported; /* link capabilities */ 229 unsigned short advertising; /* advertised capabilities */ 230 unsigned short requested_speed; /* speed user has requested */ 231 unsigned short speed; /* actual link speed */ 232 unsigned char requested_fc; /* flow control user has requested */ 233 unsigned char fc; /* actual link flow control */ 234 unsigned char autoneg; /* autonegotiating? */ 235 unsigned char link_ok; /* link up? */ 236 }; 237 238 #include "adapter.h" 239 240 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 241 u32 val); 242 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 243 int polarity, 244 int attempts, int delay, u32 *valp); 245 246 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 247 int polarity, int attempts, int delay) 248 { 249 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 250 delay, NULL); 251 } 252 253 #define for_each_port(adapter, iter) \ 254 for (iter = 0; iter < (adapter)->params.nports; ++iter) 255 256 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 257 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 258 unsigned int mask, unsigned int val); 259 void t4_intr_enable(struct adapter *adapter); 260 void t4_intr_disable(struct adapter *adapter); 261 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 262 struct link_config *lc); 263 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 264 const unsigned short *alpha, const unsigned short *beta); 265 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 266 enum dev_master master, enum dev_state *state); 267 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 268 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 269 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset); 270 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 271 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size, 272 unsigned int cache_line_size, 273 enum chip_type chip_compat); 274 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 275 unsigned int cache_line_size); 276 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 277 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 278 unsigned int vf, unsigned int nparams, const u32 *params, 279 u32 *val); 280 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 281 unsigned int pf, unsigned int vf, 282 unsigned int nparams, const u32 *params, 283 const u32 *val, int timeout); 284 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 285 unsigned int vf, unsigned int nparams, const u32 *params, 286 const u32 *val); 287 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 288 unsigned int port, unsigned int pf, unsigned int vf, 289 unsigned int nmac, u8 *mac, unsigned int *rss_size, 290 unsigned int portfunc, unsigned int idstype); 291 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 292 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 293 unsigned int *rss_size); 294 int t4_free_vi(struct adapter *adap, unsigned int mbox, 295 unsigned int pf, unsigned int vf, 296 unsigned int viid); 297 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 298 int mtu, int promisc, int all_multi, int bcast, int vlanex, 299 bool sleep_ok); 300 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 301 int idx, const u8 *addr, bool persist, bool add_smt); 302 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 303 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 304 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 305 bool rx_en, bool tx_en); 306 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 307 unsigned int pf, unsigned int vf, unsigned int iqid, 308 unsigned int fl0id, unsigned int fl1id); 309 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 310 unsigned int vf, unsigned int iqtype, unsigned int iqid, 311 unsigned int fl0id, unsigned int fl1id); 312 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 313 unsigned int vf, unsigned int eqid); 314 315 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 316 { 317 return adap->params.vpd.cclk / 1000; 318 } 319 320 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 321 unsigned int us) 322 { 323 return (us * adap->params.vpd.cclk) / 1000; 324 } 325 326 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 327 unsigned int ticks) 328 { 329 /* add Core Clock / 2 to round ticks to nearest uS */ 330 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) / 331 adapter->params.vpd.cclk); 332 } 333 334 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 335 int size, void *rpl, bool sleep_ok, int timeout); 336 int t4_wr_mbox_meat(struct adapter *adap, int mbox, 337 const void __attribute__((__may_alias__)) *cmd, int size, 338 void *rpl, bool sleep_ok); 339 340 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 341 const void *cmd, int size, void *rpl, 342 int timeout) 343 { 344 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 345 timeout); 346 } 347 348 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p); 349 350 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 351 int size, void *rpl) 352 { 353 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 354 } 355 356 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 357 int size, void *rpl) 358 { 359 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 360 } 361 362 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 363 unsigned int data_reg, u32 *vals, unsigned int nregs, 364 unsigned int start_idx); 365 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 366 unsigned int data_reg, const u32 *vals, 367 unsigned int nregs, unsigned int start_idx); 368 369 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 370 int t4_read_flash(struct adapter *adapter, unsigned int addr, 371 unsigned int nwords, u32 *data, int byte_oriented); 372 int t4_flash_cfg_addr(struct adapter *adapter); 373 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 374 const char *t4_get_port_type_description(enum fw_port_type port_type); 375 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 376 void t4_get_port_stats_offset(struct adapter *adap, int idx, 377 struct port_stats *stats, 378 struct port_stats *offset); 379 void t4_clr_port_stats(struct adapter *adap, int idx); 380 void t4_reset_link_config(struct adapter *adap, int idx); 381 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 382 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 383 int t4_get_flash_params(struct adapter *adapter); 384 int t4_prep_adapter(struct adapter *adapter); 385 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 386 int t4_init_rss_mode(struct adapter *adap, int mbox); 387 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 388 int start, int n, const u16 *rspq, unsigned int nrspq); 389 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 390 unsigned int flags, unsigned int defq); 391 392 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 393 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 394 unsigned int qtype, u64 *pbar2_qoffset, 395 unsigned int *pbar2_qid); 396 397 int t4_init_sge_params(struct adapter *adapter); 398 int t4_init_tp_params(struct adapter *adap); 399 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); 400 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 401 #endif /* __CHELSIO_COMMON_H */ 402