xref: /dpdk/drivers/net/cnxk/meson.build (revision b0d0c84b3c0ffcdd0c3ef307c4966f06bd296db7) 
1# SPDX-License-Identifier: BSD-3-Clause
2# Copyright(C) 2021 Marvell.
3#
4
5if not dpdk_conf.get('RTE_ARCH_64')
6    build = false
7    reason = 'only supported on 64-bit'
8    subdir_done()
9endif
10
11if meson.is_cross_build()
12        soc_type = meson.get_external_property('platform', '')
13else
14        soc_type = platform
15endif
16
17if soc_type != 'cn9k' and soc_type != 'cn10k' and soc_type != 'cn20k'
18        soc_type = 'all'
19endif
20
21sources = files(
22        'cnxk_ethdev.c',
23        'cnxk_ethdev_cman.c',
24        'cnxk_ethdev_devargs.c',
25        'cnxk_ethdev_mcs.c',
26        'cnxk_ethdev_mtr.c',
27        'cnxk_ethdev_ops.c',
28        'cnxk_ethdev_sec.c',
29        'cnxk_ethdev_telemetry.c',
30        'cnxk_ethdev_sec_telemetry.c',
31        'cnxk_eswitch.c',
32        'cnxk_eswitch_devargs.c',
33        'cnxk_eswitch_flow.c',
34        'cnxk_eswitch_rxtx.c',
35        'cnxk_link.c',
36        'cnxk_lookup.c',
37        'cnxk_ptp.c',
38        'cnxk_flow.c',
39        'cnxk_rep.c',
40        'cnxk_rep_msg.c',
41        'cnxk_rep_ops.c',
42        'cnxk_rep_flow.c',
43        'cnxk_stats.c',
44        'cnxk_tm.c',
45)
46
47disable_template = false
48if meson.version().version_compare('>=1.1.0')
49        if '-DCNXK_DIS_TMPLT_FUNC' in meson.build_options()
50                disable_template = true
51        endif
52endif
53
54if soc_type == 'cn9k' or soc_type == 'all'
55# CN9K
56sources += files(
57        'cn9k_ethdev.c',
58        'cn9k_ethdev_sec.c',
59        'cn9k_flow.c',
60        'cn9k_rx_select.c',
61        'cn9k_tx_select.c',
62)
63
64if host_machine.cpu_family().startswith('aarch') and not disable_template
65sources += files(
66        'rx/cn9k/rx_0_15.c',
67        'rx/cn9k/rx_16_31.c',
68        'rx/cn9k/rx_32_47.c',
69        'rx/cn9k/rx_48_63.c',
70        'rx/cn9k/rx_64_79.c',
71        'rx/cn9k/rx_80_95.c',
72        'rx/cn9k/rx_96_111.c',
73        'rx/cn9k/rx_112_127.c',
74        'rx/cn9k/rx_0_15_mseg.c',
75        'rx/cn9k/rx_16_31_mseg.c',
76        'rx/cn9k/rx_32_47_mseg.c',
77        'rx/cn9k/rx_48_63_mseg.c',
78        'rx/cn9k/rx_64_79_mseg.c',
79        'rx/cn9k/rx_80_95_mseg.c',
80        'rx/cn9k/rx_96_111_mseg.c',
81        'rx/cn9k/rx_112_127_mseg.c',
82        'rx/cn9k/rx_0_15_vec.c',
83        'rx/cn9k/rx_16_31_vec.c',
84        'rx/cn9k/rx_32_47_vec.c',
85        'rx/cn9k/rx_48_63_vec.c',
86        'rx/cn9k/rx_64_79_vec.c',
87        'rx/cn9k/rx_80_95_vec.c',
88        'rx/cn9k/rx_96_111_vec.c',
89        'rx/cn9k/rx_112_127_vec.c',
90        'rx/cn9k/rx_0_15_vec_mseg.c',
91        'rx/cn9k/rx_16_31_vec_mseg.c',
92        'rx/cn9k/rx_32_47_vec_mseg.c',
93        'rx/cn9k/rx_48_63_vec_mseg.c',
94        'rx/cn9k/rx_64_79_vec_mseg.c',
95        'rx/cn9k/rx_80_95_vec_mseg.c',
96        'rx/cn9k/rx_96_111_vec_mseg.c',
97        'rx/cn9k/rx_112_127_vec_mseg.c',
98        'rx/cn9k/rx_all_offload.c',
99)
100
101sources += files(
102        'tx/cn9k/tx_0_15.c',
103        'tx/cn9k/tx_16_31.c',
104        'tx/cn9k/tx_32_47.c',
105        'tx/cn9k/tx_48_63.c',
106        'tx/cn9k/tx_64_79.c',
107        'tx/cn9k/tx_80_95.c',
108        'tx/cn9k/tx_96_111.c',
109        'tx/cn9k/tx_112_127.c',
110        'tx/cn9k/tx_0_15_mseg.c',
111        'tx/cn9k/tx_16_31_mseg.c',
112        'tx/cn9k/tx_32_47_mseg.c',
113        'tx/cn9k/tx_48_63_mseg.c',
114        'tx/cn9k/tx_64_79_mseg.c',
115        'tx/cn9k/tx_80_95_mseg.c',
116        'tx/cn9k/tx_96_111_mseg.c',
117        'tx/cn9k/tx_112_127_mseg.c',
118        'tx/cn9k/tx_0_15_vec.c',
119        'tx/cn9k/tx_16_31_vec.c',
120        'tx/cn9k/tx_32_47_vec.c',
121        'tx/cn9k/tx_48_63_vec.c',
122        'tx/cn9k/tx_64_79_vec.c',
123        'tx/cn9k/tx_80_95_vec.c',
124        'tx/cn9k/tx_96_111_vec.c',
125        'tx/cn9k/tx_112_127_vec.c',
126        'tx/cn9k/tx_0_15_vec_mseg.c',
127        'tx/cn9k/tx_16_31_vec_mseg.c',
128        'tx/cn9k/tx_32_47_vec_mseg.c',
129        'tx/cn9k/tx_48_63_vec_mseg.c',
130        'tx/cn9k/tx_64_79_vec_mseg.c',
131        'tx/cn9k/tx_80_95_vec_mseg.c',
132        'tx/cn9k/tx_96_111_vec_mseg.c',
133        'tx/cn9k/tx_112_127_vec_mseg.c',
134        'tx/cn9k/tx_all_offload.c',
135)
136else
137sources += files(
138        'rx/cn9k/rx_all_offload.c',
139        'tx/cn9k/tx_all_offload.c',
140)
141endif
142endif
143
144if soc_type == 'cn10k' or soc_type == 'all'
145# CN10K
146sources += files(
147        'cn10k_ethdev.c',
148        'cn10k_ethdev_sec.c',
149        'cn10k_flow.c',
150        'cn10k_rx_select.c',
151        'cn10k_tx_select.c',
152)
153
154if host_machine.cpu_family().startswith('aarch') and not disable_template
155sources += files(
156        'rx/cn10k/rx_0_15.c',
157        'rx/cn10k/rx_16_31.c',
158        'rx/cn10k/rx_32_47.c',
159        'rx/cn10k/rx_48_63.c',
160        'rx/cn10k/rx_64_79.c',
161        'rx/cn10k/rx_80_95.c',
162        'rx/cn10k/rx_96_111.c',
163        'rx/cn10k/rx_112_127.c',
164        'rx/cn10k/rx_0_15_mseg.c',
165        'rx/cn10k/rx_16_31_mseg.c',
166        'rx/cn10k/rx_32_47_mseg.c',
167        'rx/cn10k/rx_48_63_mseg.c',
168        'rx/cn10k/rx_64_79_mseg.c',
169        'rx/cn10k/rx_80_95_mseg.c',
170        'rx/cn10k/rx_96_111_mseg.c',
171        'rx/cn10k/rx_112_127_mseg.c',
172        'rx/cn10k/rx_0_15_vec.c',
173        'rx/cn10k/rx_16_31_vec.c',
174        'rx/cn10k/rx_32_47_vec.c',
175        'rx/cn10k/rx_48_63_vec.c',
176        'rx/cn10k/rx_64_79_vec.c',
177        'rx/cn10k/rx_80_95_vec.c',
178        'rx/cn10k/rx_96_111_vec.c',
179        'rx/cn10k/rx_112_127_vec.c',
180        'rx/cn10k/rx_0_15_vec_mseg.c',
181        'rx/cn10k/rx_16_31_vec_mseg.c',
182        'rx/cn10k/rx_32_47_vec_mseg.c',
183        'rx/cn10k/rx_48_63_vec_mseg.c',
184        'rx/cn10k/rx_64_79_vec_mseg.c',
185        'rx/cn10k/rx_80_95_vec_mseg.c',
186        'rx/cn10k/rx_96_111_vec_mseg.c',
187        'rx/cn10k/rx_112_127_vec_mseg.c',
188        'rx/cn10k/rx_all_offload.c',
189)
190
191sources += files(
192        'tx/cn10k/tx_0_15.c',
193        'tx/cn10k/tx_16_31.c',
194        'tx/cn10k/tx_32_47.c',
195        'tx/cn10k/tx_48_63.c',
196        'tx/cn10k/tx_64_79.c',
197        'tx/cn10k/tx_80_95.c',
198        'tx/cn10k/tx_96_111.c',
199        'tx/cn10k/tx_112_127.c',
200        'tx/cn10k/tx_0_15_mseg.c',
201        'tx/cn10k/tx_16_31_mseg.c',
202        'tx/cn10k/tx_32_47_mseg.c',
203        'tx/cn10k/tx_48_63_mseg.c',
204        'tx/cn10k/tx_64_79_mseg.c',
205        'tx/cn10k/tx_80_95_mseg.c',
206        'tx/cn10k/tx_96_111_mseg.c',
207        'tx/cn10k/tx_112_127_mseg.c',
208        'tx/cn10k/tx_0_15_vec.c',
209        'tx/cn10k/tx_16_31_vec.c',
210        'tx/cn10k/tx_32_47_vec.c',
211        'tx/cn10k/tx_48_63_vec.c',
212        'tx/cn10k/tx_64_79_vec.c',
213        'tx/cn10k/tx_80_95_vec.c',
214        'tx/cn10k/tx_96_111_vec.c',
215        'tx/cn10k/tx_112_127_vec.c',
216        'tx/cn10k/tx_0_15_vec_mseg.c',
217        'tx/cn10k/tx_16_31_vec_mseg.c',
218        'tx/cn10k/tx_32_47_vec_mseg.c',
219        'tx/cn10k/tx_48_63_vec_mseg.c',
220        'tx/cn10k/tx_64_79_vec_mseg.c',
221        'tx/cn10k/tx_80_95_vec_mseg.c',
222        'tx/cn10k/tx_96_111_vec_mseg.c',
223        'tx/cn10k/tx_112_127_vec_mseg.c',
224        'tx/cn10k/tx_all_offload.c',
225)
226else
227sources += files(
228        'rx/cn10k/rx_all_offload.c',
229        'tx/cn10k/tx_all_offload.c',
230)
231endif
232endif
233
234
235if soc_type == 'cn20k' or soc_type == 'all'
236# CN20K
237sources += files(
238        'cn20k_ethdev.c',
239        'cn20k_rx_select.c',
240        'cn20k_tx_select.c',
241)
242
243if host_machine.cpu_family().startswith('aarch') and not disable_template
244sources += files(
245        'rx/cn20k/rx_0_15.c',
246        'rx/cn20k/rx_16_31.c',
247        'rx/cn20k/rx_32_47.c',
248        'rx/cn20k/rx_48_63.c',
249        'rx/cn20k/rx_64_79.c',
250        'rx/cn20k/rx_80_95.c',
251        'rx/cn20k/rx_96_111.c',
252        'rx/cn20k/rx_112_127.c',
253        'rx/cn20k/rx_0_15_mseg.c',
254        'rx/cn20k/rx_16_31_mseg.c',
255        'rx/cn20k/rx_32_47_mseg.c',
256        'rx/cn20k/rx_48_63_mseg.c',
257        'rx/cn20k/rx_64_79_mseg.c',
258        'rx/cn20k/rx_80_95_mseg.c',
259        'rx/cn20k/rx_96_111_mseg.c',
260        'rx/cn20k/rx_112_127_mseg.c',
261        'rx/cn20k/rx_0_15_vec.c',
262        'rx/cn20k/rx_16_31_vec.c',
263        'rx/cn20k/rx_32_47_vec.c',
264        'rx/cn20k/rx_48_63_vec.c',
265        'rx/cn20k/rx_64_79_vec.c',
266        'rx/cn20k/rx_80_95_vec.c',
267        'rx/cn20k/rx_96_111_vec.c',
268        'rx/cn20k/rx_112_127_vec.c',
269        'rx/cn20k/rx_0_15_vec_mseg.c',
270        'rx/cn20k/rx_16_31_vec_mseg.c',
271        'rx/cn20k/rx_32_47_vec_mseg.c',
272        'rx/cn20k/rx_48_63_vec_mseg.c',
273        'rx/cn20k/rx_64_79_vec_mseg.c',
274        'rx/cn20k/rx_80_95_vec_mseg.c',
275        'rx/cn20k/rx_96_111_vec_mseg.c',
276        'rx/cn20k/rx_112_127_vec_mseg.c',
277        'rx/cn20k/rx_all_offload.c',
278)
279
280sources += files(
281        'tx/cn20k/tx_0_15.c',
282        'tx/cn20k/tx_16_31.c',
283        'tx/cn20k/tx_32_47.c',
284        'tx/cn20k/tx_48_63.c',
285        'tx/cn20k/tx_64_79.c',
286        'tx/cn20k/tx_80_95.c',
287        'tx/cn20k/tx_96_111.c',
288        'tx/cn20k/tx_112_127.c',
289        'tx/cn20k/tx_0_15_mseg.c',
290        'tx/cn20k/tx_16_31_mseg.c',
291        'tx/cn20k/tx_32_47_mseg.c',
292        'tx/cn20k/tx_48_63_mseg.c',
293        'tx/cn20k/tx_64_79_mseg.c',
294        'tx/cn20k/tx_80_95_mseg.c',
295        'tx/cn20k/tx_96_111_mseg.c',
296        'tx/cn20k/tx_112_127_mseg.c',
297        'tx/cn20k/tx_0_15_vec.c',
298        'tx/cn20k/tx_16_31_vec.c',
299        'tx/cn20k/tx_32_47_vec.c',
300        'tx/cn20k/tx_48_63_vec.c',
301        'tx/cn20k/tx_64_79_vec.c',
302        'tx/cn20k/tx_80_95_vec.c',
303        'tx/cn20k/tx_96_111_vec.c',
304        'tx/cn20k/tx_112_127_vec.c',
305        'tx/cn20k/tx_0_15_vec_mseg.c',
306        'tx/cn20k/tx_16_31_vec_mseg.c',
307        'tx/cn20k/tx_32_47_vec_mseg.c',
308        'tx/cn20k/tx_48_63_vec_mseg.c',
309        'tx/cn20k/tx_64_79_vec_mseg.c',
310        'tx/cn20k/tx_80_95_vec_mseg.c',
311        'tx/cn20k/tx_96_111_vec_mseg.c',
312        'tx/cn20k/tx_112_127_vec_mseg.c',
313        'tx/cn20k/tx_all_offload.c',
314)
315else
316sources += files(
317        'rx/cn20k/rx_all_offload.c',
318        'tx/cn20k/tx_all_offload.c',
319)
320endif
321endif
322
323
324deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
325deps += ['common_cnxk', 'mempool_cnxk']
326
327# Allow implicit vector conversions and strict aliasing warning
328extra_flags = ['-flax-vector-conversions', '-Wno-strict-aliasing']
329if cc.get_id() == 'clang'
330        extra_flags += ['-Wno-asm-operand-widths']
331endif
332foreach flag: extra_flags
333    if cc.has_argument(flag)
334        cflags += flag
335    endif
336endforeach
337
338headers = files('rte_pmd_cnxk.h')
339
340require_iova_in_mbuf = false
341
342annotate_locks = false
343