1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2023 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <rte_common.h> 7 8 #include "cfa_resource_types.h" 9 #include "tf_device.h" 10 #include "tf_identifier.h" 11 #include "tf_tbl.h" 12 #include "tf_tcam.h" 13 #include "tf_tcam_shared.h" 14 #include "tf_em.h" 15 #include "tf_if_tbl.h" 16 #include "tfp.h" 17 #include "tf_msg_common.h" 18 #include "tf_util.h" 19 20 #define TF_DEV_P4_PARIF_MAX 16 21 #define TF_DEV_P4_PF_MASK 0xfUL 22 23 const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { 24 [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group", 25 [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ", 26 [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16", 27 [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64", 28 [CFA_RESOURCE_TYPE_P4_SP_MAC] = "sp_mac ", 29 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4", 30 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6", 31 [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ", 32 [CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port", 33 [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4", 34 [CFA_RESOURCE_TYPE_P4_METER] = "meter ", 35 [CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ", 36 [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act", 37 [CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act", 38 [CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act", 39 [CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act", 40 [CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act", 41 [CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act", 42 [CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act", 43 [CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act", 44 [CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act", 45 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi", 46 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo", 47 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi", 48 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo", 49 [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func", 50 [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam", 51 [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ", 52 [CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec ", 53 [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ", 54 [CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ", 55 [CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof", 56 [CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror ", 57 [CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ", 58 [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", 59 }; 60 61 struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { 62 [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { 63 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, 64 0, 0 65 }, 66 [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { 67 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, 68 0, 0 69 }, 70 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { 71 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, 72 0, 0 73 }, 74 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { 75 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, 76 0, 0 77 }, 78 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { 79 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, 80 0, 0 81 }, 82 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { 83 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, 84 0, 0 85 }, 86 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { 87 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, 88 0, 0 89 }, 90 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { 91 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, 92 0, 0 93 }, 94 [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { 95 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, 96 0, 0 97 }, 98 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { 99 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, 100 0, 0 101 }, 102 [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { 103 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, 104 0, 0 105 }, 106 [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { 107 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, 108 0, 0 109 }, 110 [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { 111 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, 112 0, 0 113 }, 114 [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { 115 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, 116 0, 0 117 }, 118 [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { 119 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, 120 0, 0 121 }, 122 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { 123 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, 124 0, 0 125 }, 126 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { 127 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, 128 0, 0 129 }, 130 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { 131 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, 132 0, 0 133 }, 134 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { 135 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, 136 0, 0 137 }, 138 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { 139 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, 140 0, 0 141 }, 142 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { 143 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, 144 0, 0 145 }, 146 [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { 147 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, 148 0, 0 149 }, 150 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { 151 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, 152 0, 0 153 }, 154 [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { 155 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, 156 0, 0 157 }, 158 [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { 159 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, 160 0, 0 161 }, 162 [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { 163 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, 164 0, 0 165 }, 166 }; 167 168 /** 169 * Device specific function that retrieves the MAX number of HCAPI 170 * types the device supports. 171 * 172 * [in] tfp 173 * Pointer to TF handle 174 * 175 * [out] max_types 176 * Pointer to the MAX number of CFA resource types supported 177 * 178 * Returns 179 * - (0) if successful. 180 * - (-EINVAL) on failure. 181 */ 182 static int 183 tf_dev_p4_get_max_types(struct tf *tfp, 184 uint16_t *max_types) 185 { 186 if (max_types == NULL || tfp == NULL) 187 return -EINVAL; 188 189 *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1; 190 191 return 0; 192 } 193 /** 194 * Device specific function that retrieves a human readable 195 * string to identify a CFA resource type. 196 * 197 * [in] tfp 198 * Pointer to TF handle 199 * 200 * [in] resource_id 201 * HCAPI CFA resource id 202 * 203 * [out] resource_str 204 * Resource string 205 * 206 * Returns 207 * - (0) if successful. 208 * - (-EINVAL) on failure. 209 */ 210 static int 211 tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused, 212 uint16_t resource_id, 213 const char **resource_str) 214 { 215 if (resource_str == NULL) 216 return -EINVAL; 217 218 if (resource_id > CFA_RESOURCE_TYPE_P4_LAST) 219 return -EINVAL; 220 221 *resource_str = tf_resource_str_p4[resource_id]; 222 223 return 0; 224 } 225 226 /** 227 * Device specific function that set the WC TCAM slices the 228 * device supports. 229 * 230 * [in] tfp 231 * Pointer to TF handle 232 * 233 * [in] num_slices_per_row 234 * The WC TCAM row slice configuration 235 * 236 * Returns 237 * - (0) if successful. 238 * - (-EINVAL) on failure. 239 */ 240 static int 241 tf_dev_p4_set_tcam_slice_info(struct tf *tfp, 242 enum tf_wc_num_slice num_slices_per_row) 243 { 244 int rc; 245 struct tf_session *tfs = NULL; 246 247 /* Retrieve the session information */ 248 rc = tf_session_get_session_internal(tfp, &tfs); 249 if (rc) 250 return rc; 251 252 switch (num_slices_per_row) { 253 case TF_WC_TCAM_1_SLICE_PER_ROW: 254 case TF_WC_TCAM_2_SLICE_PER_ROW: 255 case TF_WC_TCAM_4_SLICE_PER_ROW: 256 tfs->wc_num_slices_per_row = num_slices_per_row; 257 break; 258 default: 259 return -EINVAL; 260 } 261 262 return 0; 263 } 264 265 /** 266 * Device specific function that retrieves the TCAM slices the 267 * device supports. 268 * 269 * [in] tfp 270 * Pointer to TF handle 271 * 272 * [in] type 273 * TF TCAM type 274 * 275 * [in] key_sz 276 * The key size 277 * 278 * [out] num_slices_per_row 279 * Pointer to the WC TCAM row slice configuration 280 * 281 * Returns 282 * - (0) if successful. 283 * - (-EINVAL) on failure. 284 */ 285 static int 286 tf_dev_p4_get_tcam_slice_info(struct tf *tfp, 287 enum tf_tcam_tbl_type type, 288 uint16_t key_sz, 289 uint16_t *num_slices_per_row) 290 { 291 int rc; 292 struct tf_session *tfs; 293 294 /* Retrieve the session information */ 295 rc = tf_session_get_session_internal(tfp, &tfs); 296 if (rc) 297 return rc; 298 299 /* Single slice support */ 300 #define CFA_P4_WC_TCAM_SLICE_SIZE (12) 301 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { 302 if (key_sz <= 1 * CFA_P4_WC_TCAM_SLICE_SIZE) 303 *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW; 304 else if (key_sz <= 2 * CFA_P4_WC_TCAM_SLICE_SIZE) 305 *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW; 306 else if (key_sz <= 4 * CFA_P4_WC_TCAM_SLICE_SIZE) 307 *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW; 308 else 309 return -ENOTSUP; 310 } else { /* for other type of tcam */ 311 *num_slices_per_row = 1; 312 } 313 314 return 0; 315 } 316 317 static int 318 tf_dev_p4_map_parif(struct tf *tfp __rte_unused, 319 uint16_t parif_bitmask, 320 uint16_t pf, 321 uint8_t *data, 322 uint8_t *mask, 323 uint16_t sz_in_bytes) 324 { 325 uint32_t parif_pf[2] = { 0 }; 326 uint32_t parif_pf_mask[2] = { 0 }; 327 uint32_t parif; 328 uint32_t shift; 329 330 if (sz_in_bytes != sizeof(uint64_t)) 331 return -ENOTSUP; 332 333 for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) { 334 if (parif_bitmask & (1UL << parif)) { 335 if (parif < 8) { 336 shift = 4 * parif; 337 parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift; 338 parif_pf[0] |= pf << shift; 339 } else { 340 shift = 4 * (parif - 8); 341 parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift; 342 parif_pf[1] |= pf << shift; 343 } 344 } 345 } 346 tfp_memcpy(data, parif_pf, sz_in_bytes); 347 tfp_memcpy(mask, parif_pf_mask, sz_in_bytes); 348 349 return 0; 350 } 351 352 /** 353 * Device specific function that retrieves the increment 354 * required for certain table types in a shared session 355 * 356 * [in] tfp 357 * tf handle 358 * 359 * [in/out] parms 360 * pointer to parms structure 361 * 362 * Returns 363 * - (0) if successful. 364 * - (-EINVAL) on failure. 365 */ 366 static int tf_dev_p4_get_shared_tbl_increment(struct tf *tfp __rte_unused, 367 struct tf_get_shared_tbl_increment_parms *parms) 368 { 369 parms->increment_cnt = 1; 370 return 0; 371 } 372 static int tf_dev_p4_get_mailbox(void) 373 { 374 return TF_KONG_MB; 375 } 376 377 static int tf_dev_p4_word_align(uint16_t size) 378 { 379 return ((((size) + 31) >> 5) * 4); 380 } 381 382 /** 383 * Indicates whether the index table type is SRAM managed 384 * 385 * [in] tfp 386 * Pointer to TF handle 387 * 388 * [in] type 389 * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD 390 * 391 * Returns 392 * - (0) if the table is not managed by the SRAM manager 393 * - (1) if the table is managed by the SRAM manager 394 */ 395 static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, 396 enum tf_tbl_type type __rte_unused) 397 { 398 return false; 399 } 400 401 /** 402 * Device specific function that maps the hcapi resource types 403 * to Truflow type. 404 * 405 * [in] hcapi_caps 406 * CFA resource type bitmap 407 * 408 * [out] ident_caps 409 * Pointer to identifier type bitmap 410 * 411 * [out] tcam_caps 412 * Pointer to tcam type bitmap 413 * 414 * [out] tbl_caps 415 * Pointer to table type bitmap 416 * 417 * [out] em_caps 418 * Pointer to em type bitmap 419 * 420 * Returns 421 * - (0) if successful. 422 * - (-EINVAL) on failure. 423 */ 424 static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, 425 uint32_t *ident_caps, 426 uint32_t *tcam_caps, 427 uint32_t *tbl_caps, 428 uint32_t *em_caps) 429 { 430 uint32_t i; 431 432 *ident_caps = 0; 433 *tcam_caps = 0; 434 *tbl_caps = 0; 435 *em_caps = 0; 436 437 for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { 438 if (hcapi_caps & 1ULL << i) { 439 switch (tf_hcapi_res_map_p4[i].module_type) { 440 case TF_MODULE_TYPE_IDENTIFIER: 441 *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; 442 break; 443 case TF_MODULE_TYPE_TABLE: 444 *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; 445 break; 446 case TF_MODULE_TYPE_TCAM: 447 *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; 448 break; 449 case TF_MODULE_TYPE_EM: 450 *em_caps |= tf_hcapi_res_map_p4[i].type_caps; 451 break; 452 default: 453 return -EINVAL; 454 } 455 } 456 } 457 458 return 0; 459 } 460 461 /** 462 * Truflow P4 device specific functions 463 */ 464 const struct tf_dev_ops tf_dev_ops_p4_init = { 465 .tf_dev_get_max_types = tf_dev_p4_get_max_types, 466 .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, 467 .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info, 468 .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, 469 .tf_dev_alloc_ident = NULL, 470 .tf_dev_free_ident = NULL, 471 .tf_dev_search_ident = NULL, 472 .tf_dev_get_ident_resc_info = NULL, 473 .tf_dev_get_tbl_info = NULL, 474 .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed, 475 .tf_dev_alloc_ext_tbl = NULL, 476 .tf_dev_alloc_tbl = NULL, 477 .tf_dev_alloc_sram_tbl = NULL, 478 .tf_dev_free_ext_tbl = NULL, 479 .tf_dev_free_tbl = NULL, 480 .tf_dev_free_sram_tbl = NULL, 481 .tf_dev_set_tbl = NULL, 482 .tf_dev_set_ext_tbl = NULL, 483 .tf_dev_set_sram_tbl = NULL, 484 .tf_dev_get_tbl = NULL, 485 .tf_dev_get_sram_tbl = NULL, 486 .tf_dev_get_bulk_tbl = NULL, 487 .tf_dev_get_bulk_sram_tbl = NULL, 488 .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, 489 .tf_dev_get_tbl_resc_info = NULL, 490 .tf_dev_alloc_tcam = NULL, 491 .tf_dev_free_tcam = NULL, 492 .tf_dev_alloc_search_tcam = NULL, 493 .tf_dev_set_tcam = NULL, 494 .tf_dev_get_tcam = NULL, 495 .tf_dev_get_tcam_resc_info = NULL, 496 .tf_dev_insert_int_em_entry = NULL, 497 .tf_dev_delete_int_em_entry = NULL, 498 .tf_dev_insert_ext_em_entry = NULL, 499 .tf_dev_delete_ext_em_entry = NULL, 500 .tf_dev_get_em_resc_info = NULL, 501 .tf_dev_alloc_tbl_scope = NULL, 502 .tf_dev_map_tbl_scope = NULL, 503 .tf_dev_map_parif = NULL, 504 .tf_dev_free_tbl_scope = NULL, 505 .tf_dev_set_if_tbl = NULL, 506 .tf_dev_get_if_tbl = NULL, 507 .tf_dev_set_global_cfg = NULL, 508 .tf_dev_get_global_cfg = NULL, 509 .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, 510 .tf_dev_word_align = NULL, 511 .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, 512 .tf_dev_get_sram_resources = NULL, 513 .tf_dev_set_sram_policy = NULL, 514 .tf_dev_get_sram_policy = NULL, 515 #ifdef TF_FLOW_SCALE_QUERY 516 .tf_dev_update_resc_usage = NULL, 517 .tf_dev_query_resc_usage = NULL, 518 .tf_dev_update_tbl_usage_buffer = NULL, 519 #endif /* TF_FLOW_SCALE_QUERY */ 520 }; 521 522 /** 523 * Truflow P4 device specific functions 524 */ 525 const struct tf_dev_ops tf_dev_ops_p4 = { 526 .tf_dev_get_max_types = tf_dev_p4_get_max_types, 527 .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, 528 .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info, 529 .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, 530 .tf_dev_alloc_ident = tf_ident_alloc, 531 .tf_dev_free_ident = tf_ident_free, 532 .tf_dev_search_ident = tf_ident_search, 533 .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, 534 .tf_dev_get_tbl_info = NULL, 535 .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed, 536 .tf_dev_alloc_tbl = tf_tbl_alloc, 537 .tf_dev_alloc_ext_tbl = NULL, 538 .tf_dev_alloc_sram_tbl = tf_tbl_alloc, 539 .tf_dev_free_tbl = tf_tbl_free, 540 .tf_dev_free_ext_tbl = NULL, 541 .tf_dev_free_sram_tbl = tf_tbl_free, 542 .tf_dev_set_tbl = tf_tbl_set, 543 .tf_dev_set_ext_tbl = NULL, 544 .tf_dev_set_sram_tbl = NULL, 545 .tf_dev_get_tbl = tf_tbl_get, 546 .tf_dev_get_sram_tbl = NULL, 547 .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, 548 .tf_dev_get_bulk_sram_tbl = NULL, 549 .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, 550 .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, 551 .tf_dev_alloc_tcam = tf_tcam_shared_alloc, 552 .tf_dev_free_tcam = tf_tcam_shared_free, 553 .tf_dev_set_tcam = tf_tcam_shared_set, 554 .tf_dev_get_tcam = tf_tcam_shared_get, 555 .tf_dev_move_tcam = tf_tcam_shared_move_p4, 556 .tf_dev_clear_tcam = tf_tcam_shared_clear, 557 .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, 558 .tf_dev_insert_int_em_entry = tf_em_insert_int_entry, 559 .tf_dev_delete_int_em_entry = tf_em_delete_int_entry, 560 .tf_dev_insert_ext_em_entry = NULL, 561 .tf_dev_delete_ext_em_entry = NULL, 562 .tf_dev_get_em_resc_info = tf_em_get_resc_info, 563 .tf_dev_alloc_tbl_scope = NULL, 564 .tf_dev_map_tbl_scope = NULL, 565 .tf_dev_map_parif = tf_dev_p4_map_parif, 566 .tf_dev_free_tbl_scope = NULL, 567 .tf_dev_set_if_tbl = tf_if_tbl_set, 568 .tf_dev_get_if_tbl = tf_if_tbl_get, 569 .tf_dev_set_global_cfg = tf_global_cfg_set, 570 .tf_dev_get_global_cfg = tf_global_cfg_get, 571 .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, 572 .tf_dev_word_align = tf_dev_p4_word_align, 573 .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, 574 .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, 575 .tf_dev_get_sram_resources = NULL, 576 .tf_dev_set_sram_policy = NULL, 577 .tf_dev_get_sram_policy = NULL, 578 #ifdef TF_FLOW_SCALE_QUERY 579 .tf_dev_update_resc_usage = NULL, 580 .tf_dev_query_resc_usage = NULL, 581 .tf_dev_update_tbl_usage_buffer = NULL, 582 #endif /* TF_FLOW_SCALE_QUERY */ 583 }; 584