1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2023 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <pthread.h> 12 #include <sys/queue.h> 13 14 #include <rte_pci.h> 15 #include <bus_pci_driver.h> 16 #include <ethdev_driver.h> 17 #include <rte_memory.h> 18 #include <rte_lcore.h> 19 #include <rte_spinlock.h> 20 #include <rte_time.h> 21 #include <rte_eal_paging.h> 22 23 #include "bnxt_cpr.h" 24 #include "bnxt_util.h" 25 26 #include "tf_core.h" 27 #include "tfc.h" 28 #include "bnxt_ulp.h" 29 #include "bnxt_tf_common.h" 30 #include "bnxt_mpc.h" 31 #include "bnxt_vnic.h" 32 33 /* Vendor ID */ 34 #define PCI_VENDOR_ID_BROADCOM 0x14E4 35 36 /* Device IDs */ 37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 40 #define BROADCOM_DEV_ID_57414_VF 0x16c1 41 #define BROADCOM_DEV_ID_57304_VF 0x16cb 42 #define BROADCOM_DEV_ID_57417_MF 0x16cc 43 #define BROADCOM_DEV_ID_NS2 0x16cd 44 #define BROADCOM_DEV_ID_57406_VF 0x16d3 45 #define BROADCOM_DEV_ID_57412 0x16d6 46 #define BROADCOM_DEV_ID_57414 0x16d7 47 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 48 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 49 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 50 #define BROADCOM_DEV_ID_57412_MF 0x16de 51 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 52 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 53 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 54 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 55 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 56 #define BROADCOM_DEV_ID_57407_MF 0x16ea 57 #define BROADCOM_DEV_ID_57414_MF 0x16ec 58 #define BROADCOM_DEV_ID_57416_MF 0x16ee 59 #define BROADCOM_DEV_ID_57508 0x1750 60 #define BROADCOM_DEV_ID_57504 0x1751 61 #define BROADCOM_DEV_ID_57502 0x1752 62 #define BROADCOM_DEV_ID_57508_MF1 0x1800 63 #define BROADCOM_DEV_ID_57504_MF1 0x1801 64 #define BROADCOM_DEV_ID_57502_MF1 0x1802 65 #define BROADCOM_DEV_ID_57508_MF2 0x1803 66 #define BROADCOM_DEV_ID_57504_MF2 0x1804 67 #define BROADCOM_DEV_ID_57502_MF2 0x1805 68 #define BROADCOM_DEV_ID_57500_VF1 0x1806 69 #define BROADCOM_DEV_ID_57500_VF2 0x1807 70 #define BROADCOM_DEV_ID_58802 0xd802 71 #define BROADCOM_DEV_ID_58804 0xd804 72 #define BROADCOM_DEV_ID_58808 0x16f0 73 #define BROADCOM_DEV_ID_58802_VF 0xd800 74 #define BROADCOM_DEV_ID_58812 0xd812 75 #define BROADCOM_DEV_ID_58814 0xd814 76 #define BROADCOM_DEV_ID_58818 0xd818 77 #define BROADCOM_DEV_ID_58818_VF 0xd82e 78 #define BROADCOM_DEV_ID_57608 0x1760 79 #define BROADCOM_DEV_ID_57604 0x1761 80 #define BROADCOM_DEV_ID_57602 0x1762 81 #define BROADCOM_DEV_ID_57601 0x1763 82 #define BROADCOM_DEV_ID_5760X_VF 0x1819 83 84 #define BROADCOM_DEV_957508_N2100 0x5208 85 #define BROADCOM_DEV_957414_N225 0x4145 86 87 #define HWRM_SPEC_CODE_1_8_3 0x10803 88 #define HWRM_VERSION_1_9_1 0x10901 89 #define HWRM_VERSION_1_9_2 0x10903 90 #define HWRM_VERSION_1_10_2_13 0x10a020d 91 92 #define BNXT_MAX_MTU 9574 93 #define BNXT_NUM_VLANS 2 94 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 95 RTE_ETHER_CRC_LEN +\ 96 (BNXT_NUM_VLANS * RTE_VLAN_HLEN)) 97 /* FW adds extra 4 bytes for FCS */ 98 #define BNXT_VNIC_MRU(mtu)\ 99 ((mtu) + RTE_ETHER_HDR_LEN + RTE_VLAN_HLEN * BNXT_NUM_VLANS) 100 #define BNXT_VF_RSV_NUM_RSS_CTX 1 101 #define BNXT_VF_RSV_NUM_L2_CTX 4 102 /* TODO: For now, do not support VMDq/RFS on VFs. */ 103 #define BNXT_VF_RSV_NUM_VNIC 1 104 #define BNXT_MAX_LED 4 105 #define BNXT_MIN_RING_DESC 16 106 #define BNXT_MAX_TX_RING_DESC 4096 107 #define BNXT_MAX_RX_RING_DESC 8192 108 #define BNXT_DB_SIZE 0x80 109 110 #define TPA_MAX_AGGS 64 111 #define TPA_MAX_AGGS_TH 1024 112 113 #define TPA_MAX_NUM_SEGS 32 114 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 115 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 116 117 #define BNXT_TPA_MAX_AGGS(bp) \ 118 (BNXT_CHIP_P5_P7(bp) ? TPA_MAX_AGGS_TH : \ 119 TPA_MAX_AGGS) 120 121 #define BNXT_TPA_MAX_SEGS(bp) \ 122 (BNXT_CHIP_P5_P7(bp) ? TPA_MAX_SEGS_TH : \ 123 TPA_MAX_SEGS) 124 125 #define BNXT_TPA_MAX_PAGES 65536 126 127 /* 128 * Define the number of async completion rings to be used. Set to zero for 129 * configurations in which the maximum number of packet completion rings 130 * for packet completions is desired or when async completion handling 131 * cannot be interrupt-driven. 132 */ 133 #ifdef RTE_EXEC_ENV_FREEBSD 134 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 135 #define BNXT_NUM_ASYNC_CPR(bp) 0U 136 #else 137 #define BNXT_NUM_ASYNC_CPR(bp) 1U 138 #endif 139 140 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 141 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 142 143 /* Chimp Communication Channel */ 144 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 145 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 146 /* Kong Communication Channel */ 147 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 148 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 149 150 #define BNXT_INT_LAT_TMR_MIN 75 151 #define BNXT_INT_LAT_TMR_MAX 150 152 #define BNXT_NUM_CMPL_AGGR_INT 36 153 #define BNXT_CMPL_AGGR_DMA_TMR 37 154 #define BNXT_NUM_CMPL_DMA_AGGR 36 155 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 156 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 157 #define BNXT_DEVICE_SERIAL_NUM_SIZE 8 158 159 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 160 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 161 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 162 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 163 #define BNXT_DEFAULT_VNIC_ALLOC \ 164 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 165 #define BNXT_DEFAULT_VNIC_FREE \ 166 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 167 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 168 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 169 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 170 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 171 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 172 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 173 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 174 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 175 176 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 177 (((data1) & \ 178 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ 179 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 180 181 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 182 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 183 184 #define BNXT_NTOHS rte_be_to_cpu_16 185 186 struct bnxt_led_info { 187 uint8_t num_leds; 188 uint8_t led_id; 189 uint8_t led_type; 190 uint8_t led_group_id; 191 uint8_t unused; 192 uint16_t led_state_caps; 193 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 194 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 195 196 uint16_t led_color_caps; 197 }; 198 199 struct bnxt_led_cfg { 200 uint8_t led_id; 201 uint8_t led_state; 202 uint8_t led_color; 203 uint8_t unused; 204 uint16_t led_blink_on; 205 uint16_t led_blink_off; 206 uint8_t led_group_id; 207 uint8_t rsvd; 208 }; 209 210 #define BNXT_LED_DFLT_ENA \ 211 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 212 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 213 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 214 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 215 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 216 217 #define BNXT_LED_DFLT_ENA_SHIFT 6 218 219 #define BNXT_LED_DFLT_ENABLES(x) \ 220 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 221 222 struct __rte_packed_begin bnxt_vlan_table_entry { 223 uint16_t tpid; 224 uint16_t vid; 225 } __rte_packed_end; 226 227 struct __rte_packed_begin bnxt_vlan_antispoof_table_entry { 228 uint16_t tpid; 229 uint16_t vid; 230 uint16_t mask; 231 } __rte_packed_end; 232 233 struct bnxt_child_vf_info { 234 void *req_buf; 235 struct bnxt_vlan_table_entry *vlan_table; 236 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 237 STAILQ_HEAD(, bnxt_filter_info) filter; 238 uint32_t func_cfg_flags; 239 uint32_t l2_rx_mask; 240 uint16_t fid; 241 uint16_t max_tx_rate; 242 uint16_t dflt_vlan; 243 uint16_t vlan_count; 244 uint8_t mac_spoof_en; 245 uint8_t vlan_spoof_en; 246 bool random_mac; 247 bool persist_stats; 248 }; 249 250 struct bnxt_parent_info { 251 #define BNXT_PF_FID_INVALID 0xFFFF 252 uint16_t fid; 253 uint16_t vnic; 254 uint16_t port_id; 255 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 256 }; 257 258 struct bnxt_pf_info { 259 #define BNXT_FIRST_PF_FID 1 260 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 261 #define BNXT_MAX_VF_REPS_P4 64 262 #define BNXT_MAX_VF_REPS_P5 256 263 #define BNXT_MAX_VF_REPS(bp) \ 264 (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_P5 : \ 265 BNXT_MAX_VF_REPS_P4) 266 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 267 #define BNXT_FIRST_VF_FID 128 268 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 269 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 270 BNXT_PF_RINGS_USED(bp)) 271 uint16_t port_id; 272 uint16_t first_vf_id; 273 uint16_t active_vfs; 274 uint16_t max_vfs; 275 uint16_t total_vfs; /* Total VFs possible. 276 * Not necessarily enabled. 277 */ 278 uint32_t func_cfg_flags; 279 void *vf_req_buf; 280 rte_iova_t vf_req_buf_dma_addr; 281 uint32_t vf_req_fwd[8]; 282 uint16_t total_vnics; 283 struct bnxt_child_vf_info *vf_info; 284 #define BNXT_EVB_MODE_NONE 0 285 #define BNXT_EVB_MODE_VEB 1 286 #define BNXT_EVB_MODE_VEPA 2 287 uint8_t evb_mode; 288 }; 289 290 /* Max wait time for link up is 10s and link down is 500ms */ 291 #define BNXT_MAX_LINK_WAIT_CNT 200 292 #define BNXT_MIN_LINK_WAIT_CNT 10 293 #define BNXT_LINK_WAIT_INTERVAL 50 294 struct bnxt_link_info { 295 uint32_t phy_flags; 296 uint8_t mac_type; 297 uint8_t phy_link_status; 298 uint8_t loop_back; 299 uint8_t link_up; 300 uint8_t duplex; 301 uint8_t pause; 302 uint8_t force_pause; 303 uint8_t auto_pause; 304 uint8_t auto_mode; 305 #define PHY_VER_LEN 3 306 uint8_t phy_ver[PHY_VER_LEN]; 307 uint16_t link_speed; 308 uint16_t support_speeds; 309 uint16_t auto_link_speed; 310 uint16_t force_link_speed; 311 uint16_t auto_link_speed_mask; 312 uint32_t preemphasis; 313 uint8_t phy_type; 314 uint8_t media_type; 315 uint16_t support_auto_speeds; 316 uint8_t link_signal_mode; 317 uint16_t force_pam4_link_speed; 318 uint16_t support_pam4_speeds; 319 uint16_t auto_pam4_link_speed_mask; 320 uint16_t support_pam4_auto_speeds; 321 uint8_t req_signal_mode; 322 uint8_t module_status; 323 /* P7 speeds2 fields */ 324 bool support_speeds_v2; 325 uint16_t supported_speeds2_force_mode; 326 uint16_t supported_speeds2_auto_mode; 327 uint16_t support_speeds2; 328 uint16_t force_link_speeds2; 329 uint16_t auto_link_speeds2; 330 uint16_t cfg_auto_link_speeds2_mask; 331 uint8_t active_lanes; 332 uint8_t option_flags; 333 uint16_t pmd_speed_lanes; 334 }; 335 336 #define BNXT_COS_QUEUE_COUNT 8 337 struct bnxt_cos_queue_info { 338 uint8_t id; 339 uint8_t profile; 340 uint8_t profile_type; 341 }; 342 343 struct rte_flow { 344 STAILQ_ENTRY(rte_flow) next; 345 struct bnxt_filter_info *filter; 346 struct bnxt_vnic_info *vnic; 347 }; 348 349 #define BNXT_PTP_RX_PND_CNT 10 350 #define BNXT_PTP_FLAGS_PATH_TX 0x0 351 #define BNXT_PTP_FLAGS_PATH_RX 0x1 352 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 353 #define BNXT_PTP_CURRENT_TIME_MASK 0xFFFF00000000ULL 354 355 struct bnxt_ptp_cfg { 356 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 357 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 358 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 359 struct rte_timecounter tc; 360 struct rte_timecounter tx_tstamp_tc; 361 struct rte_timecounter rx_tstamp_tc; 362 struct bnxt *bp; 363 #define BNXT_MAX_TX_TS 1 364 uint16_t rxctl; 365 #define BNXT_PTP_MSG_SYNC BIT(0) 366 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 367 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 368 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 369 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 370 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 371 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 372 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 373 #define BNXT_PTP_MSG_SIGNALING BIT(12) 374 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 375 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 376 BNXT_PTP_MSG_DELAY_REQ | \ 377 BNXT_PTP_MSG_PDELAY_REQ | \ 378 BNXT_PTP_MSG_PDELAY_RESP) 379 uint8_t tx_tstamp_en:1; 380 int rx_filter; 381 uint8_t filter_all; 382 383 #define BNXT_PTP_RX_TS_L 0 384 #define BNXT_PTP_RX_TS_H 1 385 #define BNXT_PTP_RX_SEQ 2 386 #define BNXT_PTP_RX_FIFO 3 387 #define BNXT_PTP_RX_FIFO_PENDING 0x1 388 #define BNXT_PTP_RX_FIFO_ADV 4 389 #define BNXT_PTP_RX_REGS 5 390 391 #define BNXT_PTP_TX_TS_L 0 392 #define BNXT_PTP_TX_TS_H 1 393 #define BNXT_PTP_TX_SEQ 2 394 #define BNXT_PTP_TX_FIFO 3 395 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 396 #define BNXT_PTP_TX_REGS 4 397 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 398 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 399 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 400 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 401 402 /* On P5, the Rx timestamp is present in the Rx completion record */ 403 uint64_t rx_timestamp; 404 uint64_t current_time; 405 uint64_t old_time; 406 rte_spinlock_t ptp_lock; 407 }; 408 409 struct bnxt_coal { 410 uint16_t num_cmpl_aggr_int; 411 uint16_t num_cmpl_dma_aggr; 412 uint16_t num_cmpl_dma_aggr_during_int; 413 uint16_t int_lat_tmr_max; 414 uint16_t int_lat_tmr_min; 415 uint16_t cmpl_aggr_dma_tmr; 416 uint16_t cmpl_aggr_dma_tmr_during_int; 417 }; 418 419 /* 64-bit doorbell */ 420 #define DBR_EPOCH_MASK 0x01000000UL 421 #define DBR_EPOCH_SFT 24 422 #define DBR_XID_SFT 32 423 #define DBR_PATH_L2 (0x1ULL << 56) 424 #define DBR_VALID (0x1ULL << 58) 425 #define DBR_TYPE_SQ (0x0ULL << 60) 426 #define DBR_TYPE_SRQ (0x2ULL << 60) 427 #define DBR_TYPE_CQ (0x4ULL << 60) 428 #define DBR_TYPE_NQ (0xaULL << 60) 429 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 430 431 #define DB_PF_OFFSET 0x10000 432 #define DB_VF_OFFSET 0x4000 433 434 #define BNXT_RSS_TBL_SIZE_P5 512U 435 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 436 #define BNXT_MAX_RSS_CTXTS_P5 \ 437 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 438 439 #define BNXT_MAX_QUEUE 8 440 #define BNXT_MAX_TQM_SP_RINGS 1 441 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 442 #define BNXT_MAX_TQM_FP_RINGS 9 443 #define BNXT_MAX_TQM_LEGACY_RINGS \ 444 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 445 #define BNXT_MAX_TQM_RINGS \ 446 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 447 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 448 #define BNXT_BACKING_STORE_CFG_LEN \ 449 sizeof(struct hwrm_func_backing_store_cfg_input) 450 #define BNXT_PAGE_SHFT 12 451 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 452 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 453 454 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG) 455 456 #define PTU_PTE_VALID 0x1UL 457 #define PTU_PTE_LAST 0x2UL 458 #define PTU_PTE_NEXT_TO_LAST 0x4UL 459 460 #define BNXT_CTX_MIN 1 461 #define BNXT_CTX_INV 0xffff 462 463 #define BNXT_CTX_INIT_VALID(flags) \ 464 ((flags) & \ 465 HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT) 466 467 struct bnxt_ring_mem_info { 468 int nr_pages; 469 int page_size; 470 uint32_t flags; 471 #define BNXT_RMEM_VALID_PTE_FLAG 1 472 #define BNXT_RMEM_RING_PTE_FLAG 2 473 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 474 475 void **pg_arr; 476 rte_iova_t *dma_arr; 477 const struct rte_memzone *mz; 478 479 uint64_t *pg_tbl; 480 rte_iova_t pg_tbl_map; 481 const struct rte_memzone *pg_tbl_mz; 482 483 int vmem_size; 484 void **vmem; 485 }; 486 487 struct bnxt_ctx_pg_info { 488 uint32_t entries; 489 void **ctx_pg_arr; 490 rte_iova_t *ctx_dma_arr; 491 struct bnxt_ring_mem_info ring_mem; 492 }; 493 494 struct bnxt_ctx_mem { 495 uint16_t type; 496 uint16_t entry_size; 497 uint32_t flags; 498 #define BNXT_CTX_MEM_TYPE_VALID \ 499 HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID 500 uint32_t instance_bmap; 501 uint8_t init_value; 502 uint8_t entry_multiple; 503 uint16_t init_offset; 504 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff 505 uint32_t max_entries; 506 uint32_t min_entries; 507 uint8_t last:1; 508 uint8_t split_entry_cnt; 509 #define BNXT_MAX_SPLIT_ENTRY 4 510 union { 511 struct { 512 uint32_t qp_l2_entries; 513 uint32_t qp_qp1_entries; 514 uint32_t qp_fast_qpmd_entries; 515 }; 516 uint32_t srq_l2_entries; 517 uint32_t cq_l2_entries; 518 uint32_t vnic_entries; 519 struct { 520 uint32_t mrav_av_entries; 521 uint32_t mrav_num_entries_units; 522 }; 523 uint32_t split[BNXT_MAX_SPLIT_ENTRY]; 524 }; 525 struct bnxt_ctx_pg_info *pg_info; 526 }; 527 528 #define BNXT_CTX_FLAG_INITED 0x01 529 530 struct bnxt_ctx_mem_info { 531 struct bnxt_ctx_mem *ctx_arr; 532 uint32_t supported_types; 533 uint32_t flags; 534 uint16_t types; 535 uint8_t tqm_fp_rings_count; 536 537 /* The following are used for V1 */ 538 uint32_t qp_max_entries; 539 uint16_t qp_min_qp1_entries; 540 uint16_t qp_max_l2_entries; 541 uint16_t qp_entry_size; 542 uint16_t srq_max_l2_entries; 543 uint32_t srq_max_entries; 544 uint16_t srq_entry_size; 545 uint16_t cq_max_l2_entries; 546 uint32_t cq_max_entries; 547 uint16_t cq_entry_size; 548 uint16_t vnic_max_vnic_entries; 549 uint16_t vnic_max_ring_table_entries; 550 uint16_t vnic_entry_size; 551 uint32_t stat_max_entries; 552 uint16_t stat_entry_size; 553 uint16_t tqm_entry_size; 554 uint32_t tqm_min_entries_per_ring; 555 uint32_t tqm_max_entries_per_ring; 556 uint32_t mrav_max_entries; 557 uint16_t mrav_entry_size; 558 uint16_t tim_entry_size; 559 uint32_t tim_max_entries; 560 uint8_t tqm_entries_multiple; 561 uint8_t mpc_tqm_entries_multiple; 562 uint32_t mpc_tqm_max_num_entries; 563 uint32_t mpc_tqm_min_num_entries; 564 uint32_t instance_bit_map; /* MPC TQM: TE_CFA(2), RE_CFA (3) */ 565 uint16_t mpc_tqm_entry_size; 566 uint8_t ctx_init_value; 567 uint8_t ctx_init_offset; 568 569 struct bnxt_ctx_pg_info qp_mem; 570 struct bnxt_ctx_pg_info srq_mem; 571 struct bnxt_ctx_pg_info cq_mem; 572 struct bnxt_ctx_pg_info vnic_mem; 573 struct bnxt_ctx_pg_info stat_mem; 574 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; 575 #define BNXT_MAX_BMAP 0x5 576 struct bnxt_ctx_pg_info *mpc_tqm_mem[BNXT_MAX_BMAP]; 577 }; 578 579 struct bnxt_ctx_mem_buf_info { 580 void *va; 581 rte_iova_t dma; 582 uint16_t ctx_id; 583 size_t size; 584 }; 585 586 /* Maximum Firmware Reset bail out value in milliseconds */ 587 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 588 /* Minimum time required for the firmware readiness in milliseconds */ 589 #define BNXT_MIN_FW_READY_TIMEOUT 2000 590 /* Frequency for the firmware readiness check in milliseconds */ 591 #define BNXT_FW_READY_WAIT_INTERVAL 100 592 593 #define US_PER_MS 1000 594 #define NS_PER_US 1000 595 596 struct bnxt_error_recovery_info { 597 /* All units in milliseconds */ 598 uint32_t driver_polling_freq; 599 uint32_t primary_func_wait_period; 600 uint32_t normal_func_wait_period; 601 uint32_t primary_func_wait_period_after_reset; 602 uint32_t max_bailout_time_after_reset; 603 #define BNXT_FW_STATUS_REG 0 604 #define BNXT_FW_HEARTBEAT_CNT_REG 1 605 #define BNXT_FW_RECOVERY_CNT_REG 2 606 #define BNXT_FW_RESET_INPROG_REG 3 607 #define BNXT_FW_STATUS_REG_CNT 4 608 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 609 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 610 uint32_t reset_inprogress_reg_mask; 611 #define BNXT_NUM_RESET_REG 16 612 uint8_t reg_array_cnt; 613 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 614 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 615 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 616 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 617 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 618 #define BNXT_FLAG_PRIMARY_FUNC BIT(2) 619 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 620 uint32_t flags; 621 622 uint32_t last_heart_beat; 623 uint32_t last_reset_counter; 624 }; 625 626 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 627 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 628 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 629 #define BNXT_IF_CHANGE_RETRY_COUNT 40 630 631 struct bnxt_mark_info { 632 uint32_t mark_id; 633 bool valid; 634 }; 635 636 struct bnxt_rep_info { 637 struct rte_eth_dev *vfr_eth_dev; 638 pthread_mutex_t vfr_start_lock; 639 bool conduit_valid; 640 }; 641 642 /* address space location of register */ 643 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 644 /* register is located in PCIe config space */ 645 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 646 /* register is located in GRC address space */ 647 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 648 /* register is located in BAR0 */ 649 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 650 /* register is located in BAR1 */ 651 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 652 653 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 654 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 655 656 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 657 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 658 659 #define BNXT_GRCP_BASE_MASK 0xfffff000 660 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 661 662 #define BNXT_FW_STATUS_HEALTHY 0x8000 663 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 664 665 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 666 667 struct bnxt_flow_stat_info { 668 uint16_t max_fc; 669 uint16_t flow_count; 670 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 671 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 672 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 673 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 674 }; 675 676 struct bnxt_ring_stats { 677 /* Number of transmitted unicast packets */ 678 uint64_t tx_ucast_pkts; 679 /* Number of transmitted multicast packets */ 680 uint64_t tx_mcast_pkts; 681 /* Number of transmitted broadcast packets */ 682 uint64_t tx_bcast_pkts; 683 /* Number of packets discarded in transmit path */ 684 uint64_t tx_discard_pkts; 685 /* Number of packets in transmit path with error */ 686 uint64_t tx_error_pkts; 687 /* Number of transmitted bytes for unicast traffic */ 688 uint64_t tx_ucast_bytes; 689 /* Number of transmitted bytes for multicast traffic */ 690 uint64_t tx_mcast_bytes; 691 /* Number of transmitted bytes for broadcast traffic */ 692 uint64_t tx_bcast_bytes; 693 /* Number of received unicast packets */ 694 uint64_t rx_ucast_pkts; 695 /* Number of received multicast packets */ 696 uint64_t rx_mcast_pkts; 697 /* Number of received broadcast packets */ 698 uint64_t rx_bcast_pkts; 699 /* Number of packets discarded in receive path */ 700 uint64_t rx_discard_pkts; 701 /* Number of packets in receive path with errors */ 702 uint64_t rx_error_pkts; 703 /* Number of received bytes for unicast traffic */ 704 uint64_t rx_ucast_bytes; 705 /* Number of received bytes for multicast traffic */ 706 uint64_t rx_mcast_bytes; 707 /* Number of received bytes for broadcast traffic */ 708 uint64_t rx_bcast_bytes; 709 /* Number of aggregated unicast packets */ 710 uint64_t rx_agg_pkts; 711 /* Number of aggregated unicast bytes */ 712 uint64_t rx_agg_bytes; 713 /* Number of aggregation events */ 714 uint64_t rx_agg_events; 715 /* Number of aborted aggregations */ 716 uint64_t rx_agg_aborts; 717 }; 718 719 struct bnxt_ring_stats_ext { 720 /* Number of received unicast packets */ 721 uint64_t rx_ucast_pkts; 722 /* Number of received multicast packets */ 723 uint64_t rx_mcast_pkts; 724 /* Number of received broadcast packets */ 725 uint64_t rx_bcast_pkts; 726 /* Number of discarded packets on receive path */ 727 uint64_t rx_discard_pkts; 728 /* Number of packets on receive path with error */ 729 uint64_t rx_error_pkts; 730 /* Number of received bytes for unicast traffic */ 731 uint64_t rx_ucast_bytes; 732 /* Number of received bytes for multicast traffic */ 733 uint64_t rx_mcast_bytes; 734 /* Number of received bytes for broadcast traffic */ 735 uint64_t rx_bcast_bytes; 736 /* Number of transmitted unicast packets */ 737 uint64_t tx_ucast_pkts; 738 /* Number of transmitted multicast packets */ 739 uint64_t tx_mcast_pkts; 740 /* Number of transmitted broadcast packets */ 741 uint64_t tx_bcast_pkts; 742 /* Number of packets on transmit path with error */ 743 uint64_t tx_error_pkts; 744 /* Number of discarded packets on transmit path */ 745 uint64_t tx_discard_pkts; 746 /* Number of transmitted bytes for unicast traffic */ 747 uint64_t tx_ucast_bytes; 748 /* Number of transmitted bytes for multicast traffic */ 749 uint64_t tx_mcast_bytes; 750 /* Number of transmitted bytes for broadcast traffic */ 751 uint64_t tx_bcast_bytes; 752 /* Number of TPA eligible packets */ 753 uint64_t rx_tpa_eligible_pkt; 754 /* Number of TPA eligible bytes */ 755 uint64_t rx_tpa_eligible_bytes; 756 /* Number of TPA packets */ 757 uint64_t rx_tpa_pkt; 758 /* Number of TPA bytes */ 759 uint64_t rx_tpa_bytes; 760 /* Number of TPA errors */ 761 uint64_t rx_tpa_errors; 762 /* Number of TPA events */ 763 uint64_t rx_tpa_events; 764 }; 765 766 enum bnxt_session_type { 767 BNXT_SESSION_TYPE_REGULAR = 0, 768 BNXT_SESSION_TYPE_SHARED_COMMON, 769 BNXT_SESSION_TYPE_SHARED_WC, 770 BNXT_SESSION_TYPE_LAST 771 }; 772 773 #define BNXT_MAX_BUFFER_SPLIT_SEGS 2 774 #define BNXT_MULTI_POOL_BUF_SPLIT_CAP 1 775 #define BNXT_BUF_SPLIT_OFFSET_CAP 1 776 #define BNXT_BUF_SPLIT_ALIGN_CAP 0 777 778 struct bnxt { 779 void *bar0; 780 781 struct rte_eth_dev *eth_dev; 782 struct rte_pci_device *pdev; 783 void *doorbell_base; 784 int legacy_db_size; 785 786 uint32_t flags; 787 #define BNXT_FLAG_REGISTERED BIT(0) 788 #define BNXT_FLAG_VF BIT(1) 789 #define BNXT_FLAG_PORT_STATS BIT(2) 790 #define BNXT_FLAG_JUMBO BIT(3) 791 #define BNXT_FLAG_SHORT_CMD BIT(4) 792 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 793 #define BNXT_FLAG_MULTI_HOST BIT(7) 794 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 795 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 796 #define BNXT_FLAG_KONG_MB_EN BIT(10) 797 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 798 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 799 #define BNXT_FLAG_CHIP_P5 BIT(13) 800 #define BNXT_FLAG_STINGRAY BIT(14) 801 #define BNXT_FLAG_FW_RESET BIT(15) 802 #define BNXT_FLAG_FATAL_ERROR BIT(16) 803 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 804 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 805 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 806 #define BNXT_FLAG_NEW_RM BIT(20) 807 #define BNXT_FLAG_NPAR_PF BIT(21) 808 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 809 #define BNXT_FLAG_FC_THREAD BIT(23) 810 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 811 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 812 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 813 #define BNXT_FLAG_GFID_ENABLE BIT(27) 814 #define BNXT_FLAG_CHIP_P7 BIT(28) 815 #define BNXT_FLAG_FW_TIMEDOUT BIT(29) 816 #define BNXT_FLAG_RFS_NEEDS_VNIC BIT(30) 817 #define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(31) 818 #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) 819 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 820 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 821 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 822 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 823 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 824 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 825 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 826 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 827 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 828 #define BNXT_CHIP_P7(bp) ((bp)->flags & BNXT_FLAG_CHIP_P7) 829 #define BNXT_CHIP_P5_P7(bp) (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp)) 830 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 831 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5_P7(bp) 832 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5_P7(bp)) 833 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 834 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 835 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 836 #define BNXT_P7_MAX_NQ_RING_CNT 512 837 #define BNXT_P7_CQ_MAX_L2_ENT 8192 838 839 uint32_t flags2; 840 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) 841 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) 842 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ 843 ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) 844 #define BNXT_FLAGS2_TESTPMD_EN BIT(3) 845 #define BNXT_TESTPMD_EN(bp) \ 846 ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN) 847 848 uint16_t multi_host_pf_pci_id; 849 uint16_t chip_num; 850 #define BNXT_FLAGS2_MULTIROOT_EN BIT(4) 851 #define BNXT_MULTIROOT_EN(bp) \ 852 ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) 853 854 #define BNXT_FLAGS2_COMPRESSED_RX_CQE BIT(5) 855 uint32_t fw_cap; 856 #define BNXT_FW_CAP_HOT_RESET BIT(0) 857 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 858 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 859 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 860 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 861 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 862 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 863 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 864 #define BNXT_FW_CAP_TRUFLOW_EN BIT(8) 865 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9) 866 #define BNXT_FW_CAP_TX_COAL_CMPL BIT(10) 867 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(11) 868 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT(12) 869 #define BNXT_FW_CAP_RX_RATE_PROFILE BIT(17) 870 #define BNXT_FW_BACKING_STORE_V2_EN(bp) \ 871 ((bp)->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2) 872 #define BNXT_FW_BACKING_STORE_V1_EN(bp) \ 873 (BNXT_CHIP_P5_P7((bp)) && \ 874 (bp)->hwrm_spec_code >= HWRM_VERSION_1_9_2 && \ 875 !BNXT_VF((bp))) 876 #define BNXT_FW_CAP_UDP_GSO BIT(13) 877 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\ 878 (bp)->app_id != 0xFF) 879 880 pthread_mutex_t flow_lock; 881 882 uint32_t vnic_cap_flags; 883 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 884 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 885 #define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) 886 #define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3) 887 #define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 888 #define BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF BIT(4) 889 #define BNXT_VNIC_CAP_XOR_MODE BIT(5) 890 #define BNXT_VNIC_CAP_CHKSM_MODE BIT(6) 891 #define BNXT_VNIC_CAP_IPV6_FLOW_LABEL_MODE BIT(7) 892 #define BNXT_VNIC_CAP_L2_CQE_MODE BIT(8) 893 #define BNXT_VNIC_CAP_AH_SPI4_CAP BIT(9) 894 #define BNXT_VNIC_CAP_AH_SPI6_CAP BIT(10) 895 #define BNXT_VNIC_CAP_ESP_SPI4_CAP BIT(11) 896 #define BNXT_VNIC_CAP_ESP_SPI6_CAP BIT(12) 897 #define BNXT_VNIC_CAP_AH_SPI_CAP (BNXT_VNIC_CAP_AH_SPI4_CAP | BNXT_VNIC_CAP_AH_SPI6_CAP) 898 #define BNXT_VNIC_CAP_ESP_SPI_CAP (BNXT_VNIC_CAP_ESP_SPI4_CAP | BNXT_VNIC_CAP_ESP_SPI6_CAP) 899 #define BNXT_VNIC_CAP_VNIC_TUNNEL_TPA BIT(13) 900 901 unsigned int rx_nr_rings; 902 unsigned int rx_cp_nr_rings; 903 unsigned int rx_num_qs_per_vnic; 904 struct bnxt_rx_queue **rx_queues; 905 const void *rx_mem_zone; 906 struct rx_port_stats *hw_rx_port_stats; 907 rte_iova_t hw_rx_port_stats_map; 908 struct rx_port_stats_ext *hw_rx_port_stats_ext; 909 rte_iova_t hw_rx_port_stats_ext_map; 910 uint16_t fw_rx_port_stats_ext_size; 911 912 unsigned int tx_nr_rings; 913 unsigned int tx_cp_nr_rings; 914 struct bnxt_tx_queue **tx_queues; 915 const void *tx_mem_zone; 916 struct tx_port_stats *hw_tx_port_stats; 917 rte_iova_t hw_tx_port_stats_map; 918 struct tx_port_stats_ext *hw_tx_port_stats_ext; 919 rte_iova_t hw_tx_port_stats_ext_map; 920 uint16_t fw_tx_port_stats_ext_size; 921 922 /* Default completion ring */ 923 struct bnxt_cp_ring_info *async_cp_ring; 924 struct bnxt_cp_ring_info *rxtx_nq_ring; 925 uint32_t max_ring_grps; 926 struct bnxt_ring_grp_info *grp_info; 927 928 uint16_t nr_vnics; 929 930 struct bnxt_vnic_info *vnic_info; 931 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 932 const struct rte_memzone *vnic_rss_mz; 933 934 struct bnxt_filter_info *filter_info; 935 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 936 937 struct bnxt_irq *irq_tbl; 938 939 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 940 941 uint16_t chimp_cmd_seq; 942 uint16_t kong_cmd_seq; 943 void *hwrm_cmd_resp_addr; 944 rte_iova_t hwrm_cmd_resp_dma_addr; 945 void *hwrm_short_cmd_req_addr; 946 rte_iova_t hwrm_short_cmd_req_dma_addr; 947 rte_spinlock_t hwrm_lock; 948 /* synchronize between dev_configure_op and int handler */ 949 pthread_mutex_t def_cp_lock; 950 /* synchronize between dev_start_op and async evt handler 951 * Locking sequence in async evt handler will be 952 * def_cp_lock 953 * health_check_lock 954 */ 955 pthread_mutex_t health_check_lock; 956 /* synchronize between dev_stop/dev_close_op and 957 * error recovery thread triggered as part of 958 * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 959 */ 960 pthread_mutex_t err_recovery_lock; 961 uint16_t max_req_len; 962 uint16_t max_resp_len; 963 uint16_t hwrm_max_ext_req_len; 964 965 /* default command timeout value of 500ms */ 966 #define DFLT_HWRM_CMD_TIMEOUT 500000 967 #define PCI_FUNC_RESET_WAIT_TIMEOUT 1500000 968 /* short command timeout value of 50ms */ 969 #define SHORT_HWRM_CMD_TIMEOUT 50000 970 /* default HWRM request timeout value */ 971 uint32_t hwrm_cmd_timeout; 972 973 struct bnxt_link_info *link_info; 974 struct bnxt_cos_queue_info *rx_cos_queue; 975 struct bnxt_cos_queue_info *tx_cos_queue; 976 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 977 uint8_t rx_cosq_cnt; 978 uint8_t max_tc; 979 uint8_t max_lltc; 980 uint8_t max_q; 981 982 uint16_t fw_fid; 983 uint16_t max_rsscos_ctx; 984 uint16_t max_cp_rings; 985 uint16_t max_tx_rings; 986 uint16_t max_rx_rings; 987 #define MAX_STINGRAY_RINGS 236U 988 #define BNXT_MAX_VF_REP_RINGS 8U 989 990 uint16_t max_nq_rings; 991 uint16_t max_l2_ctx; 992 uint16_t max_rx_em_flows; 993 uint16_t max_vnics; 994 #define BNXT_MAX_VNICS_COS_CLASSIFY 8 995 uint16_t max_stat_ctx; 996 uint16_t max_tpa_v2; 997 uint16_t first_vf_id; 998 uint16_t vlan; 999 #define BNXT_OUTER_TPID_MASK 0x0000ffff 1000 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 1001 #define BNXT_OUTER_TPID_BD_SHFT 16 1002 uint32_t outer_tpid_bd; 1003 struct bnxt_pf_info *pf; 1004 struct bnxt_parent_info *parent; 1005 uint8_t port_cnt; 1006 uint8_t vxlan_port_cnt; 1007 uint8_t geneve_port_cnt; 1008 uint8_t ecpri_port_cnt; 1009 uint8_t l2_etype_tunnel_cnt; 1010 uint16_t vxlan_port; 1011 uint16_t vxlan_ip_port; 1012 uint16_t geneve_port; 1013 uint16_t ecpri_port; 1014 uint16_t vxlan_fw_dst_port_id; 1015 uint16_t geneve_fw_dst_port_id; 1016 uint16_t ecpri_fw_dst_port_id; 1017 #define BNXT_L2_ETYPE_TUNNEL_ID 0xFFFF /* CUSTOM L2 ENCAP - VF representors */ 1018 uint16_t l2_etype_tunnel_id; 1019 uint16_t ecpri_upar_in_use; 1020 uint8_t l2_etype_upar_in_use; 1021 uint8_t vxlan_ip_upar_in_use; 1022 uint32_t fw_ver; 1023 uint32_t hwrm_spec_code; 1024 1025 struct bnxt_led_info *leds; 1026 uint8_t ieee_1588; 1027 struct bnxt_ptp_cfg *ptp_cfg; 1028 uint8_t ptp_all_rx_tstamp; 1029 uint16_t vf_resv_strategy; 1030 struct bnxt_ctx_mem_info *ctx; 1031 1032 uint16_t fw_reset_min_msecs; 1033 uint16_t fw_reset_max_msecs; 1034 uint16_t switch_domain_id; 1035 uint16_t num_reps; 1036 struct bnxt_rep_info *rep_info; 1037 uint16_t *cfa_code_map; 1038 /* Device Serial Number */ 1039 uint8_t dsn[BNXT_DEVICE_SERIAL_NUM_SIZE]; 1040 /* Struct to hold adapter error recovery related info */ 1041 struct bnxt_error_recovery_info *recovery_info; 1042 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 1043 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 1044 #define BNXT_FLOW_ID_MASK 0x0000ffff 1045 struct bnxt_mark_info *mark_table; 1046 1047 #define BNXT_SVIF_INVALID 0xFFFF 1048 uint16_t func_svif; 1049 uint16_t port_svif; 1050 1051 struct tf tfp[BNXT_SESSION_TYPE_LAST]; 1052 struct tfc tfcp; 1053 struct bnxt_ulp_context *ulp_ctx; 1054 struct bnxt_flow_stat_info *flow_stat; 1055 uint16_t max_num_kflows; 1056 uint8_t app_id; 1057 uint32_t tx_cfa_action; 1058 struct bnxt_ring_stats *prev_rx_ring_stats; 1059 struct bnxt_ring_stats *prev_tx_ring_stats; 1060 struct bnxt_ring_stats_ext *prev_rx_ring_stats_ext; 1061 struct bnxt_ring_stats_ext *prev_tx_ring_stats_ext; 1062 struct bnxt_vnic_queue_db vnic_queue_db; 1063 1064 struct bnxt_mpc *mpc; 1065 #define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr) 1066 struct rte_ether_addr *mcast_addr_list; 1067 rte_iova_t mc_list_dma_addr; 1068 uint32_t nb_mc_addr; 1069 #define BNXT_DFLT_MAX_MC_ADDR 16 /* for compatibility with older firmware */ 1070 uint32_t max_mcast_addr; /* maximum number of mcast filters supported */ 1071 1072 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1073 uint16_t tunnel_disable_flag; /* tunnel stateless offloads status */ 1074 uint8_t chip_rev; 1075 }; 1076 1077 static 1078 inline uint16_t bnxt_max_rings(struct bnxt *bp) 1079 { 1080 uint16_t max_tx_rings = bp->max_tx_rings; 1081 uint16_t max_rx_rings = bp->max_rx_rings; 1082 uint16_t max_cp_rings = bp->max_cp_rings; 1083 uint16_t max_rings; 1084 1085 /* For the sake of symmetry: 1086 * max Tx rings == max Rx rings, one stat ctx for each. 1087 */ 1088 if (BNXT_STINGRAY(bp)) { 1089 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 1090 MAX_STINGRAY_RINGS), 1091 bp->max_stat_ctx / 2U); 1092 } else { 1093 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 1094 bp->max_stat_ctx / 2U); 1095 } 1096 1097 /* 1098 * RSS table size in P5 is 512. 1099 * Cap max Rx rings to the same value for RSS. 1100 */ 1101 if (BNXT_CHIP_P5_P7(bp)) 1102 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5); 1103 1104 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 1105 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 1106 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 1107 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 1108 1109 return max_rings; 1110 } 1111 1112 static inline bool 1113 bnxt_compressed_rx_cqe_mode_enabled(struct bnxt *bp) 1114 { 1115 uint64_t rx_offloads = bp->eth_dev->data->dev_conf.rxmode.offloads; 1116 1117 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_L2_CQE_MODE && 1118 bp->flags2 & BNXT_FLAGS2_COMPRESSED_RX_CQE && 1119 !(rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) && 1120 !(rx_offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) && 1121 !bp->num_reps && !bp->ieee_1588) 1122 return true; 1123 1124 return false; 1125 } 1126 1127 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 1128 1129 /** 1130 * Structure to store private data for each VF representor instance 1131 */ 1132 struct bnxt_representor { 1133 uint16_t switch_domain_id; 1134 uint16_t vf_id; 1135 #define BNXT_REP_IS_PF BIT(0) 1136 #define BNXT_REP_Q_R2F_VALID BIT(1) 1137 #define BNXT_REP_Q_F2R_VALID BIT(2) 1138 #define BNXT_REP_FC_R2F_VALID BIT(3) 1139 #define BNXT_REP_FC_F2R_VALID BIT(4) 1140 #define BNXT_REP_BASED_PF_VALID BIT(5) 1141 uint32_t flags; 1142 uint16_t fw_fid; 1143 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 1144 uint16_t dflt_vnic_id; 1145 uint16_t svif; 1146 uint32_t vfr_tx_cfa_action; 1147 uint8_t parent_pf_idx; /* Logical PF index */ 1148 uint32_t dpdk_port_id; 1149 uint32_t rep_based_pf; 1150 uint8_t rep_q_r2f; 1151 uint8_t rep_q_f2r; 1152 uint8_t rep_fc_r2f; 1153 uint8_t rep_fc_f2r; 1154 /* Private data store of associated PF/Trusted VF */ 1155 struct rte_eth_dev *parent_dev; 1156 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 1157 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 1158 struct bnxt_rx_queue **rx_queues; 1159 unsigned int rx_nr_rings; 1160 unsigned int tx_nr_rings; 1161 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 1162 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 1163 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 1164 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 1165 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 1166 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 1167 }; 1168 1169 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 1170 #define BNXT_REP_BASED_PF(vfr_bp) \ 1171 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 1172 1173 struct bnxt_vf_rep_tx_queue { 1174 struct bnxt_tx_queue *txq; 1175 struct bnxt_representor *bp; 1176 }; 1177 1178 #define I2C_DEV_ADDR_A0 0xa0 1179 #define I2C_DEV_ADDR_A2 0xa2 1180 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 1181 #define SFF_MODULE_ID_SFP 0x3 1182 #define SFF_MODULE_ID_QSFP 0xc 1183 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1184 #define SFF_MODULE_ID_QSFP28 0x11 1185 #define SFF8636_FLATMEM_OFFSET 0x2 1186 #define SFF8636_FLATMEM_MASK 0x4 1187 #define SFF8636_OPT_PAGES_OFFSET 0xc3 1188 #define SFF8636_PAGE1_MASK 0x40 1189 #define SFF8636_PAGE2_MASK 0x80 1190 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1191 1192 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 1193 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1194 bool exp_link_status); 1195 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 1196 int is_bnxt_in_error(struct bnxt *bp); 1197 1198 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 1199 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 1200 void bnxt_schedule_fw_health_check(struct bnxt *bp); 1201 1202 bool is_bnxt_supported(struct rte_eth_dev *dev); 1203 bool bnxt_stratus_device(struct bnxt *bp); 1204 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 1205 uint16_t bnxt_rss_ctxts(const struct bnxt *bp); 1206 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 1207 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1208 int wait_to_complete); 1209 int 1210 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1211 struct rte_eth_udp_tunnel *udp_tunnel); 1212 int 1213 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1214 struct rte_eth_udp_tunnel *udp_tunnel); 1215 1216 extern const struct rte_flow_ops bnxt_flow_ops; 1217 extern const struct rte_flow_ops bnxt_flow_meter_ops; 1218 1219 #define bnxt_acquire_flow_lock(bp) \ 1220 pthread_mutex_lock(&(bp)->flow_lock) 1221 1222 #define bnxt_release_flow_lock(bp) \ 1223 pthread_mutex_unlock(&(bp)->flow_lock) 1224 1225 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 1226 if ((vnic_id) >= (bp)->max_vnics) { \ 1227 rte_flow_error_set(error, \ 1228 EINVAL, \ 1229 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 1230 NULL, \ 1231 "Group id is invalid!"); \ 1232 rc = -rte_errno; \ 1233 goto ret; \ 1234 } \ 1235 } while (0) 1236 1237 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 1238 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1239 1240 extern int bnxt_logtype_driver; 1241 #define RTE_LOGTYPE_BNXT bnxt_logtype_driver 1242 #define PMD_DRV_LOG_LINE(level, ...) \ 1243 RTE_LOG_LINE_PREFIX(level, BNXT, "%s(): ", __func__, __VA_ARGS__) 1244 1245 #define BNXT_LINK_SPEEDS_V2_OPTIONS(f) \ 1246 ((f) & HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED) 1247 #define BNXT_LINK_SPEEDS_V2_VF(bp) (BNXT_VF((bp)) && ((bp)->link_info->option_flags)) 1248 #define BNXT_LINK_SPEEDS_V2(bp) (((bp)->link_info) && (((bp)->link_info->support_speeds_v2) || \ 1249 BNXT_LINK_SPEEDS_V2_VF((bp)))) 1250 #define BNXT_MAX_SPEED_LANES 8 1251 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 1252 int32_t bnxt_ulp_port_init(struct bnxt *bp); 1253 void bnxt_ulp_port_deinit(struct bnxt *bp); 1254 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 1255 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 1256 int32_t 1257 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 1258 int32_t 1259 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 1260 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 1261 1262 void bnxt_cancel_fc_thread(struct bnxt *bp); 1263 void bnxt_flow_cnt_alarm_cb(void *arg); 1264 int bnxt_flow_stats_req(struct bnxt *bp); 1265 int bnxt_flow_stats_cnt(struct bnxt *bp); 1266 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 1267 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 1268 const struct rte_flow_ops **ops); 1269 int bnxt_dev_start_op(struct rte_eth_dev *eth_dev); 1270 int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev); 1271 void bnxt_handle_vf_cfg_change(void *arg); 1272 int bnxt_flow_meter_ops_get(struct rte_eth_dev *eth_dev, void *arg); 1273 struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp); 1274 uint64_t bnxt_eth_rss_support(struct bnxt *bp); 1275 uint16_t bnxt_parse_eth_link_speed_v2(struct bnxt *bp); 1276 struct bnxt *bnxt_pmd_get_bp(uint16_t port); 1277 #endif 1278