1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Advanced Micro Devices, Inc. All rights reserved.
3 */
4 #ifndef RTE_ETH_AXGBE_REGS_H_
5 #define RTE_ETH_AXGBE_REGS_H_
6
7 #include "axgbe_common.h"
8
9 static const uint32_t dma_reg_tbl[] = {
10 DMA_MR, /* DMA Mode */
11 DMA_SBMR, /* DMA Sys Bus Mode */
12 DMA_ISR, /* DMA Interrupt Status */
13 DMA_AXIARCR, /* DMA AXI Tx AR ACE Ctrl */
14 DMA_AXIAWCR, /* DMA AXI Rx AW ACE Ctrl */
15 DMA_AXIAWRCR, /* DMA AXI TxRx AWR ACE Ctrl */
16 DMA_DSR0, /* DMA Debug Status0 */
17 DMA_DSR1, /* DMA Debug Status1 */
18 EDMA_TX_CONTROL,/* DMA Tx EDMA Ctrl */
19 EDMA_RX_CONTROL,/* DMA Rx EDMA Ctrl */
20 };
21
22 static const uint32_t dma_txch_reg_tbl[] = {
23 DMA_CH_CR, /* DMA Channel Ctrl */
24 DMA_CH_TCR, /* DMA Tx Ctrl */
25 DMA_CH_TDLR_HI, /* DMA TxDescList HAddr */
26 DMA_CH_TDLR_LO, /* DMA TxDescList LAddr */
27 DMA_CH_TDTR_LO, /* DMA TxDescTail LAddr */
28 DMA_CH_TDRLR, /* DMA TxDescRing Length */
29 DMA_CH_IER, /* DMA Interrupt Enable */
30 DMA_CH_CATDR_LO,/* DMA CurrApp TxDesc LAddr */
31 DMA_CH_CATBR_HI,/* DMA CurrApp TxBuf HAddr */
32 DMA_CH_CATBR_LO,/* DMA CurrApp TxBuf LAddr */
33 DMA_CH_SR, /* DMA Channel Status */
34 };
35
36 static const uint32_t dma_rxch_reg_tbl[] = {
37 DMA_CH_RCR, /* DMA Rx Ctrl */
38 DMA_CH_RDLR_HI, /* DMA RxDescList HAddr */
39 DMA_CH_RDLR_LO, /* DMA RxDescList LAddr */
40 DMA_CH_RDTR_LO, /* DMA RxDescTail LAddr */
41 DMA_CH_RDRLR, /* DMA RxDescRing Length */
42 DMA_CH_RIWT, /* DMA Rx Interrupt WatchDog Timer */
43 DMA_CH_CARDR_LO,/* DMA CurrApp RxDesc LAddr */
44 DMA_CH_CARBR_HI,/* DMA CurrApp RxBuf HAddr */
45 DMA_CH_CARBR_LO,/* DMA CurrApp RxBuf LAddr */
46
47 };
48
49 static const uint32_t mtl_reg_tbl[] = {
50 MTL_OMR, /* MTL Operation Mode */
51 MTL_FDCR, /* MTL FIFO Debug Ctrl */
52 MTL_FDSR, /* MTL FIFO Debug Status */
53 MTL_FDDR, /* MTL FIFO Debug Data */
54 MTL_ISR, /* MTL Interrupt Status */
55 MTL_RQDCM0R, /* MTL RxQ DMA Map0 */
56 MTL_TCPM0R, /* MTL TC Prty Map0 */
57 MTL_TCPM1R, /* MTL TC Prty Map1 */
58 };
59
60 static const uint32_t mtl_txq_reg_tbl[] = {
61 MTL_Q_TQOMR, /* MTL TxQ Operation Mode */
62 MTL_Q_TQUR, /* MTL TxQ Underflow */
63 MTL_Q_TQDR, /* MTL TxQ Debug */
64 MTL_Q_IER, /* MTL Q Interrupt Enable */
65 MTL_Q_ISR, /* MTL Q Interrupt Status */
66 };
67
68 static const uint32_t mtl_rxq_reg_tbl[] = {
69 MTL_Q_RQOMR, /* MTL RxQ Operation Mode */
70 MTL_Q_RQMPOCR, /* MTL RxQ Missed Pkt OverFlow Cnt */
71 MTL_Q_RQDR, /* MTL RxQ Debug */
72 MTL_Q_RQFCR, /* MTL RxQ Flow Control */
73 };
74
75 static const uint32_t mac_reg_tbl[] = {
76 MAC_TCR, /* MAC Tx Config */
77 MAC_RCR, /* MAC Rx Config */
78 MAC_PFR, /* MAC Packet Filter */
79 MAC_WTR, /* MAC WatchDog Timeout */
80 MAC_HTR0, /* MAC Hash Table0 */
81 MAC_VLANTR, /* MAC VLAN Tag Ctrl */
82 MAC_VLANHTR, /* MAC VLAN Hash Table */
83 MAC_VLANIR, /* MAC VLAN Incl */
84 MAC_IVLANIR, /* MAC Inner VLAN Incl */
85 MAC_RETMR, /* MAC Rx Eth Type Match */
86 MAC_Q0TFCR, /* MAC Q0 Tx Flow Ctrl */
87 MAC_RFCR, /* MAC Rx Flow Ctrl */
88 MAC_RQC0R, /* MAC RxQ Ctrl0 */
89 MAC_RQC1R, /* MAC RxQ Ctrl1 */
90 MAC_RQC2R, /* MAC RxQ Ctrl2 */
91 MAC_RQC3R, /* MAC RxQ Ctrl3 */
92 MAC_ISR, /* MAC Interrupt Status */
93 MAC_IER, /* MAC Interrupt Enable */
94 MAC_RTSR, /* MAC Rx Tx Status */
95 MAC_PMTCSR, /* MAC PMT Ctrl Status */
96 MAC_RWKPFR, /* MAC RWK Packet Filter */
97 MAC_LPICSR, /* MAC LPI Ctrl Status */
98 MAC_LPITCR, /* MAC LPI Timers Ctrl */
99 MAC_VR, /* MAC Version */
100 MAC_DR, /* MAC Debug Status */
101 MAC_HWF0R, /* MAC HW Feature0 */
102 MAC_HWF1R, /* MAC HW Feature1 */
103 MAC_HWF2R, /* MAC HW Feature2 */
104 MAC_MDIOSCAR, /* MDIO Single Cmd Addr */
105 MAC_MDIOSCCDR, /* MDIO Single Cmd/Data */
106 MAC_MDIOISR, /* MDIO Interrupt Status */
107 MAC_MDIOIER, /* MDIO Interrupt Enable */
108 MAC_MDIOCL22R, /* MDIO Clause22 Port */
109 MAC_GPIOCR, /* MAC GPIO Ctrl */
110 MAC_GPIOSR, /* MAC GPIO Status */
111 MAC_RSSCR, /* MAC RSS Ctrl */
112 MAC_RSSAR, /* MAC RSS Addr */
113 };
114
115 /* MAC Address Register Table */
116 static const uint32_t mac_addr_reg_tbl[] = {
117 MAC_MACAHR(0), MAC_MACALR(0), MAC_MACAHR(1), MAC_MACALR(1),
118 MAC_MACAHR(2), MAC_MACALR(2), MAC_MACAHR(3), MAC_MACALR(3),
119 MAC_MACAHR(4), MAC_MACALR(4), MAC_MACAHR(5), MAC_MACALR(5),
120 MAC_MACAHR(6), MAC_MACALR(6), MAC_MACAHR(7), MAC_MACALR(7),
121 MAC_MACAHR(8), MAC_MACALR(8), MAC_MACAHR(9), MAC_MACALR(9),
122 MAC_MACAHR(10), MAC_MACALR(10), MAC_MACAHR(11), MAC_MACALR(11),
123 MAC_MACAHR(12), MAC_MACALR(12), MAC_MACAHR(13), MAC_MACALR(13),
124 MAC_MACAHR(14), MAC_MACALR(14), MAC_MACAHR(15), MAC_MACALR(15),
125 MAC_MACAHR(16), MAC_MACALR(16), MAC_MACAHR(17), MAC_MACALR(17),
126 MAC_MACAHR(18), MAC_MACALR(18), MAC_MACAHR(19), MAC_MACALR(19),
127 MAC_MACAHR(20), MAC_MACALR(20), MAC_MACAHR(21), MAC_MACALR(21),
128 MAC_MACAHR(22), MAC_MACALR(22), MAC_MACAHR(23), MAC_MACALR(23),
129 MAC_MACAHR(24), MAC_MACALR(24), MAC_MACAHR(25), MAC_MACALR(25),
130 MAC_MACAHR(26), MAC_MACALR(26), MAC_MACAHR(27), MAC_MACALR(27),
131 MAC_MACAHR(28), MAC_MACALR(28), MAC_MACAHR(29), MAC_MACALR(29),
132 MAC_MACAHR(30), MAC_MACALR(30), MAC_MACAHR(31), MAC_MACALR(31),
133
134 };
135
136 static const uint32_t mac_ieee1558_reg_tbl[] = {
137 MAC_RSSDR, /* MAC RSS Data */
138 MAC_TSCR, /* MAC TimeStamp Ctrl */
139 MAC_SSIR, /* MAC Sub Second Incr */
140 MAC_STSR, /* MAC Sys Time Secs */
141 MAC_STNR, /* MAC Sys Time NSecs */
142 MAC_STSUR, /* MAC Sys Time Secs Update */
143 MAC_STNUR, /* MAC Sys Time NSecs Update */
144 MAC_TSAR, /* MAC TimeStamp Addend */
145 MAC_TSSR, /* MAC TimeStamp Status */
146 MAC_TXSNR, /* MAC TxTS Status NSecs */
147 MAC_TXSSR, /* MAC TxTS Status Secs */
148 };
149
150 static inline int
axgbe_regs_get_count(struct axgbe_port * pdata)151 axgbe_regs_get_count(struct axgbe_port *pdata)
152 {
153 int count = 0;
154 unsigned int i = 0;
155
156 count = ARRAY_SIZE(dma_reg_tbl);
157 for (i = 0; i < pdata->tx_ring_count; i++)
158 count += ARRAY_SIZE(dma_txch_reg_tbl);
159 for (i = 0; i < pdata->rx_ring_count; i++)
160 count += ARRAY_SIZE(dma_rxch_reg_tbl);
161 count += ARRAY_SIZE(mtl_reg_tbl);
162 for (i = 0; i < pdata->tx_q_count; i++)
163 count += ARRAY_SIZE(mtl_txq_reg_tbl);
164 for (i = 0; i < pdata->rx_q_count; i++)
165 count += ARRAY_SIZE(mtl_rxq_reg_tbl);
166 count += ARRAY_SIZE(mac_reg_tbl);
167 count += ARRAY_SIZE(mac_addr_reg_tbl);
168 count += ARRAY_SIZE(mac_ieee1558_reg_tbl);
169
170 return count;
171 };
172
173 static inline int
axgbe_regs_dump(struct axgbe_port * pdata,uint32_t * data)174 axgbe_regs_dump(struct axgbe_port *pdata, uint32_t *data)
175 {
176 unsigned int i = 0, j = 0;
177 unsigned int base_reg, reg;
178
179 for (i = 0; i < ARRAY_SIZE(dma_reg_tbl); i++)
180 *data++ = AXGMAC_IOREAD(pdata, dma_reg_tbl[i]);
181
182 for (j = 0; j < pdata->tx_ring_count; j++) {
183 base_reg = DMA_CH_BASE + (j * DMA_CH_INC);
184 for (i = 0; i < ARRAY_SIZE(dma_txch_reg_tbl); i++) {
185 reg = base_reg + dma_txch_reg_tbl[i];
186 *data++ = AXGMAC_IOREAD(pdata, reg);
187 }
188 }
189
190 for (j = 0; j < pdata->rx_ring_count; j++) {
191 base_reg = DMA_CH_BASE + (j * DMA_CH_INC);
192 for (i = 0; i < ARRAY_SIZE(dma_rxch_reg_tbl); i++) {
193 reg = base_reg + dma_rxch_reg_tbl[i];
194 *data++ = AXGMAC_IOREAD(pdata, reg);
195 }
196 }
197
198 for (i = 0; i < ARRAY_SIZE(mtl_reg_tbl); i++)
199 *data++ = AXGMAC_IOREAD(pdata, mtl_reg_tbl[i]);
200
201 for (j = 0; j < pdata->tx_q_count; j++) {
202 base_reg = MTL_Q_BASE + (j * MTL_Q_INC);
203 for (i = 0; i < ARRAY_SIZE(mtl_txq_reg_tbl); i++) {
204 reg = base_reg + mtl_txq_reg_tbl[i];
205 *data++ = AXGMAC_IOREAD(pdata, reg);
206 }
207 }
208
209 for (j = 0; j < pdata->rx_q_count; j++) {
210 base_reg = MTL_Q_BASE + (j * MTL_Q_INC);
211 for (i = 0; i < ARRAY_SIZE(mtl_rxq_reg_tbl); i++) {
212 reg = base_reg + mtl_rxq_reg_tbl[i];
213 *data++ = AXGMAC_IOREAD(pdata, reg);
214 }
215 }
216
217 for (i = 0; i < ARRAY_SIZE(mac_reg_tbl); i++)
218 *data++ = AXGMAC_IOREAD(pdata, mac_reg_tbl[i]);
219
220 for (i = 0; i < ARRAY_SIZE(mac_addr_reg_tbl); i++)
221 *data++ = AXGMAC_IOREAD(pdata, mac_addr_reg_tbl[i]);
222
223 for (i = 0; i < ARRAY_SIZE(mac_ieee1558_reg_tbl); i++)
224 *data++ = AXGMAC_IOREAD(pdata, mac_ieee1558_reg_tbl[i]);
225
226 return 0;
227 };
228
229 #endif /* RTE_ETH_AXGBE_REGS_H_ */
230